Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157494	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3932381

1

T1

8

T2

16

T4

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1065077	1			T1	75		T2	171		T4	58
values[0x0]	1485129	1			T12	25015		T26	22163		T27	21847
values[0x1]	1539669	1			T12	25709		T26	22725		T27	22569

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	81453	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4008422

1

T1

45

T2

102

T4

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16176	1			T72	1		T128	4		T12	249
valid_sources[0x01]	15747	1			T128	1		T12	268		T57	1
valid_sources[0x02]	15724	1			T64	1		T128	2		T12	267
valid_sources[0x03]	14833	1			T74	19		T128	1		T12	257
valid_sources[0x04]	15291	1			T11	3		T72	1		T64	3
valid_sources[0x05]	15226	1			T4	1		T64	1		T128	1
valid_sources[0x06]	14785	1			T73	2		T64	1		T128	1
valid_sources[0x07]	15808	1			T2	4		T73	1		T12	269
valid_sources[0x08]	17567	1			T51	11		T73	3		T12	288
valid_sources[0x09]	16339	1			T1	1		T11	1		T73	1
valid_sources[0x0a]	15936	1			T73	2		T128	2		T12	307
valid_sources[0x0b]	15095	1			T4	1		T11	1		T72	1
valid_sources[0x0c]	15757	1			T72	7		T73	1		T64	1
valid_sources[0x0d]	14755	1			T72	1		T128	1		T12	296
valid_sources[0x0e]	16410	1			T2	8		T4	2		T13	1
valid_sources[0x0f]	16785	1			T73	1		T64	1		T12	249
valid_sources[0x10]	15387	1			T71	3		T72	4		T73	4
valid_sources[0x11]	16865	1			T13	1		T64	1		T128	2
valid_sources[0x12]	15155	1			T73	1		T64	2		T128	3
valid_sources[0x13]	17182	1			T71	11		T72	2		T73	1
valid_sources[0x14]	14351	1			T14	2		T72	1		T73	3
valid_sources[0x15]	14695	1			T4	2		T73	2		T64	1
valid_sources[0x16]	14512	1			T11	2		T72	2		T73	1
valid_sources[0x17]	16868	1			T12	327		T57	1		T101	2
valid_sources[0x18]	14581	1			T128	2		T12	255		T57	2
valid_sources[0x19]	17795	1			T2	2		T6	58		T128	2
valid_sources[0x1a]	16508	1			T4	3		T73	1		T128	3
valid_sources[0x1b]	16876	1			T4	6		T128	1		T12	280
valid_sources[0x1c]	16818	1			T2	10		T64	1		T12	274
valid_sources[0x1d]	16649	1			T12	234		T57	1		T129	1
valid_sources[0x1e]	15299	1			T4	3		T128	1		T12	275
valid_sources[0x1f]	16480	1			T73	6		T12	212		T58	1
valid_sources[0x20]	15949	1			T128	2		T12	244		T20	1
valid_sources[0x21]	18157	1			T2	5		T6	13		T72	1
valid_sources[0x22]	16825	1			T1	1		T2	3		T4	1
valid_sources[0x23]	15643	1			T8	15		T11	1		T72	5
valid_sources[0x24]	15029	1			T11	1		T73	1		T12	248
valid_sources[0x25]	17015	1			T73	5		T128	3		T12	299
valid_sources[0x26]	15988	1			T72	3		T73	3		T128	1
valid_sources[0x27]	15037	1			T64	2		T12	285		T130	3
valid_sources[0x28]	15240	1			T1	1		T4	1		T71	11
valid_sources[0x29]	16134	1			T64	1		T12	281		T129	3
valid_sources[0x2a]	15601	1			T72	3		T128	2		T12	263
valid_sources[0x2b]	15643	1			T73	1		T12	260		T57	2
valid_sources[0x2c]	16659	1			T72	1		T73	1		T128	2
valid_sources[0x2d]	15189	1			T73	2		T64	1		T128	3
valid_sources[0x2e]	15963	1			T4	4		T8	69		T72	1
valid_sources[0x2f]	16917	1			T72	5		T73	1		T74	33
valid_sources[0x30]	16872	1			T11	3		T72	2		T73	1
valid_sources[0x31]	16147	1			T1	4		T73	2		T128	1
valid_sources[0x32]	15626	1			T6	12		T72	1		T64	1
valid_sources[0x33]	15031	1			T6	23		T72	2		T73	1
valid_sources[0x34]	15715	1			T1	1		T4	6		T11	3
valid_sources[0x35]	15996	1			T11	1		T73	1		T128	2
valid_sources[0x36]	16586	1			T11	1		T73	1		T12	267
valid_sources[0x37]	14982	1			T72	5		T73	1		T128	1
valid_sources[0x38]	15416	1			T1	1		T2	29		T12	271
valid_sources[0x39]	16133	1			T72	2		T73	3		T128	1
valid_sources[0x3a]	16760	1			T4	2		T72	3		T73	2
valid_sources[0x3b]	15513	1			T11	3		T71	8		T128	1
valid_sources[0x3c]	15599	1			T73	3		T128	1		T12	283
valid_sources[0x3d]	15889	1			T72	2		T64	1		T128	1
valid_sources[0x3e]	15763	1			T1	1		T64	1		T128	2
valid_sources[0x3f]	14633	1			T72	1		T12	223		T83	2
valid_sources[0x40]	16827	1			T72	4		T128	1		T12	319
valid_sources[0x41]	16881	1			T73	1		T12	229		T57	1
valid_sources[0x42]	15383	1			T73	1		T12	265		T57	1
valid_sources[0x43]	16928	1			T72	1		T64	1		T128	2
valid_sources[0x44]	15795	1			T2	12		T11	1		T72	2
valid_sources[0x45]	16487	1			T73	1		T12	215		T102	3
valid_sources[0x46]	16747	1			T73	2		T64	2		T128	1
valid_sources[0x47]	15848	1			T72	2		T12	263		T57	1
valid_sources[0x48]	17002	1			T11	3		T12	251		T131	4
valid_sources[0x49]	17435	1			T71	6		T12	245		T20	1
valid_sources[0x4a]	16032	1			T13	1		T11	2		T72	5
valid_sources[0x4b]	15354	1			T72	1		T73	2		T128	2
valid_sources[0x4c]	17325	1			T71	5		T72	3		T128	2
valid_sources[0x4d]	14949	1			T72	7		T12	242		T131	1
valid_sources[0x4e]	15846	1			T51	17		T73	2		T64	1
valid_sources[0x4f]	16146	1			T72	1		T73	1		T128	1
valid_sources[0x50]	18110	1			T128	1		T12	275		T131	2
valid_sources[0x51]	15091	1			T4	1		T11	1		T72	3
valid_sources[0x52]	16320	1			T11	1		T73	1		T128	1
valid_sources[0x53]	15427	1			T1	5		T72	3		T73	5
valid_sources[0x54]	16420	1			T4	1		T73	2		T64	2
valid_sources[0x55]	15255	1			T11	1		T71	3		T128	1
valid_sources[0x56]	14936	1			T73	2		T64	1		T128	1
valid_sources[0x57]	15859	1			T72	3		T73	3		T64	1
valid_sources[0x58]	16838	1			T1	1		T72	1		T73	1
valid_sources[0x59]	17538	1			T72	15		T128	2		T12	301
valid_sources[0x5a]	16092	1			T64	1		T128	1		T12	311
valid_sources[0x5b]	16094	1			T64	1		T128	1		T12	269
valid_sources[0x5c]	16052	1			T11	1		T71	6		T73	2
valid_sources[0x5d]	15687	1			T128	1		T12	288		T57	1
valid_sources[0x5e]	15596	1			T51	30		T73	1		T128	1
valid_sources[0x5f]	16009	1			T7	3		T11	1		T72	1
valid_sources[0x60]	16618	1			T11	2		T72	3		T74	19
valid_sources[0x61]	15997	1			T72	8		T73	1		T12	251
valid_sources[0x62]	16363	1			T71	10		T72	6		T73	2
valid_sources[0x63]	15461	1			T2	8		T72	3		T73	3
valid_sources[0x64]	15790	1			T128	3		T12	266		T57	2
valid_sources[0x65]	16289	1			T12	295		T57	1		T131	4
valid_sources[0x66]	16660	1			T2	3		T72	1		T73	2
valid_sources[0x67]	17289	1			T72	2		T73	1		T12	302
valid_sources[0x68]	15442	1			T6	47		T14	1		T71	2
valid_sources[0x69]	15716	1			T1	1		T73	2		T128	1
valid_sources[0x6a]	15401	1			T4	2		T71	2		T128	5
valid_sources[0x6b]	15762	1			T128	1		T12	283		T57	2
valid_sources[0x6c]	15797	1			T4	2		T128	1		T12	255
valid_sources[0x6d]	15582	1			T74	50		T64	1		T128	2
valid_sources[0x6e]	16546	1			T2	16		T128	2		T12	265
valid_sources[0x6f]	15881	1			T1	1		T72	3		T73	2
valid_sources[0x70]	16014	1			T1	1		T73	3		T64	1
valid_sources[0x71]	16055	1			T15	14		T72	7		T73	1
valid_sources[0x72]	16441	1			T73	3		T128	8		T12	270
valid_sources[0x73]	15123	1			T13	6		T71	5		T73	1
valid_sources[0x74]	15054	1			T128	4		T12	259		T57	1
valid_sources[0x75]	15228	1			T6	14		T73	1		T64	1
valid_sources[0x76]	16027	1			T11	1		T72	2		T12	280
valid_sources[0x77]	15716	1			T11	1		T15	24		T72	2
valid_sources[0x78]	16061	1			T72	1		T128	1		T12	254
valid_sources[0x79]	14733	1			T72	2		T128	1		T12	240
valid_sources[0x7a]	16422	1			T73	1		T12	236		T57	1
valid_sources[0x7b]	15696	1			T6	67		T128	2		T12	237
valid_sources[0x7c]	15680	1			T73	4		T64	1		T128	1
valid_sources[0x7d]	16585	1			T73	1		T128	4		T12	268
valid_sources[0x7e]	15617	1			T64	1		T12	224		T20	1
valid_sources[0x7f]	16800	1			T4	1		T72	5		T73	2
valid_sources[0x80]	15253	1			T1	1		T11	1		T72	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

987367

1

T1

8

T2

16

T4

5

values[0x0]

all_enables

biggest_size

1472108

1

T12

24792

T26

21966

T27

21645

values[0x1]

all_enables

biggest_size

1472906

1

T12

24596

T26

21815

T27

21543

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	289000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2987276

1

T3

6

T4

15

T7

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	817736	1			T4	32		T7	30		T9	34
values[0x0]	1138382	1			T3	7		T5	1		T16	5
values[0x1]	1320158	1			T3	11		T5	2		T16	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3148485

1

T3

8

T4

18

T7

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14042	1			T7	1		T51	2		T12	209
valid_sources[0x01]	11324	1			T12	174		T34	1		T20	1
valid_sources[0x02]	12011	1			T4	1		T13	1		T12	201
valid_sources[0x03]	12589	1			T12	202		T83	1		T24	2
valid_sources[0x04]	11971	1			T12	216		T58	1		T20	1
valid_sources[0x05]	12158	1			T64	2		T12	164		T47	1
valid_sources[0x06]	11521	1			T12	209		T50	2		T85	2
valid_sources[0x07]	12355	1			T4	1		T12	154		T48	1
valid_sources[0x08]	13384	1			T51	1		T64	1		T12	204
valid_sources[0x09]	12315	1			T15	1		T51	1		T12	205
valid_sources[0x0a]	12727	1			T9	1		T64	1		T12	230
valid_sources[0x0b]	11939	1			T12	178		T130	1		T27	216
valid_sources[0x0c]	12814	1			T12	239		T57	3		T130	1
valid_sources[0x0d]	12571	1			T4	1		T12	216		T20	1
valid_sources[0x0e]	12891	1			T51	1		T12	248		T83	1
valid_sources[0x0f]	13042	1			T14	2		T12	173		T47	2
valid_sources[0x10]	12307	1			T12	201		T17	1		T130	1
valid_sources[0x11]	12824	1			T7	3		T12	182		T58	1
valid_sources[0x12]	12017	1			T12	221		T20	1		T130	1
valid_sources[0x13]	14690	1			T7	1		T13	1		T12	215
valid_sources[0x14]	12591	1			T12	191		T101	1		T26	61
valid_sources[0x15]	11444	1			T9	1		T12	198		T57	2
valid_sources[0x16]	13012	1			T15	1		T51	1		T12	171
valid_sources[0x17]	13291	1			T12	215		T24	3		T26	1
valid_sources[0x18]	12860	1			T12	230		T58	1		T50	1
valid_sources[0x19]	12967	1			T12	239		T34	1		T132	2
valid_sources[0x1a]	13479	1			T12	227		T131	2		T101	1
valid_sources[0x1b]	11742	1			T22	1		T12	199		T130	1
valid_sources[0x1c]	12465	1			T4	2		T13	1		T11	32
valid_sources[0x1d]	13685	1			T12	238		T33	1		T20	1
valid_sources[0x1e]	13439	1			T51	2		T12	215		T131	1
valid_sources[0x1f]	13521	1			T12	220		T44	1		T50	1
valid_sources[0x20]	12026	1			T13	1		T12	228		T26	3
valid_sources[0x21]	13227	1			T12	208		T131	2		T130	1
valid_sources[0x22]	12245	1			T12	226		T20	1		T26	4
valid_sources[0x23]	14125	1			T4	2		T9	3		T12	181
valid_sources[0x24]	13486	1			T7	2		T15	1		T51	1
valid_sources[0x25]	13775	1			T12	240		T58	1		T131	1
valid_sources[0x26]	13006	1			T51	1		T12	246		T27	173
valid_sources[0x27]	13590	1			T12	206		T34	1		T47	1
valid_sources[0x28]	12648	1			T4	1		T12	203		T131	1
valid_sources[0x29]	14154	1			T4	3		T51	1		T12	198
valid_sources[0x2a]	13543	1			T12	207		T25	1		T26	584
valid_sources[0x2b]	11442	1			T14	1		T12	203		T57	3
valid_sources[0x2c]	12697	1			T51	1		T12	204		T101	1
valid_sources[0x2d]	12419	1			T12	216		T44	2		T26	202
valid_sources[0x2e]	13429	1			T12	209		T36	1		T102	1
valid_sources[0x2f]	13273	1			T13	1		T12	204		T131	2
valid_sources[0x30]	12894	1			T12	187		T131	1		T24	1
valid_sources[0x31]	14270	1			T15	1		T51	1		T12	194
valid_sources[0x32]	11687	1			T51	1		T12	216		T83	1
valid_sources[0x33]	12601	1			T64	1		T12	218		T85	2
valid_sources[0x34]	12007	1			T12	195		T58	1		T26	1
valid_sources[0x35]	12910	1			T64	1		T12	205		T20	1
valid_sources[0x36]	12662	1			T51	1		T12	220		T58	1
valid_sources[0x37]	11725	1			T16	5		T12	218		T83	2
valid_sources[0x38]	12481	1			T9	1		T15	1		T12	235
valid_sources[0x39]	12897	1			T12	193		T58	1		T133	1
valid_sources[0x3a]	13932	1			T12	180		T26	124		T27	215
valid_sources[0x3b]	11991	1			T13	2		T64	1		T12	234
valid_sources[0x3c]	12563	1			T4	1		T51	3		T12	185
valid_sources[0x3d]	14427	1			T12	227		T83	2		T20	1
valid_sources[0x3e]	11811	1			T16	1		T12	187		T34	1
valid_sources[0x3f]	13346	1			T51	1		T12	236		T34	1
valid_sources[0x40]	13079	1			T51	1		T12	209		T50	2
valid_sources[0x41]	13052	1			T64	2		T69	1		T12	199
valid_sources[0x42]	12199	1			T5	3		T15	1		T12	183
valid_sources[0x43]	13027	1			T15	1		T51	1		T12	196
valid_sources[0x44]	13044	1			T12	200		T50	1		T26	141
valid_sources[0x45]	14179	1			T13	1		T69	1		T12	197
valid_sources[0x46]	13201	1			T15	1		T69	1		T12	167
valid_sources[0x47]	12159	1			T51	1		T12	218		T20	1
valid_sources[0x48]	14212	1			T15	1		T64	1		T12	193
valid_sources[0x49]	13328	1			T3	3		T64	1		T12	207
valid_sources[0x4a]	12721	1			T12	226		T34	1		T101	1
valid_sources[0x4b]	12215	1			T4	1		T15	3		T12	216
valid_sources[0x4c]	12122	1			T12	197		T47	1		T134	2
valid_sources[0x4d]	12329	1			T64	1		T12	216		T36	1
valid_sources[0x4e]	11980	1			T51	1		T12	193		T34	1
valid_sources[0x4f]	13192	1			T51	1		T12	200		T26	170
valid_sources[0x50]	14024	1			T51	1		T12	182		T58	1
valid_sources[0x51]	11794	1			T7	3		T15	1		T51	1
valid_sources[0x52]	11996	1			T12	223		T83	1		T131	1
valid_sources[0x53]	12924	1			T7	1		T13	1		T14	5
valid_sources[0x54]	13583	1			T64	1		T12	191		T58	1
valid_sources[0x55]	13330	1			T14	2		T51	1		T12	208
valid_sources[0x56]	12192	1			T12	198		T133	1		T101	1
valid_sources[0x57]	12752	1			T13	1		T51	2		T70	1
valid_sources[0x58]	13055	1			T51	1		T12	201		T57	4
valid_sources[0x59]	12611	1			T7	1		T15	1		T51	1
valid_sources[0x5a]	12475	1			T13	1		T12	135		T132	2
valid_sources[0x5b]	12469	1			T12	206		T135	2		T102	1
valid_sources[0x5c]	14227	1			T13	1		T12	224		T132	2
valid_sources[0x5d]	13032	1			T12	221		T47	2		T130	1
valid_sources[0x5e]	11342	1			T51	1		T12	201		T50	2
valid_sources[0x5f]	11351	1			T12	181		T20	1		T135	6
valid_sources[0x60]	13318	1			T12	217		T58	1		T21	1
valid_sources[0x61]	13599	1			T7	2		T12	204		T135	8
valid_sources[0x62]	13950	1			T14	2		T12	192		T26	200
valid_sources[0x63]	13524	1			T12	205		T135	12		T131	1
valid_sources[0x64]	12917	1			T12	188		T130	1		T101	2
valid_sources[0x65]	14206	1			T12	198		T101	1		T27	217
valid_sources[0x66]	13474	1			T51	1		T70	4		T12	171
valid_sources[0x67]	12941	1			T12	178		T24	1		T84	6
valid_sources[0x68]	14342	1			T51	1		T12	197		T57	1
valid_sources[0x69]	12516	1			T51	1		T12	178		T101	1
valid_sources[0x6a]	13391	1			T12	186		T47	4		T20	1
valid_sources[0x6b]	12610	1			T12	211		T20	2		T135	1
valid_sources[0x6c]	13148	1			T13	1		T12	239		T57	4
valid_sources[0x6d]	11477	1			T12	186		T26	104		T27	190
valid_sources[0x6e]	12769	1			T3	14		T12	169		T33	1
valid_sources[0x6f]	14117	1			T51	2		T12	211		T57	3
valid_sources[0x70]	11989	1			T13	1		T12	211		T34	1
valid_sources[0x71]	13279	1			T69	1		T12	207		T58	1
valid_sources[0x72]	11904	1			T4	1		T15	1		T12	191
valid_sources[0x73]	11997	1			T12	239		T20	1		T101	2
valid_sources[0x74]	12520	1			T13	1		T51	3		T12	143
valid_sources[0x75]	12443	1			T12	227		T34	1		T26	85
valid_sources[0x76]	12065	1			T12	235		T58	1		T21	2
valid_sources[0x77]	13352	1			T15	1		T12	208		T57	3
valid_sources[0x78]	11541	1			T7	1		T64	2		T12	173
valid_sources[0x79]	12784	1			T12	184		T26	63		T27	207
valid_sources[0x7a]	11711	1			T14	3		T51	1		T12	254
valid_sources[0x7b]	12802	1			T14	3		T12	192		T50	1
valid_sources[0x7c]	12469	1			T15	1		T12	190		T131	1
valid_sources[0x7d]	12483	1			T12	196		T49	8		T131	1
valid_sources[0x7e]	12609	1			T7	1		T13	1		T12	204
valid_sources[0x7f]	12144	1			T12	226		T131	1		T101	1
valid_sources[0x80]	13415	1			T12	197		T102	2		T26	222

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

756496

1

T4

15

T7

13

T9

20

values[0x0]

all_enables

biggest_size

1115794

1

T3

4

T16

4

T67

1

values[0x1]

all_enables

biggest_size

1114986

1

T3

2

T16

1

T67

1