Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

7151934

1

T1

67

T2

155

T4

53

full_word

4586129

1

T1

8

T2

16

T4

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	11737783	1			T1	75		T2	171		T4	58
auto[TlIntgErrCmd]	95	1			T61	8		T62	3		T63	7
auto[TlIntgErrData]	92	1			T61	7		T62	1		T63	1
auto[TlIntgErrBoth]	93	1			T61	5		T62	6		T63	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1860001

1

T1

75

T2

171

T4

58

auto[1]

9878062

1

T12

159822

T26

141277

T27

149332

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	777698	1			T1	67		T2	155		T4	53
auto[TlIntgErrNone]	partial	auto[1]	6373976	1			T12	101588		T26	89657		T27	97671
auto[TlIntgErrNone]	full_word	auto[0]	1082183	1			T1	8		T2	16		T4	5
auto[TlIntgErrNone]	full_word	auto[1]	3503926	1			T12	58234		T26	51620		T27	51661
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T61	5		T63	2		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T61	3		T62	3		T63	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T123	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T63	1		T117	2		T113	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T61	3		T112	1		T117	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T61	3		T62	1		T63	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T118	1		T115	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T61	1		T113	2		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T61	3		T62	2		T117	4
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T61	2		T62	4		T63	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T126	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T126	1		T119	1		-	-