Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.49	96.96	93.40	97.88	100.00	98.68	98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	95.92	100.00	96.30	90.00	100.00	98.31	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.59	91.45	86.03	99.07		96.39	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	437	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
207	1	1
253	1	1
308	1	1
409	8	8
410	8	8
412	8	8
413	8	8
415	8	8
416	8	8
420	1	1
422	1	1
425	1	1
426	1	1
427	1	1
428	1	1
433	1	1
437	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       207
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       253
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T13
1	1	Covered	T1,T2,T4

 LINE       413
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       413
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T33,T34
1	0	Not Covered

 LINE       422
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T13
1	0	Covered	T7,T9,T10

 LINE       433
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T16
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T5,T16

 LINE       437
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T9,T13
0	1	0	Covered	T7,T9,T10
1	0	0	Covered	T32,T33,T34

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T7,T9	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T6,T8	Yes	T1,T6,T8	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T6,T9,T35	Yes	T1,T6,T9	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
rom_tl_o.a_ready	Yes	Yes	T4,T7,T9	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T12,T26,T27	Yes	T12,T26,T27	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T12,*T26,*T27	Yes	T12,T26,T27	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T7	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T3,T4,T7	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T7	Yes	T3,T7,T16	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T7	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T3,T4,T7	Yes	T2,T3,T4	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T3,T5,T7	Yes	T2,T3,T7	INPUT
regs_tl_i.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
regs_tl_o.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_error	Yes	Yes	T12,T26,T27	Yes	T12,T26,T27	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T7,T9	Yes	T4,T7,T9	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T3,*T4,*T7	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T4,T7,T9	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T7	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T3,T4,T7	Yes	T3,T4,T5	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T4,*T7,*T9	Yes	T4,T7,T9	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T4,T7,T9	OUTPUT
keymgr_data_o.valid	Yes	Yes	T4,T7,T9	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T7,T9,T13	Yes	T3,T4,T6	OUTPUT
kmac_data_i.error	No	Yes	T10,T22,T23	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T7,T9,T13	Yes	T7,T9,T13	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T7,T9,T10	Yes	T4,T7,T9	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	207	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	207	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	418563241	418215839	0	0
BusRomIndicesMatch_A	418538215	418202969	0	0
FpvSecCmFifoRptrCheck_A	418563241	0	0	0
FpvSecCmFifoWptrCheck_A	418563241	0	0	0
FpvSecCmRegWeOnehotCheck_A	418563241	140	0	0
KeymgrDataODataKnown_A	418563241	155935946	0	0
KeymgrDataODataKnown_AKnownEnable	418563241	418215839	0	0
KeymgrDataOValidKnown_A	418563241	418215839	0	0
KeymgrValidChk_A	418563241	0	0	648
KmacDataODataKnown_A	418563241	262046674	0	0
KmacDataODataKnown_AKnownEnable	418563241	418215839	0	0
KmacDataOValidKnown_A	418563241	418215839	0	0
PwrmgrDataChk_A	418563241	0	0	648
PwrmgrDataOKnown_A	418563241	418215839	0	0
RegsTlOAReadyKnown_A	418563241	418215839	0	0
RegsTlODDataKnown_A	418563241	18819705	0	0
RegsTlODDataKnown_AKnownEnable	418563241	418215839	0	0
RegsTlODValidKnown_A	418563241	418215839	0	0
RomTlOAReadyKnown_A	418563241	418215839	0	0
RomTlODDataKnown_A	418563241	29551731	0	0
RomTlODDataKnown_AKnownEnable	418563241	418215839	0	0
RomTlODValidKnown_A	418563241	418215839	0	0
StabilityChkKmac_A	418563241	262041811	0	0
StabilityChkkeymgr_A	418563241	155933542	0	0
TlAccessChk_A	418563241	262279893	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	418563241	140	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	418563241	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	418563241	981	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	418563241	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418538215	418202969	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138742	138507	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	140	0	0
T18	16848	0	0	0
T32	81654	20	0	0
T33	114822	10	0	0
T34	22369	20	0	0
T36	0	20	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	20	0	0
T41	0	10	0	0
T42	0	10	0	0
T43	8298	0	0	0
T44	167150	0	0	0
T45	115306	0	0	0
T46	28810	0	0	0
T47	18098	0	0	0
T48	139960	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	155935946	0	0
T1	95123	743	0	0
T2	177860	1364	0	0
T3	28986	134	0	0
T4	75616	1711	0	0
T5	12505	61	0	0
T6	196570	1401	0	0
T7	138770	3764	0	0
T8	161680	901	0	0
T9	363021	6307	0	0
T10	252969	277	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	0	0	648

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	262046674	0	0
T1	95123	94174	0	0
T2	177860	176348	0	0
T3	28986	28686	0	0
T4	75616	73709	0	0
T5	12505	12325	0	0
T6	196570	195062	0	0
T7	138770	137951	0	0
T8	161680	160615	0	0
T9	363021	361940	0	0
T10	252969	252404	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	0	0	648

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	18819705	0	0
T3	28986	53	0	0
T4	75616	153	0	0
T5	12505	13	0	0
T6	196570	0	0	0
T7	138770	30	0	0
T8	161680	0	0	0
T9	363021	34	0	0
T10	252969	2	0	0
T11	0	107	0	0
T13	193496	31	0	0
T14	0	114	0	0
T16	8353	9	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	29551731	0	0
T1	95123	75	0	0
T2	177860	171	0	0
T3	28986	0	0	0
T4	75616	306	0	0
T5	12505	0	0	0
T6	196570	440	0	0
T7	138770	3	0	0
T8	161680	166	0	0
T9	363021	0	0	0
T10	252969	0	0	0
T11	0	316	0	0
T13	0	26	0	0
T14	0	11	0	0
T15	0	48	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	418215839	0	0
T1	95123	95027	0	0
T2	177860	177764	0	0
T3	28986	28914	0	0
T4	75616	75486	0	0
T5	12505	12409	0	0
T6	196570	196498	0	0
T7	138770	138528	0	0
T8	161680	161624	0	0
T9	363021	362733	0	0
T10	252969	252839	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	262041811	0	0
T1	95123	94173	0	0
T2	177860	176347	0	0
T3	28986	28685	0	0
T4	75616	73707	0	0
T5	12505	12324	0	0
T6	196570	195061	0	0
T7	138770	137948	0	0
T8	161680	160614	0	0
T9	363021	361936	0	0
T10	252969	252402	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	155933542	0	0
T1	95123	742	0	0
T2	177860	1363	0	0
T3	28986	133	0	0
T4	75616	1709	0	0
T5	12505	60	0	0
T6	196570	1400	0	0
T7	138770	3748	0	0
T8	161680	900	0	0
T9	363021	6291	0	0
T10	252969	276	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	262279893	0	0
T1	95123	94284	0	0
T2	177860	176400	0	0
T3	28986	28780	0	0
T4	75616	73775	0	0
T5	12505	12348	0	0
T6	196570	195097	0	0
T7	138770	138151	0	0
T8	161680	160723	0	0
T9	363021	362103	0	0
T10	252969	252562	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	140	0	0
T18	16848	0	0	0
T32	81654	20	0	0
T33	114822	10	0	0
T34	22369	20	0	0
T36	0	20	0	0
T37	0	10	0	0
T38	0	10	0	0
T39	0	10	0	0
T40	0	20	0	0
T41	0	10	0	0
T42	0	10	0	0
T43	8298	0	0	0
T44	167150	0	0	0
T45	115306	0	0	0
T46	28810	0	0	0
T47	18098	0	0	0
T48	139960	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	981	0	0
T7	138770	10	0	0
T8	161680	0	0	0
T9	363021	10	0	0
T10	252969	0	0	0
T11	26349	0	0	0
T13	193496	10	0	0
T14	121025	10	0	0
T15	287990	0	0	0
T16	8353	0	0	0
T32	0	20	0	0
T33	0	10	0	0
T34	0	20	0	0
T35	0	10	0	0
T49	0	10	0	0
T50	0	10	0	0
T51	400752	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418563241	0	0	0