Module Definition
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Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 66.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_rom
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN22100.00
ALWAYS2722100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 0 1
27 1 1
28 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_rom
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 27 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 27 if (req_i)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_generic_rom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
noXOnCsI 418563241 418563241 0 0


noXOnCsI
NameAttemptsReal SuccessesFailuresIncomplete
Total 418563241 418563241 0 0
T1 95123 95123 0 0
T2 177860 177860 0 0
T3 28986 28986 0 0
T4 75616 75616 0 0
T5 12505 12505 0 0
T6 196570 196570 0 0
T7 138770 138770 0 0
T8 161680 161680 0 0
T9 363021 363021 0 0
T10 252969 252969 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%