Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3499486

1

T3

70

T4

62

T9

314

full_word

2205988

1

T2

2

T3

4

T4

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5704864	1			T2	2		T3	74		T4	68
auto[TlIntgErrCmd]	207	1			T67	8		T68	3		T69	8
auto[TlIntgErrData]	197	1			T67	5		T68	3		T69	2
auto[TlIntgErrBoth]	206	1			T67	7		T68	4		T69	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

922502

1

T2

2

T3

74

T4

68

auto[1]

4782972

1

T20

110703

T21

158416

T22

120687

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	398768	1			T3	70		T4	62		T9	314
auto[TlIntgErrNone]	partial	auto[1]	3100155	1			T20	73315		T21	102737		T22	77027
auto[TlIntgErrNone]	full_word	auto[0]	523452	1			T2	2		T3	4		T4	6
auto[TlIntgErrNone]	full_word	auto[1]	1682489	1			T20	37388		T21	55679		T22	43660
auto[TlIntgErrCmd]	partial	auto[0]	84	1			T67	4		T68	1		T69	3
auto[TlIntgErrCmd]	partial	auto[1]	111	1			T67	4		T68	1		T69	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T133	1		T129	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T68	1		T138	1		T139	1
auto[TlIntgErrData]	partial	auto[0]	91	1			T67	2		T68	2		T69	1
auto[TlIntgErrData]	partial	auto[1]	86	1			T67	3		T68	1		T69	1
auto[TlIntgErrData]	full_word	auto[0]	12	1			T140	1		T129	1		T138	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T129	1		T141	1		T139	2
auto[TlIntgErrBoth]	partial	auto[0]	78	1			T67	3		T68	1		T69	2
auto[TlIntgErrBoth]	partial	auto[1]	113	1			T67	4		T68	3		T69	8
auto[TlIntgErrBoth]	full_word	auto[0]	10	1			T129	1		T137	2		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T133	1		T143	1		T140	1