Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl_counter
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_counter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.64 100.00 98.18 100.00 100.00 75.00 gen_fsm_scramble_enabled.u_checker_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl_counter
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN7411100.00
ALWAYS7633100.00
ALWAYS8466100.00
ALWAYS9455100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 1 1
76 1 1
77 1 1
79 1 1
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
89 1 1
MISSING_ELSE
94 1 1
95 1 1
96 1 1
101 1 1
104 1 1
108 1 1
110 1 1
111 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1


Cond Coverage for Module : rom_ctrl_counter
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (addr_q == TopAddr)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 EXPRESSION (data_rdy_i & vld_q & ((~done_d)))
             -----1----   --2--   -----3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       111
 EXPRESSION (addr_q == TNTAddr)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       114
 EXPRESSION (go ? addr_d : addr_q)
             -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : rom_ctrl_counter
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 114 2 2 100.00
IF 76 2 2 100.00
IF 84 3 3 100.00
IF 94 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 114 (go) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 84 if ((!rst_ni)) -2-: 87 if (go)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : rom_ctrl_counter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NonTopCountValid_A 628 628 0 0
TopCountValid_A 628 628 0 0


NonTopCountValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TopCountValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%