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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.68 96.96 93.11 97.88 100.00 98.68 98.04 99.07


Total test records in report: 916
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T766 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2301652006 Mar 28 12:43:54 PM PDT 24 Mar 28 12:44:31 PM PDT 24 20442525315 ps
T767 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.698701493 Mar 28 12:43:59 PM PDT 24 Mar 28 12:44:07 PM PDT 24 272759659 ps
T768 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1776551088 Mar 28 12:43:57 PM PDT 24 Mar 28 12:44:58 PM PDT 24 22153127113 ps
T769 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2135624546 Mar 28 12:44:22 PM PDT 24 Mar 28 12:47:34 PM PDT 24 23579125110 ps
T770 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.113544419 Mar 28 12:50:09 PM PDT 24 Mar 28 12:50:48 PM PDT 24 4107011873 ps
T771 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3221005341 Mar 28 12:44:18 PM PDT 24 Mar 28 12:44:50 PM PDT 24 34979279554 ps
T772 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.66027650 Mar 28 12:43:50 PM PDT 24 Mar 28 12:43:59 PM PDT 24 918425276 ps
T773 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1344240285 Mar 28 12:50:22 PM PDT 24 Mar 28 12:50:40 PM PDT 24 5829318870 ps
T774 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1295845769 Mar 28 12:44:18 PM PDT 24 Mar 28 12:44:35 PM PDT 24 655559380 ps
T775 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2372722230 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:23 PM PDT 24 302575821 ps
T776 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3281207453 Mar 28 12:43:59 PM PDT 24 Mar 28 12:45:34 PM PDT 24 2544912088 ps
T777 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.253167904 Mar 28 12:43:58 PM PDT 24 Mar 28 12:44:27 PM PDT 24 3699747957 ps
T778 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3968020992 Mar 28 12:44:19 PM PDT 24 Mar 28 12:44:47 PM PDT 24 3541146104 ps
T779 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.505697176 Mar 28 12:50:09 PM PDT 24 Mar 28 12:50:34 PM PDT 24 6473177873 ps
T780 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4001208788 Mar 28 12:50:24 PM PDT 24 Mar 28 12:51:52 PM PDT 24 4248748910 ps
T781 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2926252004 Mar 28 12:50:01 PM PDT 24 Mar 28 12:50:22 PM PDT 24 4089185561 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.379417591 Mar 28 12:50:05 PM PDT 24 Mar 28 12:53:02 PM PDT 24 21667279122 ps
T141 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.424051529 Mar 28 12:50:12 PM PDT 24 Mar 28 12:51:38 PM PDT 24 2165756470 ps
T782 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1936044047 Mar 28 12:44:20 PM PDT 24 Mar 28 12:44:58 PM PDT 24 8564397948 ps
T783 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3724709136 Mar 28 12:44:01 PM PDT 24 Mar 28 12:44:30 PM PDT 24 4033653154 ps
T784 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1217159667 Mar 28 12:50:20 PM PDT 24 Mar 28 12:50:47 PM PDT 24 12798604030 ps
T785 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3695218727 Mar 28 12:44:14 PM PDT 24 Mar 28 12:44:36 PM PDT 24 5335707234 ps
T786 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3294697905 Mar 28 12:50:05 PM PDT 24 Mar 28 12:50:24 PM PDT 24 1735846167 ps
T787 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4081227037 Mar 28 12:44:17 PM PDT 24 Mar 28 12:44:39 PM PDT 24 6109774875 ps
T788 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1592356713 Mar 28 12:43:56 PM PDT 24 Mar 28 12:44:05 PM PDT 24 345559974 ps
T100 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.948795571 Mar 28 12:44:16 PM PDT 24 Mar 28 12:44:46 PM PDT 24 7529294429 ps
T139 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2485760011 Mar 28 12:50:09 PM PDT 24 Mar 28 12:52:54 PM PDT 24 8053820109 ps
T789 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3888654144 Mar 28 12:43:56 PM PDT 24 Mar 28 12:44:31 PM PDT 24 13762734421 ps
T137 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1212937607 Mar 28 12:50:19 PM PDT 24 Mar 28 12:52:50 PM PDT 24 307856552 ps
T790 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.764302823 Mar 28 12:50:08 PM PDT 24 Mar 28 12:50:41 PM PDT 24 16816351765 ps
T791 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3171975206 Mar 28 12:44:17 PM PDT 24 Mar 28 12:47:43 PM PDT 24 32196793563 ps
T792 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.136667041 Mar 28 12:43:56 PM PDT 24 Mar 28 12:44:35 PM PDT 24 13788468242 ps
T793 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3190447775 Mar 28 12:43:57 PM PDT 24 Mar 28 12:44:21 PM PDT 24 11041720875 ps
T794 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3764596694 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:44 PM PDT 24 3725466265 ps
T795 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.637456656 Mar 28 12:50:22 PM PDT 24 Mar 28 12:52:04 PM PDT 24 9487593435 ps
T796 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3519005330 Mar 28 12:44:17 PM PDT 24 Mar 28 12:44:47 PM PDT 24 19054178349 ps
T797 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1739653428 Mar 28 12:43:54 PM PDT 24 Mar 28 12:44:13 PM PDT 24 7205387301 ps
T798 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4088180391 Mar 28 12:43:57 PM PDT 24 Mar 28 12:46:29 PM PDT 24 17992679343 ps
T799 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2210997054 Mar 28 12:43:54 PM PDT 24 Mar 28 12:45:38 PM PDT 24 4185293142 ps
T800 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4134537343 Mar 28 12:43:57 PM PDT 24 Mar 28 12:44:05 PM PDT 24 917737786 ps
T801 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.316422201 Mar 28 12:44:16 PM PDT 24 Mar 28 12:44:33 PM PDT 24 1236372063 ps
T802 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1763174077 Mar 28 12:44:16 PM PDT 24 Mar 28 12:44:43 PM PDT 24 20342972506 ps
T803 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.348055841 Mar 28 12:44:14 PM PDT 24 Mar 28 12:47:15 PM PDT 24 35690724651 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2868614875 Mar 28 12:43:59 PM PDT 24 Mar 28 12:46:35 PM PDT 24 16746050944 ps
T804 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1790965239 Mar 28 12:50:23 PM PDT 24 Mar 28 12:50:47 PM PDT 24 2645980199 ps
T805 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1166543439 Mar 28 12:50:06 PM PDT 24 Mar 28 12:50:43 PM PDT 24 31412315941 ps
T806 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4265468510 Mar 28 12:50:21 PM PDT 24 Mar 28 12:50:40 PM PDT 24 3161292902 ps
T807 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3554538114 Mar 28 12:50:05 PM PDT 24 Mar 28 12:50:39 PM PDT 24 8339472026 ps
T99 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4151693827 Mar 28 12:50:22 PM PDT 24 Mar 28 12:52:55 PM PDT 24 31557277641 ps
T808 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2865403106 Mar 28 12:50:05 PM PDT 24 Mar 28 12:50:15 PM PDT 24 518607681 ps
T809 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1363790902 Mar 28 12:50:09 PM PDT 24 Mar 28 12:52:55 PM PDT 24 5822868359 ps
T810 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.466863289 Mar 28 12:44:17 PM PDT 24 Mar 28 12:47:08 PM PDT 24 4260068805 ps
T811 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2161363465 Mar 28 12:50:09 PM PDT 24 Mar 28 12:51:54 PM PDT 24 7467261541 ps
T812 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3125129554 Mar 28 12:50:05 PM PDT 24 Mar 28 12:50:14 PM PDT 24 688645250 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1076191190 Mar 28 12:43:57 PM PDT 24 Mar 28 12:44:18 PM PDT 24 8919064070 ps
T813 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1122993136 Mar 28 12:50:12 PM PDT 24 Mar 28 12:50:21 PM PDT 24 319258168 ps
T814 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.475926669 Mar 28 12:44:06 PM PDT 24 Mar 28 12:44:37 PM PDT 24 6445328218 ps
T815 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1574842188 Mar 28 12:50:20 PM PDT 24 Mar 28 12:50:34 PM PDT 24 2742962072 ps
T816 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2966476011 Mar 28 12:50:05 PM PDT 24 Mar 28 12:50:31 PM PDT 24 11836219231 ps
T142 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3396568139 Mar 28 12:50:06 PM PDT 24 Mar 28 12:51:49 PM PDT 24 15972186293 ps
T817 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3380480262 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:40 PM PDT 24 5667930742 ps
T818 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2941176105 Mar 28 12:44:13 PM PDT 24 Mar 28 12:44:37 PM PDT 24 6878567638 ps
T819 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2695028272 Mar 28 12:50:09 PM PDT 24 Mar 28 12:50:45 PM PDT 24 4246083321 ps
T820 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2361754253 Mar 28 12:50:06 PM PDT 24 Mar 28 12:50:29 PM PDT 24 5333828131 ps
T821 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2299956503 Mar 28 12:49:42 PM PDT 24 Mar 28 12:51:50 PM PDT 24 32162821004 ps
T134 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1377524692 Mar 28 12:43:53 PM PDT 24 Mar 28 12:45:28 PM PDT 24 9560200342 ps
T103 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.784409691 Mar 28 12:44:20 PM PDT 24 Mar 28 12:44:42 PM PDT 24 8905282197 ps
T822 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1864012407 Mar 28 12:50:08 PM PDT 24 Mar 28 12:51:56 PM PDT 24 11425160336 ps
T823 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3867200273 Mar 28 12:44:21 PM PDT 24 Mar 28 12:47:01 PM PDT 24 648048781 ps
T824 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4015846795 Mar 28 12:44:01 PM PDT 24 Mar 28 12:46:46 PM PDT 24 1843010761 ps
T825 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2458845067 Mar 28 12:50:05 PM PDT 24 Mar 28 12:50:13 PM PDT 24 170740720 ps
T826 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1014309061 Mar 28 12:50:10 PM PDT 24 Mar 28 12:50:36 PM PDT 24 14139412395 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1568712979 Mar 28 12:50:06 PM PDT 24 Mar 28 12:50:19 PM PDT 24 521224024 ps
T827 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3234755800 Mar 28 12:44:20 PM PDT 24 Mar 28 12:44:49 PM PDT 24 13365152232 ps
T828 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2652225444 Mar 28 12:50:03 PM PDT 24 Mar 28 12:50:28 PM PDT 24 37284098120 ps
T829 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3973412226 Mar 28 12:50:08 PM PDT 24 Mar 28 12:50:41 PM PDT 24 4169421951 ps
T830 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2230256394 Mar 28 12:44:16 PM PDT 24 Mar 28 12:44:33 PM PDT 24 6584374410 ps
T135 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2931195991 Mar 28 12:50:19 PM PDT 24 Mar 28 12:53:06 PM PDT 24 2498333288 ps
T831 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3968317884 Mar 28 12:50:06 PM PDT 24 Mar 28 12:50:28 PM PDT 24 6905660382 ps
T832 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1126916221 Mar 28 12:43:56 PM PDT 24 Mar 28 12:44:23 PM PDT 24 12360167458 ps
T833 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.789833480 Mar 28 12:44:14 PM PDT 24 Mar 28 12:44:22 PM PDT 24 167419099 ps
T834 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3855521666 Mar 28 12:50:05 PM PDT 24 Mar 28 12:50:31 PM PDT 24 4505259635 ps
T835 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3231168433 Mar 28 12:44:21 PM PDT 24 Mar 28 12:44:31 PM PDT 24 198303768 ps
T102 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4207594353 Mar 28 12:44:00 PM PDT 24 Mar 28 12:47:20 PM PDT 24 100307281361 ps
T836 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3583307621 Mar 28 12:50:22 PM PDT 24 Mar 28 12:50:49 PM PDT 24 6133722871 ps
T837 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.691016882 Mar 28 12:50:19 PM PDT 24 Mar 28 12:50:47 PM PDT 24 3101566957 ps
T838 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.46799884 Mar 28 12:43:58 PM PDT 24 Mar 28 12:44:24 PM PDT 24 8888092308 ps
T839 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2532501503 Mar 28 12:44:18 PM PDT 24 Mar 28 12:44:50 PM PDT 24 11661533287 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4046262747 Mar 28 12:50:22 PM PDT 24 Mar 28 12:52:39 PM PDT 24 12833461847 ps
T840 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2113218713 Mar 28 12:50:08 PM PDT 24 Mar 28 12:50:30 PM PDT 24 2306925353 ps
T841 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1043146897 Mar 28 12:44:21 PM PDT 24 Mar 28 12:47:08 PM PDT 24 87293006807 ps
T842 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3901236500 Mar 28 12:44:15 PM PDT 24 Mar 28 12:45:07 PM PDT 24 2117084377 ps
T843 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2729013795 Mar 28 12:50:10 PM PDT 24 Mar 28 12:51:06 PM PDT 24 1056331853 ps
T844 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2794014754 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:23 PM PDT 24 174588056 ps
T845 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2015178702 Mar 28 12:43:52 PM PDT 24 Mar 28 12:45:32 PM PDT 24 10494238385 ps
T846 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.625344110 Mar 28 12:50:09 PM PDT 24 Mar 28 12:50:38 PM PDT 24 3542377418 ps
T847 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.394263105 Mar 28 12:43:51 PM PDT 24 Mar 28 12:44:12 PM PDT 24 2204541079 ps
T848 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3610244873 Mar 28 12:44:22 PM PDT 24 Mar 28 12:44:52 PM PDT 24 7592853527 ps
T849 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3606126259 Mar 28 12:50:28 PM PDT 24 Mar 28 12:50:39 PM PDT 24 2348924900 ps
T850 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3232498544 Mar 28 12:43:57 PM PDT 24 Mar 28 12:44:27 PM PDT 24 11178172367 ps
T851 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1260697832 Mar 28 12:43:59 PM PDT 24 Mar 28 12:44:20 PM PDT 24 2264208682 ps
T852 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2429909293 Mar 28 12:50:08 PM PDT 24 Mar 28 12:50:31 PM PDT 24 9208087708 ps
T853 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2075983084 Mar 28 12:50:07 PM PDT 24 Mar 28 12:52:58 PM PDT 24 12946733168 ps
T854 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1055316960 Mar 28 12:43:58 PM PDT 24 Mar 28 12:44:36 PM PDT 24 1408409869 ps
T855 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2905134930 Mar 28 12:44:14 PM PDT 24 Mar 28 12:45:41 PM PDT 24 27976908320 ps
T856 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.818355666 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:42 PM PDT 24 2204025279 ps
T857 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.321716800 Mar 28 12:50:12 PM PDT 24 Mar 28 12:51:16 PM PDT 24 40354824565 ps
T858 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2213137722 Mar 28 12:50:03 PM PDT 24 Mar 28 12:50:37 PM PDT 24 15706830400 ps
T859 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3138254440 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:38 PM PDT 24 2414742245 ps
T860 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.932060269 Mar 28 12:43:57 PM PDT 24 Mar 28 12:44:10 PM PDT 24 216710700 ps
T861 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3118000447 Mar 28 12:43:57 PM PDT 24 Mar 28 12:45:23 PM PDT 24 872118000 ps
T862 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3267722560 Mar 28 12:44:21 PM PDT 24 Mar 28 12:44:32 PM PDT 24 916432755 ps
T863 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.580734465 Mar 28 12:50:07 PM PDT 24 Mar 28 12:52:32 PM PDT 24 86239253608 ps
T864 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4021242079 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:37 PM PDT 24 2355044459 ps
T865 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.257942165 Mar 28 12:44:22 PM PDT 24 Mar 28 12:44:33 PM PDT 24 376178011 ps
T866 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.366920121 Mar 28 12:44:00 PM PDT 24 Mar 28 12:44:34 PM PDT 24 17135951060 ps
T867 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1734905327 Mar 28 12:44:21 PM PDT 24 Mar 28 12:47:17 PM PDT 24 20102081911 ps
T868 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3668512467 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:28 PM PDT 24 2022966917 ps
T869 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3790989018 Mar 28 12:50:07 PM PDT 24 Mar 28 12:50:26 PM PDT 24 1541875246 ps
T870 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3453310507 Mar 28 12:50:09 PM PDT 24 Mar 28 12:50:36 PM PDT 24 2319319152 ps
T871 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2154159603 Mar 28 12:50:09 PM PDT 24 Mar 28 12:50:36 PM PDT 24 3038150850 ps
T872 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2735691145 Mar 28 12:50:21 PM PDT 24 Mar 28 12:52:31 PM PDT 24 30798037420 ps
T873 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2392532573 Mar 28 12:50:07 PM PDT 24 Mar 28 12:50:23 PM PDT 24 173980788 ps
T874 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2252160715 Mar 28 12:43:59 PM PDT 24 Mar 28 12:44:29 PM PDT 24 14958332377 ps
T875 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2683275922 Mar 28 12:44:19 PM PDT 24 Mar 28 12:44:50 PM PDT 24 15275014306 ps
T876 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1385555188 Mar 28 12:50:09 PM PDT 24 Mar 28 12:53:02 PM PDT 24 7905145255 ps
T877 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3228001143 Mar 28 12:50:09 PM PDT 24 Mar 28 12:50:23 PM PDT 24 2438404642 ps
T878 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1327863191 Mar 28 12:43:57 PM PDT 24 Mar 28 12:44:05 PM PDT 24 660660128 ps
T879 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2196784169 Mar 28 12:44:21 PM PDT 24 Mar 28 12:45:45 PM PDT 24 1915551512 ps
T880 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.133643282 Mar 28 12:50:07 PM PDT 24 Mar 28 12:51:03 PM PDT 24 4575149214 ps
T881 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3929590050 Mar 28 12:44:21 PM PDT 24 Mar 28 12:44:44 PM PDT 24 8894798428 ps
T882 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.442051901 Mar 28 12:50:19 PM PDT 24 Mar 28 12:51:34 PM PDT 24 22721141827 ps
T883 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2760609044 Mar 28 12:50:19 PM PDT 24 Mar 28 12:52:54 PM PDT 24 407103793 ps
T884 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2764880560 Mar 28 12:50:21 PM PDT 24 Mar 28 12:50:35 PM PDT 24 167305720 ps
T885 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.140839336 Mar 28 12:50:10 PM PDT 24 Mar 28 12:50:19 PM PDT 24 178726204 ps
T886 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2136059261 Mar 28 12:50:21 PM PDT 24 Mar 28 12:50:38 PM PDT 24 4432704627 ps
T887 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3112070006 Mar 28 12:50:21 PM PDT 24 Mar 28 12:50:30 PM PDT 24 186072263 ps
T888 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2458586282 Mar 28 12:44:16 PM PDT 24 Mar 28 12:44:44 PM PDT 24 5420349919 ps
T889 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.311121485 Mar 28 12:50:08 PM PDT 24 Mar 28 12:50:28 PM PDT 24 8147126773 ps
T890 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1790503100 Mar 28 12:44:12 PM PDT 24 Mar 28 12:44:25 PM PDT 24 2848245812 ps
T891 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1077415834 Mar 28 12:50:07 PM PDT 24 Mar 28 12:51:05 PM PDT 24 4143520005 ps
T892 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.724045402 Mar 28 12:43:56 PM PDT 24 Mar 28 12:44:15 PM PDT 24 1801009979 ps
T893 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3403579729 Mar 28 12:43:59 PM PDT 24 Mar 28 12:44:07 PM PDT 24 1372799223 ps
T894 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3275757601 Mar 28 12:44:20 PM PDT 24 Mar 28 12:44:34 PM PDT 24 256147828 ps
T895 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2084829161 Mar 28 12:50:12 PM PDT 24 Mar 28 12:50:44 PM PDT 24 19376342401 ps
T896 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3029460974 Mar 28 12:50:06 PM PDT 24 Mar 28 12:50:19 PM PDT 24 776223221 ps
T897 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2471991945 Mar 28 12:50:07 PM PDT 24 Mar 28 12:50:27 PM PDT 24 10636308553 ps
T898 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3861748348 Mar 28 12:44:14 PM PDT 24 Mar 28 12:47:04 PM PDT 24 6324785251 ps
T899 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4284394914 Mar 28 12:50:07 PM PDT 24 Mar 28 12:50:24 PM PDT 24 1974669085 ps
T900 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2916187788 Mar 28 12:43:55 PM PDT 24 Mar 28 12:44:14 PM PDT 24 6367088044 ps
T901 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3340418732 Mar 28 12:44:16 PM PDT 24 Mar 28 12:46:01 PM PDT 24 40138269437 ps
T902 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4103170236 Mar 28 12:43:51 PM PDT 24 Mar 28 12:44:19 PM PDT 24 3161733511 ps
T903 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3882135263 Mar 28 12:50:26 PM PDT 24 Mar 28 12:52:06 PM PDT 24 22122233882 ps
T904 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3061625641 Mar 28 12:44:12 PM PDT 24 Mar 28 12:46:09 PM PDT 24 14398368428 ps
T905 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.342373294 Mar 28 12:50:24 PM PDT 24 Mar 28 12:50:51 PM PDT 24 9145458166 ps
T906 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3317192019 Mar 28 12:43:59 PM PDT 24 Mar 28 12:44:32 PM PDT 24 8891954743 ps
T907 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1566376065 Mar 28 12:44:20 PM PDT 24 Mar 28 12:44:34 PM PDT 24 661400094 ps
T908 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1175441831 Mar 28 12:43:56 PM PDT 24 Mar 28 12:44:04 PM PDT 24 660306363 ps
T909 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1259061141 Mar 28 12:43:54 PM PDT 24 Mar 28 12:46:54 PM PDT 24 42969853540 ps
T910 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3613175020 Mar 28 12:50:08 PM PDT 24 Mar 28 12:50:19 PM PDT 24 171165889 ps
T911 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1917364810 Mar 28 12:50:25 PM PDT 24 Mar 28 12:50:55 PM PDT 24 3848095042 ps
T912 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.70648594 Mar 28 12:44:15 PM PDT 24 Mar 28 12:44:41 PM PDT 24 11705776809 ps
T913 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2929677506 Mar 28 12:50:21 PM PDT 24 Mar 28 12:50:34 PM PDT 24 696456687 ps
T914 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.288427892 Mar 28 12:44:01 PM PDT 24 Mar 28 12:44:15 PM PDT 24 2162485463 ps
T915 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2137100766 Mar 28 12:50:22 PM PDT 24 Mar 28 12:53:21 PM PDT 24 3306412541 ps
T916 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.645555124 Mar 28 12:43:58 PM PDT 24 Mar 28 12:44:33 PM PDT 24 24687360333 ps

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.431582818
Short name T2
Test name
Test status
Simulation time 166739152926 ps
CPU time 568.74 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 01:01:16 PM PDT 24
Peak memory 237420 kb
Host smart-33dece2f-566c-40ef-bd1b-8ac50492a353
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431582818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.431582818
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2613389615
Short name T21
Test name
Test status
Simulation time 193900607597 ps
CPU time 1088.42 seconds
Started Mar 28 12:52:08 PM PDT 24
Finished Mar 28 01:10:16 PM PDT 24
Peak memory 236472 kb
Host smart-5df22e9d-2615-4fb7-ba9f-943eb7a1ccb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613389615 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2613389615
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1537501747
Short name T37
Test name
Test status
Simulation time 6113922225 ps
CPU time 85.08 seconds
Started Mar 28 12:51:46 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 219824 kb
Host smart-18248e8b-3031-49aa-b7b6-ddbef2687322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537501747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1537501747
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3431975846
Short name T31
Test name
Test status
Simulation time 3761769418 ps
CPU time 150.48 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:54:19 PM PDT 24
Peak memory 240864 kb
Host smart-534f5d85-2e99-439c-bdca-1abbcf8f4177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431975846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3431975846
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1336104216
Short name T129
Test name
Test status
Simulation time 3193824091 ps
CPU time 159.95 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:46:55 PM PDT 24
Peak memory 213628 kb
Host smart-2e2082dc-5924-49f0-a8b4-850261e037c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336104216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1336104216
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.12132471
Short name T11
Test name
Test status
Simulation time 5782644177 ps
CPU time 59.43 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 217712 kb
Host smart-382d98f6-f43b-4aa2-b549-5a3456b4c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12132471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.12132471
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3475990417
Short name T35
Test name
Test status
Simulation time 5436405348 ps
CPU time 226.99 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:55:21 PM PDT 24
Peak memory 237380 kb
Host smart-6430ea69-2651-46ed-9c1c-b141f56bd9ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475990417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3475990417
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1655322669
Short name T73
Test name
Test status
Simulation time 2861661451 ps
CPU time 24.68 seconds
Started Mar 28 12:43:53 PM PDT 24
Finished Mar 28 12:44:18 PM PDT 24
Peak memory 211384 kb
Host smart-d0543cd3-b10d-4438-8e71-df9050999791
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655322669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1655322669
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2625664256
Short name T4
Test name
Test status
Simulation time 34142596483 ps
CPU time 95.9 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:53:45 PM PDT 24
Peak memory 218316 kb
Host smart-339087db-85a3-4e57-bd2d-25f842f1589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625664256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2625664256
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1376192884
Short name T133
Test name
Test status
Simulation time 589431173 ps
CPU time 152.62 seconds
Started Mar 28 12:50:18 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 214456 kb
Host smart-424f599d-d735-41fe-898e-d35c6491a6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376192884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1376192884
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3861748348
Short name T898
Test name
Test status
Simulation time 6324785251 ps
CPU time 170.76 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:47:04 PM PDT 24
Peak memory 213960 kb
Host smart-a1bfe440-a2f5-4c28-bbc4-b85c429ef5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861748348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3861748348
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2310250122
Short name T63
Test name
Test status
Simulation time 11930634640 ps
CPU time 26.27 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:22 PM PDT 24
Peak memory 212868 kb
Host smart-17898217-c133-4e39-92bc-9205ef00c72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310250122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2310250122
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1593974429
Short name T30
Test name
Test status
Simulation time 13762780215 ps
CPU time 60.93 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 214616 kb
Host smart-11f83e72-6ce7-42e6-a6d3-5dfff707a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593974429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1593974429
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3769687712
Short name T424
Test name
Test status
Simulation time 332183604 ps
CPU time 19.07 seconds
Started Mar 28 12:40:18 PM PDT 24
Finished Mar 28 12:40:37 PM PDT 24
Peak memory 215244 kb
Host smart-62464f5d-8a63-4030-a841-ba920cd34de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769687712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3769687712
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1111893095
Short name T28
Test name
Test status
Simulation time 31796654239 ps
CPU time 59.39 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:33 PM PDT 24
Peak memory 215528 kb
Host smart-b06a4e7c-05aa-44c7-8ca7-874c230e63a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111893095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1111893095
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2868614875
Short name T98
Test name
Test status
Simulation time 16746050944 ps
CPU time 155.83 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:46:35 PM PDT 24
Peak memory 214084 kb
Host smart-6f968f5a-d96d-44c0-b3b0-6847feceef02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868614875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2868614875
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3915637703
Short name T27
Test name
Test status
Simulation time 32242826470 ps
CPU time 343.42 seconds
Started Mar 28 12:41:06 PM PDT 24
Finished Mar 28 12:46:49 PM PDT 24
Peak memory 237352 kb
Host smart-990b3e1a-533d-4861-8ab5-c1ed51027e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915637703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3915637703
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2180087886
Short name T116
Test name
Test status
Simulation time 10893982728 ps
CPU time 25.02 seconds
Started Mar 28 12:43:55 PM PDT 24
Finished Mar 28 12:44:20 PM PDT 24
Peak memory 212120 kb
Host smart-66f3a943-b251-48df-a8ae-f2d767a1d613
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180087886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2180087886
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2890289340
Short name T106
Test name
Test status
Simulation time 4234720493 ps
CPU time 33.8 seconds
Started Mar 28 12:51:46 PM PDT 24
Finished Mar 28 12:52:20 PM PDT 24
Peak memory 212280 kb
Host smart-86fc9ddf-94dc-4266-99a9-b4fc14d359cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890289340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2890289340
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.780576564
Short name T23
Test name
Test status
Simulation time 52144140389 ps
CPU time 992.74 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:58:19 PM PDT 24
Peak memory 236360 kb
Host smart-b0713d8c-8c0e-46cd-89c8-5ebf99b6b89d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780576564 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.780576564
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1748959658
Short name T739
Test name
Test status
Simulation time 6897826114 ps
CPU time 18.89 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 211728 kb
Host smart-00f91ed8-9bed-4e77-9943-2c291bd2a527
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748959658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1748959658
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.66027650
Short name T772
Test name
Test status
Simulation time 918425276 ps
CPU time 8.68 seconds
Started Mar 28 12:43:50 PM PDT 24
Finished Mar 28 12:43:59 PM PDT 24
Peak memory 210908 kb
Host smart-65062a45-1fd1-4673-b850-26f80f7d3566
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66027650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasi
ng.66027650
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2471991945
Short name T897
Test name
Test status
Simulation time 10636308553 ps
CPU time 19.83 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 211564 kb
Host smart-1dded636-0431-49a1-80fd-1e6d587e7c91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471991945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2471991945
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4036569953
Short name T702
Test name
Test status
Simulation time 8175255786 ps
CPU time 16.67 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:13 PM PDT 24
Peak memory 210956 kb
Host smart-f13c6ffd-5c7e-4d56-b3ab-2a2ddee93f48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036569953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4036569953
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2173216650
Short name T79
Test name
Test status
Simulation time 1920550392 ps
CPU time 23.92 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:18 PM PDT 24
Peak memory 211256 kb
Host smart-1c3492a1-d916-4ebc-82fe-179186af68e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173216650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2173216650
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2617575127
Short name T732
Test name
Test status
Simulation time 3637579198 ps
CPU time 17.13 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:27 PM PDT 24
Peak memory 211052 kb
Host smart-ca3fa96c-faf6-4a17-9708-ad91e8e96fb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617575127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2617575127
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2213137722
Short name T858
Test name
Test status
Simulation time 15706830400 ps
CPU time 34.01 seconds
Started Mar 28 12:50:03 PM PDT 24
Finished Mar 28 12:50:37 PM PDT 24
Peak memory 219056 kb
Host smart-c04409b1-ba0b-4e01-bb4e-56c07f930823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213137722 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2213137722
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.253167904
Short name T777
Test name
Test status
Simulation time 3699747957 ps
CPU time 29.15 seconds
Started Mar 28 12:43:58 PM PDT 24
Finished Mar 28 12:44:27 PM PDT 24
Peak memory 214680 kb
Host smart-f5a58657-437b-4d93-9776-a1704ac1a832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253167904 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.253167904
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2649275565
Short name T699
Test name
Test status
Simulation time 12302513580 ps
CPU time 33.15 seconds
Started Mar 28 12:43:51 PM PDT 24
Finished Mar 28 12:44:25 PM PDT 24
Peak memory 211920 kb
Host smart-beb2d5c8-a30d-458d-a3ba-748c2066913d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649275565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2649275565
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.357672996
Short name T692
Test name
Test status
Simulation time 2504792583 ps
CPU time 23.17 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 210960 kb
Host smart-e6ac0f30-caeb-4f7d-b692-06708764b27c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357672996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.357672996
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2966476011
Short name T816
Test name
Test status
Simulation time 11836219231 ps
CPU time 25.68 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 210720 kb
Host smart-f1a21873-41ed-4b55-a63b-ebfbe140e5d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966476011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2966476011
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4103170236
Short name T902
Test name
Test status
Simulation time 3161733511 ps
CPU time 27.14 seconds
Started Mar 28 12:43:51 PM PDT 24
Finished Mar 28 12:44:19 PM PDT 24
Peak memory 210804 kb
Host smart-ef0e25c8-7de0-410c-910d-1ba6dfc5a460
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103170236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4103170236
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1739653428
Short name T797
Test name
Test status
Simulation time 7205387301 ps
CPU time 18.89 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:13 PM PDT 24
Peak memory 210736 kb
Host smart-55e6c94b-d5f9-4c42-8ec7-082292fa68c9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739653428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1739653428
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3968317884
Short name T831
Test name
Test status
Simulation time 6905660382 ps
CPU time 21.71 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 210920 kb
Host smart-f71e7a9b-73a3-4ea2-b5a7-2c1796dc4f58
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968317884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3968317884
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1055316960
Short name T854
Test name
Test status
Simulation time 1408409869 ps
CPU time 38.48 seconds
Started Mar 28 12:43:58 PM PDT 24
Finished Mar 28 12:44:36 PM PDT 24
Peak memory 212872 kb
Host smart-7fd47368-37e1-49ae-a0d0-5e1072cbc44d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055316960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1055316960
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2299956503
Short name T821
Test name
Test status
Simulation time 32162821004 ps
CPU time 127.98 seconds
Started Mar 28 12:49:42 PM PDT 24
Finished Mar 28 12:51:50 PM PDT 24
Peak memory 213068 kb
Host smart-d4c6106e-a093-435d-8f76-2aa00ed83e46
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299956503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2299956503
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3228001143
Short name T877
Test name
Test status
Simulation time 2438404642 ps
CPU time 13.06 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:23 PM PDT 24
Peak memory 210924 kb
Host smart-bf8c494b-2784-4cf6-9830-68f29a7dbf2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228001143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3228001143
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2300384569
Short name T686
Test name
Test status
Simulation time 2645578945 ps
CPU time 28.25 seconds
Started Mar 28 12:49:35 PM PDT 24
Finished Mar 28 12:50:04 PM PDT 24
Peak memory 218016 kb
Host smart-3926097f-720e-4aa4-b919-3aa0e893c93f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300384569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2300384569
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3724709136
Short name T783
Test name
Test status
Simulation time 4033653154 ps
CPU time 28.51 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:44:30 PM PDT 24
Peak memory 218108 kb
Host smart-c96b46ca-00dd-4ab5-a9ca-7cda936c780b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724709136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3724709136
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1377524692
Short name T134
Test name
Test status
Simulation time 9560200342 ps
CPU time 94.06 seconds
Started Mar 28 12:43:53 PM PDT 24
Finished Mar 28 12:45:28 PM PDT 24
Peak memory 213544 kb
Host smart-9e0784e2-7a44-4351-86d9-ab6635ce9a12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377524692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1377524692
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2075983084
Short name T853
Test name
Test status
Simulation time 12946733168 ps
CPU time 170.41 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 214680 kb
Host smart-054f1e8c-58ea-49be-9fba-21f6f79f34d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075983084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2075983084
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.625344110
Short name T846
Test name
Test status
Simulation time 3542377418 ps
CPU time 28.16 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:38 PM PDT 24
Peak memory 211204 kb
Host smart-7000d8f6-45c3-4fce-99bc-15fb49da2524
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625344110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.625344110
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1126916221
Short name T832
Test name
Test status
Simulation time 12360167458 ps
CPU time 27.1 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:23 PM PDT 24
Peak memory 211564 kb
Host smart-2c09c295-7b63-43d8-8e63-639e518cf936
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126916221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1126916221
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1926477629
Short name T731
Test name
Test status
Simulation time 4108202840 ps
CPU time 21.79 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 210968 kb
Host smart-c7871a74-5667-4408-9661-76dfc3c5cced
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926477629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1926477629
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.113544419
Short name T770
Test name
Test status
Simulation time 4107011873 ps
CPU time 38.63 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 211304 kb
Host smart-8c70997e-c47f-41a5-8a4f-76a10cd3078b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113544419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.113544419
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.645555124
Short name T916
Test name
Test status
Simulation time 24687360333 ps
CPU time 34.73 seconds
Started Mar 28 12:43:58 PM PDT 24
Finished Mar 28 12:44:33 PM PDT 24
Peak memory 211540 kb
Host smart-2c70a0f7-1981-4554-95f2-1a1a14a300c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645555124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.645555124
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1243291960
Short name T714
Test name
Test status
Simulation time 659783843 ps
CPU time 8.92 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:06 PM PDT 24
Peak memory 216472 kb
Host smart-ca1e7d29-a26a-40b5-9123-61f775b8f36f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243291960 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1243291960
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2361754253
Short name T820
Test name
Test status
Simulation time 5333828131 ps
CPU time 22.78 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 217368 kb
Host smart-a548df63-e24f-4c23-8b51-648e44477603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361754253 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2361754253
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2865403106
Short name T808
Test name
Test status
Simulation time 518607681 ps
CPU time 9.92 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:15 PM PDT 24
Peak memory 210908 kb
Host smart-1dbcf642-75bb-477d-bf3d-e90cb89b350f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865403106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2865403106
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4134537343
Short name T800
Test name
Test status
Simulation time 917737786 ps
CPU time 8.09 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:05 PM PDT 24
Peak memory 210888 kb
Host smart-5f06ce6d-6e45-4f08-b45f-939b82ed59fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134537343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4134537343
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3029460974
Short name T896
Test name
Test status
Simulation time 776223221 ps
CPU time 12.89 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:19 PM PDT 24
Peak memory 210792 kb
Host smart-1f39a8d6-2aec-4a18-b106-6bc9d74d1cc7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029460974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3029460974
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.329968437
Short name T716
Test name
Test status
Simulation time 3288011460 ps
CPU time 11.84 seconds
Started Mar 28 12:43:58 PM PDT 24
Finished Mar 28 12:44:10 PM PDT 24
Peak memory 210760 kb
Host smart-50fe4ad7-8b57-4b3d-b47e-2c5e557e5233
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329968437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.329968437
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1122993136
Short name T813
Test name
Test status
Simulation time 319258168 ps
CPU time 8.19 seconds
Started Mar 28 12:50:12 PM PDT 24
Finished Mar 28 12:50:21 PM PDT 24
Peak memory 210812 kb
Host smart-5dd5dbe8-cd8a-44a9-b4e1-ac11d50907ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122993136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1122993136
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2744395295
Short name T694
Test name
Test status
Simulation time 751926708 ps
CPU time 8.16 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:02 PM PDT 24
Peak memory 210672 kb
Host smart-b350fbbf-51f5-4d0e-8119-51aaf6e458e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744395295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2744395295
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1259061141
Short name T909
Test name
Test status
Simulation time 42969853540 ps
CPU time 180.18 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:46:54 PM PDT 24
Peak memory 215088 kb
Host smart-decbb6f4-1473-4ef0-8007-3284ca85e8c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259061141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1259061141
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.133643282
Short name T880
Test name
Test status
Simulation time 4575149214 ps
CPU time 54.59 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:51:03 PM PDT 24
Peak memory 213224 kb
Host smart-864b4f36-39d4-45ae-a884-673c8ae2b6ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133643282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.133643282
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.311121485
Short name T889
Test name
Test status
Simulation time 8147126773 ps
CPU time 19.13 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 212432 kb
Host smart-ad84fba3-0fa4-48b5-9b39-bb72b0bd73db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311121485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.311121485
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.861164868
Short name T742
Test name
Test status
Simulation time 4739823309 ps
CPU time 16.25 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:10 PM PDT 24
Peak memory 210896 kb
Host smart-dcc155d6-7a8b-4b6e-818c-40d06e1d99b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861164868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.861164868
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2167930349
Short name T749
Test name
Test status
Simulation time 13118089921 ps
CPU time 30.81 seconds
Started Mar 28 12:50:04 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 217216 kb
Host smart-ad45f42c-cab5-4b7a-88d7-c85fa113fb36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167930349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2167930349
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2301652006
Short name T766
Test name
Test status
Simulation time 20442525315 ps
CPU time 37.32 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:31 PM PDT 24
Peak memory 218540 kb
Host smart-c56514ae-8af0-4e93-b809-e06dd9728ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301652006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2301652006
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2161363465
Short name T811
Test name
Test status
Simulation time 7467261541 ps
CPU time 104.21 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:51:54 PM PDT 24
Peak memory 213644 kb
Host smart-4ea8f4e5-4b11-4343-aed3-b70fd0c8bc12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161363465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2161363465
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4015846795
Short name T824
Test name
Test status
Simulation time 1843010761 ps
CPU time 164.91 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:46:46 PM PDT 24
Peak memory 214436 kb
Host smart-a8c4b5b9-871b-46c9-87e7-013079dcf57e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015846795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4015846795
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.142518361
Short name T710
Test name
Test status
Simulation time 1641789962 ps
CPU time 18.29 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 215088 kb
Host smart-0465c043-538f-474a-952d-f955417e05ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142518361 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.142518361
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3267722560
Short name T862
Test name
Test status
Simulation time 916432755 ps
CPU time 11.47 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:44:32 PM PDT 24
Peak memory 216184 kb
Host smart-eb91a300-51f5-46bf-a319-44c4e966c23a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267722560 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3267722560
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2372722230
Short name T775
Test name
Test status
Simulation time 302575821 ps
CPU time 7.96 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:23 PM PDT 24
Peak memory 210808 kb
Host smart-3c411b2c-42f8-4f95-8b6e-d8837644d4e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372722230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2372722230
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3606126259
Short name T849
Test name
Test status
Simulation time 2348924900 ps
CPU time 10.23 seconds
Started Mar 28 12:50:28 PM PDT 24
Finished Mar 28 12:50:39 PM PDT 24
Peak memory 210968 kb
Host smart-088f82e7-6d22-489f-bcf4-b57dc5fb8755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606126259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3606126259
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3171975206
Short name T791
Test name
Test status
Simulation time 32196793563 ps
CPU time 204.54 seconds
Started Mar 28 12:44:17 PM PDT 24
Finished Mar 28 12:47:43 PM PDT 24
Peak memory 215188 kb
Host smart-693298b1-b68d-42e2-88ef-5a8e1207d17c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171975206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3171975206
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.321716800
Short name T857
Test name
Test status
Simulation time 40354824565 ps
CPU time 63.68 seconds
Started Mar 28 12:50:12 PM PDT 24
Finished Mar 28 12:51:16 PM PDT 24
Peak memory 213016 kb
Host smart-7567dcaa-dfbf-4195-9279-adb96343bc88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321716800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.321716800
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1790503100
Short name T890
Test name
Test status
Simulation time 2848245812 ps
CPU time 12.75 seconds
Started Mar 28 12:44:12 PM PDT 24
Finished Mar 28 12:44:25 PM PDT 24
Peak memory 210804 kb
Host smart-a830b79f-ac94-451f-ace3-eaed88f88ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790503100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1790503100
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3337257273
Short name T738
Test name
Test status
Simulation time 6877154303 ps
CPU time 28.59 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 212052 kb
Host smart-a576f5b0-cbbf-40cf-a5cd-31fbb3506c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337257273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3337257273
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1324403419
Short name T721
Test name
Test status
Simulation time 4294413320 ps
CPU time 37.28 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 218168 kb
Host smart-b9dddd9d-72be-4f09-8d41-914f9e99c1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324403419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1324403419
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.70648594
Short name T912
Test name
Test status
Simulation time 11705776809 ps
CPU time 26.44 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:41 PM PDT 24
Peak memory 218260 kb
Host smart-23184a82-b4c0-4e00-8f44-29e0c4c9e9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70648594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.70648594
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2196784169
Short name T879
Test name
Test status
Simulation time 1915551512 ps
CPU time 83.54 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:45:45 PM PDT 24
Peak memory 213276 kb
Host smart-af8a816b-d258-459d-8fec-219c6bfdd462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196784169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2196784169
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2760609044
Short name T883
Test name
Test status
Simulation time 407103793 ps
CPU time 153.47 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 213552 kb
Host smart-20f2d9f4-b7d5-437c-95fa-a53142378191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760609044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2760609044
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3540582703
Short name T706
Test name
Test status
Simulation time 10923966435 ps
CPU time 25.23 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 217476 kb
Host smart-f923411e-9094-40de-b497-dcd43bf82393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540582703 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3540582703
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3764596694
Short name T794
Test name
Test status
Simulation time 3725466265 ps
CPU time 29.25 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:44 PM PDT 24
Peak memory 217380 kb
Host smart-7375e9ae-989b-415a-838d-ba55435a9ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764596694 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3764596694
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2480145206
Short name T122
Test name
Test status
Simulation time 338791350 ps
CPU time 8.21 seconds
Started Mar 28 12:44:19 PM PDT 24
Finished Mar 28 12:44:28 PM PDT 24
Peak memory 210752 kb
Host smart-627c2843-5bed-472d-a90a-7129fb2a6891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480145206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2480145206
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2623309078
Short name T723
Test name
Test status
Simulation time 1831933536 ps
CPU time 8.21 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 210844 kb
Host smart-25645101-2a7b-4492-93e6-922c35e365ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623309078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2623309078
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.610345202
Short name T81
Test name
Test status
Simulation time 16404023471 ps
CPU time 153.28 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:46:49 PM PDT 24
Peak memory 215184 kb
Host smart-012bcdb7-090d-4a60-8e05-ed6e29064bb1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610345202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.610345202
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3610244873
Short name T848
Test name
Test status
Simulation time 7592853527 ps
CPU time 30.03 seconds
Started Mar 28 12:44:22 PM PDT 24
Finished Mar 28 12:44:52 PM PDT 24
Peak memory 211964 kb
Host smart-caaf47b9-c377-484e-a1f6-dd012a2644ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610244873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3610244873
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3738121398
Short name T733
Test name
Test status
Simulation time 5615784430 ps
CPU time 19.79 seconds
Started Mar 28 12:50:17 PM PDT 24
Finished Mar 28 12:50:37 PM PDT 24
Peak memory 212356 kb
Host smart-16c09acb-f6d5-4c71-815a-4913df998063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738121398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3738121398
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3060508946
Short name T740
Test name
Test status
Simulation time 4097626777 ps
CPU time 35.22 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:56 PM PDT 24
Peak memory 217168 kb
Host smart-cfc60848-236f-4009-ba0e-34b5369ca648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060508946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3060508946
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3407739276
Short name T712
Test name
Test status
Simulation time 3569795908 ps
CPU time 32.03 seconds
Started Mar 28 12:44:22 PM PDT 24
Finished Mar 28 12:44:55 PM PDT 24
Peak memory 218064 kb
Host smart-9773b85c-cab7-44c9-bc28-34c02db80664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407739276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3407739276
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1116674789
Short name T140
Test name
Test status
Simulation time 1274515784 ps
CPU time 154.32 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:46:48 PM PDT 24
Peak memory 213600 kb
Host smart-a52fc04a-1291-4547-816d-9b8edd7f39fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116674789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1116674789
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1545639598
Short name T718
Test name
Test status
Simulation time 11093294194 ps
CPU time 21.79 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:44:37 PM PDT 24
Peak memory 216540 kb
Host smart-c939a48a-7626-48a6-b7e8-e62e2c41436b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545639598 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1545639598
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3603441843
Short name T729
Test name
Test status
Simulation time 3628507514 ps
CPU time 31.03 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:51 PM PDT 24
Peak memory 217912 kb
Host smart-6a2e6123-3dbb-465a-bc26-1455dbce654b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603441843 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3603441843
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2337921390
Short name T713
Test name
Test status
Simulation time 7810633737 ps
CPU time 19.05 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:50:39 PM PDT 24
Peak memory 211744 kb
Host smart-d9e7f828-94d6-4495-af03-fe765c4d3cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337921390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2337921390
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2341689155
Short name T762
Test name
Test status
Simulation time 6153869344 ps
CPU time 17.55 seconds
Started Mar 28 12:44:17 PM PDT 24
Finished Mar 28 12:44:35 PM PDT 24
Peak memory 211800 kb
Host smart-e2d3297b-c904-4bb6-90e2-428559aa9cdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341689155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2341689155
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3061625641
Short name T904
Test name
Test status
Simulation time 14398368428 ps
CPU time 117.54 seconds
Started Mar 28 12:44:12 PM PDT 24
Finished Mar 28 12:46:09 PM PDT 24
Peak memory 214032 kb
Host smart-da422cb5-5196-4510-b097-4f22aeb05e83
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061625641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3061625641
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.957870420
Short name T90
Test name
Test status
Simulation time 18097039608 ps
CPU time 88.66 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:51:49 PM PDT 24
Peak memory 213292 kb
Host smart-fd300dd7-710d-4d25-a56e-966297c1c1af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957870420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.957870420
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.182528086
Short name T753
Test name
Test status
Simulation time 8897911153 ps
CPU time 21.65 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:42 PM PDT 24
Peak memory 212268 kb
Host smart-33001d89-6a92-427e-8914-8cb4242e688c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182528086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.182528086
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.316422201
Short name T801
Test name
Test status
Simulation time 1236372063 ps
CPU time 16.3 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:44:33 PM PDT 24
Peak memory 210924 kb
Host smart-5a593dbb-ca8f-45e7-b165-abb01df0d1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316422201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.316422201
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1574842188
Short name T815
Test name
Test status
Simulation time 2742962072 ps
CPU time 14.13 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 217044 kb
Host smart-db383046-c22a-4921-87fb-95af247087a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574842188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1574842188
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2740516710
Short name T698
Test name
Test status
Simulation time 2022318341 ps
CPU time 23.45 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:38 PM PDT 24
Peak memory 216980 kb
Host smart-8ae1f355-3c95-4eba-8659-737c709b28b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740516710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2740516710
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1212937607
Short name T137
Test name
Test status
Simulation time 307856552 ps
CPU time 151.51 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:52:50 PM PDT 24
Peak memory 213532 kb
Host smart-863fac4c-08ba-4cc0-ba19-be13f21913c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212937607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1212937607
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1747332735
Short name T741
Test name
Test status
Simulation time 11020089464 ps
CPU time 93.91 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:45:49 PM PDT 24
Peak memory 213480 kb
Host smart-279cbc2c-25ba-4ca6-a075-f4f534db1004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747332735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1747332735
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2929677506
Short name T913
Test name
Test status
Simulation time 696456687 ps
CPU time 12.06 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 214092 kb
Host smart-5c5794ef-11a4-4b21-bee7-dddddc4df909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929677506 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2929677506
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.933834724
Short name T752
Test name
Test status
Simulation time 1359454456 ps
CPU time 13.72 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:44:28 PM PDT 24
Peak memory 216796 kb
Host smart-ee2bb113-3c04-4813-8b9f-b065f4d0b9a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933834724 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.933834724
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2458586282
Short name T888
Test name
Test status
Simulation time 5420349919 ps
CPU time 28.16 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:44:44 PM PDT 24
Peak memory 212172 kb
Host smart-42121f35-d80d-4f8a-bf81-8b0bf57594ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458586282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2458586282
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3112070006
Short name T887
Test name
Test status
Simulation time 186072263 ps
CPU time 8.4 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 210776 kb
Host smart-ad6a2500-ff47-4070-958c-ae9983533df7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112070006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3112070006
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1734905327
Short name T867
Test name
Test status
Simulation time 20102081911 ps
CPU time 175.24 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:47:17 PM PDT 24
Peak memory 215056 kb
Host smart-1b1068b7-0a98-4641-b190-0000204f96d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734905327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1734905327
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2047524218
Short name T82
Test name
Test status
Simulation time 23412450754 ps
CPU time 110.76 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:52:13 PM PDT 24
Peak memory 215108 kb
Host smart-11b1db4c-5a2b-4a43-b3ed-bd8af1242b1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047524218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2047524218
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2068057764
Short name T83
Test name
Test status
Simulation time 2540766491 ps
CPU time 27.19 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 212080 kb
Host smart-3d840ccc-0b93-48d2-a165-cae20da0a8c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068057764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2068057764
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2230256394
Short name T830
Test name
Test status
Simulation time 6584374410 ps
CPU time 16.6 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:44:33 PM PDT 24
Peak memory 211012 kb
Host smart-073e842e-d716-41e5-b81b-2cc1e006dddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230256394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2230256394
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1009391463
Short name T743
Test name
Test status
Simulation time 4453290271 ps
CPU time 20.04 seconds
Started Mar 28 12:44:17 PM PDT 24
Finished Mar 28 12:44:38 PM PDT 24
Peak memory 218564 kb
Host smart-b0e46153-a91c-4eb9-b2fa-e0b3b3594416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009391463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1009391463
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.153418126
Short name T689
Test name
Test status
Simulation time 4459556682 ps
CPU time 24.58 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:46 PM PDT 24
Peak memory 218604 kb
Host smart-21db36c9-a9f3-44ca-95a1-d2745cc4e5c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153418126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.153418126
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2137100766
Short name T915
Test name
Test status
Simulation time 3306412541 ps
CPU time 177.94 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:53:21 PM PDT 24
Peak memory 213604 kb
Host smart-ffeef737-661b-43a3-b00b-214a3aa32d03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137100766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2137100766
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2392402920
Short name T725
Test name
Test status
Simulation time 1766458183 ps
CPU time 80.49 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:45:42 PM PDT 24
Peak memory 213136 kb
Host smart-5ba1f040-1463-4b46-a55b-7626791fcd86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392402920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2392402920
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2566475716
Short name T737
Test name
Test status
Simulation time 1872449128 ps
CPU time 20.11 seconds
Started Mar 28 12:50:17 PM PDT 24
Finished Mar 28 12:50:38 PM PDT 24
Peak memory 217816 kb
Host smart-f0c72812-c7e7-4625-8f6d-7bc1952fb4c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566475716 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2566475716
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3221005341
Short name T771
Test name
Test status
Simulation time 34979279554 ps
CPU time 31.58 seconds
Started Mar 28 12:44:18 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 218284 kb
Host smart-01e88537-bac7-4a57-92ef-9cb382386fde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221005341 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3221005341
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1344240285
Short name T773
Test name
Test status
Simulation time 5829318870 ps
CPU time 17.05 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:40 PM PDT 24
Peak memory 211760 kb
Host smart-09edefae-1cf2-4b7e-a253-80dc023781db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344240285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1344240285
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.948795571
Short name T100
Test name
Test status
Simulation time 7529294429 ps
CPU time 29.63 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 211992 kb
Host smart-e93d8ef6-9ed7-469e-8714-746f5dbbb503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948795571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.948795571
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2905134930
Short name T855
Test name
Test status
Simulation time 27976908320 ps
CPU time 86.48 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:45:41 PM PDT 24
Peak memory 214068 kb
Host smart-d7e4dfac-fa39-467b-aa68-b20dcfa0ee50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905134930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2905134930
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4151693827
Short name T99
Test name
Test status
Simulation time 31557277641 ps
CPU time 152.44 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:52:55 PM PDT 24
Peak memory 215104 kb
Host smart-a7659c3f-e6d8-4a04-9a3b-a94fdeeace67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151693827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4151693827
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1790965239
Short name T804
Test name
Test status
Simulation time 2645980199 ps
CPU time 24.35 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 211896 kb
Host smart-9d892e39-e24c-4d3b-a7f4-25dda5af9a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790965239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1790965239
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.834720614
Short name T730
Test name
Test status
Simulation time 577365188 ps
CPU time 12.42 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:44:34 PM PDT 24
Peak memory 210752 kb
Host smart-2c338cec-0bb6-4c2d-869a-a4bf339a203d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834720614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.834720614
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2941176105
Short name T818
Test name
Test status
Simulation time 6878567638 ps
CPU time 23.99 seconds
Started Mar 28 12:44:13 PM PDT 24
Finished Mar 28 12:44:37 PM PDT 24
Peak memory 218632 kb
Host smart-1ba7bcdb-6d70-4b07-b215-bb569a70b980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941176105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2941176105
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4123883495
Short name T709
Test name
Test status
Simulation time 1906823747 ps
CPU time 25.94 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:48 PM PDT 24
Peak memory 218420 kb
Host smart-0acbd84c-eaa8-4a1e-b425-779d47b582d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123883495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4123883495
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2157691536
Short name T67
Test name
Test status
Simulation time 29111970301 ps
CPU time 173.01 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:53:16 PM PDT 24
Peak memory 213824 kb
Host smart-21a52878-b638-453d-be4c-8f75fcdc2d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157691536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2157691536
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3672986357
Short name T132
Test name
Test status
Simulation time 4107782994 ps
CPU time 176.76 seconds
Started Mar 28 12:44:19 PM PDT 24
Finished Mar 28 12:47:16 PM PDT 24
Peak memory 214384 kb
Host smart-761c924c-8df5-4a6d-833e-49605a8bb1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672986357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3672986357
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2522126642
Short name T701
Test name
Test status
Simulation time 3439308308 ps
CPU time 13.57 seconds
Started Mar 28 12:50:29 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 214048 kb
Host smart-2d49c862-4f2b-4a12-8dd5-288640bb7bfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522126642 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2522126642
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2683275922
Short name T875
Test name
Test status
Simulation time 15275014306 ps
CPU time 30.51 seconds
Started Mar 28 12:44:19 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 217308 kb
Host smart-2f058eed-bb06-46fc-b7f8-1eaee6533678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683275922 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2683275922
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1948900861
Short name T746
Test name
Test status
Simulation time 10311016146 ps
CPU time 26.82 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 211508 kb
Host smart-49f2836f-3261-4344-ad25-7328fdf17da7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948900861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1948900861
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3847457674
Short name T74
Test name
Test status
Simulation time 3784562794 ps
CPU time 19.52 seconds
Started Mar 28 12:44:20 PM PDT 24
Finished Mar 28 12:44:40 PM PDT 24
Peak memory 211676 kb
Host smart-0570aa1f-79ce-472a-904c-df2b975ed646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847457674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3847457674
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2135624546
Short name T769
Test name
Test status
Simulation time 23579125110 ps
CPU time 191.74 seconds
Started Mar 28 12:44:22 PM PDT 24
Finished Mar 28 12:47:34 PM PDT 24
Peak memory 215128 kb
Host smart-27d9008d-5795-415d-a653-2b2d7ade1a96
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135624546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2135624546
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3215750631
Short name T93
Test name
Test status
Simulation time 14778800423 ps
CPU time 66.37 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:51:29 PM PDT 24
Peak memory 214128 kb
Host smart-f68db53c-27da-48ef-9941-d3df325f8535
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215750631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3215750631
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1357741863
Short name T727
Test name
Test status
Simulation time 987114248 ps
CPU time 14.36 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 210892 kb
Host smart-6f5a5f02-9fc7-437c-8875-fef0cb124a0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357741863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1357741863
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3380480262
Short name T817
Test name
Test status
Simulation time 5667930742 ps
CPU time 24.95 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:40 PM PDT 24
Peak memory 211704 kb
Host smart-9475bca5-b321-4ad5-b3ad-c1a52becd165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380480262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3380480262
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.342373294
Short name T905
Test name
Test status
Simulation time 9145458166 ps
CPU time 26.93 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:51 PM PDT 24
Peak memory 218116 kb
Host smart-27b2c5f4-73f1-4544-8b45-9935d3a83c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342373294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.342373294
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4081227037
Short name T787
Test name
Test status
Simulation time 6109774875 ps
CPU time 21.84 seconds
Started Mar 28 12:44:17 PM PDT 24
Finished Mar 28 12:44:39 PM PDT 24
Peak memory 217512 kb
Host smart-bf49ce88-43f5-456c-8ca1-16d605aadff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081227037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4081227037
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.637456656
Short name T795
Test name
Test status
Simulation time 9487593435 ps
CPU time 101.93 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:52:04 PM PDT 24
Peak memory 213124 kb
Host smart-35c192fc-e07f-4bba-a6b4-3f271ecbfca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637456656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.637456656
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2684064585
Short name T687
Test name
Test status
Simulation time 17814103134 ps
CPU time 33.19 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:57 PM PDT 24
Peak memory 217628 kb
Host smart-f5aca636-d9b3-4ec5-94ab-c02b28d5474d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684064585 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2684064585
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3968020992
Short name T778
Test name
Test status
Simulation time 3541146104 ps
CPU time 27.92 seconds
Started Mar 28 12:44:19 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 216656 kb
Host smart-79c7d24c-48d4-4c5a-b564-ad8764acc5db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968020992 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3968020992
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3929590050
Short name T881
Test name
Test status
Simulation time 8894798428 ps
CPU time 21.53 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:44:44 PM PDT 24
Peak memory 212016 kb
Host smart-edc5d196-708e-4b77-8a01-fb3210d576af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929590050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3929590050
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4265468510
Short name T806
Test name
Test status
Simulation time 3161292902 ps
CPU time 17.98 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:40 PM PDT 24
Peak memory 211416 kb
Host smart-8f4cd2db-273b-40cc-9a81-7b0caacd3359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265468510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4265468510
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2735691145
Short name T872
Test name
Test status
Simulation time 30798037420 ps
CPU time 129.29 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:52:31 PM PDT 24
Peak memory 214952 kb
Host smart-d198a640-203e-4606-9a91-7a84379da838
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735691145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2735691145
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3901236500
Short name T842
Test name
Test status
Simulation time 2117084377 ps
CPU time 51.36 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:45:07 PM PDT 24
Peak memory 212992 kb
Host smart-b92ad13f-7fde-4bfc-ae5b-35ed50b7bef9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901236500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3901236500
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1217159667
Short name T784
Test name
Test status
Simulation time 12798604030 ps
CPU time 27.21 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 212036 kb
Host smart-6d85dbf6-f539-48fb-812d-328f0b7b3393
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217159667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1217159667
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3519005330
Short name T796
Test name
Test status
Simulation time 19054178349 ps
CPU time 30.65 seconds
Started Mar 28 12:44:17 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 212212 kb
Host smart-5dfbadc4-dae8-46d7-8326-7819b657b977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519005330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3519005330
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2764880560
Short name T884
Test name
Test status
Simulation time 167305720 ps
CPU time 13.03 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 218240 kb
Host smart-381be6e3-1dbe-42d1-8d35-0112b62db3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764880560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2764880560
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.745372520
Short name T691
Test name
Test status
Simulation time 33558782820 ps
CPU time 32.52 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 218604 kb
Host smart-6c363f06-d7ff-4121-9bdf-67d42abd8a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745372520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.745372520
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2931195991
Short name T135
Test name
Test status
Simulation time 2498333288 ps
CPU time 165.84 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 214684 kb
Host smart-c5ff376b-27f0-4984-ba76-e6b32c93c853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931195991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2931195991
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3340418732
Short name T901
Test name
Test status
Simulation time 40138269437 ps
CPU time 104.22 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:46:01 PM PDT 24
Peak memory 213148 kb
Host smart-b71b24a5-26e8-4d53-9560-b57a872ba479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340418732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3340418732
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3231168433
Short name T835
Test name
Test status
Simulation time 198303768 ps
CPU time 9.48 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:44:31 PM PDT 24
Peak memory 217184 kb
Host smart-ab66fd37-8a78-49f3-b615-fd49eb923b12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231168433 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3231168433
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3716243630
Short name T764
Test name
Test status
Simulation time 7022806959 ps
CPU time 28.57 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:51 PM PDT 24
Peak memory 216268 kb
Host smart-c862be19-41cc-4594-8051-bb84bb8e11e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716243630 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3716243630
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.691016882
Short name T837
Test name
Test status
Simulation time 3101566957 ps
CPU time 27.71 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 211200 kb
Host smart-f04e2072-44c2-4414-9f76-37c1016c9190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691016882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.691016882
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.789833480
Short name T833
Test name
Test status
Simulation time 167419099 ps
CPU time 8.14 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:44:22 PM PDT 24
Peak memory 210928 kb
Host smart-d1c713f0-8ffb-439a-9cc0-4eeab48d2df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789833480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.789833480
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.348055841
Short name T803
Test name
Test status
Simulation time 35690724651 ps
CPU time 180.43 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:47:15 PM PDT 24
Peak memory 214100 kb
Host smart-8e6e9e61-f026-4a38-afdf-ab7b3506ace3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348055841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.348055841
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4046262747
Short name T105
Test name
Test status
Simulation time 12833461847 ps
CPU time 136.25 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 215452 kb
Host smart-473d528c-0e18-49a4-983e-7d2e2e75d844
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046262747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4046262747
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3476687365
Short name T756
Test name
Test status
Simulation time 3550937467 ps
CPU time 14.1 seconds
Started Mar 28 12:44:17 PM PDT 24
Finished Mar 28 12:44:31 PM PDT 24
Peak memory 210856 kb
Host smart-90da5da6-aa51-4fb0-a46a-8b457d14cd2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476687365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3476687365
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3583307621
Short name T836
Test name
Test status
Simulation time 6133722871 ps
CPU time 26.64 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 212156 kb
Host smart-afdaba5a-701c-4cf0-b6b0-761537410103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583307621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3583307621
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1295845769
Short name T774
Test name
Test status
Simulation time 655559380 ps
CPU time 16.82 seconds
Started Mar 28 12:44:18 PM PDT 24
Finished Mar 28 12:44:35 PM PDT 24
Peak memory 217044 kb
Host smart-d6f352d2-b132-4694-9184-48937a8d6400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295845769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1295845769
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4284905900
Short name T697
Test name
Test status
Simulation time 658291752 ps
CPU time 15.96 seconds
Started Mar 28 12:50:20 PM PDT 24
Finished Mar 28 12:50:37 PM PDT 24
Peak memory 218020 kb
Host smart-2582e63c-9003-45a4-b12f-0767e9dd918f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284905900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4284905900
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2801623976
Short name T130
Test name
Test status
Simulation time 810834181 ps
CPU time 167.1 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:53:09 PM PDT 24
Peak memory 214792 kb
Host smart-5b762865-52d6-4f63-8314-3303be02a44b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801623976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2801623976
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.257942165
Short name T865
Test name
Test status
Simulation time 376178011 ps
CPU time 10.44 seconds
Started Mar 28 12:44:22 PM PDT 24
Finished Mar 28 12:44:33 PM PDT 24
Peak memory 217336 kb
Host smart-4b6ae091-a4d2-464e-9f01-50dc833274b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257942165 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.257942165
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4113117241
Short name T736
Test name
Test status
Simulation time 683476625 ps
CPU time 11.26 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 216256 kb
Host smart-6e641f06-010a-4010-83b2-c0269e4055d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113117241 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4113117241
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2136059261
Short name T886
Test name
Test status
Simulation time 4432704627 ps
CPU time 15.38 seconds
Started Mar 28 12:50:21 PM PDT 24
Finished Mar 28 12:50:38 PM PDT 24
Peak memory 210960 kb
Host smart-bf2efbd0-20e7-4758-bc25-d2be7a36bfd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136059261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2136059261
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3421522223
Short name T72
Test name
Test status
Simulation time 2557782721 ps
CPU time 23.29 seconds
Started Mar 28 12:44:28 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 211544 kb
Host smart-f6842728-dabc-4827-985f-98e58b44c81f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421522223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3421522223
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1936044047
Short name T782
Test name
Test status
Simulation time 8564397948 ps
CPU time 37.86 seconds
Started Mar 28 12:44:20 PM PDT 24
Finished Mar 28 12:44:58 PM PDT 24
Peak memory 213972 kb
Host smart-0ae8a1fd-48fa-4602-ba1c-0dc9cb5968f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936044047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1936044047
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.442051901
Short name T882
Test name
Test status
Simulation time 22721141827 ps
CPU time 75.42 seconds
Started Mar 28 12:50:19 PM PDT 24
Finished Mar 28 12:51:34 PM PDT 24
Peak memory 215124 kb
Host smart-c673f99d-2077-4c1b-859a-e149e1fa6460
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442051901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.442051901
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3129809771
Short name T120
Test name
Test status
Simulation time 338337175 ps
CPU time 8.31 seconds
Started Mar 28 12:50:23 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 210928 kb
Host smart-165900ff-4bdf-432c-a2e7-a11c8734fb2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129809771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3129809771
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3202771442
Short name T117
Test name
Test status
Simulation time 13882564066 ps
CPU time 25.88 seconds
Started Mar 28 12:44:19 PM PDT 24
Finished Mar 28 12:44:45 PM PDT 24
Peak memory 212316 kb
Host smart-ad83239d-23e9-4b2e-951c-fc365c38bd11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202771442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3202771442
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4021242079
Short name T864
Test name
Test status
Simulation time 2355044459 ps
CPU time 13.09 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:37 PM PDT 24
Peak memory 217012 kb
Host smart-ce60ebd0-16ef-42a6-8d93-0439cae44942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021242079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4021242079
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.818355666
Short name T856
Test name
Test status
Simulation time 2204025279 ps
CPU time 26.74 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:42 PM PDT 24
Peak memory 216996 kb
Host smart-db177a45-6f6d-4212-93de-8e484cb53e07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818355666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.818355666
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4001208788
Short name T780
Test name
Test status
Simulation time 4248748910 ps
CPU time 88.62 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:51:52 PM PDT 24
Peak memory 212948 kb
Host smart-55561019-06e1-43f1-a8b5-f86824e48283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001208788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4001208788
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.513357190
Short name T143
Test name
Test status
Simulation time 12780810641 ps
CPU time 161.9 seconds
Started Mar 28 12:44:19 PM PDT 24
Finished Mar 28 12:47:01 PM PDT 24
Peak memory 213588 kb
Host smart-c444b9f5-6c1b-4886-a9ba-3be3c398c93d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513357190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.513357190
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3668512467
Short name T868
Test name
Test status
Simulation time 2022966917 ps
CPU time 12.15 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:28 PM PDT 24
Peak memory 215948 kb
Host smart-a2c7ae7b-0227-4acb-b397-d3aab99eb69a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668512467 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3668512467
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4028760869
Short name T703
Test name
Test status
Simulation time 12538527405 ps
CPU time 26.86 seconds
Started Mar 28 12:50:22 PM PDT 24
Finished Mar 28 12:50:50 PM PDT 24
Peak memory 217512 kb
Host smart-9f4f0a35-3f23-49c9-af1e-9e675476a5d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028760869 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4028760869
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3005613552
Short name T124
Test name
Test status
Simulation time 2472835966 ps
CPU time 22.79 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:49 PM PDT 24
Peak memory 211444 kb
Host smart-3621aab8-f5b1-4446-983d-32ced16364cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005613552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3005613552
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3270459774
Short name T693
Test name
Test status
Simulation time 1683172292 ps
CPU time 13.75 seconds
Started Mar 28 12:44:26 PM PDT 24
Finished Mar 28 12:44:40 PM PDT 24
Peak memory 210884 kb
Host smart-bde4acc8-42b1-479c-96fb-c18d981fb430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270459774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3270459774
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2729366615
Short name T92
Test name
Test status
Simulation time 10339700418 ps
CPU time 66.95 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:45:29 PM PDT 24
Peak memory 213924 kb
Host smart-d822d007-4992-4bb7-af3c-ad57832c525d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729366615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2729366615
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1917364810
Short name T911
Test name
Test status
Simulation time 3848095042 ps
CPU time 30.32 seconds
Started Mar 28 12:50:25 PM PDT 24
Finished Mar 28 12:50:55 PM PDT 24
Peak memory 211916 kb
Host smart-099e5b98-27d1-4481-ac87-771ce9185577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917364810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1917364810
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3234755800
Short name T827
Test name
Test status
Simulation time 13365152232 ps
CPU time 28.3 seconds
Started Mar 28 12:44:20 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 212168 kb
Host smart-283f5bf0-0fe5-46b7-9cba-9248f3e35013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234755800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3234755800
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1566376065
Short name T907
Test name
Test status
Simulation time 661400094 ps
CPU time 13.35 seconds
Started Mar 28 12:44:20 PM PDT 24
Finished Mar 28 12:44:34 PM PDT 24
Peak memory 217260 kb
Host smart-dee43542-e593-4093-a292-1f8b1346333c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566376065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1566376065
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4031431226
Short name T705
Test name
Test status
Simulation time 4936709890 ps
CPU time 33.25 seconds
Started Mar 28 12:50:24 PM PDT 24
Finished Mar 28 12:50:57 PM PDT 24
Peak memory 218496 kb
Host smart-f6d7c644-9f9b-4c37-9aa7-e39ed975456d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031431226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4031431226
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1527142985
Short name T131
Test name
Test status
Simulation time 14376418554 ps
CPU time 166.17 seconds
Started Mar 28 12:44:25 PM PDT 24
Finished Mar 28 12:47:11 PM PDT 24
Peak memory 213880 kb
Host smart-5251b51d-b240-4d11-b61f-df5852428459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527142985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1527142985
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3882135263
Short name T903
Test name
Test status
Simulation time 22122233882 ps
CPU time 99.21 seconds
Started Mar 28 12:50:26 PM PDT 24
Finished Mar 28 12:52:06 PM PDT 24
Peak memory 214324 kb
Host smart-492957f2-b31c-40d6-884d-702c210c852a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882135263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3882135263
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1076191190
Short name T101
Test name
Test status
Simulation time 8919064070 ps
CPU time 21.04 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:18 PM PDT 24
Peak memory 211364 kb
Host smart-bb37a62c-b3fa-4f82-95ee-b15a49f7b107
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076191190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1076191190
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1651421549
Short name T748
Test name
Test status
Simulation time 7386602038 ps
CPU time 18.65 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 211900 kb
Host smart-512df1b2-b948-4267-a01f-16a6d15ddad8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651421549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1651421549
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.363360892
Short name T715
Test name
Test status
Simulation time 16460199649 ps
CPU time 14.78 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:23 PM PDT 24
Peak memory 210864 kb
Host smart-7937e801-893a-4350-9b32-386172ff09ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363360892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.363360892
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.965215690
Short name T750
Test name
Test status
Simulation time 1077074842 ps
CPU time 15.3 seconds
Started Mar 28 12:43:51 PM PDT 24
Finished Mar 28 12:44:07 PM PDT 24
Peak memory 210864 kb
Host smart-5b4c91f3-436d-411a-aef2-e13c6cfa1dc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965215690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.965215690
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2406318749
Short name T123
Test name
Test status
Simulation time 8057628207 ps
CPU time 35.61 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:44 PM PDT 24
Peak memory 211508 kb
Host smart-275b4c81-0a28-4d66-8228-73f997aa4209
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406318749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2406318749
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3888654144
Short name T789
Test name
Test status
Simulation time 13762734421 ps
CPU time 35.36 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:31 PM PDT 24
Peak memory 211648 kb
Host smart-28ef4b3b-b379-48aa-a56e-d650ecfc213d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888654144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3888654144
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1065222807
Short name T704
Test name
Test status
Simulation time 8519669277 ps
CPU time 33.3 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:29 PM PDT 24
Peak memory 216880 kb
Host smart-1ec0fc44-1830-4165-a109-8411314d35ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065222807 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1065222807
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3554538114
Short name T807
Test name
Test status
Simulation time 8339472026 ps
CPU time 33.48 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:39 PM PDT 24
Peak memory 215752 kb
Host smart-df1b2547-4a9b-42aa-acb7-df3848b566fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554538114 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3554538114
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1568712979
Short name T104
Test name
Test status
Simulation time 521224024 ps
CPU time 11.78 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:19 PM PDT 24
Peak memory 210840 kb
Host smart-ae1bfc2e-888c-467e-b65d-7edc3cbfd8a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568712979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1568712979
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.288427892
Short name T914
Test name
Test status
Simulation time 2162485463 ps
CPU time 13.64 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:44:15 PM PDT 24
Peak memory 210928 kb
Host smart-24bb808e-53bd-424a-90db-9d37395bbe52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288427892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.288427892
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1592356713
Short name T788
Test name
Test status
Simulation time 345559974 ps
CPU time 8.19 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:05 PM PDT 24
Peak memory 210792 kb
Host smart-89e9a749-bbbf-42fd-8aed-6e32a39ced47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592356713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1592356713
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3294697905
Short name T786
Test name
Test status
Simulation time 1735846167 ps
CPU time 18.48 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:24 PM PDT 24
Peak memory 210648 kb
Host smart-ee2ec8e8-e606-4659-a0a0-5ad9f0f94d1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294697905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3294697905
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.212822575
Short name T696
Test name
Test status
Simulation time 9185800463 ps
CPU time 21.44 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:29 PM PDT 24
Peak memory 210788 kb
Host smart-40139670-5cfa-4897-a819-a837672a2caf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212822575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
212822575
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2916187788
Short name T900
Test name
Test status
Simulation time 6367088044 ps
CPU time 18.69 seconds
Started Mar 28 12:43:55 PM PDT 24
Finished Mar 28 12:44:14 PM PDT 24
Peak memory 210836 kb
Host smart-d8811e12-698f-49c8-9149-c3cad182287a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916187788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2916187788
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2015178702
Short name T845
Test name
Test status
Simulation time 10494238385 ps
CPU time 99.21 seconds
Started Mar 28 12:43:52 PM PDT 24
Finished Mar 28 12:45:32 PM PDT 24
Peak memory 214196 kb
Host smart-567d732e-ffd1-4c6f-8928-bcbe2b2c716d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015178702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2015178702
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.580734465
Short name T863
Test name
Test status
Simulation time 86239253608 ps
CPU time 145.27 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:52:32 PM PDT 24
Peak memory 215380 kb
Host smart-eb47e43b-949e-46c5-9b0f-07c325761254
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580734465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.580734465
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2652225444
Short name T828
Test name
Test status
Simulation time 37284098120 ps
CPU time 24.73 seconds
Started Mar 28 12:50:03 PM PDT 24
Finished Mar 28 12:50:28 PM PDT 24
Peak memory 212292 kb
Host smart-e34130cf-734f-4664-ad4e-b6ac7c5bfafe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652225444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2652225444
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3098993436
Short name T84
Test name
Test status
Simulation time 4919337123 ps
CPU time 26.6 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:23 PM PDT 24
Peak memory 212192 kb
Host smart-70e4e14d-b671-4175-8b2e-211a5ed05f7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098993436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3098993436
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1141415627
Short name T700
Test name
Test status
Simulation time 689636882 ps
CPU time 13.37 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:10 PM PDT 24
Peak memory 217412 kb
Host smart-3717e60f-7a6f-4fe0-86f2-40686bfcf3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141415627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1141415627
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1166543439
Short name T805
Test name
Test status
Simulation time 31412315941 ps
CPU time 36.04 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:43 PM PDT 24
Peak memory 216960 kb
Host smart-cbff99a4-e78e-4038-b209-359190981cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166543439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1166543439
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2585300515
Short name T763
Test name
Test status
Simulation time 16946267349 ps
CPU time 105.3 seconds
Started Mar 28 12:43:55 PM PDT 24
Finished Mar 28 12:45:41 PM PDT 24
Peak memory 213560 kb
Host smart-9f5df5a8-7776-44ee-9193-c1feb632d3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585300515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2585300515
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.549594834
Short name T69
Test name
Test status
Simulation time 1314970998 ps
CPU time 151.87 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:52:41 PM PDT 24
Peak memory 213436 kb
Host smart-7775886c-107b-494f-bc7d-19e614bddd53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549594834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.549594834
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3125129554
Short name T812
Test name
Test status
Simulation time 688645250 ps
CPU time 8.26 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:14 PM PDT 24
Peak memory 210752 kb
Host smart-1fbf476c-4376-4614-8f67-272ad0103a74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125129554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3125129554
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.724045402
Short name T892
Test name
Test status
Simulation time 1801009979 ps
CPU time 19.5 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:15 PM PDT 24
Peak memory 211012 kb
Host smart-99d97ebe-1a1e-4da5-bb4d-db3d2dc243d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724045402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.724045402
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1260697832
Short name T851
Test name
Test status
Simulation time 2264208682 ps
CPU time 21.63 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:44:20 PM PDT 24
Peak memory 210992 kb
Host smart-fcf713a9-cd21-4149-9776-ba4f34206cf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260697832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1260697832
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1310794931
Short name T735
Test name
Test status
Simulation time 3298910155 ps
CPU time 8.44 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:15 PM PDT 24
Peak memory 210824 kb
Host smart-2ae2a2b9-0e9c-4a76-9e90-0195f1b48dfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310794931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1310794931
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1492578696
Short name T758
Test name
Test status
Simulation time 1013007266 ps
CPU time 18.91 seconds
Started Mar 28 12:43:50 PM PDT 24
Finished Mar 28 12:44:09 PM PDT 24
Peak memory 211508 kb
Host smart-11ac70d4-79e7-4215-9fea-b5101572639a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492578696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1492578696
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2392532573
Short name T873
Test name
Test status
Simulation time 173980788 ps
CPU time 15.19 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:23 PM PDT 24
Peak memory 211500 kb
Host smart-243e3031-de06-4466-af72-95b728d8183e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392532573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2392532573
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1536142610
Short name T707
Test name
Test status
Simulation time 777090538 ps
CPU time 9.4 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:06 PM PDT 24
Peak memory 216164 kb
Host smart-6c0625b1-5b48-4246-8338-9a958c3f8240
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536142610 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1536142610
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.428091167
Short name T711
Test name
Test status
Simulation time 6785595690 ps
CPU time 15.92 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:23 PM PDT 24
Peak memory 216756 kb
Host smart-3820d8c1-bfc0-4a7f-8b78-2b3ce30ea8d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428091167 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.428091167
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2113218713
Short name T840
Test name
Test status
Simulation time 2306925353 ps
CPU time 21.96 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 210984 kb
Host smart-74a7fd20-a8fd-4c07-a212-f5c3ea8b6a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113218713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2113218713
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3403579729
Short name T893
Test name
Test status
Simulation time 1372799223 ps
CPU time 8.17 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:44:07 PM PDT 24
Peak memory 210900 kb
Host smart-340d5c20-d5d1-414e-9b4c-274e28347a83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403579729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3403579729
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2429909293
Short name T852
Test name
Test status
Simulation time 9208087708 ps
CPU time 22.16 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 210860 kb
Host smart-847da50d-a131-4e8d-b480-096a70c9a1f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429909293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2429909293
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.394263105
Short name T847
Test name
Test status
Simulation time 2204541079 ps
CPU time 20.71 seconds
Started Mar 28 12:43:51 PM PDT 24
Finished Mar 28 12:44:12 PM PDT 24
Peak memory 210860 kb
Host smart-3a13caf3-2a09-4880-9478-df8f53ab66a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394263105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.394263105
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2738448974
Short name T759
Test name
Test status
Simulation time 851788199 ps
CPU time 13.85 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:44:15 PM PDT 24
Peak memory 210700 kb
Host smart-ce1d0f2b-3b87-4172-862b-b353cdccdb13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738448974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2738448974
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2926252004
Short name T781
Test name
Test status
Simulation time 4089185561 ps
CPU time 20.68 seconds
Started Mar 28 12:50:01 PM PDT 24
Finished Mar 28 12:50:22 PM PDT 24
Peak memory 210944 kb
Host smart-a57b7028-9c6a-45d5-a82e-cc5eb6b08a6a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926252004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2926252004
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.136667041
Short name T792
Test name
Test status
Simulation time 13788468242 ps
CPU time 39.22 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:35 PM PDT 24
Peak memory 214080 kb
Host smart-37062ae3-3336-4665-9e06-8ac5b0bd2b75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136667041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.136667041
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1798058769
Short name T754
Test name
Test status
Simulation time 31443792646 ps
CPU time 83.5 seconds
Started Mar 28 12:50:00 PM PDT 24
Finished Mar 28 12:51:24 PM PDT 24
Peak memory 215144 kb
Host smart-d1e58987-3c1f-4d12-8996-1ad57d7c3867
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798058769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1798058769
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1427019472
Short name T722
Test name
Test status
Simulation time 26106493305 ps
CPU time 37.19 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:47 PM PDT 24
Peak memory 212328 kb
Host smart-a913c506-ad2f-4870-84c0-f8e0c61b3aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427019472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1427019472
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3317192019
Short name T906
Test name
Test status
Simulation time 8891954743 ps
CPU time 33.6 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:44:32 PM PDT 24
Peak memory 212060 kb
Host smart-36acfa3d-8493-4c92-ae17-773c9ee3eb21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317192019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3317192019
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.46799884
Short name T838
Test name
Test status
Simulation time 8888092308 ps
CPU time 25.7 seconds
Started Mar 28 12:43:58 PM PDT 24
Finished Mar 28 12:44:24 PM PDT 24
Peak memory 217108 kb
Host smart-184d8a3a-b7c0-4fa5-9dfa-d77b0aa8f376
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46799884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.46799884
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.505697176
Short name T779
Test name
Test status
Simulation time 6473177873 ps
CPU time 24.13 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 217188 kb
Host smart-ab42af2b-a449-45dc-9eef-3032913892a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505697176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.505697176
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3847227537
Short name T136
Test name
Test status
Simulation time 3816036087 ps
CPU time 91.72 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:51:40 PM PDT 24
Peak memory 213200 kb
Host smart-195c1a5a-5b31-4855-9abb-4944e86173bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847227537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3847227537
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.417039887
Short name T68
Test name
Test status
Simulation time 2699552306 ps
CPU time 94.22 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:45:31 PM PDT 24
Peak memory 213288 kb
Host smart-1a64c330-322a-456b-bff6-9d550c9a6ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417039887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.417039887
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1570347710
Short name T708
Test name
Test status
Simulation time 31991284485 ps
CPU time 26.04 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:24 PM PDT 24
Peak memory 211892 kb
Host smart-431e3886-8636-4bb0-b12a-3103818187e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570347710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1570347710
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3855521666
Short name T834
Test name
Test status
Simulation time 4505259635 ps
CPU time 25.41 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 211388 kb
Host smart-3c3d3d1e-7ab4-4838-b747-452d99a47883
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855521666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3855521666
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1327863191
Short name T878
Test name
Test status
Simulation time 660660128 ps
CPU time 8.43 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:05 PM PDT 24
Peak memory 210772 kb
Host smart-c7747d24-ef58-4c82-86ff-253808f5021f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327863191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1327863191
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4284394914
Short name T899
Test name
Test status
Simulation time 1974669085 ps
CPU time 15.83 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:24 PM PDT 24
Peak memory 210836 kb
Host smart-1dbf0e90-fba2-4877-a523-ed3c78f072fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284394914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4284394914
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2252160715
Short name T874
Test name
Test status
Simulation time 14958332377 ps
CPU time 30.59 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:44:29 PM PDT 24
Peak memory 211908 kb
Host smart-42e65bc8-9d3e-4161-9f8f-7a548d967cd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252160715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2252160715
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.42061978
Short name T757
Test name
Test status
Simulation time 16742527707 ps
CPU time 35.36 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:44 PM PDT 24
Peak memory 211316 kb
Host smart-9f9854ed-9f45-4288-8c62-8cb33f4405fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42061978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_res
et.42061978
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1108223553
Short name T690
Test name
Test status
Simulation time 357457668 ps
CPU time 9.85 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:17 PM PDT 24
Peak memory 217308 kb
Host smart-e6ee58da-bee1-4f36-8a7d-e0e1b1ea6714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108223553 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1108223553
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3190447775
Short name T793
Test name
Test status
Simulation time 11041720875 ps
CPU time 23.62 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:21 PM PDT 24
Peak memory 217924 kb
Host smart-21d3a1ff-6609-4031-a14a-fb4de4e3548b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190447775 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3190447775
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1556071630
Short name T720
Test name
Test status
Simulation time 4346241050 ps
CPU time 31.92 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 212016 kb
Host smart-428bd57b-b549-407e-a702-368040b41ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556071630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1556071630
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4250942721
Short name T91
Test name
Test status
Simulation time 4936411179 ps
CPU time 15.4 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:13 PM PDT 24
Peak memory 211244 kb
Host smart-c001e66c-6ea3-4749-9493-7ea32b4c6284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250942721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4250942721
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.324189144
Short name T724
Test name
Test status
Simulation time 5520111674 ps
CPU time 23.75 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:32 PM PDT 24
Peak memory 210716 kb
Host smart-3f74c0c5-eabb-4b5b-81ad-9d0b22472269
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324189144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.324189144
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.698701493
Short name T767
Test name
Test status
Simulation time 272759659 ps
CPU time 8.31 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:44:07 PM PDT 24
Peak memory 210764 kb
Host smart-7b9a1782-a10a-47be-88d6-2173666d3e21
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698701493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.698701493
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2458845067
Short name T825
Test name
Test status
Simulation time 170740720 ps
CPU time 8.27 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:13 PM PDT 24
Peak memory 210840 kb
Host smart-81fdd872-2252-4e14-9c18-be6e3f8acdfc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458845067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2458845067
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3485134628
Short name T760
Test name
Test status
Simulation time 752098761 ps
CPU time 8.02 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:44:07 PM PDT 24
Peak memory 209672 kb
Host smart-066ba193-b4ee-4136-9a19-95cea5fbdf6b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485134628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3485134628
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1077415834
Short name T891
Test name
Test status
Simulation time 4143520005 ps
CPU time 57.33 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:51:05 PM PDT 24
Peak memory 213996 kb
Host smart-cdc6712a-ad31-402c-9066-4967dfd146a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077415834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1077415834
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3543606154
Short name T747
Test name
Test status
Simulation time 4800586812 ps
CPU time 20.06 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:50:26 PM PDT 24
Peak memory 212356 kb
Host smart-f682a685-8b4f-43d7-8b32-bb22df2f3763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543606154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3543606154
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3920568075
Short name T726
Test name
Test status
Simulation time 3985080915 ps
CPU time 31.6 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:29 PM PDT 24
Peak memory 212076 kb
Host smart-6508e76a-1af3-462f-a84d-fbad09c0a1f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920568075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3920568075
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1044640631
Short name T695
Test name
Test status
Simulation time 661860130 ps
CPU time 12.38 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:19 PM PDT 24
Peak memory 217012 kb
Host smart-0a84496c-f412-443b-87c2-4afce0f738af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044640631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1044640631
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3232498544
Short name T850
Test name
Test status
Simulation time 11178172367 ps
CPU time 29.55 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:27 PM PDT 24
Peak memory 218300 kb
Host smart-b0b29f64-ed73-4870-abe1-d8c34d7da7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232498544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3232498544
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3281207453
Short name T776
Test name
Test status
Simulation time 2544912088 ps
CPU time 94.95 seconds
Started Mar 28 12:43:59 PM PDT 24
Finished Mar 28 12:45:34 PM PDT 24
Peak memory 213376 kb
Host smart-b4c4efe3-e00e-47b4-8e05-e761cbfa6e78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281207453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3281207453
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3396568139
Short name T142
Test name
Test status
Simulation time 15972186293 ps
CPU time 102.51 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:51:49 PM PDT 24
Peak memory 213628 kb
Host smart-2a67ecc5-0a35-42e6-9db9-d71dd7633b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396568139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3396568139
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1726346372
Short name T755
Test name
Test status
Simulation time 8871643003 ps
CPU time 21.43 seconds
Started Mar 28 12:50:04 PM PDT 24
Finished Mar 28 12:50:26 PM PDT 24
Peak memory 215200 kb
Host smart-f4e7da47-c09d-419a-9b41-8ffe6ebf2aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726346372 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1726346372
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.313307268
Short name T688
Test name
Test status
Simulation time 721313870 ps
CPU time 8.88 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:44:11 PM PDT 24
Peak memory 215324 kb
Host smart-a2f2ff3c-6f29-43ef-a550-7061dee863ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313307268 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.313307268
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3721714576
Short name T80
Test name
Test status
Simulation time 4257415251 ps
CPU time 15.16 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:44:17 PM PDT 24
Peak memory 210536 kb
Host smart-62a409d2-8d8a-4e93-9af7-ad6d790e4be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721714576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3721714576
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3790989018
Short name T869
Test name
Test status
Simulation time 1541875246 ps
CPU time 17.85 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:26 PM PDT 24
Peak memory 211248 kb
Host smart-cccc3ad9-1aa1-4244-acce-5ab00cdb0ef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790989018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3790989018
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.265694580
Short name T85
Test name
Test status
Simulation time 1071930133 ps
CPU time 57.34 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:51:05 PM PDT 24
Peak memory 214008 kb
Host smart-eca5e95a-775e-483a-819b-a31ea748e320
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265694580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.265694580
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4207594353
Short name T102
Test name
Test status
Simulation time 100307281361 ps
CPU time 200.18 seconds
Started Mar 28 12:44:00 PM PDT 24
Finished Mar 28 12:47:20 PM PDT 24
Peak memory 214664 kb
Host smart-94bae950-0f05-4e7c-91b3-b4a563dd5002
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207594353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4207594353
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2903643047
Short name T121
Test name
Test status
Simulation time 8875108430 ps
CPU time 21.66 seconds
Started Mar 28 12:44:06 PM PDT 24
Finished Mar 28 12:44:28 PM PDT 24
Peak memory 212312 kb
Host smart-ad6178a6-c9c9-428d-84db-1502b6fd5253
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903643047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2903643047
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.529865297
Short name T751
Test name
Test status
Simulation time 13152652820 ps
CPU time 27.52 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 212296 kb
Host smart-c0209b67-ff40-40ec-8a57-d503a7bf1d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529865297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.529865297
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2719551403
Short name T765
Test name
Test status
Simulation time 576937450 ps
CPU time 17.29 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:24 PM PDT 24
Peak memory 217028 kb
Host smart-e182a508-5db1-4f92-ad84-142ba0db254b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719551403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2719551403
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.366920121
Short name T866
Test name
Test status
Simulation time 17135951060 ps
CPU time 33.78 seconds
Started Mar 28 12:44:00 PM PDT 24
Finished Mar 28 12:44:34 PM PDT 24
Peak memory 218420 kb
Host smart-12ff7958-f115-4499-9b80-c560c827c4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366920121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.366920121
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1385555188
Short name T876
Test name
Test status
Simulation time 7905145255 ps
CPU time 172.66 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:53:02 PM PDT 24
Peak memory 213784 kb
Host smart-62776549-3bc2-453e-86ac-6b66f5125221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385555188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1385555188
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3118000447
Short name T861
Test name
Test status
Simulation time 872118000 ps
CPU time 85.94 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:45:23 PM PDT 24
Peak memory 211964 kb
Host smart-70788abe-908c-4417-947a-854c48ae5a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118000447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3118000447
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.140839336
Short name T885
Test name
Test status
Simulation time 178726204 ps
CPU time 8.57 seconds
Started Mar 28 12:50:10 PM PDT 24
Finished Mar 28 12:50:19 PM PDT 24
Peak memory 214264 kb
Host smart-2777e731-b9da-4fc7-ab9e-d4fd033281fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140839336 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.140839336
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4156872753
Short name T734
Test name
Test status
Simulation time 8217173296 ps
CPU time 13.58 seconds
Started Mar 28 12:43:52 PM PDT 24
Finished Mar 28 12:44:06 PM PDT 24
Peak memory 214412 kb
Host smart-ff75cd7d-d068-4974-ac69-7bc943eaa421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156872753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4156872753
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1175441831
Short name T908
Test name
Test status
Simulation time 660306363 ps
CPU time 8.2 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:04 PM PDT 24
Peak memory 210844 kb
Host smart-7a298ce0-e248-4784-bf5a-dce24569d081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175441831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1175441831
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.266305197
Short name T119
Test name
Test status
Simulation time 6846583877 ps
CPU time 27.69 seconds
Started Mar 28 12:50:07 PM PDT 24
Finished Mar 28 12:50:35 PM PDT 24
Peak memory 211820 kb
Host smart-77f18a6c-389a-4f33-a5bd-0c7a545aa951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266305197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.266305197
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1776551088
Short name T768
Test name
Test status
Simulation time 22153127113 ps
CPU time 60.84 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:58 PM PDT 24
Peak memory 212792 kb
Host smart-60f73304-b15e-4646-a6ff-7edcc1e47400
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776551088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1776551088
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.379417591
Short name T97
Test name
Test status
Simulation time 21667279122 ps
CPU time 176.66 seconds
Started Mar 28 12:50:05 PM PDT 24
Finished Mar 28 12:53:02 PM PDT 24
Peak memory 215396 kb
Host smart-eb52db3b-a8c5-4306-b2bd-797ecbc8a8a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379417591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.379417591
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2228542221
Short name T744
Test name
Test status
Simulation time 1613860592 ps
CPU time 18.08 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:16 PM PDT 24
Peak memory 211900 kb
Host smart-6e6d7810-f5ce-4f35-8a0d-511003e499cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228542221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2228542221
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2403493835
Short name T118
Test name
Test status
Simulation time 3472057089 ps
CPU time 19.16 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 211840 kb
Host smart-e264d9cb-c51e-4a97-a28f-672174d9a961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403493835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2403493835
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1570538583
Short name T745
Test name
Test status
Simulation time 8954637083 ps
CPU time 18.5 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:50:25 PM PDT 24
Peak memory 217372 kb
Host smart-a380fcd2-a79f-4f9c-a29e-99afcecd25e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570538583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1570538583
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.932060269
Short name T860
Test name
Test status
Simulation time 216710700 ps
CPU time 12.94 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:10 PM PDT 24
Peak memory 217232 kb
Host smart-f7c0d259-75de-4dcb-90e8-0267d05eb150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932060269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.932060269
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1327243991
Short name T128
Test name
Test status
Simulation time 1149683237 ps
CPU time 83.3 seconds
Started Mar 28 12:44:02 PM PDT 24
Finished Mar 28 12:45:25 PM PDT 24
Peak memory 213152 kb
Host smart-9aadc5f8-e2ca-44ae-93c7-876bb5df7cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327243991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1327243991
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.424051529
Short name T141
Test name
Test status
Simulation time 2165756470 ps
CPU time 85.82 seconds
Started Mar 28 12:50:12 PM PDT 24
Finished Mar 28 12:51:38 PM PDT 24
Peak memory 214072 kb
Host smart-0e59a6d1-b2c3-4a26-93dc-ac1753574e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424051529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.424051529
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1014309061
Short name T826
Test name
Test status
Simulation time 14139412395 ps
CPU time 26.15 seconds
Started Mar 28 12:50:10 PM PDT 24
Finished Mar 28 12:50:36 PM PDT 24
Peak memory 216068 kb
Host smart-5b2fd970-ada3-404b-b656-1967b209d31f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014309061 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1014309061
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2532501503
Short name T839
Test name
Test status
Simulation time 11661533287 ps
CPU time 31.91 seconds
Started Mar 28 12:44:18 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 215876 kb
Host smart-4795ee73-ad30-4a31-8f47-1e3ffd75333b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532501503 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2532501503
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4208980899
Short name T95
Test name
Test status
Simulation time 3186018655 ps
CPU time 26.16 seconds
Started Mar 28 12:50:10 PM PDT 24
Finished Mar 28 12:50:36 PM PDT 24
Peak memory 211424 kb
Host smart-4a9849b6-b7a1-403b-8b8d-aa3d4f25ddf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208980899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4208980899
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.508568403
Short name T94
Test name
Test status
Simulation time 3935631415 ps
CPU time 20.59 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:44:43 PM PDT 24
Peak memory 211440 kb
Host smart-8f2b0fb6-21b6-4c21-85f6-0a4441809399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508568403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.508568403
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1864012407
Short name T822
Test name
Test status
Simulation time 11425160336 ps
CPU time 107.51 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:51:56 PM PDT 24
Peak memory 214000 kb
Host smart-d1a2eb35-7486-4a83-83bf-281009386cc8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864012407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1864012407
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4088180391
Short name T798
Test name
Test status
Simulation time 17992679343 ps
CPU time 152.01 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:46:29 PM PDT 24
Peak memory 215080 kb
Host smart-f8b59fab-51c6-4e86-9955-983176411008
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088180391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4088180391
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3695218727
Short name T785
Test name
Test status
Simulation time 5335707234 ps
CPU time 21.49 seconds
Started Mar 28 12:44:14 PM PDT 24
Finished Mar 28 12:44:36 PM PDT 24
Peak memory 211200 kb
Host smart-bc880720-40e3-4941-a252-096ceaac2ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695218727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3695218727
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3973412226
Short name T829
Test name
Test status
Simulation time 4169421951 ps
CPU time 32.54 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 211952 kb
Host smart-904de6e5-1aa7-4860-acf8-de93bed91a25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973412226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3973412226
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3613175020
Short name T910
Test name
Test status
Simulation time 171165889 ps
CPU time 11.05 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:19 PM PDT 24
Peak memory 216324 kb
Host smart-6f3714bb-2981-43ff-918e-e6e4903bc9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613175020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3613175020
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.475926669
Short name T814
Test name
Test status
Simulation time 6445328218 ps
CPU time 30.67 seconds
Started Mar 28 12:44:06 PM PDT 24
Finished Mar 28 12:44:37 PM PDT 24
Peak memory 218852 kb
Host smart-a7d82029-fa67-44ad-bbfa-4c3f9f2759fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475926669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.475926669
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1363790902
Short name T809
Test name
Test status
Simulation time 5822868359 ps
CPU time 165.17 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:52:55 PM PDT 24
Peak memory 213844 kb
Host smart-55240824-be23-42a3-9a65-227246a409dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363790902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1363790902
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2210997054
Short name T799
Test name
Test status
Simulation time 4185293142 ps
CPU time 103.78 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:45:38 PM PDT 24
Peak memory 213344 kb
Host smart-5ffca987-80f4-4f9f-a80a-768bbab5eb6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210997054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2210997054
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3138254440
Short name T859
Test name
Test status
Simulation time 2414742245 ps
CPU time 22.9 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:38 PM PDT 24
Peak memory 218012 kb
Host smart-1b2d24c3-b053-40a6-9210-1be3e223be1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138254440 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3138254440
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3809286037
Short name T719
Test name
Test status
Simulation time 179013490 ps
CPU time 8.84 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:18 PM PDT 24
Peak memory 214444 kb
Host smart-c5b2d337-2df5-432d-8540-cfee0d79abd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809286037 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3809286037
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2154159603
Short name T871
Test name
Test status
Simulation time 3038150850 ps
CPU time 26.59 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:36 PM PDT 24
Peak memory 211292 kb
Host smart-a7006144-de61-48a3-ab12-5c01a3285de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154159603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2154159603
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.784409691
Short name T103
Test name
Test status
Simulation time 8905282197 ps
CPU time 21.34 seconds
Started Mar 28 12:44:20 PM PDT 24
Finished Mar 28 12:44:42 PM PDT 24
Peak memory 211664 kb
Host smart-16c8b87b-88f6-481c-a025-69cfd58ff927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784409691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.784409691
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1043146897
Short name T841
Test name
Test status
Simulation time 87293006807 ps
CPU time 166.52 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:47:08 PM PDT 24
Peak memory 214084 kb
Host smart-f706603f-88e5-464e-9437-64b645f1c8ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043146897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1043146897
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1910769869
Short name T89
Test name
Test status
Simulation time 36766748284 ps
CPU time 162.14 seconds
Started Mar 28 12:50:06 PM PDT 24
Finished Mar 28 12:52:49 PM PDT 24
Peak memory 215144 kb
Host smart-65068a38-a1e7-4377-a056-bbafce7b6682
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910769869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1910769869
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3275757601
Short name T894
Test name
Test status
Simulation time 256147828 ps
CPU time 13.29 seconds
Started Mar 28 12:44:20 PM PDT 24
Finished Mar 28 12:44:34 PM PDT 24
Peak memory 210892 kb
Host smart-3d744fff-ec29-47ea-8386-ad9a14b5ece5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275757601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3275757601
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3453310507
Short name T870
Test name
Test status
Simulation time 2319319152 ps
CPU time 25.97 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:36 PM PDT 24
Peak memory 211968 kb
Host smart-85830243-f85b-4119-94e0-af456c4ed94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453310507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3453310507
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.482337039
Short name T761
Test name
Test status
Simulation time 6354696718 ps
CPU time 24.02 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:39 PM PDT 24
Peak memory 217644 kb
Host smart-90d90941-771f-4514-97e5-159623d17e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482337039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.482337039
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.764302823
Short name T790
Test name
Test status
Simulation time 16816351765 ps
CPU time 31.98 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 218424 kb
Host smart-8821eb1c-ec8d-44be-b906-d8189f87f782
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764302823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.764302823
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.466863289
Short name T810
Test name
Test status
Simulation time 4260068805 ps
CPU time 171.09 seconds
Started Mar 28 12:44:17 PM PDT 24
Finished Mar 28 12:47:08 PM PDT 24
Peak memory 213440 kb
Host smart-7152f1ab-4789-4cd1-a7d3-780d6fb52f91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466863289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.466863289
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.884278478
Short name T138
Test name
Test status
Simulation time 3676666654 ps
CPU time 89.06 seconds
Started Mar 28 12:50:10 PM PDT 24
Finished Mar 28 12:51:39 PM PDT 24
Peak memory 212916 kb
Host smart-514e4faf-c313-4c27-9a32-a94149e24dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884278478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.884278478
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1763174077
Short name T802
Test name
Test status
Simulation time 20342972506 ps
CPU time 26.53 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:44:43 PM PDT 24
Peak memory 218076 kb
Host smart-2686cf18-e203-41cf-a987-d1d056b99887
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763174077 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1763174077
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4038658951
Short name T728
Test name
Test status
Simulation time 5833113664 ps
CPU time 25.66 seconds
Started Mar 28 12:50:08 PM PDT 24
Finished Mar 28 12:50:34 PM PDT 24
Peak memory 217212 kb
Host smart-58082dd6-1d89-4c91-956c-ab44975d2187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038658951 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4038658951
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2324293589
Short name T78
Test name
Test status
Simulation time 16776574639 ps
CPU time 31.69 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:41 PM PDT 24
Peak memory 211092 kb
Host smart-5299a6a7-b8e3-4906-b97d-cfece7d763b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324293589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2324293589
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2794014754
Short name T844
Test name
Test status
Simulation time 174588056 ps
CPU time 7.99 seconds
Started Mar 28 12:44:15 PM PDT 24
Finished Mar 28 12:44:23 PM PDT 24
Peak memory 210832 kb
Host smart-bfb546a3-9c84-4447-a7c0-b48fb194edbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794014754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2794014754
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2729013795
Short name T843
Test name
Test status
Simulation time 1056331853 ps
CPU time 56.09 seconds
Started Mar 28 12:50:10 PM PDT 24
Finished Mar 28 12:51:06 PM PDT 24
Peak memory 213892 kb
Host smart-d0ea7cdd-24cf-46b9-b1fe-9a8c718257b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729013795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2729013795
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3451766740
Short name T96
Test name
Test status
Simulation time 17873710479 ps
CPU time 164.21 seconds
Started Mar 28 12:44:20 PM PDT 24
Finished Mar 28 12:47:04 PM PDT 24
Peak memory 215004 kb
Host smart-104ac6e5-692f-462b-8bad-996552ab172a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451766740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3451766740
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2084829161
Short name T895
Test name
Test status
Simulation time 19376342401 ps
CPU time 32 seconds
Started Mar 28 12:50:12 PM PDT 24
Finished Mar 28 12:50:44 PM PDT 24
Peak memory 212104 kb
Host smart-ffc5ad5e-e578-49e3-a5b6-4d12cec85525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084829161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2084829161
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3079836819
Short name T717
Test name
Test status
Simulation time 2883047700 ps
CPU time 25.08 seconds
Started Mar 28 12:44:16 PM PDT 24
Finished Mar 28 12:44:42 PM PDT 24
Peak memory 211440 kb
Host smart-d0fabccd-1b9c-44c9-a279-6b8d7bb7a226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079836819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3079836819
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2695028272
Short name T819
Test name
Test status
Simulation time 4246083321 ps
CPU time 35.63 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:50:45 PM PDT 24
Peak memory 218160 kb
Host smart-e9fd0ed4-e1f5-47d6-9ef7-17f1b64e29d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695028272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2695028272
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3429845927
Short name T685
Test name
Test status
Simulation time 331732342 ps
CPU time 12.16 seconds
Started Mar 28 12:44:13 PM PDT 24
Finished Mar 28 12:44:25 PM PDT 24
Peak memory 216936 kb
Host smart-fbd28065-fea6-4df5-bc4f-41b95fdd4215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429845927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3429845927
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2485760011
Short name T139
Test name
Test status
Simulation time 8053820109 ps
CPU time 164.75 seconds
Started Mar 28 12:50:09 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 213772 kb
Host smart-745dd083-82b6-4aa6-abda-005b6e207ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485760011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2485760011
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3867200273
Short name T823
Test name
Test status
Simulation time 648048781 ps
CPU time 158.91 seconds
Started Mar 28 12:44:21 PM PDT 24
Finished Mar 28 12:47:01 PM PDT 24
Peak memory 213608 kb
Host smart-6389b011-f320-4a42-84a5-18bcde37a320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867200273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3867200273
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.242683474
Short name T410
Test name
Test status
Simulation time 742532897 ps
CPU time 13.67 seconds
Started Mar 28 12:40:22 PM PDT 24
Finished Mar 28 12:40:36 PM PDT 24
Peak memory 211804 kb
Host smart-e4c11c63-059f-486e-aab7-cb3dc1252568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242683474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.242683474
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3589426208
Short name T291
Test name
Test status
Simulation time 687864701 ps
CPU time 8.35 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:51:42 PM PDT 24
Peak memory 211920 kb
Host smart-efdeebca-b021-4ea9-8bda-5f75d11398c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589426208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3589426208
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3090956663
Short name T55
Test name
Test status
Simulation time 224109484750 ps
CPU time 512.59 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 01:00:06 PM PDT 24
Peak memory 238368 kb
Host smart-f20abe49-5e9a-404b-b621-bfeb55a2e729
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090956663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3090956663
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.948142722
Short name T392
Test name
Test status
Simulation time 2994396972 ps
CPU time 199.49 seconds
Started Mar 28 12:40:25 PM PDT 24
Finished Mar 28 12:43:44 PM PDT 24
Peak memory 227572 kb
Host smart-730d801d-42b6-41b8-91b0-8a635b10472f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948142722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.948142722
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.274315678
Short name T255
Test name
Test status
Simulation time 51629992891 ps
CPU time 61.36 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 215664 kb
Host smart-974e1e5f-ef5e-4b50-973c-e0b472206659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274315678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.274315678
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2194749637
Short name T9
Test name
Test status
Simulation time 4195356809 ps
CPU time 26.21 seconds
Started Mar 28 12:40:25 PM PDT 24
Finished Mar 28 12:40:51 PM PDT 24
Peak memory 212144 kb
Host smart-93e0f1fd-9a04-48ae-9876-f548af9b59df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194749637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2194749637
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3710411605
Short name T155
Test name
Test status
Simulation time 187589933 ps
CPU time 10.64 seconds
Started Mar 28 12:51:28 PM PDT 24
Finished Mar 28 12:51:40 PM PDT 24
Peak memory 212848 kb
Host smart-08ab407c-d631-46c9-8639-fa6beaae70ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710411605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3710411605
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3231486842
Short name T39
Test name
Test status
Simulation time 578635283 ps
CPU time 227.85 seconds
Started Mar 28 12:40:19 PM PDT 24
Finished Mar 28 12:44:07 PM PDT 24
Peak memory 237832 kb
Host smart-432db0fa-1adc-453b-b8c2-1b37a823b13f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231486842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3231486842
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.701143613
Short name T44
Test name
Test status
Simulation time 243658537 ps
CPU time 116.75 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:53:31 PM PDT 24
Peak memory 237324 kb
Host smart-49ceaef4-8622-4b9e-8312-5efd6487e7c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701143613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.701143613
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1353170339
Short name T183
Test name
Test status
Simulation time 22655715671 ps
CPU time 52.68 seconds
Started Mar 28 12:40:14 PM PDT 24
Finished Mar 28 12:41:07 PM PDT 24
Peak memory 218140 kb
Host smart-d4f39760-8f26-4cd6-97bc-f5e5a32462cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353170339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1353170339
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2979859432
Short name T376
Test name
Test status
Simulation time 14470122833 ps
CPU time 35.53 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:10 PM PDT 24
Peak memory 215084 kb
Host smart-bc6bc172-4573-4b03-915e-f89164829a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979859432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2979859432
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1443627547
Short name T622
Test name
Test status
Simulation time 13115132036 ps
CPU time 34.51 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:08 PM PDT 24
Peak memory 214832 kb
Host smart-67dece9e-85f6-44e5-bc1d-cb82c69f6554
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443627547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1443627547
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4157088816
Short name T514
Test name
Test status
Simulation time 5171610516 ps
CPU time 55.03 seconds
Started Mar 28 12:40:29 PM PDT 24
Finished Mar 28 12:41:24 PM PDT 24
Peak memory 218968 kb
Host smart-c3e51298-4db7-4c82-a5b5-7f5512069039
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157088816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4157088816
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3836538672
Short name T50
Test name
Test status
Simulation time 44314348451 ps
CPU time 864.18 seconds
Started Mar 28 12:40:15 PM PDT 24
Finished Mar 28 12:54:39 PM PDT 24
Peak memory 231168 kb
Host smart-ed8f9f3a-fa03-4904-ae07-43af0f5e392f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836538672 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3836538672
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.345449388
Short name T328
Test name
Test status
Simulation time 19637890681 ps
CPU time 32.44 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:12 PM PDT 24
Peak memory 212908 kb
Host smart-29c7a29d-e947-4cfd-bbb9-26b05e4e2fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345449388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.345449388
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.74929464
Short name T588
Test name
Test status
Simulation time 2319280396 ps
CPU time 22.49 seconds
Started Mar 28 12:51:32 PM PDT 24
Finished Mar 28 12:51:55 PM PDT 24
Peak memory 212628 kb
Host smart-21870df3-8698-484a-bbbe-4d64731b0198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74929464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.74929464
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3190967773
Short name T405
Test name
Test status
Simulation time 273622300799 ps
CPU time 611.56 seconds
Started Mar 28 12:40:19 PM PDT 24
Finished Mar 28 12:50:31 PM PDT 24
Peak memory 216472 kb
Host smart-deae0811-edb9-46bf-b9dc-80a991d76e61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190967773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3190967773
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.341151502
Short name T247
Test name
Test status
Simulation time 125517780782 ps
CPU time 342.68 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 241188 kb
Host smart-bdbdaa63-f14d-4cdb-99d6-6de8a43903a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341151502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.341151502
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1364005446
Short name T598
Test name
Test status
Simulation time 5457602515 ps
CPU time 51.69 seconds
Started Mar 28 12:51:36 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 215616 kb
Host smart-2588dd9e-4cc9-48f7-a40a-a27372fa1dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364005446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1364005446
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.183071326
Short name T48
Test name
Test status
Simulation time 21884070693 ps
CPU time 51.27 seconds
Started Mar 28 12:40:45 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 215592 kb
Host smart-842b061c-5c58-47f2-9236-2cb17ee6cac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183071326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.183071326
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4037187013
Short name T148
Test name
Test status
Simulation time 11305446304 ps
CPU time 26.73 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:00 PM PDT 24
Peak memory 213288 kb
Host smart-ac7aa3ed-c5fa-4338-b86a-8f5744959fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037187013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4037187013
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4090927605
Short name T175
Test name
Test status
Simulation time 3724550337 ps
CPU time 32.57 seconds
Started Mar 28 12:40:16 PM PDT 24
Finished Mar 28 12:40:49 PM PDT 24
Peak memory 211840 kb
Host smart-b0079cb4-3c63-4d74-aeea-8b0be568b775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090927605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4090927605
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2915857715
Short name T43
Test name
Test status
Simulation time 8642387029 ps
CPU time 249.4 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 239548 kb
Host smart-6eb78e9c-74b9-40ef-b003-aab081deec89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915857715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2915857715
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.351631496
Short name T40
Test name
Test status
Simulation time 10743164343 ps
CPU time 130.02 seconds
Started Mar 28 12:51:35 PM PDT 24
Finished Mar 28 12:53:45 PM PDT 24
Peak memory 238316 kb
Host smart-cf8afaa6-2489-4975-a756-63c6a7955d96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351631496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.351631496
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1056263879
Short name T508
Test name
Test status
Simulation time 18267987585 ps
CPU time 39.88 seconds
Started Mar 28 12:51:36 PM PDT 24
Finished Mar 28 12:52:16 PM PDT 24
Peak memory 218664 kb
Host smart-833ef7fd-f7bd-449b-86b1-9620c41745a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056263879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1056263879
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3486332975
Short name T443
Test name
Test status
Simulation time 13047385990 ps
CPU time 43.93 seconds
Started Mar 28 12:40:23 PM PDT 24
Finished Mar 28 12:41:07 PM PDT 24
Peak memory 215816 kb
Host smart-5e5631b0-aa6f-410c-b674-a869e2bcdf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486332975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3486332975
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3376590661
Short name T169
Test name
Test status
Simulation time 446994960 ps
CPU time 27.97 seconds
Started Mar 28 12:40:18 PM PDT 24
Finished Mar 28 12:40:47 PM PDT 24
Peak memory 215856 kb
Host smart-c75e36b7-c601-4056-b8c9-85c76dde6759
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376590661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3376590661
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3708680322
Short name T218
Test name
Test status
Simulation time 30239335618 ps
CPU time 76.2 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:49 PM PDT 24
Peak memory 216976 kb
Host smart-2e9cf961-10a0-49cd-945c-d9aad2399213
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708680322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3708680322
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.441515462
Short name T653
Test name
Test status
Simulation time 11397004638 ps
CPU time 26.56 seconds
Started Mar 28 12:51:41 PM PDT 24
Finished Mar 28 12:52:08 PM PDT 24
Peak memory 212664 kb
Host smart-4b0dc4d0-77ef-4d53-94b5-16565629142a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441515462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.441515462
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.962227467
Short name T677
Test name
Test status
Simulation time 1646430393 ps
CPU time 8.31 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:40:48 PM PDT 24
Peak memory 211744 kb
Host smart-efeca1a7-d1dd-4d08-9c9b-eb1b4f489e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962227467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.962227467
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2222634765
Short name T595
Test name
Test status
Simulation time 118569524978 ps
CPU time 1121.82 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 01:10:38 PM PDT 24
Peak memory 240920 kb
Host smart-3c96f251-b865-4ebd-a87a-4462b572a8b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222634765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2222634765
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3657155521
Short name T359
Test name
Test status
Simulation time 5803352563 ps
CPU time 410.2 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:47:30 PM PDT 24
Peak memory 230012 kb
Host smart-7ce7a30a-0a1b-4a7a-bcce-8cffd10831cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657155521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3657155521
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2397106389
Short name T427
Test name
Test status
Simulation time 33401703480 ps
CPU time 66.33 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 213420 kb
Host smart-ee58d54e-0e80-482d-9781-48442e4fd729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397106389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2397106389
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3528688154
Short name T545
Test name
Test status
Simulation time 2852388522 ps
CPU time 29.25 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:25 PM PDT 24
Peak memory 214372 kb
Host smart-279ec663-b01a-4418-98f6-8da9b95b61d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528688154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3528688154
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2642425472
Short name T333
Test name
Test status
Simulation time 2095573115 ps
CPU time 14.39 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:40:54 PM PDT 24
Peak memory 211436 kb
Host smart-f9c00c20-fe2d-4f7b-9a3d-377eb97e6501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642425472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2642425472
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3239734671
Short name T536
Test name
Test status
Simulation time 1155480482 ps
CPU time 17.31 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:52:07 PM PDT 24
Peak memory 212024 kb
Host smart-40ed13ca-d0db-407f-8199-3421334c3eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239734671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3239734671
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1508226640
Short name T153
Test name
Test status
Simulation time 5859774750 ps
CPU time 36.43 seconds
Started Mar 28 12:40:34 PM PDT 24
Finished Mar 28 12:41:12 PM PDT 24
Peak memory 218184 kb
Host smart-8e3139db-9226-4e84-83d0-03659635b01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508226640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1508226640
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1914729299
Short name T166
Test name
Test status
Simulation time 18909406656 ps
CPU time 60.33 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 218508 kb
Host smart-4ced006b-122d-4c99-896c-9890d5a5ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914729299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1914729299
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1733898518
Short name T12
Test name
Test status
Simulation time 718387541 ps
CPU time 44.51 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 219812 kb
Host smart-5ca6cb12-aa53-4848-843a-6aa3f6c67d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733898518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1733898518
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2024991460
Short name T444
Test name
Test status
Simulation time 521701331 ps
CPU time 24.68 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:04 PM PDT 24
Peak memory 215888 kb
Host smart-e2291925-4be6-48b0-8d9d-4aae2af9b3aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024991460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2024991460
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1768083180
Short name T22
Test name
Test status
Simulation time 92259707468 ps
CPU time 8887.39 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 03:08:48 PM PDT 24
Peak memory 236240 kb
Host smart-3b170871-c570-4b73-8e94-26f7dedbcfe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768083180 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1768083180
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2070406072
Short name T61
Test name
Test status
Simulation time 180438409965 ps
CPU time 1736.74 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 01:20:53 PM PDT 24
Peak memory 244632 kb
Host smart-b25f187f-54fb-4b49-8dd0-9b5f1f43e9da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070406072 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2070406072
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2147309075
Short name T517
Test name
Test status
Simulation time 589673019 ps
CPU time 12.4 seconds
Started Mar 28 12:51:51 PM PDT 24
Finished Mar 28 12:52:04 PM PDT 24
Peak memory 211904 kb
Host smart-c5d6133d-62a2-4817-a89d-49095b0ff012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147309075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2147309075
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2159603858
Short name T305
Test name
Test status
Simulation time 325740073 ps
CPU time 8.53 seconds
Started Mar 28 12:40:40 PM PDT 24
Finished Mar 28 12:40:49 PM PDT 24
Peak memory 211808 kb
Host smart-3829956b-5e04-4f3a-921f-24518ecd9f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159603858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2159603858
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1656429594
Short name T365
Test name
Test status
Simulation time 107157473686 ps
CPU time 292.28 seconds
Started Mar 28 12:51:43 PM PDT 24
Finished Mar 28 12:56:35 PM PDT 24
Peak memory 229720 kb
Host smart-4b09ffac-74ee-47ba-a924-95e4f7b22632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656429594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1656429594
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1716521021
Short name T679
Test name
Test status
Simulation time 73033227906 ps
CPU time 831.72 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:54:31 PM PDT 24
Peak memory 238844 kb
Host smart-ff110d29-32de-48f5-99a3-67deb196a4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716521021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1716521021
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1969019555
Short name T230
Test name
Test status
Simulation time 14540862453 ps
CPU time 36 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:32 PM PDT 24
Peak memory 216964 kb
Host smart-a57c0036-796b-4b28-b37a-545036dba322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969019555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1969019555
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3225983882
Short name T654
Test name
Test status
Simulation time 4260181718 ps
CPU time 45.6 seconds
Started Mar 28 12:40:40 PM PDT 24
Finished Mar 28 12:41:27 PM PDT 24
Peak memory 215276 kb
Host smart-1dff49d5-b12e-4806-9e5a-9c3ec5192a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225983882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3225983882
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2884988960
Short name T502
Test name
Test status
Simulation time 2218847088 ps
CPU time 22.76 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:03 PM PDT 24
Peak memory 211816 kb
Host smart-e66b6a84-1082-4011-8cf3-5ae1002d06dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884988960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2884988960
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.4191875461
Short name T325
Test name
Test status
Simulation time 13718038243 ps
CPU time 29.81 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:52:19 PM PDT 24
Peak memory 212432 kb
Host smart-2555a09a-c06b-457f-8328-023b0567722a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191875461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.4191875461
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1243855231
Short name T627
Test name
Test status
Simulation time 27737898033 ps
CPU time 66.62 seconds
Started Mar 28 12:51:46 PM PDT 24
Finished Mar 28 12:52:53 PM PDT 24
Peak memory 218384 kb
Host smart-daf0d718-8244-42f3-8fc1-847e920e8861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243855231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1243855231
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4053333708
Short name T301
Test name
Test status
Simulation time 1532830530 ps
CPU time 32.78 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:12 PM PDT 24
Peak memory 217396 kb
Host smart-987d3795-61e7-4e25-ab6a-ff788beed000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053333708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4053333708
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1464334820
Short name T616
Test name
Test status
Simulation time 18022079631 ps
CPU time 76.03 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 12:53:03 PM PDT 24
Peak memory 221704 kb
Host smart-6e952ba7-007c-46fb-9953-0821aa1322d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464334820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1464334820
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4032132664
Short name T421
Test name
Test status
Simulation time 37056991752 ps
CPU time 189.43 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:43:49 PM PDT 24
Peak memory 228052 kb
Host smart-17c8a553-f918-493f-ae40-06e0f7b538bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032132664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4032132664
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.408618499
Short name T532
Test name
Test status
Simulation time 53027861328 ps
CPU time 26.08 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 12:52:13 PM PDT 24
Peak memory 211616 kb
Host smart-56d7daca-ecca-4f98-b483-c62511a59fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408618499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.408618499
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.569316137
Short name T236
Test name
Test status
Simulation time 1271007855 ps
CPU time 15.85 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:40:55 PM PDT 24
Peak memory 212280 kb
Host smart-de1a694b-f6de-4c68-8fe9-1e703060cd48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569316137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.569316137
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3294493225
Short name T386
Test name
Test status
Simulation time 76154236274 ps
CPU time 438.24 seconds
Started Mar 28 12:40:40 PM PDT 24
Finished Mar 28 12:47:59 PM PDT 24
Peak memory 217760 kb
Host smart-a1f0987f-e6d4-4325-b646-42eb7c7fcd3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294493225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3294493225
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.4073380938
Short name T435
Test name
Test status
Simulation time 149005860137 ps
CPU time 488.07 seconds
Started Mar 28 12:51:40 PM PDT 24
Finished Mar 28 12:59:48 PM PDT 24
Peak memory 240840 kb
Host smart-e9c62751-8716-41fc-aa69-f28227cd7b46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073380938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.4073380938
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3367392213
Short name T196
Test name
Test status
Simulation time 8313775545 ps
CPU time 64.99 seconds
Started Mar 28 12:40:44 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 215812 kb
Host smart-2a2982ac-eb4d-43aa-b117-2518002b522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367392213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3367392213
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4105002453
Short name T207
Test name
Test status
Simulation time 4093143684 ps
CPU time 44.53 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:41 PM PDT 24
Peak memory 215480 kb
Host smart-d9919d7d-6490-44ed-8ae0-dd6f5da127e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105002453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4105002453
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3807680048
Short name T285
Test name
Test status
Simulation time 3621223549 ps
CPU time 30.11 seconds
Started Mar 28 12:40:52 PM PDT 24
Finished Mar 28 12:41:22 PM PDT 24
Peak memory 212804 kb
Host smart-6daf01b7-bfe6-477b-b903-bf284449766e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807680048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3807680048
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.926337513
Short name T556
Test name
Test status
Simulation time 341810824 ps
CPU time 12.7 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:52:02 PM PDT 24
Peak memory 211804 kb
Host smart-574b233e-820d-40e3-a449-992b5293fd0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926337513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.926337513
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2709404279
Short name T402
Test name
Test status
Simulation time 14415620822 ps
CPU time 47.56 seconds
Started Mar 28 12:51:40 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 217536 kb
Host smart-45f5b25e-d5b3-44ff-9c94-7b6d7bbc4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709404279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2709404279
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.989334554
Short name T205
Test name
Test status
Simulation time 352543581 ps
CPU time 20.03 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:00 PM PDT 24
Peak memory 217200 kb
Host smart-a89e7114-90c2-474a-bf34-7b71ea68d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989334554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.989334554
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3329409792
Short name T471
Test name
Test status
Simulation time 54206881283 ps
CPU time 134.37 seconds
Started Mar 28 12:40:41 PM PDT 24
Finished Mar 28 12:42:55 PM PDT 24
Peak memory 220856 kb
Host smart-9338e426-794c-43b7-9899-9e1b1ce09b76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329409792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3329409792
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.505132957
Short name T334
Test name
Test status
Simulation time 509236502 ps
CPU time 17.11 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:52:08 PM PDT 24
Peak memory 211728 kb
Host smart-ecec5f57-341c-4fb6-942d-4628b765a2ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505132957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.505132957
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1572146141
Short name T246
Test name
Test status
Simulation time 4966293219 ps
CPU time 30.9 seconds
Started Mar 28 12:51:39 PM PDT 24
Finished Mar 28 12:52:10 PM PDT 24
Peak memory 211836 kb
Host smart-8f035445-793b-43b9-b4c6-05a783dc8329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572146141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1572146141
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4142563668
Short name T356
Test name
Test status
Simulation time 1832613188 ps
CPU time 8.5 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:40:48 PM PDT 24
Peak memory 211688 kb
Host smart-c83d2c32-4464-4526-a3b4-d93145542a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142563668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4142563668
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1331070607
Short name T569
Test name
Test status
Simulation time 36606670936 ps
CPU time 404.73 seconds
Started Mar 28 12:51:41 PM PDT 24
Finished Mar 28 12:58:26 PM PDT 24
Peak memory 226008 kb
Host smart-84380078-5951-4c58-9763-ca855b7c5338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331070607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1331070607
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.387118701
Short name T275
Test name
Test status
Simulation time 50912832938 ps
CPU time 482.95 seconds
Started Mar 28 12:40:47 PM PDT 24
Finished Mar 28 12:48:51 PM PDT 24
Peak memory 240312 kb
Host smart-59288062-571e-4a1b-914a-9a9bebc116ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387118701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.387118701
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1009584674
Short name T440
Test name
Test status
Simulation time 21000650907 ps
CPU time 70.59 seconds
Started Mar 28 12:51:41 PM PDT 24
Finished Mar 28 12:52:52 PM PDT 24
Peak memory 215592 kb
Host smart-01bde9d1-110a-475e-be18-966964c5c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009584674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1009584674
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1166893162
Short name T548
Test name
Test status
Simulation time 1377595642 ps
CPU time 18.96 seconds
Started Mar 28 12:40:47 PM PDT 24
Finished Mar 28 12:41:07 PM PDT 24
Peak memory 215256 kb
Host smart-98eacc24-4dd4-42ae-811b-f38f5c04bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166893162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1166893162
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.665026691
Short name T594
Test name
Test status
Simulation time 5186408843 ps
CPU time 25.01 seconds
Started Mar 28 12:40:47 PM PDT 24
Finished Mar 28 12:41:13 PM PDT 24
Peak memory 212412 kb
Host smart-e01d519c-8fd9-4abd-8aac-9d7d680859bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665026691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.665026691
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1031457609
Short name T350
Test name
Test status
Simulation time 4318762061 ps
CPU time 45.14 seconds
Started Mar 28 12:40:45 PM PDT 24
Finished Mar 28 12:41:30 PM PDT 24
Peak memory 217312 kb
Host smart-107eb8a5-daa6-41c6-8458-a7f74a02039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031457609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1031457609
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.155828903
Short name T88
Test name
Test status
Simulation time 9038333779 ps
CPU time 53.1 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:49 PM PDT 24
Peak memory 218532 kb
Host smart-3033fed1-2b5d-434b-bf59-46801e5a0ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155828903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.155828903
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3402696273
Short name T180
Test name
Test status
Simulation time 2225996113 ps
CPU time 69.4 seconds
Started Mar 28 12:40:44 PM PDT 24
Finished Mar 28 12:41:53 PM PDT 24
Peak memory 219716 kb
Host smart-f17b9e9e-3e57-4669-bfd0-def9761c2ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402696273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3402696273
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.899958758
Short name T475
Test name
Test status
Simulation time 6763045051 ps
CPU time 69.7 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:53:03 PM PDT 24
Peak memory 216392 kb
Host smart-3ba96ad0-0c67-4d37-ae88-43ef30bb05ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899958758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.899958758
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2098273420
Short name T349
Test name
Test status
Simulation time 2553730499 ps
CPU time 23.15 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:17 PM PDT 24
Peak memory 212624 kb
Host smart-d5b5bd3f-5cb2-491a-982a-489a00520bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098273420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2098273420
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3167293366
Short name T423
Test name
Test status
Simulation time 1818868402 ps
CPU time 19.02 seconds
Started Mar 28 12:40:41 PM PDT 24
Finished Mar 28 12:41:00 PM PDT 24
Peak memory 212412 kb
Host smart-4436d885-efc6-467a-84d4-cfe2ca5dd765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167293366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3167293366
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4037275703
Short name T144
Test name
Test status
Simulation time 80306490375 ps
CPU time 258.6 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:44:59 PM PDT 24
Peak memory 240852 kb
Host smart-c053a558-8d15-4fd4-a67c-9ff2d8ba0b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037275703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4037275703
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.550897403
Short name T243
Test name
Test status
Simulation time 12113394499 ps
CPU time 279.16 seconds
Started Mar 28 12:51:41 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 230172 kb
Host smart-7e3b0606-c3fa-407e-bc3e-8b2163634fef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550897403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.550897403
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3632183273
Short name T1
Test name
Test status
Simulation time 13172837408 ps
CPU time 24.26 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:41:02 PM PDT 24
Peak memory 215492 kb
Host smart-56173968-d259-4045-8e60-7068e2e9af3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632183273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3632183273
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2213944500
Short name T192
Test name
Test status
Simulation time 992796993 ps
CPU time 16.67 seconds
Started Mar 28 12:51:56 PM PDT 24
Finished Mar 28 12:52:14 PM PDT 24
Peak memory 211840 kb
Host smart-cb6bd58f-ffff-409a-b21c-b189e420d128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213944500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2213944500
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3059355538
Short name T193
Test name
Test status
Simulation time 4731952266 ps
CPU time 23.47 seconds
Started Mar 28 12:40:51 PM PDT 24
Finished Mar 28 12:41:15 PM PDT 24
Peak memory 212016 kb
Host smart-beb4ad1d-99a1-402c-8e89-c07887f7c87a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3059355538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3059355538
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2763246305
Short name T642
Test name
Test status
Simulation time 8263205185 ps
CPU time 67.86 seconds
Started Mar 28 12:40:40 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 217264 kb
Host smart-dd20b966-b55b-4087-8803-f140801b7381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763246305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2763246305
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3067027233
Short name T518
Test name
Test status
Simulation time 2807748199 ps
CPU time 25.18 seconds
Started Mar 28 12:51:40 PM PDT 24
Finished Mar 28 12:52:06 PM PDT 24
Peak memory 217032 kb
Host smart-331ba4ce-e543-4421-b706-8a0d8e6b7002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067027233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3067027233
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1541308638
Short name T379
Test name
Test status
Simulation time 9603924484 ps
CPU time 59.2 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 219872 kb
Host smart-c7f12484-53be-4025-93b0-99f8849f3915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541308638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1541308638
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1856585548
Short name T511
Test name
Test status
Simulation time 5707057463 ps
CPU time 110.18 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:53:44 PM PDT 24
Peak memory 222332 kb
Host smart-bfcdd964-6f54-4836-8b77-2d392feb57cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856585548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1856585548
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3103584441
Short name T416
Test name
Test status
Simulation time 72660799471 ps
CPU time 3133.46 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 01:32:50 PM PDT 24
Peak memory 236368 kb
Host smart-ff5c16d0-dc5c-42c6-bddb-e46b2601e2c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103584441 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3103584441
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1128241310
Short name T610
Test name
Test status
Simulation time 171130907 ps
CPU time 8.34 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:40:47 PM PDT 24
Peak memory 211680 kb
Host smart-906a6936-976c-4a19-8b90-8e856d88d6d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128241310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1128241310
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3364117027
Short name T5
Test name
Test status
Simulation time 144913080188 ps
CPU time 729.19 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 237648 kb
Host smart-b021ba9e-cfea-4d8a-b7b3-5f513412cc04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364117027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3364117027
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1403093133
Short name T179
Test name
Test status
Simulation time 1375721149 ps
CPU time 18.84 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:13 PM PDT 24
Peak memory 215360 kb
Host smart-86995e71-d7c9-468d-ab44-085cec9000b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403093133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1403093133
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2232726511
Short name T504
Test name
Test status
Simulation time 675627788 ps
CPU time 19.5 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:00 PM PDT 24
Peak memory 215128 kb
Host smart-d0d85aa0-fc20-462e-8ddb-966faf178ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232726511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2232726511
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.275557531
Short name T337
Test name
Test status
Simulation time 2645166423 ps
CPU time 13.62 seconds
Started Mar 28 12:51:45 PM PDT 24
Finished Mar 28 12:51:59 PM PDT 24
Peak memory 212004 kb
Host smart-1e9003eb-2f21-40c1-9073-c42802e6da77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275557531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.275557531
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4145450676
Short name T454
Test name
Test status
Simulation time 6457972229 ps
CPU time 30.55 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:41:07 PM PDT 24
Peak memory 211804 kb
Host smart-b7f866ed-ee0e-4cd7-b1e0-773d14344ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145450676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4145450676
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1234780101
Short name T510
Test name
Test status
Simulation time 32725851785 ps
CPU time 43.3 seconds
Started Mar 28 12:51:45 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 218108 kb
Host smart-75af0e59-4989-443b-892d-aae1afedfade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234780101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1234780101
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3162798182
Short name T419
Test name
Test status
Simulation time 5097903474 ps
CPU time 42.13 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:22 PM PDT 24
Peak memory 218148 kb
Host smart-f4faabbe-fd75-43bb-bc32-fe5ba9aba5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162798182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3162798182
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2143769902
Short name T360
Test name
Test status
Simulation time 11121954963 ps
CPU time 62.35 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:52:53 PM PDT 24
Peak memory 219920 kb
Host smart-ec3264fd-a0c0-4018-b165-279a4ec1eab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143769902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2143769902
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2263485237
Short name T182
Test name
Test status
Simulation time 38693244521 ps
CPU time 25.62 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:06 PM PDT 24
Peak memory 214744 kb
Host smart-f1bbd75d-bbe8-46e9-8bb8-8de1f76a06bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263485237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2263485237
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3682131931
Short name T488
Test name
Test status
Simulation time 7912642609 ps
CPU time 32.68 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:12 PM PDT 24
Peak memory 211952 kb
Host smart-23fa4ab6-51d8-434b-938a-00cece0cd63f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682131931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3682131931
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4207376001
Short name T566
Test name
Test status
Simulation time 12850636544 ps
CPU time 27.64 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:52:17 PM PDT 24
Peak memory 211948 kb
Host smart-626326b7-95ed-46ff-8269-3fe2af5edf3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207376001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4207376001
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2440227063
Short name T221
Test name
Test status
Simulation time 8141072326 ps
CPU time 242.41 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:44:42 PM PDT 24
Peak memory 220028 kb
Host smart-bda60a89-14a3-46d7-8262-0e2a0c9cf856
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440227063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2440227063
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.93675164
Short name T573
Test name
Test status
Simulation time 51211053246 ps
CPU time 264.32 seconds
Started Mar 28 12:51:41 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 220256 kb
Host smart-9b5e9655-27a3-4aa6-b6c4-a45faff2a47e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93675164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.93675164
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2685878443
Short name T319
Test name
Test status
Simulation time 512335755 ps
CPU time 21.96 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:52:13 PM PDT 24
Peak memory 215340 kb
Host smart-2142e30d-7985-4fee-9241-00662ebd2c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685878443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2685878443
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3159980947
Short name T450
Test name
Test status
Simulation time 2062887347 ps
CPU time 18.68 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:40:57 PM PDT 24
Peak memory 215224 kb
Host smart-06384ba8-d04e-4901-be01-fa804ad3a5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159980947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3159980947
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1016541419
Short name T260
Test name
Test status
Simulation time 510082174 ps
CPU time 11.99 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:52:04 PM PDT 24
Peak memory 212732 kb
Host smart-ef7bbc73-bef5-4d9c-a2c2-46b51e50cceb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016541419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1016541419
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3889161414
Short name T437
Test name
Test status
Simulation time 2135891371 ps
CPU time 22.38 seconds
Started Mar 28 12:40:31 PM PDT 24
Finished Mar 28 12:40:53 PM PDT 24
Peak memory 213036 kb
Host smart-65d6f240-42b1-43ec-b914-a9e4c8dca3f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889161414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3889161414
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2520903761
Short name T152
Test name
Test status
Simulation time 4307162569 ps
CPU time 34.24 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:41:11 PM PDT 24
Peak memory 218392 kb
Host smart-bbd31a25-1b02-426d-8f0e-ca267362f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520903761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2520903761
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1891112904
Short name T161
Test name
Test status
Simulation time 791037772 ps
CPU time 43.17 seconds
Started Mar 28 12:51:44 PM PDT 24
Finished Mar 28 12:52:27 PM PDT 24
Peak memory 219820 kb
Host smart-7b28bb5f-5812-4fd7-8eb5-2084865ac82c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891112904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1891112904
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2327496959
Short name T446
Test name
Test status
Simulation time 539772014 ps
CPU time 33.17 seconds
Started Mar 28 12:40:42 PM PDT 24
Finished Mar 28 12:41:15 PM PDT 24
Peak memory 217052 kb
Host smart-7f8031ac-01e9-4b47-bb5f-260b8762f991
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327496959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2327496959
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3733390548
Short name T213
Test name
Test status
Simulation time 70745974675 ps
CPU time 31.35 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 212936 kb
Host smart-7210469c-2717-46c4-b696-aeb0280ea969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733390548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3733390548
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3892753842
Short name T626
Test name
Test status
Simulation time 1333842027 ps
CPU time 16.83 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:40:56 PM PDT 24
Peak memory 211808 kb
Host smart-7913491a-8ee7-4f4f-bd2b-9ef3bbca59b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892753842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3892753842
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2791130461
Short name T530
Test name
Test status
Simulation time 106689786946 ps
CPU time 342.85 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:46:22 PM PDT 24
Peak memory 237444 kb
Host smart-c6d1e90d-ade8-472d-b439-6ae63edc8e81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791130461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2791130461
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3911035540
Short name T54
Test name
Test status
Simulation time 25423942363 ps
CPU time 264.14 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 237300 kb
Host smart-d36ed5cc-7466-4064-99e2-6d4eba80d479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911035540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3911035540
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1995141490
Short name T439
Test name
Test status
Simulation time 2766297067 ps
CPU time 19.6 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:00 PM PDT 24
Peak memory 217080 kb
Host smart-a3559e15-6b4c-4375-ab08-357ca75b06bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995141490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1995141490
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2544369337
Short name T468
Test name
Test status
Simulation time 7917001919 ps
CPU time 33.04 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:52:22 PM PDT 24
Peak memory 215528 kb
Host smart-79f606bc-c1ed-4111-ad5c-6de5452c6f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544369337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2544369337
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1494736813
Short name T303
Test name
Test status
Simulation time 360252895 ps
CPU time 10.51 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:40:50 PM PDT 24
Peak memory 212300 kb
Host smart-3b51992d-e0d8-48cf-995e-e9069a818b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494736813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1494736813
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3088253405
Short name T47
Test name
Test status
Simulation time 2648963991 ps
CPU time 18.5 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:52:09 PM PDT 24
Peak memory 212824 kb
Host smart-8621d824-1e77-4708-839a-ccfce2c11f76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088253405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3088253405
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1226534104
Short name T216
Test name
Test status
Simulation time 35530567277 ps
CPU time 67.62 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 12:52:55 PM PDT 24
Peak memory 217820 kb
Host smart-6703a216-e9e3-4fce-ba7f-d0e50c9158ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226534104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1226534104
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4151979241
Short name T393
Test name
Test status
Simulation time 31012266990 ps
CPU time 60.21 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 218180 kb
Host smart-9af5aeb0-5b46-4a17-b505-8f006b6c553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151979241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4151979241
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2337475866
Short name T229
Test name
Test status
Simulation time 31965159331 ps
CPU time 140.46 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:54:13 PM PDT 24
Peak memory 228384 kb
Host smart-309a1e9b-e4e8-4365-b3c4-7664082a0dd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337475866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2337475866
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3062793015
Short name T542
Test name
Test status
Simulation time 31075226971 ps
CPU time 84.86 seconds
Started Mar 28 12:40:33 PM PDT 24
Finished Mar 28 12:41:58 PM PDT 24
Peak memory 221396 kb
Host smart-417bed30-bb0e-44b5-a592-5a143e78c7aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062793015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3062793015
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.36226871
Short name T484
Test name
Test status
Simulation time 345949970 ps
CPU time 8.42 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:05 PM PDT 24
Peak memory 211816 kb
Host smart-d4d19a64-e7ec-4bc8-8db6-d65c58a53d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.36226871
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4127978349
Short name T529
Test name
Test status
Simulation time 7149472226 ps
CPU time 34.68 seconds
Started Mar 28 12:40:49 PM PDT 24
Finished Mar 28 12:41:24 PM PDT 24
Peak memory 212804 kb
Host smart-39a41593-aaa0-443c-a2fd-17bdd8a45a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127978349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4127978349
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1586824881
Short name T645
Test name
Test status
Simulation time 43682156096 ps
CPU time 493.37 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 01:00:07 PM PDT 24
Peak memory 217380 kb
Host smart-04c079ec-24f7-4898-9d4d-b8734d715fa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586824881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1586824881
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2638836141
Short name T398
Test name
Test status
Simulation time 21591362150 ps
CPU time 318.37 seconds
Started Mar 28 12:40:41 PM PDT 24
Finished Mar 28 12:46:00 PM PDT 24
Peak memory 226244 kb
Host smart-9e4049a0-580d-4db8-9e4b-1df04e8c93d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638836141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2638836141
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3372376899
Short name T555
Test name
Test status
Simulation time 13179059101 ps
CPU time 60.52 seconds
Started Mar 28 12:51:42 PM PDT 24
Finished Mar 28 12:52:43 PM PDT 24
Peak memory 215596 kb
Host smart-11fda4e5-012f-4fbd-b62a-749599500eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372376899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3372376899
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3779337283
Short name T167
Test name
Test status
Simulation time 6071103776 ps
CPU time 54.82 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:34 PM PDT 24
Peak memory 215656 kb
Host smart-f049bd06-45bd-4136-914b-bfa70c6f3b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779337283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3779337283
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2786605519
Short name T383
Test name
Test status
Simulation time 360952660 ps
CPU time 10.3 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:51:59 PM PDT 24
Peak memory 212764 kb
Host smart-9ff74d60-55c4-46ca-a483-544cf13bead0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786605519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2786605519
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2925856900
Short name T227
Test name
Test status
Simulation time 3203638721 ps
CPU time 18.99 seconds
Started Mar 28 12:40:40 PM PDT 24
Finished Mar 28 12:40:59 PM PDT 24
Peak memory 212796 kb
Host smart-3182333d-8d57-4822-bd0d-cafb2c4311e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925856900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2925856900
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4218137974
Short name T668
Test name
Test status
Simulation time 876041654 ps
CPU time 26.13 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:06 PM PDT 24
Peak memory 215264 kb
Host smart-f7159aa0-ad02-4ca4-8f2a-e3e399de386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218137974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4218137974
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.961882188
Short name T553
Test name
Test status
Simulation time 14065822354 ps
CPU time 68.26 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:53:01 PM PDT 24
Peak memory 219512 kb
Host smart-2298b4c6-54cf-456c-ba39-2e0c647ca923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961882188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.961882188
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1008522493
Short name T385
Test name
Test status
Simulation time 14905733696 ps
CPU time 103.18 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:53:35 PM PDT 24
Peak memory 219964 kb
Host smart-3cf0fd31-96c9-427b-990b-f63ce3ab3925
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008522493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1008522493
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4169221950
Short name T572
Test name
Test status
Simulation time 1428214370 ps
CPU time 21.28 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:00 PM PDT 24
Peak memory 218812 kb
Host smart-f32ad49a-6d90-4ebd-a4fa-0cdb9eafbb6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169221950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4169221950
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2784599439
Short name T657
Test name
Test status
Simulation time 474302615413 ps
CPU time 1711.15 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 01:09:11 PM PDT 24
Peak memory 237276 kb
Host smart-6abb2527-c0d3-432d-9316-b2b2c6eaf088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784599439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2784599439
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1313075245
Short name T469
Test name
Test status
Simulation time 8207931119 ps
CPU time 32.24 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:12 PM PDT 24
Peak memory 212748 kb
Host smart-e39384a5-29ad-4f5b-9f16-65b2da7bf1e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313075245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1313075245
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4095584741
Short name T501
Test name
Test status
Simulation time 3781045596 ps
CPU time 29.64 seconds
Started Mar 28 12:51:56 PM PDT 24
Finished Mar 28 12:52:27 PM PDT 24
Peak memory 212520 kb
Host smart-de30551d-7891-44e1-853c-c14078e4aa0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095584741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4095584741
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2399220142
Short name T604
Test name
Test status
Simulation time 22351021659 ps
CPU time 366.51 seconds
Started Mar 28 12:51:56 PM PDT 24
Finished Mar 28 12:58:04 PM PDT 24
Peak memory 238516 kb
Host smart-496f7b7f-1272-4977-8dfe-ac77e5aa0ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399220142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2399220142
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4136505082
Short name T234
Test name
Test status
Simulation time 61500592296 ps
CPU time 270.23 seconds
Started Mar 28 12:40:44 PM PDT 24
Finished Mar 28 12:45:15 PM PDT 24
Peak memory 237260 kb
Host smart-a5174ae9-19e4-4b51-af38-390025ff5d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136505082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4136505082
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3418374682
Short name T467
Test name
Test status
Simulation time 67438432055 ps
CPU time 55.3 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:52 PM PDT 24
Peak memory 215640 kb
Host smart-bf37c86d-d3c4-428e-aaf6-afc7bf1eec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418374682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3418374682
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3597365021
Short name T541
Test name
Test status
Simulation time 22585749305 ps
CPU time 53.64 seconds
Started Mar 28 12:40:46 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 215588 kb
Host smart-8f5e6748-5002-4836-b7b8-5cd17226bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597365021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3597365021
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2947867822
Short name T18
Test name
Test status
Simulation time 1079854976 ps
CPU time 17.24 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:15 PM PDT 24
Peak memory 212656 kb
Host smart-939f7ff8-2367-4b83-b513-738d4d78788a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2947867822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2947867822
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.483974443
Short name T355
Test name
Test status
Simulation time 996596475 ps
CPU time 13.18 seconds
Started Mar 28 12:40:44 PM PDT 24
Finished Mar 28 12:40:57 PM PDT 24
Peak memory 211668 kb
Host smart-f704ae39-f894-4c7a-b22b-ca836db6adf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483974443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.483974443
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2853097086
Short name T107
Test name
Test status
Simulation time 8861829622 ps
CPU time 51.24 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 218184 kb
Host smart-aba3a807-c5ea-41dc-a951-bfd11df642b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853097086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2853097086
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.505651239
Short name T658
Test name
Test status
Simulation time 3855365670 ps
CPU time 43.16 seconds
Started Mar 28 12:40:49 PM PDT 24
Finished Mar 28 12:41:33 PM PDT 24
Peak memory 216816 kb
Host smart-bd26f2c3-2928-4020-bda6-3f97e0d2c0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505651239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.505651239
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1587900789
Short name T559
Test name
Test status
Simulation time 29877247680 ps
CPU time 28.25 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:07 PM PDT 24
Peak memory 212296 kb
Host smart-336c34b3-6d8c-4ab9-b8fb-a56a07a6e282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587900789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1587900789
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.987793640
Short name T498
Test name
Test status
Simulation time 33026588497 ps
CPU time 78.65 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:53:09 PM PDT 24
Peak memory 220736 kb
Host smart-1200c524-fe1e-4c65-a0db-ec0169f99e2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987793640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.987793640
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2065529973
Short name T497
Test name
Test status
Simulation time 6071179000 ps
CPU time 25.25 seconds
Started Mar 28 12:40:33 PM PDT 24
Finished Mar 28 12:40:59 PM PDT 24
Peak memory 212660 kb
Host smart-9bf0b05e-e8d7-45e6-a337-3c200fbedb81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065529973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2065529973
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3683435316
Short name T426
Test name
Test status
Simulation time 8248670010 ps
CPU time 20.35 seconds
Started Mar 28 12:51:35 PM PDT 24
Finished Mar 28 12:51:55 PM PDT 24
Peak memory 212912 kb
Host smart-f0963fac-2247-4c37-b953-2fd7d4ce02e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683435316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3683435316
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1390456427
Short name T399
Test name
Test status
Simulation time 525483365437 ps
CPU time 532.32 seconds
Started Mar 28 12:40:29 PM PDT 24
Finished Mar 28 12:49:22 PM PDT 24
Peak memory 237348 kb
Host smart-f1adfbcb-64bc-4ed0-a399-eced16d7084b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390456427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1390456427
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.525511896
Short name T281
Test name
Test status
Simulation time 15947424832 ps
CPU time 257.78 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:56:29 PM PDT 24
Peak memory 220004 kb
Host smart-4526c382-a8bf-46d7-9242-c18c33badb1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525511896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.525511896
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1115158527
Short name T617
Test name
Test status
Simulation time 26585453844 ps
CPU time 46.03 seconds
Started Mar 28 12:51:37 PM PDT 24
Finished Mar 28 12:52:24 PM PDT 24
Peak memory 214552 kb
Host smart-d0e9499f-bada-4758-a034-338786aab441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115158527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1115158527
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2313076691
Short name T326
Test name
Test status
Simulation time 1377652909 ps
CPU time 19.43 seconds
Started Mar 28 12:40:31 PM PDT 24
Finished Mar 28 12:40:50 PM PDT 24
Peak memory 215316 kb
Host smart-a01f060e-e2ba-4a43-a464-58f336bd21a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313076691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2313076691
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3522171106
Short name T64
Test name
Test status
Simulation time 3467788271 ps
CPU time 21.39 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:00 PM PDT 24
Peak memory 213016 kb
Host smart-6aa58aec-61e7-4ca6-ae21-fdc7c83f88ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522171106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3522171106
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3726594074
Short name T172
Test name
Test status
Simulation time 10046087606 ps
CPU time 21.16 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:51:55 PM PDT 24
Peak memory 213476 kb
Host smart-07e8de44-a595-40eb-9270-92da74c3f066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726594074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3726594074
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.120015236
Short name T36
Test name
Test status
Simulation time 15603983295 ps
CPU time 254.57 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:44:53 PM PDT 24
Peak memory 253476 kb
Host smart-83e3e1bb-3513-44e8-85c9-37ed16b312c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120015236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.120015236
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2467791852
Short name T42
Test name
Test status
Simulation time 8004866285 ps
CPU time 139.57 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:53:54 PM PDT 24
Peak memory 237348 kb
Host smart-52e6d90f-7020-49e5-91a1-5859af523720
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467791852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2467791852
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2377782533
Short name T476
Test name
Test status
Simulation time 9739346771 ps
CPU time 64.15 seconds
Started Mar 28 12:51:36 PM PDT 24
Finished Mar 28 12:52:40 PM PDT 24
Peak memory 218868 kb
Host smart-69e60b73-4abf-4211-9e3d-b7c2ee7298ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377782533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2377782533
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2622092473
Short name T400
Test name
Test status
Simulation time 6347364964 ps
CPU time 47.09 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:41:24 PM PDT 24
Peak memory 218004 kb
Host smart-93f6331f-86c9-441f-8bdc-8cb2d0a91a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622092473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2622092473
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3408230223
Short name T403
Test name
Test status
Simulation time 37983560949 ps
CPU time 113.8 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:42:33 PM PDT 24
Peak memory 220664 kb
Host smart-0bb0cbec-a68c-4336-90de-bef0b470a401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408230223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3408230223
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.395876773
Short name T262
Test name
Test status
Simulation time 1054028866 ps
CPU time 30.91 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:05 PM PDT 24
Peak memory 219936 kb
Host smart-63edcc2d-4285-4500-9a5b-01c824c71305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395876773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.395876773
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2907152234
Short name T603
Test name
Test status
Simulation time 2531109566 ps
CPU time 19.73 seconds
Started Mar 28 12:41:10 PM PDT 24
Finished Mar 28 12:41:30 PM PDT 24
Peak memory 212600 kb
Host smart-beb7f20c-1fe7-4cd6-8eaf-69aca8374aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907152234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2907152234
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3074476695
Short name T189
Test name
Test status
Simulation time 613285772 ps
CPU time 8.31 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 12:51:55 PM PDT 24
Peak memory 211924 kb
Host smart-263880be-96e8-41fb-aace-bf3a6ec38ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074476695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3074476695
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3060327047
Short name T527
Test name
Test status
Simulation time 73979632516 ps
CPU time 369.75 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:46:50 PM PDT 24
Peak memory 218296 kb
Host smart-abb4f759-92b6-4623-a947-a0161f177f90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060327047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3060327047
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.806410689
Short name T32
Test name
Test status
Simulation time 3774886379 ps
CPU time 268.03 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:56:22 PM PDT 24
Peak memory 225948 kb
Host smart-6180d6eb-f1bb-4f51-86fc-f2ca723f860e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806410689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.806410689
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1939956070
Short name T163
Test name
Test status
Simulation time 30012579182 ps
CPU time 60.24 seconds
Started Mar 28 12:40:44 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 215604 kb
Host smart-d8ddfc66-3aa6-4870-b9e2-40e5a9643b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939956070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1939956070
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2431219915
Short name T682
Test name
Test status
Simulation time 5612269427 ps
CPU time 36.99 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:33 PM PDT 24
Peak memory 221736 kb
Host smart-359c1b3a-7567-471c-985a-89607cdaf7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431219915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2431219915
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2083679156
Short name T286
Test name
Test status
Simulation time 180305304 ps
CPU time 10.7 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:08 PM PDT 24
Peak memory 212976 kb
Host smart-9e788bfe-c359-40d4-96d6-1ad092cbb1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083679156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2083679156
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3628066724
Short name T294
Test name
Test status
Simulation time 14649768108 ps
CPU time 18.9 seconds
Started Mar 28 12:40:44 PM PDT 24
Finished Mar 28 12:41:03 PM PDT 24
Peak memory 213328 kb
Host smart-6185715c-3959-4f3c-b8cd-0135041f6188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628066724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3628066724
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1958712030
Short name T560
Test name
Test status
Simulation time 23844765627 ps
CPU time 50.14 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 218976 kb
Host smart-4db7aec0-0336-461c-9aec-8db6f474da55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958712030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1958712030
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.662420890
Short name T367
Test name
Test status
Simulation time 1913751281 ps
CPU time 20.02 seconds
Started Mar 28 12:40:42 PM PDT 24
Finished Mar 28 12:41:02 PM PDT 24
Peak memory 217964 kb
Host smart-2ad73aee-05ab-4ce2-a883-7a19048239aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662420890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.662420890
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3455740097
Short name T578
Test name
Test status
Simulation time 12520437788 ps
CPU time 49.17 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:28 PM PDT 24
Peak memory 219896 kb
Host smart-cd8c42a4-227f-4bd7-b4bb-e340b444c8aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455740097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3455740097
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.533744509
Short name T641
Test name
Test status
Simulation time 14650371455 ps
CPU time 80.01 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:53:14 PM PDT 24
Peak memory 219796 kb
Host smart-6f5caff4-5697-41ab-af1d-6ce9668886ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533744509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.533744509
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2604667690
Short name T519
Test name
Test status
Simulation time 1544748242 ps
CPU time 18.25 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:52:08 PM PDT 24
Peak memory 212428 kb
Host smart-3c42e745-de01-4ed7-815e-0e8bcdc37978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604667690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2604667690
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.669342391
Short name T619
Test name
Test status
Simulation time 338408590 ps
CPU time 8.41 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:17 PM PDT 24
Peak memory 211808 kb
Host smart-46c66efc-e562-4d7e-984e-a416c9bdbafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669342391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.669342391
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3383985238
Short name T477
Test name
Test status
Simulation time 13512295760 ps
CPU time 190.03 seconds
Started Mar 28 12:41:05 PM PDT 24
Finished Mar 28 12:44:16 PM PDT 24
Peak memory 228808 kb
Host smart-cf82f2d9-3b88-427a-a273-dfbb46692a91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383985238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3383985238
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.535436284
Short name T204
Test name
Test status
Simulation time 200971455882 ps
CPU time 474.88 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:59:48 PM PDT 24
Peak memory 239824 kb
Host smart-1bfbf3c9-45c1-47ba-ad1f-dfc3a7ac2643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535436284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.535436284
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1796756385
Short name T552
Test name
Test status
Simulation time 14875809652 ps
CPU time 40.73 seconds
Started Mar 28 12:41:04 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 214544 kb
Host smart-322937d0-810a-434c-a83c-a9f818a38099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796756385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1796756385
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2624312509
Short name T486
Test name
Test status
Simulation time 8144850393 ps
CPU time 64.06 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:59 PM PDT 24
Peak memory 215544 kb
Host smart-df9a0b38-c4fe-4c30-90ac-a31f43faa317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624312509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2624312509
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2013930395
Short name T472
Test name
Test status
Simulation time 5768072447 ps
CPU time 33.68 seconds
Started Mar 28 12:41:03 PM PDT 24
Finished Mar 28 12:41:37 PM PDT 24
Peak memory 213140 kb
Host smart-79818d24-7770-433c-964b-6c177d7e1be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013930395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2013930395
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2290893036
Short name T45
Test name
Test status
Simulation time 3727767948 ps
CPU time 30.94 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:25 PM PDT 24
Peak memory 211764 kb
Host smart-cbb9ffbe-51e8-4d6c-a48f-070b39214fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290893036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2290893036
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.308365693
Short name T296
Test name
Test status
Simulation time 7229871273 ps
CPU time 69.39 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:42:18 PM PDT 24
Peak memory 217732 kb
Host smart-babe3978-e7d2-4aa3-915a-7ecf190ead61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308365693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.308365693
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3964341778
Short name T516
Test name
Test status
Simulation time 2098654891 ps
CPU time 34.1 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 217044 kb
Host smart-f760338c-f804-464f-81d4-1d0e163ae948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964341778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3964341778
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1628670762
Short name T549
Test name
Test status
Simulation time 815655219 ps
CPU time 27.87 seconds
Started Mar 28 12:41:10 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 215800 kb
Host smart-29e99411-dbe9-4761-8f67-fd797b2cc16f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628670762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1628670762
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.768506034
Short name T212
Test name
Test status
Simulation time 3024655497 ps
CPU time 46.62 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:40 PM PDT 24
Peak memory 217248 kb
Host smart-5b81106b-16f5-4062-a8e7-f2c788c2615b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768506034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.768506034
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.173587164
Short name T317
Test name
Test status
Simulation time 2885013297 ps
CPU time 25.1 seconds
Started Mar 28 12:51:56 PM PDT 24
Finished Mar 28 12:52:23 PM PDT 24
Peak memory 212512 kb
Host smart-0695c841-3aa3-4ab1-a3c9-4e764ca9ba89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173587164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.173587164
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1781760448
Short name T401
Test name
Test status
Simulation time 1032036180 ps
CPU time 10.05 seconds
Started Mar 28 12:41:05 PM PDT 24
Finished Mar 28 12:41:15 PM PDT 24
Peak memory 211808 kb
Host smart-d243b1c9-0ab6-481c-95ad-3154cedc2287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781760448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1781760448
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1084076539
Short name T177
Test name
Test status
Simulation time 130310174929 ps
CPU time 312.73 seconds
Started Mar 28 12:41:16 PM PDT 24
Finished Mar 28 12:46:28 PM PDT 24
Peak memory 217232 kb
Host smart-32fc78a2-8960-4727-94f6-0ee0c8b81c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084076539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1084076539
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1234134727
Short name T274
Test name
Test status
Simulation time 474932542873 ps
CPU time 502.53 seconds
Started Mar 28 12:51:57 PM PDT 24
Finished Mar 28 01:00:20 PM PDT 24
Peak memory 234292 kb
Host smart-2b0668ae-d38a-4454-bae3-8171981e23ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234134727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1234134727
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1371147084
Short name T636
Test name
Test status
Simulation time 8373182844 ps
CPU time 66.69 seconds
Started Mar 28 12:41:06 PM PDT 24
Finished Mar 28 12:42:13 PM PDT 24
Peak memory 215756 kb
Host smart-e0596ad5-22f9-4ef4-bad0-09387b15505a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371147084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1371147084
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1392905717
Short name T624
Test name
Test status
Simulation time 22203695423 ps
CPU time 55.03 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:52:45 PM PDT 24
Peak memory 214548 kb
Host smart-8561980f-b8b4-4a15-891a-10fe912259fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392905717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1392905717
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.103083812
Short name T611
Test name
Test status
Simulation time 1719394422 ps
CPU time 10.27 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:18 PM PDT 24
Peak memory 212180 kb
Host smart-8c4afcb0-e97e-40a4-9c74-08ea2a2b7838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103083812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.103083812
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2564429725
Short name T584
Test name
Test status
Simulation time 81159952406 ps
CPU time 33.28 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:30 PM PDT 24
Peak memory 212280 kb
Host smart-36e19430-3693-41da-a541-49592c70a336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564429725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2564429725
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2710557483
Short name T407
Test name
Test status
Simulation time 5842537582 ps
CPU time 66.31 seconds
Started Mar 28 12:41:07 PM PDT 24
Finished Mar 28 12:42:14 PM PDT 24
Peak memory 218644 kb
Host smart-d54fdd7d-3fb4-49ab-8b1c-d3a50bff9b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710557483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2710557483
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2918766423
Short name T304
Test name
Test status
Simulation time 5739783811 ps
CPU time 65.76 seconds
Started Mar 28 12:51:48 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 217932 kb
Host smart-4c58f2f3-4296-4386-b630-376f53bd5625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918766423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2918766423
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2681801473
Short name T363
Test name
Test status
Simulation time 33078243427 ps
CPU time 61.76 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:42:11 PM PDT 24
Peak memory 219456 kb
Host smart-7c37222a-29c1-462a-b78a-81597e54bfba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681801473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2681801473
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.529235540
Short name T495
Test name
Test status
Simulation time 538480665 ps
CPU time 34.38 seconds
Started Mar 28 12:51:44 PM PDT 24
Finished Mar 28 12:52:19 PM PDT 24
Peak memory 218084 kb
Host smart-188e664f-acab-484a-9b6c-6c5c23b1a796
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529235540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.529235540
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3581642923
Short name T683
Test name
Test status
Simulation time 3685787639 ps
CPU time 22.8 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:31 PM PDT 24
Peak memory 212508 kb
Host smart-65e6afe0-78a8-43c3-82f1-e1c3af54ee2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581642923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3581642923
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.439628482
Short name T368
Test name
Test status
Simulation time 5227516389 ps
CPU time 22.7 seconds
Started Mar 28 12:51:57 PM PDT 24
Finished Mar 28 12:52:20 PM PDT 24
Peak memory 211664 kb
Host smart-0be0ed92-3b64-4152-9861-489d0d9b91c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439628482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.439628482
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1471565895
Short name T308
Test name
Test status
Simulation time 67644899185 ps
CPU time 312.34 seconds
Started Mar 28 12:41:04 PM PDT 24
Finished Mar 28 12:46:17 PM PDT 24
Peak memory 238044 kb
Host smart-e0e69e87-2edf-43e8-8e94-c81d78e12103
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471565895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1471565895
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1970478665
Short name T457
Test name
Test status
Simulation time 12554473757 ps
CPU time 224.11 seconds
Started Mar 28 12:51:45 PM PDT 24
Finished Mar 28 12:55:29 PM PDT 24
Peak memory 241192 kb
Host smart-34aa854f-e239-405c-8af5-683518721ae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970478665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1970478665
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1739645700
Short name T546
Test name
Test status
Simulation time 84395921990 ps
CPU time 56.04 seconds
Started Mar 28 12:51:56 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 215244 kb
Host smart-87360a84-7d0b-43b7-aa74-14e461119f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739645700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1739645700
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2127380528
Short name T259
Test name
Test status
Simulation time 11972428883 ps
CPU time 47.22 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 12:41:59 PM PDT 24
Peak memory 215608 kb
Host smart-6476962e-dc6c-4d27-a267-96c96fa2cda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127380528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2127380528
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3351890743
Short name T562
Test name
Test status
Simulation time 5060566621 ps
CPU time 17.76 seconds
Started Mar 28 12:51:56 PM PDT 24
Finished Mar 28 12:52:15 PM PDT 24
Peak memory 213316 kb
Host smart-661df537-939f-4b08-85d9-32741ddf5df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351890743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3351890743
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4043120977
Short name T577
Test name
Test status
Simulation time 6204743202 ps
CPU time 27.99 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:37 PM PDT 24
Peak memory 213452 kb
Host smart-43b11922-8047-4525-b68b-1cbfc6acaa38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043120977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4043120977
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3126714502
Short name T576
Test name
Test status
Simulation time 3015386858 ps
CPU time 29.87 seconds
Started Mar 28 12:51:57 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 216212 kb
Host smart-fdd152e3-f69e-475b-9885-904ea6c1a916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126714502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3126714502
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.787834587
Short name T184
Test name
Test status
Simulation time 7214699568 ps
CPU time 61.52 seconds
Started Mar 28 12:41:04 PM PDT 24
Finished Mar 28 12:42:06 PM PDT 24
Peak memory 218640 kb
Host smart-ff7e41e7-f926-4c51-8976-5490f11cd60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787834587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.787834587
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1754878567
Short name T436
Test name
Test status
Simulation time 15213093418 ps
CPU time 163.66 seconds
Started Mar 28 12:41:06 PM PDT 24
Finished Mar 28 12:43:50 PM PDT 24
Peak memory 222080 kb
Host smart-ea2f2386-e839-409f-9a36-140f2e7082f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754878567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1754878567
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.784066949
Short name T506
Test name
Test status
Simulation time 660303834 ps
CPU time 9.92 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:06 PM PDT 24
Peak memory 213028 kb
Host smart-975cdeea-bc3d-476d-9646-8b11a71ba7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784066949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.784066949
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3498433124
Short name T341
Test name
Test status
Simulation time 3130369462 ps
CPU time 26.46 seconds
Started Mar 28 12:41:10 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 211984 kb
Host smart-04e7fc0a-0436-47b4-b603-3d6345599c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498433124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3498433124
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.578500637
Short name T252
Test name
Test status
Simulation time 174248333 ps
CPU time 8.23 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:51:59 PM PDT 24
Peak memory 211896 kb
Host smart-caf3de51-2262-43a9-b99a-80a4806209ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578500637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.578500637
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1364057895
Short name T113
Test name
Test status
Simulation time 196080093938 ps
CPU time 922.21 seconds
Started Mar 28 12:41:07 PM PDT 24
Finished Mar 28 12:56:30 PM PDT 24
Peak memory 229504 kb
Host smart-3b338045-8d34-46e5-a1e9-827f17ed24ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364057895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1364057895
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2087192484
Short name T593
Test name
Test status
Simulation time 71681995484 ps
CPU time 395.86 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:58:27 PM PDT 24
Peak memory 230288 kb
Host smart-be69c013-a249-4729-8b09-2621a9ad3f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087192484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2087192484
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2516815486
Short name T646
Test name
Test status
Simulation time 7686679622 ps
CPU time 63.18 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:53:00 PM PDT 24
Peak memory 215616 kb
Host smart-9f3a31af-80e3-4fd2-bd69-5574e4d45698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516815486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2516815486
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2533640098
Short name T463
Test name
Test status
Simulation time 17375329359 ps
CPU time 36.27 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 215688 kb
Host smart-a6c78df9-21e4-45a3-a6f4-5d0669f1cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533640098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2533640098
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1073648625
Short name T671
Test name
Test status
Simulation time 10270888408 ps
CPU time 26.58 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:35 PM PDT 24
Peak memory 212108 kb
Host smart-b755308a-75c0-48a7-9239-d25375244bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073648625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1073648625
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2885186952
Short name T625
Test name
Test status
Simulation time 187371446 ps
CPU time 10.58 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:07 PM PDT 24
Peak memory 211820 kb
Host smart-ba512cad-5cf8-4b00-9edf-1cd3f640b1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885186952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2885186952
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1926997465
Short name T404
Test name
Test status
Simulation time 702837535 ps
CPU time 24.57 seconds
Started Mar 28 12:41:06 PM PDT 24
Finished Mar 28 12:41:31 PM PDT 24
Peak memory 217716 kb
Host smart-a3e9e34f-164e-4ab4-b62f-b71d5d985e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926997465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1926997465
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.530227933
Short name T49
Test name
Test status
Simulation time 4922691750 ps
CPU time 19.99 seconds
Started Mar 28 12:51:57 PM PDT 24
Finished Mar 28 12:52:18 PM PDT 24
Peak memory 217440 kb
Host smart-6da5b461-6931-41a2-b397-69fd6134a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530227933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.530227933
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1497389737
Short name T453
Test name
Test status
Simulation time 17742891003 ps
CPU time 46.92 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:56 PM PDT 24
Peak memory 214612 kb
Host smart-999f14e2-5158-422d-9398-4db44a086964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497389737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1497389737
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.742608550
Short name T295
Test name
Test status
Simulation time 98706482983 ps
CPU time 94.08 seconds
Started Mar 28 12:51:48 PM PDT 24
Finished Mar 28 12:53:23 PM PDT 24
Peak memory 219968 kb
Host smart-c483c524-9846-413e-ba4e-541e71dc3057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742608550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.742608550
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2443175275
Short name T481
Test name
Test status
Simulation time 2061034371 ps
CPU time 20.23 seconds
Started Mar 28 12:51:48 PM PDT 24
Finished Mar 28 12:52:09 PM PDT 24
Peak memory 211904 kb
Host smart-fcbac227-0638-42da-9e15-077328ee7b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443175275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2443175275
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3914399494
Short name T269
Test name
Test status
Simulation time 14301137423 ps
CPU time 22.06 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:31 PM PDT 24
Peak memory 212836 kb
Host smart-60875978-1164-41b0-8274-278369d6375c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914399494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3914399494
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1224178994
Short name T146
Test name
Test status
Simulation time 237285657875 ps
CPU time 367.5 seconds
Started Mar 28 12:51:51 PM PDT 24
Finished Mar 28 12:57:58 PM PDT 24
Peak memory 229576 kb
Host smart-f98963dd-4230-4856-a2a2-c90c49735694
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224178994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1224178994
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.288033782
Short name T289
Test name
Test status
Simulation time 14903737672 ps
CPU time 59.51 seconds
Started Mar 28 12:41:07 PM PDT 24
Finished Mar 28 12:42:06 PM PDT 24
Peak memory 215392 kb
Host smart-e77a5015-7872-461a-85ed-8f61badf55bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288033782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.288033782
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.728885252
Short name T676
Test name
Test status
Simulation time 24971237184 ps
CPU time 58.48 seconds
Started Mar 28 12:51:50 PM PDT 24
Finished Mar 28 12:52:49 PM PDT 24
Peak memory 215600 kb
Host smart-0cf6e097-b13c-4294-9489-d8d11918b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728885252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.728885252
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.106402584
Short name T270
Test name
Test status
Simulation time 3450485700 ps
CPU time 30.91 seconds
Started Mar 28 12:51:57 PM PDT 24
Finished Mar 28 12:52:29 PM PDT 24
Peak memory 212148 kb
Host smart-7bd45c35-9b59-4ea3-bd2c-b5c7d7ba34b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106402584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.106402584
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.770101337
Short name T558
Test name
Test status
Simulation time 1331263164 ps
CPU time 10.19 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:18 PM PDT 24
Peak memory 213116 kb
Host smart-46d11485-dc07-4dcd-8924-cdc6bbeac8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770101337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.770101337
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2890722730
Short name T53
Test name
Test status
Simulation time 25160996441 ps
CPU time 62.07 seconds
Started Mar 28 12:51:51 PM PDT 24
Finished Mar 28 12:52:53 PM PDT 24
Peak memory 219160 kb
Host smart-cbfdeaf7-f394-421d-86b7-d6af2e92701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890722730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2890722730
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.539265206
Short name T543
Test name
Test status
Simulation time 3652892584 ps
CPU time 35.26 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 217492 kb
Host smart-4fa7d403-10de-4d98-ba31-49086ec56079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539265206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.539265206
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2722605269
Short name T429
Test name
Test status
Simulation time 16962703735 ps
CPU time 140.31 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:43:34 PM PDT 24
Peak memory 222028 kb
Host smart-044f5ac5-07e3-47bf-b719-a6a10c1ee056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722605269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2722605269
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3188360960
Short name T612
Test name
Test status
Simulation time 2530504205 ps
CPU time 48.73 seconds
Started Mar 28 12:51:51 PM PDT 24
Finished Mar 28 12:52:40 PM PDT 24
Peak memory 219936 kb
Host smart-93e5160c-96fa-445b-b1a9-16da1f9fd7e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188360960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3188360960
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3911607193
Short name T438
Test name
Test status
Simulation time 49560079921 ps
CPU time 472.19 seconds
Started Mar 28 12:41:07 PM PDT 24
Finished Mar 28 12:48:59 PM PDT 24
Peak memory 236436 kb
Host smart-86bcf915-b06a-4e54-8181-b362505f9af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911607193 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3911607193
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1244481933
Short name T425
Test name
Test status
Simulation time 9221115771 ps
CPU time 22.01 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:18 PM PDT 24
Peak memory 213004 kb
Host smart-3fdb5027-33bb-4c3b-9f40-d21766a31883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244481933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1244481933
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3107276254
Short name T601
Test name
Test status
Simulation time 1081164850 ps
CPU time 15.48 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:24 PM PDT 24
Peak memory 211732 kb
Host smart-702c9566-b61f-46b9-8099-686989dd5121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107276254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3107276254
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1076381266
Short name T630
Test name
Test status
Simulation time 9273588630 ps
CPU time 293.68 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:46:02 PM PDT 24
Peak memory 239660 kb
Host smart-8e45c0fe-e66e-4110-9fd4-9e06bae76a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076381266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1076381266
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.138917878
Short name T574
Test name
Test status
Simulation time 81299584980 ps
CPU time 403.05 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:58:39 PM PDT 24
Peak memory 238084 kb
Host smart-fa058390-2bf9-4d12-ba33-b756dda8c196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138917878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.138917878
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1194926634
Short name T272
Test name
Test status
Simulation time 10929374361 ps
CPU time 40.83 seconds
Started Mar 28 12:51:53 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 215496 kb
Host smart-973faee4-2be7-435b-8faf-23192b1cf9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194926634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1194926634
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.822702213
Short name T669
Test name
Test status
Simulation time 55754164804 ps
CPU time 68.11 seconds
Started Mar 28 12:41:04 PM PDT 24
Finished Mar 28 12:42:13 PM PDT 24
Peak memory 215856 kb
Host smart-3e5a4d6f-ed52-4122-a1ed-b7427db1c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822702213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.822702213
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2120614996
Short name T149
Test name
Test status
Simulation time 29351328499 ps
CPU time 32.9 seconds
Started Mar 28 12:41:07 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 212388 kb
Host smart-c7df92ab-1690-4856-8555-dc0f9b9eb1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120614996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2120614996
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.516158692
Short name T673
Test name
Test status
Simulation time 434776752 ps
CPU time 13.63 seconds
Started Mar 28 12:51:52 PM PDT 24
Finished Mar 28 12:52:06 PM PDT 24
Peak memory 211748 kb
Host smart-cf1bb2ae-97ce-4131-930a-77a0ea0ed892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516158692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.516158692
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2134496739
Short name T235
Test name
Test status
Simulation time 36829324150 ps
CPU time 46.9 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:43 PM PDT 24
Peak memory 218360 kb
Host smart-de9056fc-7c08-4d7f-bafd-58a706b1c56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134496739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2134496739
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3496534238
Short name T684
Test name
Test status
Simulation time 4658477954 ps
CPU time 29.18 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 217960 kb
Host smart-9e76a26d-6837-4b8f-965e-58c0a1b2eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496534238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3496534238
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1648665413
Short name T614
Test name
Test status
Simulation time 22171612912 ps
CPU time 39.58 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:47 PM PDT 24
Peak memory 219544 kb
Host smart-193b3ea2-71c4-42c9-b16a-cd2f90f0b539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648665413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1648665413
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.485357288
Short name T87
Test name
Test status
Simulation time 4386048245 ps
CPU time 28.89 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:52:25 PM PDT 24
Peak memory 214180 kb
Host smart-ef5e33ed-d6d7-4522-95d9-c7f44ddc8f40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485357288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.485357288
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1300046933
Short name T587
Test name
Test status
Simulation time 971496905 ps
CPU time 10.46 seconds
Started Mar 28 12:52:12 PM PDT 24
Finished Mar 28 12:52:23 PM PDT 24
Peak memory 211856 kb
Host smart-da13f66b-c6d2-4b39-afc5-f1e0f8ddd5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300046933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1300046933
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3779712232
Short name T24
Test name
Test status
Simulation time 332348414 ps
CPU time 8.28 seconds
Started Mar 28 12:41:10 PM PDT 24
Finished Mar 28 12:41:18 PM PDT 24
Peak memory 211648 kb
Host smart-2de19bc4-aa42-42bb-8243-541ce31258d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779712232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3779712232
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3841833080
Short name T597
Test name
Test status
Simulation time 121944952735 ps
CPU time 386.93 seconds
Started Mar 28 12:41:07 PM PDT 24
Finished Mar 28 12:47:34 PM PDT 24
Peak memory 240360 kb
Host smart-f930c6bf-ad5d-4130-9dfb-8ce095cf1b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841833080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3841833080
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2608210439
Short name T199
Test name
Test status
Simulation time 25047833501 ps
CPU time 48.57 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 214664 kb
Host smart-10f14ac3-dc42-41f1-ab89-b8bb32c4e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608210439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2608210439
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3697383030
Short name T661
Test name
Test status
Simulation time 6841515717 ps
CPU time 40.23 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 215720 kb
Host smart-293d434a-c5fb-4ce2-9e5e-244903c717f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697383030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3697383030
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.383214715
Short name T238
Test name
Test status
Simulation time 2464796415 ps
CPU time 10.18 seconds
Started Mar 28 12:51:55 PM PDT 24
Finished Mar 28 12:52:07 PM PDT 24
Peak memory 213172 kb
Host smart-735425b6-4bc6-494f-a59b-dca4438b6fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383214715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.383214715
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4016507439
Short name T448
Test name
Test status
Simulation time 1997529786 ps
CPU time 13.98 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:23 PM PDT 24
Peak memory 211780 kb
Host smart-324c45ab-6334-4a0b-a3a3-9ec72e8366ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016507439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4016507439
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2343032115
Short name T479
Test name
Test status
Simulation time 15200090244 ps
CPU time 52.95 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:42:02 PM PDT 24
Peak memory 218736 kb
Host smart-db012b16-f3ed-4b2a-bfd2-11cc20d426dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343032115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2343032115
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.976498329
Short name T580
Test name
Test status
Simulation time 6744650305 ps
CPU time 66.44 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:53:03 PM PDT 24
Peak memory 215572 kb
Host smart-0898b810-da69-4bc2-a2ae-f0837d8836a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976498329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.976498329
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2006677739
Short name T647
Test name
Test status
Simulation time 63136170076 ps
CPU time 135.53 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:43:24 PM PDT 24
Peak memory 219908 kb
Host smart-a5437008-54e1-45a6-a0ab-3dab2b2396cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006677739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2006677739
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2747485626
Short name T228
Test name
Test status
Simulation time 7901933466 ps
CPU time 65.46 seconds
Started Mar 28 12:51:54 PM PDT 24
Finished Mar 28 12:53:01 PM PDT 24
Peak memory 219932 kb
Host smart-2a591e5c-e4ec-492d-9cc7-b40f48b16b80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747485626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2747485626
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1241660994
Short name T649
Test name
Test status
Simulation time 5117072666 ps
CPU time 17.83 seconds
Started Mar 28 12:52:10 PM PDT 24
Finished Mar 28 12:52:29 PM PDT 24
Peak memory 212036 kb
Host smart-dcda9465-5fc2-4c2b-839c-01f498635d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241660994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1241660994
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3242562906
Short name T432
Test name
Test status
Simulation time 3880302116 ps
CPU time 31.56 seconds
Started Mar 28 12:41:10 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 212460 kb
Host smart-69f2b17a-3c4f-446a-93d7-cd663daafe96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242562906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3242562906
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1165319717
Short name T248
Test name
Test status
Simulation time 110485996882 ps
CPU time 615.19 seconds
Started Mar 28 12:52:08 PM PDT 24
Finished Mar 28 01:02:23 PM PDT 24
Peak memory 240440 kb
Host smart-1d55810c-0d72-44bc-808e-71c3a626997d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165319717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1165319717
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1454056213
Short name T525
Test name
Test status
Simulation time 203066734213 ps
CPU time 496.12 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:49:24 PM PDT 24
Peak memory 216340 kb
Host smart-d13cd9d0-b793-4719-9dbf-ae3f8406b0e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454056213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1454056213
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3017276244
Short name T526
Test name
Test status
Simulation time 2221954883 ps
CPU time 34.19 seconds
Started Mar 28 12:52:10 PM PDT 24
Finished Mar 28 12:52:44 PM PDT 24
Peak memory 215364 kb
Host smart-1276c16c-3c00-416b-9163-8233ecd74d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017276244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3017276244
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3664858922
Short name T485
Test name
Test status
Simulation time 1434337095 ps
CPU time 20.44 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:30 PM PDT 24
Peak memory 215104 kb
Host smart-49e35af8-d258-4ea2-90ff-13f9265799da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664858922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3664858922
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1941537067
Short name T14
Test name
Test status
Simulation time 4132119502 ps
CPU time 21.72 seconds
Started Mar 28 12:41:11 PM PDT 24
Finished Mar 28 12:41:32 PM PDT 24
Peak memory 212104 kb
Host smart-f75dccbc-272a-40f6-994f-add982eee856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941537067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1941537067
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4147281385
Short name T165
Test name
Test status
Simulation time 3790819133 ps
CPU time 16 seconds
Started Mar 28 12:52:07 PM PDT 24
Finished Mar 28 12:52:24 PM PDT 24
Peak memory 212848 kb
Host smart-db88c1d2-fe86-4280-9809-1dc69c2cf294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147281385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4147281385
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2035568684
Short name T242
Test name
Test status
Simulation time 6166327286 ps
CPU time 55.69 seconds
Started Mar 28 12:41:11 PM PDT 24
Finished Mar 28 12:42:07 PM PDT 24
Peak memory 218832 kb
Host smart-01f2c911-e316-4345-8978-973382e4a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035568684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2035568684
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.522505102
Short name T433
Test name
Test status
Simulation time 17446723755 ps
CPU time 88.67 seconds
Started Mar 28 12:52:07 PM PDT 24
Finished Mar 28 12:53:36 PM PDT 24
Peak memory 217572 kb
Host smart-ed7c3f6e-ffae-4e71-a44b-2bc98e04b868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522505102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.522505102
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1256236863
Short name T565
Test name
Test status
Simulation time 26376582965 ps
CPU time 79.86 seconds
Started Mar 28 12:52:13 PM PDT 24
Finished Mar 28 12:53:33 PM PDT 24
Peak memory 219924 kb
Host smart-9ef2e7c3-8bcc-4367-99ef-8c1040c74203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256236863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1256236863
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.89132422
Short name T156
Test name
Test status
Simulation time 1323911690 ps
CPU time 30.34 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 217508 kb
Host smart-28a284f7-2fdd-4003-8973-c9f0f7c5bc2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89132422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.rom_ctrl_stress_all.89132422
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1574083439
Short name T60
Test name
Test status
Simulation time 117478077747 ps
CPU time 1358.27 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 01:03:51 PM PDT 24
Peak memory 236376 kb
Host smart-9a347325-68c9-48bd-b5d9-9e34dfd77aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574083439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1574083439
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2140362220
Short name T297
Test name
Test status
Simulation time 11202667511 ps
CPU time 27 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 212800 kb
Host smart-01f2d9c5-5f60-4644-85b5-d0c6844e965f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140362220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2140362220
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.230056918
Short name T114
Test name
Test status
Simulation time 2720010569 ps
CPU time 24.18 seconds
Started Mar 28 12:52:07 PM PDT 24
Finished Mar 28 12:52:31 PM PDT 24
Peak memory 212436 kb
Host smart-8338db4f-4b75-464c-bed7-a7abd7037115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230056918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.230056918
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1038327357
Short name T226
Test name
Test status
Simulation time 304725860869 ps
CPU time 290.39 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:46:04 PM PDT 24
Peak memory 249644 kb
Host smart-2881a465-1b0d-4108-b269-7112ef57df54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038327357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1038327357
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.94459778
Short name T674
Test name
Test status
Simulation time 44872742910 ps
CPU time 608.58 seconds
Started Mar 28 12:52:10 PM PDT 24
Finished Mar 28 01:02:19 PM PDT 24
Peak memory 218808 kb
Host smart-e5899e8d-05d3-4882-9d7b-79cadfbae012
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94459778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_co
rrupt_sig_fatal_chk.94459778
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2697936744
Short name T589
Test name
Test status
Simulation time 15777183969 ps
CPU time 43.41 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:52:53 PM PDT 24
Peak memory 215660 kb
Host smart-2450b078-6e66-426e-b588-bbdc844f2f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697936744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2697936744
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.75857303
Short name T150
Test name
Test status
Simulation time 58596837275 ps
CPU time 45.11 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 12:41:58 PM PDT 24
Peak memory 215588 kb
Host smart-409f6f20-b315-415a-a789-bb6dd9cd926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75857303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.75857303
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1053410657
Short name T384
Test name
Test status
Simulation time 3505847694 ps
CPU time 30.1 seconds
Started Mar 28 12:41:10 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 211896 kb
Host smart-3a51d23c-6aab-4ca7-b56f-077da286e035
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1053410657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1053410657
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2154532511
Short name T271
Test name
Test status
Simulation time 191272729 ps
CPU time 10.84 seconds
Started Mar 28 12:52:10 PM PDT 24
Finished Mar 28 12:52:21 PM PDT 24
Peak memory 213108 kb
Host smart-17c3f1bc-f1fb-437e-9c13-75dba0f46dbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154532511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2154532511
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3597964639
Short name T499
Test name
Test status
Simulation time 834752094 ps
CPU time 25.26 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 12:41:38 PM PDT 24
Peak memory 215104 kb
Host smart-c0b51a2f-436e-4a03-ae32-d757e720820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597964639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3597964639
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.416504444
Short name T191
Test name
Test status
Simulation time 26745610511 ps
CPU time 60.47 seconds
Started Mar 28 12:52:06 PM PDT 24
Finished Mar 28 12:53:07 PM PDT 24
Peak memory 214976 kb
Host smart-dbcf6995-5009-4157-8511-8e1624da04d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416504444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.416504444
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1614137085
Short name T348
Test name
Test status
Simulation time 3624394867 ps
CPU time 32.86 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 218640 kb
Host smart-245a375e-0a8a-4b81-b5df-949475222303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614137085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1614137085
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1669392208
Short name T16
Test name
Test status
Simulation time 1343470627 ps
CPU time 29.81 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:52:41 PM PDT 24
Peak memory 217592 kb
Host smart-981ceb3c-2766-4e8a-b0d0-d053b48a4238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669392208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1669392208
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2773584576
Short name T127
Test name
Test status
Simulation time 268031515103 ps
CPU time 2512.23 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 01:23:05 PM PDT 24
Peak memory 244692 kb
Host smart-9cd90140-5bab-4a1a-92a8-cde3720aaed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773584576 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2773584576
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2802287048
Short name T62
Test name
Test status
Simulation time 23226790183 ps
CPU time 945.37 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 01:07:54 PM PDT 24
Peak memory 234604 kb
Host smart-cdfa74c4-5a8f-4494-b5c4-00e39eae06da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802287048 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2802287048
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1539544500
Short name T507
Test name
Test status
Simulation time 751151728 ps
CPU time 8.27 seconds
Started Mar 28 12:51:37 PM PDT 24
Finished Mar 28 12:51:45 PM PDT 24
Peak memory 211928 kb
Host smart-be59c3cd-0ca7-4ca1-8d66-9bb6b746ac42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539544500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1539544500
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.690939735
Short name T174
Test name
Test status
Simulation time 68872174095 ps
CPU time 32.19 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:12 PM PDT 24
Peak memory 212820 kb
Host smart-c17625b5-016d-43c2-9124-125b539ef31f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690939735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.690939735
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1424573850
Short name T395
Test name
Test status
Simulation time 27170775990 ps
CPU time 254.66 seconds
Started Mar 28 12:40:33 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 240360 kb
Host smart-0094e0f9-e987-4c7d-8b0f-3fd73d9ccfca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424573850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1424573850
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3774965281
Short name T109
Test name
Test status
Simulation time 86798183338 ps
CPU time 438.98 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:58:52 PM PDT 24
Peak memory 238608 kb
Host smart-fc5f443c-7172-425e-bbca-55ed072860f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774965281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3774965281
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1155626594
Short name T188
Test name
Test status
Simulation time 6238237062 ps
CPU time 54.66 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:35 PM PDT 24
Peak memory 216244 kb
Host smart-97ace0fa-6eb1-48c1-b358-3114a1583c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155626594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1155626594
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.397800022
Short name T168
Test name
Test status
Simulation time 6970393590 ps
CPU time 59.94 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:34 PM PDT 24
Peak memory 215516 kb
Host smart-11a1fa8f-a4e4-460a-b634-93532ead1016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397800022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.397800022
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2362139561
Short name T522
Test name
Test status
Simulation time 586413439 ps
CPU time 13.77 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:40:52 PM PDT 24
Peak memory 212680 kb
Host smart-baf1784f-7a1b-4135-9614-d27ffafd027a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362139561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2362139561
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.553125860
Short name T430
Test name
Test status
Simulation time 13185276766 ps
CPU time 30.09 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:04 PM PDT 24
Peak memory 211848 kb
Host smart-87eb1fc8-c1ab-4d76-8011-3d96c4adb83b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553125860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.553125860
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.521390711
Short name T38
Test name
Test status
Simulation time 3165628287 ps
CPU time 243.61 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:44:42 PM PDT 24
Peak memory 237292 kb
Host smart-7bba03f5-65f7-4abe-8479-afb9a63257fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521390711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.521390711
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3221029584
Short name T302
Test name
Test status
Simulation time 6548457239 ps
CPU time 64.1 seconds
Started Mar 28 12:51:32 PM PDT 24
Finished Mar 28 12:52:36 PM PDT 24
Peak memory 214744 kb
Host smart-aa2a5f00-d0d6-423a-b434-7387c577ade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221029584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3221029584
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.470901119
Short name T265
Test name
Test status
Simulation time 7197201860 ps
CPU time 32.71 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:12 PM PDT 24
Peak memory 218636 kb
Host smart-07a0e39a-38ee-4247-92eb-80338c8ce441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470901119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.470901119
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3077148561
Short name T346
Test name
Test status
Simulation time 1384963838 ps
CPU time 36.59 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:10 PM PDT 24
Peak memory 217716 kb
Host smart-3550b470-ca0e-4a9a-9d99-a7b36bdaa3b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077148561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3077148561
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.934983949
Short name T371
Test name
Test status
Simulation time 7603000015 ps
CPU time 69.54 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 220332 kb
Host smart-c2371f20-7ad7-445e-aa62-54eced658c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934983949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.934983949
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3653847170
Short name T273
Test name
Test status
Simulation time 15754375904 ps
CPU time 32.08 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 212860 kb
Host smart-899f18b7-3d0e-46d3-af26-592cd006332b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653847170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3653847170
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.799887368
Short name T607
Test name
Test status
Simulation time 56234512771 ps
CPU time 31.86 seconds
Started Mar 28 12:52:12 PM PDT 24
Finished Mar 28 12:52:44 PM PDT 24
Peak memory 212816 kb
Host smart-5cef3a9f-eb77-482b-999d-a0c674761e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799887368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.799887368
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1804785362
Short name T112
Test name
Test status
Simulation time 25949254408 ps
CPU time 310.98 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:46:25 PM PDT 24
Peak memory 234328 kb
Host smart-c2ac17ed-b2c9-44ed-be96-0cdfb0b3a0ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804785362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1804785362
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2992773782
Short name T451
Test name
Test status
Simulation time 5404148532 ps
CPU time 151.57 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:54:41 PM PDT 24
Peak memory 240832 kb
Host smart-8c7011c1-0c47-4cae-bc91-7a0961783d21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992773782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2992773782
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1001895391
Short name T284
Test name
Test status
Simulation time 27592180186 ps
CPU time 63.39 seconds
Started Mar 28 12:41:13 PM PDT 24
Finished Mar 28 12:42:16 PM PDT 24
Peak memory 215444 kb
Host smart-b3bcb96f-3135-4111-abac-27905d688bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001895391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1001895391
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.909389204
Short name T321
Test name
Test status
Simulation time 4605860741 ps
CPU time 27.15 seconds
Started Mar 28 12:52:07 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 215692 kb
Host smart-fc056a53-f41e-4ed3-9a09-ed60a6f6f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909389204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.909389204
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1602485884
Short name T176
Test name
Test status
Simulation time 1055526392 ps
CPU time 17.19 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 212904 kb
Host smart-f0ee638f-6a5a-4892-a8ae-f373afdb406f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602485884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1602485884
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3684837257
Short name T364
Test name
Test status
Simulation time 2604049887 ps
CPU time 25.74 seconds
Started Mar 28 12:41:11 PM PDT 24
Finished Mar 28 12:41:37 PM PDT 24
Peak memory 211992 kb
Host smart-0bac53fa-354b-428a-bdd7-08e3216ece14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684837257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3684837257
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2696375161
Short name T314
Test name
Test status
Simulation time 664150240 ps
CPU time 20.16 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:30 PM PDT 24
Peak memory 217796 kb
Host smart-1e9044f0-d371-40ef-a68a-8073ecacde8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696375161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2696375161
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.177029202
Short name T366
Test name
Test status
Simulation time 4529389510 ps
CPU time 49.66 seconds
Started Mar 28 12:52:12 PM PDT 24
Finished Mar 28 12:53:02 PM PDT 24
Peak memory 219956 kb
Host smart-0988ce81-b585-4439-b908-d4d453225b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177029202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.177029202
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.904138657
Short name T380
Test name
Test status
Simulation time 5556288312 ps
CPU time 28.95 seconds
Started Mar 28 12:41:11 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 214692 kb
Host smart-5d970187-66b5-4169-a00f-ad3cfb22526b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904138657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.904138657
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1240930578
Short name T480
Test name
Test status
Simulation time 128474297925 ps
CPU time 4620.72 seconds
Started Mar 28 12:41:15 PM PDT 24
Finished Mar 28 01:58:16 PM PDT 24
Peak memory 260956 kb
Host smart-fd6df853-3b08-4ef9-a774-ea79ba4fc803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240930578 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1240930578
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1422627596
Short name T592
Test name
Test status
Simulation time 7922178599 ps
CPU time 23.04 seconds
Started Mar 28 12:41:13 PM PDT 24
Finished Mar 28 12:41:37 PM PDT 24
Peak memory 212852 kb
Host smart-5f1eccd0-450b-4039-a23c-f3ed384d97f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422627596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1422627596
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2210346659
Short name T280
Test name
Test status
Simulation time 167376584 ps
CPU time 8.31 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:52:18 PM PDT 24
Peak memory 211920 kb
Host smart-2ddc2cdc-d1b9-405e-9eb5-eeb1606e7f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210346659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2210346659
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3022707787
Short name T417
Test name
Test status
Simulation time 78525692020 ps
CPU time 850.97 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 01:06:22 PM PDT 24
Peak memory 237980 kb
Host smart-f0e42ed2-5173-4e53-a16b-e2e2b3963f63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022707787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3022707787
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.563809000
Short name T239
Test name
Test status
Simulation time 112690221571 ps
CPU time 436.09 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 12:48:29 PM PDT 24
Peak memory 228512 kb
Host smart-5e259a79-b891-4dc7-b39f-b8988361cbd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563809000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.563809000
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1666755598
Short name T26
Test name
Test status
Simulation time 5904885694 ps
CPU time 39.17 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 213920 kb
Host smart-7bfb9fbe-84ea-4797-bf6e-3f52b9da113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666755598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1666755598
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2858049149
Short name T557
Test name
Test status
Simulation time 3691180909 ps
CPU time 31.94 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:41 PM PDT 24
Peak memory 213212 kb
Host smart-3bc71d12-3f9d-4145-ad78-126bdd0d5766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858049149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2858049149
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.201458152
Short name T17
Test name
Test status
Simulation time 181751848 ps
CPU time 10 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:24 PM PDT 24
Peak memory 212972 kb
Host smart-b895c5db-74d6-4cd7-acc3-b4d7d89c4dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201458152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.201458152
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4148408305
Short name T52
Test name
Test status
Simulation time 3432482728 ps
CPU time 10.25 seconds
Started Mar 28 12:52:10 PM PDT 24
Finished Mar 28 12:52:20 PM PDT 24
Peak memory 213260 kb
Host smart-f8082c82-73dd-49e4-93ab-24c9bf3686ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148408305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4148408305
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1588097710
Short name T330
Test name
Test status
Simulation time 8354027763 ps
CPU time 77.01 seconds
Started Mar 28 12:52:14 PM PDT 24
Finished Mar 28 12:53:31 PM PDT 24
Peak memory 219068 kb
Host smart-c8d9d475-5747-4e70-af5a-51bd483e2752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588097710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1588097710
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3540586867
Short name T3
Test name
Test status
Simulation time 5375517189 ps
CPU time 51.12 seconds
Started Mar 28 12:41:07 PM PDT 24
Finished Mar 28 12:41:59 PM PDT 24
Peak memory 218072 kb
Host smart-4cab885f-7d8f-473a-ab0e-d0fe8adb39fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540586867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3540586867
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3848851260
Short name T279
Test name
Test status
Simulation time 4073776782 ps
CPU time 43.05 seconds
Started Mar 28 12:41:13 PM PDT 24
Finished Mar 28 12:41:56 PM PDT 24
Peak memory 220004 kb
Host smart-b3b9ec75-ccc5-4372-9554-afabc0e96ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848851260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3848851260
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4058385468
Short name T219
Test name
Test status
Simulation time 7414037437 ps
CPU time 105.7 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:53:54 PM PDT 24
Peak memory 222088 kb
Host smart-4ac6f49b-521e-4e4b-a407-69e18d25b660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058385468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4058385468
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2473967026
Short name T345
Test name
Test status
Simulation time 63561469150 ps
CPU time 2639.76 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 01:25:15 PM PDT 24
Peak memory 247936 kb
Host smart-edd15959-6228-4e79-b155-647a858b4533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473967026 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2473967026
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3929537689
Short name T282
Test name
Test status
Simulation time 2414727623 ps
CPU time 22.93 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:52:34 PM PDT 24
Peak memory 212460 kb
Host smart-a12c81db-5acc-4a01-868f-1ebbd9881a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929537689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3929537689
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.654137484
Short name T159
Test name
Test status
Simulation time 14017774815 ps
CPU time 29.62 seconds
Started Mar 28 12:41:15 PM PDT 24
Finished Mar 28 12:41:44 PM PDT 24
Peak memory 212832 kb
Host smart-a6c3775c-fc3b-4f4e-b486-a962e6969009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654137484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.654137484
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3230111219
Short name T57
Test name
Test status
Simulation time 18115327415 ps
CPU time 464.03 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:59:54 PM PDT 24
Peak memory 241280 kb
Host smart-a62c1f70-aeab-4946-b8ff-16e6367c3e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230111219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3230111219
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4156406020
Short name T621
Test name
Test status
Simulation time 239887107499 ps
CPU time 1109.67 seconds
Started Mar 28 12:41:27 PM PDT 24
Finished Mar 28 12:59:56 PM PDT 24
Peak memory 238252 kb
Host smart-a6e1c99f-9e08-4f41-a658-9bad31bfeec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156406020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4156406020
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.136819022
Short name T283
Test name
Test status
Simulation time 2221441625 ps
CPU time 33.07 seconds
Started Mar 28 12:52:07 PM PDT 24
Finished Mar 28 12:52:40 PM PDT 24
Peak memory 215404 kb
Host smart-f14c25f1-7e82-4542-9efb-12739c702c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136819022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.136819022
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3226597276
Short name T253
Test name
Test status
Simulation time 27752445695 ps
CPU time 53.09 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:42:03 PM PDT 24
Peak memory 215956 kb
Host smart-86831d86-b7b6-495a-ba5e-8dc961787197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226597276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3226597276
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1663864993
Short name T181
Test name
Test status
Simulation time 4772059419 ps
CPU time 25.48 seconds
Started Mar 28 12:52:06 PM PDT 24
Finished Mar 28 12:52:32 PM PDT 24
Peak memory 212024 kb
Host smart-e17f0cb8-422c-493c-8e97-a7aebaa5ccf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663864993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1663864993
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3675005849
Short name T544
Test name
Test status
Simulation time 1987818473 ps
CPU time 22.13 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 211780 kb
Host smart-c668174b-6a68-4dbd-bbd1-156093845aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675005849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3675005849
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1688334011
Short name T298
Test name
Test status
Simulation time 21195871417 ps
CPU time 49.29 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:53:00 PM PDT 24
Peak memory 218024 kb
Host smart-88526340-bb13-4696-8615-fe88ee29e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688334011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1688334011
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2111477236
Short name T361
Test name
Test status
Simulation time 23944319485 ps
CPU time 53.15 seconds
Started Mar 28 12:41:13 PM PDT 24
Finished Mar 28 12:42:06 PM PDT 24
Peak memory 218120 kb
Host smart-d11cd4bd-242a-46f0-8e14-e996ed394f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111477236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2111477236
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2374241139
Short name T171
Test name
Test status
Simulation time 8764327099 ps
CPU time 61.54 seconds
Started Mar 28 12:52:05 PM PDT 24
Finished Mar 28 12:53:08 PM PDT 24
Peak memory 215696 kb
Host smart-d2c920c8-5a17-4461-a395-6f1a599cf665
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374241139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2374241139
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3036694998
Short name T396
Test name
Test status
Simulation time 25550881474 ps
CPU time 67.06 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:42:22 PM PDT 24
Peak memory 216968 kb
Host smart-c9dc7135-a7cb-490f-9d7a-ef2a25243f79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036694998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3036694998
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.205334556
Short name T388
Test name
Test status
Simulation time 3009557990 ps
CPU time 25.46 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:40 PM PDT 24
Peak memory 212428 kb
Host smart-e4d9c6f8-cdea-43c6-8df8-321817fa8bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205334556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.205334556
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3114063063
Short name T170
Test name
Test status
Simulation time 1115620343 ps
CPU time 15.22 seconds
Started Mar 28 12:52:13 PM PDT 24
Finished Mar 28 12:52:28 PM PDT 24
Peak memory 211864 kb
Host smart-525b910c-86f2-4c13-a4fd-522ce061c5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114063063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3114063063
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1103195433
Short name T362
Test name
Test status
Simulation time 30821592148 ps
CPU time 461.51 seconds
Started Mar 28 12:41:15 PM PDT 24
Finished Mar 28 12:48:57 PM PDT 24
Peak memory 240424 kb
Host smart-019e9960-9958-4478-b7c2-be7cd798f742
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103195433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1103195433
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1917885877
Short name T33
Test name
Test status
Simulation time 403272182843 ps
CPU time 1055.94 seconds
Started Mar 28 12:52:07 PM PDT 24
Finished Mar 28 01:09:44 PM PDT 24
Peak memory 235480 kb
Host smart-99453af7-d065-4d83-bc93-cb3b54ae14d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917885877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1917885877
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2396850349
Short name T389
Test name
Test status
Simulation time 5114988719 ps
CPU time 50.32 seconds
Started Mar 28 12:41:25 PM PDT 24
Finished Mar 28 12:42:15 PM PDT 24
Peak memory 215624 kb
Host smart-4621228c-f47d-48e5-a372-ac934cb14f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396850349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2396850349
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2922151676
Short name T251
Test name
Test status
Simulation time 2126737270 ps
CPU time 32.68 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:52:42 PM PDT 24
Peak memory 215440 kb
Host smart-6c009837-3382-4cf0-99fe-fa1f41f32dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922151676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2922151676
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1683862219
Short name T590
Test name
Test status
Simulation time 6958992881 ps
CPU time 21.72 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 211900 kb
Host smart-16ee772e-b836-4615-bccd-81296cc12337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683862219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1683862219
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2618942534
Short name T473
Test name
Test status
Simulation time 359418892 ps
CPU time 10.16 seconds
Started Mar 28 12:52:10 PM PDT 24
Finished Mar 28 12:52:21 PM PDT 24
Peak memory 213016 kb
Host smart-988509e2-26a2-4900-b4dd-9ed422b93360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618942534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2618942534
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3242523207
Short name T652
Test name
Test status
Simulation time 1370561428 ps
CPU time 20.5 seconds
Started Mar 28 12:52:10 PM PDT 24
Finished Mar 28 12:52:30 PM PDT 24
Peak memory 217964 kb
Host smart-1d42e5a1-4fd1-478f-a1b1-472accd6a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242523207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3242523207
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3669005369
Short name T232
Test name
Test status
Simulation time 6549164177 ps
CPU time 56.67 seconds
Started Mar 28 12:41:15 PM PDT 24
Finished Mar 28 12:42:12 PM PDT 24
Peak memory 218384 kb
Host smart-b1c60f0a-a454-4a62-875b-a51c5d4e2ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669005369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3669005369
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3012977147
Short name T670
Test name
Test status
Simulation time 28060247092 ps
CPU time 71.29 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:42:25 PM PDT 24
Peak memory 219876 kb
Host smart-0c09f0aa-89e8-4d7e-a52c-440b23c97755
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012977147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3012977147
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3694063908
Short name T534
Test name
Test status
Simulation time 7385293612 ps
CPU time 45.71 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:52:57 PM PDT 24
Peak memory 218432 kb
Host smart-ca7ab68a-3163-4473-b6b5-a1bbadaa2161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694063908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3694063908
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3346213304
Short name T540
Test name
Test status
Simulation time 16331187753 ps
CPU time 33.26 seconds
Started Mar 28 12:41:17 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 212732 kb
Host smart-9c9335d2-ed58-4f40-9309-f819b2968bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346213304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3346213304
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.6630212
Short name T381
Test name
Test status
Simulation time 167515552 ps
CPU time 8.29 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:52:20 PM PDT 24
Peak memory 211276 kb
Host smart-17bbf3de-2d7d-459b-9469-3e6d2fb0a67d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6630212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.6630212
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3216357647
Short name T442
Test name
Test status
Simulation time 102651299390 ps
CPU time 490.8 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 01:00:22 PM PDT 24
Peak memory 228824 kb
Host smart-b41674ee-d309-4740-b1a2-4944e840a173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216357647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3216357647
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3841026709
Short name T357
Test name
Test status
Simulation time 638130082394 ps
CPU time 709.31 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:53:04 PM PDT 24
Peak memory 240216 kb
Host smart-f7394bd0-b6bd-4953-a763-9c2a68ff685a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841026709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3841026709
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3128833350
Short name T474
Test name
Test status
Simulation time 1036113797 ps
CPU time 22.31 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 215144 kb
Host smart-9dda82ef-8f22-4172-87e1-d36c8cdc6008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128833350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3128833350
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4288821894
Short name T681
Test name
Test status
Simulation time 7712186908 ps
CPU time 57.74 seconds
Started Mar 28 12:52:11 PM PDT 24
Finished Mar 28 12:53:09 PM PDT 24
Peak memory 215748 kb
Host smart-579e7b0d-3bf7-478b-8230-79c25840f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288821894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4288821894
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1166313201
Short name T523
Test name
Test status
Simulation time 12204902302 ps
CPU time 30.92 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:52:40 PM PDT 24
Peak memory 212364 kb
Host smart-b8a999cb-6593-4aea-b997-d68f8d8046cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166313201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1166313201
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1788871809
Short name T460
Test name
Test status
Simulation time 2855695233 ps
CPU time 27.49 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:41:42 PM PDT 24
Peak memory 211820 kb
Host smart-221d3d51-e7dc-4243-a93f-3fcd7bd0ef20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788871809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1788871809
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1741163359
Short name T157
Test name
Test status
Simulation time 33423664600 ps
CPU time 65.62 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:42:20 PM PDT 24
Peak memory 218328 kb
Host smart-6c43206f-a5b2-4412-8184-5b64de951dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741163359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1741163359
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.699825023
Short name T10
Test name
Test status
Simulation time 4143715839 ps
CPU time 27.8 seconds
Started Mar 28 12:52:08 PM PDT 24
Finished Mar 28 12:52:36 PM PDT 24
Peak memory 217512 kb
Host smart-ba472eb7-762c-4aef-885e-4cf3c9540076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699825023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.699825023
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3162518750
Short name T631
Test name
Test status
Simulation time 6274660663 ps
CPU time 72.59 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:53:21 PM PDT 24
Peak memory 221100 kb
Host smart-381d427e-e625-459f-b82d-2079547da446
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162518750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3162518750
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3500439076
Short name T215
Test name
Test status
Simulation time 8832008243 ps
CPU time 50.54 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:42:05 PM PDT 24
Peak memory 219844 kb
Host smart-c193a592-5760-4711-a304-cf677ee686ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500439076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3500439076
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3793655362
Short name T59
Test name
Test status
Simulation time 898096952880 ps
CPU time 5346.6 seconds
Started Mar 28 12:52:06 PM PDT 24
Finished Mar 28 02:21:14 PM PDT 24
Peak memory 261612 kb
Host smart-83be7cee-6d84-4662-9853-e47944addd43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793655362 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3793655362
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.123186758
Short name T575
Test name
Test status
Simulation time 332204464 ps
CPU time 7.98 seconds
Started Mar 28 12:41:16 PM PDT 24
Finished Mar 28 12:41:24 PM PDT 24
Peak memory 211816 kb
Host smart-b308734b-2b40-4953-ac5d-535915930281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123186758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.123186758
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3465210186
Short name T640
Test name
Test status
Simulation time 1720467377 ps
CPU time 18.71 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:50 PM PDT 24
Peak memory 212364 kb
Host smart-2b44a30e-eb3b-46af-8d7f-6d1ff6b31071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465210186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3465210186
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.608067421
Short name T206
Test name
Test status
Simulation time 21477786350 ps
CPU time 289.77 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 225164 kb
Host smart-d90bd0db-1304-4355-ac9f-38f8395ad25e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608067421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.608067421
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.787243279
Short name T465
Test name
Test status
Simulation time 39593647698 ps
CPU time 438.97 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:48:27 PM PDT 24
Peak memory 238364 kb
Host smart-3f083d51-4479-490e-a0e5-b9506933e648
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787243279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.787243279
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2091192380
Short name T108
Test name
Test status
Simulation time 11413123840 ps
CPU time 43.73 seconds
Started Mar 28 12:52:26 PM PDT 24
Finished Mar 28 12:53:10 PM PDT 24
Peak memory 215740 kb
Host smart-a69e0baf-265c-4b7e-8bde-c2f2ee9a816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091192380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2091192380
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.209835697
Short name T223
Test name
Test status
Simulation time 3890911808 ps
CPU time 29.22 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 215336 kb
Host smart-8368331d-bf6d-4298-a8a3-bc8abcc3ed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209835697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.209835697
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1390021104
Short name T343
Test name
Test status
Simulation time 8243203380 ps
CPU time 23.45 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 212372 kb
Host smart-88047262-a135-4c66-b956-eccd280c8bfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390021104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1390021104
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3662281242
Short name T222
Test name
Test status
Simulation time 18544695845 ps
CPU time 19.33 seconds
Started Mar 28 12:41:16 PM PDT 24
Finished Mar 28 12:41:36 PM PDT 24
Peak memory 213040 kb
Host smart-de0c6de1-2045-490f-bb22-e73103dd80b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662281242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3662281242
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.621071368
Short name T391
Test name
Test status
Simulation time 5081790442 ps
CPU time 49.99 seconds
Started Mar 28 12:52:09 PM PDT 24
Finished Mar 28 12:52:59 PM PDT 24
Peak memory 215628 kb
Host smart-c5a4b9dc-9763-441c-b2d5-52b9be27ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621071368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.621071368
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.849144647
Short name T445
Test name
Test status
Simulation time 4013470907 ps
CPU time 28.76 seconds
Started Mar 28 12:41:17 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 217568 kb
Host smart-3aa00720-54ed-49f1-a312-13ea86d6cc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849144647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.849144647
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.317054637
Short name T178
Test name
Test status
Simulation time 16726993421 ps
CPU time 96.35 seconds
Started Mar 28 12:52:08 PM PDT 24
Finished Mar 28 12:53:44 PM PDT 24
Peak memory 220796 kb
Host smart-0ce9b93b-ab22-49a3-8a9b-516527c9ee75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317054637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.317054637
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.818363670
Short name T491
Test name
Test status
Simulation time 14972908606 ps
CPU time 70.29 seconds
Started Mar 28 12:41:17 PM PDT 24
Finished Mar 28 12:42:27 PM PDT 24
Peak memory 217668 kb
Host smart-f29ff373-4a87-4119-8c97-23fa1fa8ade3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818363670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.818363670
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2183998524
Short name T582
Test name
Test status
Simulation time 1269603359 ps
CPU time 8.31 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:40 PM PDT 24
Peak memory 211936 kb
Host smart-a29494e3-43c9-48aa-a7ca-87267a517244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183998524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2183998524
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.895948901
Short name T194
Test name
Test status
Simulation time 7614755911 ps
CPU time 15.78 seconds
Started Mar 28 12:41:11 PM PDT 24
Finished Mar 28 12:41:27 PM PDT 24
Peak memory 211948 kb
Host smart-340d494a-d00b-419b-93a0-9e1fe7761691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895948901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.895948901
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2135636648
Short name T56
Test name
Test status
Simulation time 2778116103 ps
CPU time 212.23 seconds
Started Mar 28 12:52:33 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 238368 kb
Host smart-188ab0dd-dab4-4275-8632-0929bc804fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135636648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2135636648
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2227615660
Short name T571
Test name
Test status
Simulation time 22424986343 ps
CPU time 428.63 seconds
Started Mar 28 12:41:09 PM PDT 24
Finished Mar 28 12:48:18 PM PDT 24
Peak memory 238552 kb
Host smart-02d25c71-420a-46b1-95b7-71ecbe095d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227615660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2227615660
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2726624966
Short name T489
Test name
Test status
Simulation time 6570561969 ps
CPU time 59.04 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:53:26 PM PDT 24
Peak memory 215804 kb
Host smart-909364fb-1d4b-49b1-8d60-79fc556c7718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726624966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2726624966
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3221137912
Short name T8
Test name
Test status
Simulation time 1374216191 ps
CPU time 19.01 seconds
Started Mar 28 12:41:11 PM PDT 24
Finished Mar 28 12:41:30 PM PDT 24
Peak memory 215200 kb
Host smart-f355ccc2-e156-4a6c-82c7-6dd0b4dddecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221137912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3221137912
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2952496040
Short name T567
Test name
Test status
Simulation time 1663435676 ps
CPU time 15.93 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:52:42 PM PDT 24
Peak memory 212996 kb
Host smart-74d110f4-828f-41c0-945e-17fc18f5861a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2952496040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2952496040
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4126692528
Short name T539
Test name
Test status
Simulation time 2006535927 ps
CPU time 20.58 seconds
Started Mar 28 12:41:16 PM PDT 24
Finished Mar 28 12:41:37 PM PDT 24
Peak memory 211936 kb
Host smart-8e630e01-dd49-46cc-a11f-8db1891fe6bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126692528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4126692528
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1422847614
Short name T579
Test name
Test status
Simulation time 3063856553 ps
CPU time 45.89 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:53:13 PM PDT 24
Peak memory 218252 kb
Host smart-b6787699-99b4-4950-ae07-627ae1f1b046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422847614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1422847614
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3276780334
Short name T201
Test name
Test status
Simulation time 13752712794 ps
CPU time 45.17 seconds
Started Mar 28 12:41:08 PM PDT 24
Finished Mar 28 12:41:53 PM PDT 24
Peak memory 216120 kb
Host smart-aa6dad21-74b4-413c-aca4-e2e1f35fba4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276780334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3276780334
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2664626121
Short name T596
Test name
Test status
Simulation time 71754238096 ps
CPU time 84.79 seconds
Started Mar 28 12:41:10 PM PDT 24
Finished Mar 28 12:42:35 PM PDT 24
Peak memory 219952 kb
Host smart-9f78aaae-09d3-4614-aa22-ab237b8f4ee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664626121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2664626121
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.949171151
Short name T200
Test name
Test status
Simulation time 410039613 ps
CPU time 24.3 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 218512 kb
Host smart-5217f7c6-4789-454c-89d5-58b4df6f4dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949171151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.949171151
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2474460493
Short name T77
Test name
Test status
Simulation time 8242705800 ps
CPU time 14.16 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:52:42 PM PDT 24
Peak memory 212932 kb
Host smart-7f4dd3a2-89f5-4842-a1b2-c7108b87d878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474460493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2474460493
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3458177482
Short name T370
Test name
Test status
Simulation time 169016093 ps
CPU time 8.4 seconds
Started Mar 28 12:41:34 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 211804 kb
Host smart-177e4320-8226-405e-a135-3ce0fa09afc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458177482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3458177482
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3090345034
Short name T413
Test name
Test status
Simulation time 15783554550 ps
CPU time 274.85 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 12:45:47 PM PDT 24
Peak memory 234652 kb
Host smart-1fda9e40-9cb3-4527-9f6f-e23f5e9692ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090345034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3090345034
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.636592122
Short name T406
Test name
Test status
Simulation time 130815417121 ps
CPU time 373.77 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:58:42 PM PDT 24
Peak memory 237952 kb
Host smart-84479f20-38b5-4f89-bd17-809d5fc74906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636592122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.636592122
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3006637594
Short name T217
Test name
Test status
Simulation time 688836739 ps
CPU time 18.89 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 215124 kb
Host smart-5aecbb0e-b57d-4a40-b6a9-2dd0c630d7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006637594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3006637594
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3517270615
Short name T241
Test name
Test status
Simulation time 4322022053 ps
CPU time 30.8 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 215636 kb
Host smart-34542636-2db3-4e54-a9b1-9222ac157cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517270615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3517270615
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1604876813
Short name T208
Test name
Test status
Simulation time 180428324 ps
CPU time 10.11 seconds
Started Mar 28 12:41:12 PM PDT 24
Finished Mar 28 12:41:23 PM PDT 24
Peak memory 212780 kb
Host smart-070706b3-2c65-4952-a2b2-f538d0ed1bda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604876813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1604876813
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2173942673
Short name T512
Test name
Test status
Simulation time 13802817311 ps
CPU time 32.7 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:53:02 PM PDT 24
Peak memory 212292 kb
Host smart-70ff16bc-ebe8-4b99-b685-76df5c06fa6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173942673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2173942673
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1654604260
Short name T528
Test name
Test status
Simulation time 8043181732 ps
CPU time 75.34 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:53:41 PM PDT 24
Peak memory 218064 kb
Host smart-c96bf091-2967-448d-8b10-ac373c5049fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654604260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1654604260
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.486801656
Short name T249
Test name
Test status
Simulation time 1169863379 ps
CPU time 19.83 seconds
Started Mar 28 12:41:11 PM PDT 24
Finished Mar 28 12:41:31 PM PDT 24
Peak memory 217196 kb
Host smart-24056da1-5d60-4a3e-a8bb-cbc04d7b60b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486801656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.486801656
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1641645892
Short name T66
Test name
Test status
Simulation time 15347236815 ps
CPU time 34.87 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:53:02 PM PDT 24
Peak memory 212080 kb
Host smart-3bf97df0-c9fa-4df4-a5b2-c67b3cfbbd79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641645892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1641645892
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2106441172
Short name T655
Test name
Test status
Simulation time 33661375606 ps
CPU time 70.83 seconds
Started Mar 28 12:41:14 PM PDT 24
Finished Mar 28 12:42:25 PM PDT 24
Peak memory 219420 kb
Host smart-64720d72-72d0-4a29-8095-1d9b1179787c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106441172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2106441172
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2971544002
Short name T311
Test name
Test status
Simulation time 6352513133 ps
CPU time 26.46 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 212296 kb
Host smart-06c27d36-1447-47db-bf0f-e300b7a79137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971544002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2971544002
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3092086673
Short name T538
Test name
Test status
Simulation time 2625015753 ps
CPU time 12.64 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:41:42 PM PDT 24
Peak memory 212008 kb
Host smart-fb36e75c-b409-4731-a440-01eb0a6a2720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092086673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3092086673
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1907303202
Short name T672
Test name
Test status
Simulation time 388664264240 ps
CPU time 560.68 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 01:01:47 PM PDT 24
Peak memory 218244 kb
Host smart-a25899fb-d1dd-4529-907c-5aa7b3457bfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907303202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1907303202
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4135595433
Short name T644
Test name
Test status
Simulation time 64513123311 ps
CPU time 365.42 seconds
Started Mar 28 12:41:28 PM PDT 24
Finished Mar 28 12:47:34 PM PDT 24
Peak memory 228364 kb
Host smart-cddca360-8e6b-4281-90a9-61713a3449ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135595433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4135595433
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1342766907
Short name T25
Test name
Test status
Simulation time 332299011 ps
CPU time 19.49 seconds
Started Mar 28 12:41:31 PM PDT 24
Finished Mar 28 12:41:51 PM PDT 24
Peak memory 215200 kb
Host smart-5d991377-38bd-43ca-8b16-83da6efba41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342766907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1342766907
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.723459271
Short name T203
Test name
Test status
Simulation time 63685561404 ps
CPU time 53.95 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:53:22 PM PDT 24
Peak memory 215604 kb
Host smart-3b812a7a-0bf8-4502-8159-3fa1cbc095ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723459271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.723459271
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2451600878
Short name T313
Test name
Test status
Simulation time 4900392574 ps
CPU time 18.05 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 213444 kb
Host smart-691e72ef-f932-4bfa-811a-9e87b5c90b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451600878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2451600878
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2908058163
Short name T605
Test name
Test status
Simulation time 2793181627 ps
CPU time 21.95 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:52:52 PM PDT 24
Peak memory 212348 kb
Host smart-d4e2426f-3f40-4698-92be-59e16d5102dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908058163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2908058163
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2270728925
Short name T496
Test name
Test status
Simulation time 6014806559 ps
CPU time 51.36 seconds
Started Mar 28 12:41:33 PM PDT 24
Finished Mar 28 12:42:24 PM PDT 24
Peak memory 218184 kb
Host smart-250d95ae-2663-49a8-b565-89d40a8a7b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270728925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2270728925
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.968199815
Short name T638
Test name
Test status
Simulation time 3126894172 ps
CPU time 20.4 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:52:46 PM PDT 24
Peak memory 217952 kb
Host smart-7eade49b-e03a-40d2-a74f-1ce238503138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968199815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.968199815
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1945593441
Short name T197
Test name
Test status
Simulation time 558478059 ps
CPU time 33.72 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:42:04 PM PDT 24
Peak memory 219620 kb
Host smart-779013c1-4dbe-4ed4-ab99-9dc4de2081cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945593441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1945593441
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3971887887
Short name T632
Test name
Test status
Simulation time 2617634307 ps
CPU time 76.95 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:53:48 PM PDT 24
Peak memory 219960 kb
Host smart-c4d798ab-c924-4b1f-9773-15aabddb58f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971887887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3971887887
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3182247008
Short name T20
Test name
Test status
Simulation time 40752372759 ps
CPU time 767.39 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:54:26 PM PDT 24
Peak memory 236336 kb
Host smart-ab8ce5ac-d655-4efd-808a-5eef90475dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182247008 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3182247008
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2386043260
Short name T447
Test name
Test status
Simulation time 28106799578 ps
CPU time 33.94 seconds
Started Mar 28 12:41:28 PM PDT 24
Finished Mar 28 12:42:02 PM PDT 24
Peak memory 212816 kb
Host smart-0912dc66-f1d1-41de-b351-0efd2bf19201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386043260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2386043260
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3452348456
Short name T306
Test name
Test status
Simulation time 3194779907 ps
CPU time 26.8 seconds
Started Mar 28 12:52:29 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 212508 kb
Host smart-1682ba22-e7b3-496a-8093-f1e8600cc930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452348456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3452348456
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2855651525
Short name T307
Test name
Test status
Simulation time 157815139384 ps
CPU time 409.38 seconds
Started Mar 28 12:52:26 PM PDT 24
Finished Mar 28 12:59:16 PM PDT 24
Peak memory 220268 kb
Host smart-8de0b9bf-e881-4893-85b5-2eaa440cff86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855651525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2855651525
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.759220009
Short name T374
Test name
Test status
Simulation time 12909742929 ps
CPU time 189.53 seconds
Started Mar 28 12:41:27 PM PDT 24
Finished Mar 28 12:44:37 PM PDT 24
Peak memory 216612 kb
Host smart-ed58c08b-1814-4409-9606-206e06e65b50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759220009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.759220009
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1716025673
Short name T609
Test name
Test status
Simulation time 1376005692 ps
CPU time 19.17 seconds
Started Mar 28 12:41:31 PM PDT 24
Finished Mar 28 12:41:50 PM PDT 24
Peak memory 215320 kb
Host smart-3f733a71-71fa-4d81-93cb-9e3fedad846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716025673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1716025673
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3262870829
Short name T51
Test name
Test status
Simulation time 953092800 ps
CPU time 22.7 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:52:50 PM PDT 24
Peak memory 215408 kb
Host smart-4b11cf6c-4cc7-45cd-a6ed-dd247181d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262870829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3262870829
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.305558768
Short name T643
Test name
Test status
Simulation time 178868445 ps
CPU time 10.51 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:52:41 PM PDT 24
Peak memory 213096 kb
Host smart-e09eeb2f-0019-4eb8-8fb7-22a40fa54720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305558768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.305558768
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.564263311
Short name T535
Test name
Test status
Simulation time 180562245 ps
CPU time 10.74 seconds
Started Mar 28 12:41:34 PM PDT 24
Finished Mar 28 12:41:45 PM PDT 24
Peak memory 212808 kb
Host smart-246cb2c2-d3d6-4a21-a1c7-1cc021a1e825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564263311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.564263311
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4054549018
Short name T245
Test name
Test status
Simulation time 7388657935 ps
CPU time 72.72 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:42:42 PM PDT 24
Peak memory 217432 kb
Host smart-5ddbc572-85e0-494c-9583-9c4f719bc4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054549018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4054549018
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4291810800
Short name T483
Test name
Test status
Simulation time 40584673775 ps
CPU time 61.52 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:53:27 PM PDT 24
Peak memory 219320 kb
Host smart-ffb2e204-e9e3-4d84-b78a-596eec41900c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291810800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4291810800
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2011603573
Short name T537
Test name
Test status
Simulation time 1763034002 ps
CPU time 53 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:53:24 PM PDT 24
Peak memory 220644 kb
Host smart-44fdf73e-6d6a-4a35-9a56-16ba11cee0dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011603573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2011603573
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3065288351
Short name T585
Test name
Test status
Simulation time 9228643237 ps
CPU time 23.13 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:41:52 PM PDT 24
Peak memory 213408 kb
Host smart-2550ac6f-77ec-44c3-b097-b3bea4140875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065288351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3065288351
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.340481526
Short name T470
Test name
Test status
Simulation time 130382685444 ps
CPU time 8105.74 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 03:07:34 PM PDT 24
Peak memory 236840 kb
Host smart-e479e50d-2175-4b5c-80c2-01d60babc778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340481526 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.340481526
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1154272069
Short name T250
Test name
Test status
Simulation time 8215203886 ps
CPU time 23.22 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:51:56 PM PDT 24
Peak memory 212092 kb
Host smart-7b0a2da6-ccf9-448e-ae5e-8062d1867845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154272069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1154272069
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3424030625
Short name T75
Test name
Test status
Simulation time 718163638 ps
CPU time 8.38 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:40:45 PM PDT 24
Peak memory 211804 kb
Host smart-d57959b3-6ad7-46a7-9a14-494febd7b759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424030625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3424030625
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.302212321
Short name T633
Test name
Test status
Simulation time 13833731628 ps
CPU time 378.22 seconds
Started Mar 28 12:51:32 PM PDT 24
Finished Mar 28 12:57:51 PM PDT 24
Peak memory 229688 kb
Host smart-2214320a-5efd-4299-b6ca-b757d7d4e139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302212321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.302212321
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3212736103
Short name T256
Test name
Test status
Simulation time 131856503273 ps
CPU time 730.43 seconds
Started Mar 28 12:40:33 PM PDT 24
Finished Mar 28 12:52:44 PM PDT 24
Peak memory 234364 kb
Host smart-f47e51ac-cfce-4869-8739-55d2175ad819
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212736103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3212736103
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2576770344
Short name T561
Test name
Test status
Simulation time 27284515785 ps
CPU time 44.84 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:41:22 PM PDT 24
Peak memory 215544 kb
Host smart-d39710b9-3337-42ed-91ce-25bd4d68a445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576770344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2576770344
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3981658129
Short name T164
Test name
Test status
Simulation time 63104482833 ps
CPU time 34.35 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:41:11 PM PDT 24
Peak memory 213260 kb
Host smart-214ac92c-590e-4aa1-a124-a6b8de3aec46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981658129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3981658129
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4243320970
Short name T466
Test name
Test status
Simulation time 2303619194 ps
CPU time 24.29 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:51:57 PM PDT 24
Peak memory 211912 kb
Host smart-6df106d6-90f8-4947-9cb7-dd3467a351e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4243320970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4243320970
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1355048570
Short name T34
Test name
Test status
Simulation time 996439709 ps
CPU time 118.57 seconds
Started Mar 28 12:40:34 PM PDT 24
Finished Mar 28 12:42:34 PM PDT 24
Peak memory 237812 kb
Host smart-a8f17764-09d0-4015-aaa4-c92e21b11e82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355048570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1355048570
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3585176415
Short name T41
Test name
Test status
Simulation time 2734503073 ps
CPU time 132.18 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:53:46 PM PDT 24
Peak memory 240056 kb
Host smart-b1680562-f8c7-48f4-aad3-96c3296119b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585176415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3585176415
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.39272446
Short name T623
Test name
Test status
Simulation time 8513185983 ps
CPU time 78.46 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 218324 kb
Host smart-6d29fc05-e08d-4631-821f-ac24871e6841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39272446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.39272446
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.737755106
Short name T375
Test name
Test status
Simulation time 2007338998 ps
CPU time 26.79 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:06 PM PDT 24
Peak memory 218084 kb
Host smart-cd070721-5047-4e0b-a056-acf3b45cb048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737755106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.737755106
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1189015350
Short name T198
Test name
Test status
Simulation time 50230612243 ps
CPU time 121.26 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:42:38 PM PDT 24
Peak memory 217820 kb
Host smart-8c94396b-5c5b-498d-86eb-c20f14666a7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189015350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1189015350
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3500133466
Short name T70
Test name
Test status
Simulation time 189779200755 ps
CPU time 365.66 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:57:39 PM PDT 24
Peak memory 222356 kb
Host smart-212bb189-3a93-4ba9-a891-a38378b98464
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500133466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3500133466
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.19593614
Short name T300
Test name
Test status
Simulation time 4144952015 ps
CPU time 32.18 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:52:59 PM PDT 24
Peak memory 212484 kb
Host smart-5a25a11d-73d3-4054-b2df-eade3c6382e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19593614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.19593614
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2663923402
Short name T358
Test name
Test status
Simulation time 2038958267 ps
CPU time 20.79 seconds
Started Mar 28 12:41:32 PM PDT 24
Finished Mar 28 12:41:53 PM PDT 24
Peak memory 212488 kb
Host smart-1443e786-6946-40a8-9180-22b938188a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663923402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2663923402
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1506644318
Short name T214
Test name
Test status
Simulation time 107214280966 ps
CPU time 453.47 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 01:00:00 PM PDT 24
Peak memory 225872 kb
Host smart-e3fb8e83-27b9-4259-b9c9-2fad631590a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506644318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1506644318
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3774075759
Short name T675
Test name
Test status
Simulation time 142425765994 ps
CPU time 379.86 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:47:50 PM PDT 24
Peak memory 234344 kb
Host smart-88b2cf3d-155b-4986-b0ae-7e0c4d707037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774075759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3774075759
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.288222658
Short name T550
Test name
Test status
Simulation time 3344094277 ps
CPU time 40.09 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:42:09 PM PDT 24
Peak memory 215696 kb
Host smart-4d4c9447-8501-42cf-8282-4dd4fd6e7987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288222658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.288222658
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3662450417
Short name T224
Test name
Test status
Simulation time 5395285818 ps
CPU time 46.16 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:53:13 PM PDT 24
Peak memory 215632 kb
Host smart-f08c67f1-af76-47b9-8bc1-69001630b2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662450417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3662450417
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2286437280
Short name T185
Test name
Test status
Simulation time 68803619051 ps
CPU time 31.36 seconds
Started Mar 28 12:41:34 PM PDT 24
Finished Mar 28 12:42:06 PM PDT 24
Peak memory 213336 kb
Host smart-4fda2cbb-dd8b-40b7-9dd0-3bab812b4036
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286437280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2286437280
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3198600467
Short name T428
Test name
Test status
Simulation time 181518654 ps
CPU time 10.48 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:52:38 PM PDT 24
Peak memory 212816 kb
Host smart-a375ab17-ed32-468f-a109-4536fbfd1ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198600467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3198600467
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3429229567
Short name T449
Test name
Test status
Simulation time 1376580262 ps
CPU time 19.75 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:52:44 PM PDT 24
Peak memory 217864 kb
Host smart-9c1e48ed-43a8-40d1-875c-32f46fff5145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429229567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3429229567
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.482970025
Short name T563
Test name
Test status
Simulation time 348164637 ps
CPU time 19.47 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:41:49 PM PDT 24
Peak memory 216912 kb
Host smart-52600095-ddf8-43e1-a3c4-3a5dca1ed9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482970025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.482970025
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2573293356
Short name T551
Test name
Test status
Simulation time 1502123600 ps
CPU time 44.16 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:42:21 PM PDT 24
Peak memory 219700 kb
Host smart-e1e8b0ab-cfe9-45da-b601-8b84ded8610b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573293356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2573293356
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2985422565
Short name T494
Test name
Test status
Simulation time 13833859735 ps
CPU time 79.32 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:53:48 PM PDT 24
Peak memory 222428 kb
Host smart-151cb424-218c-4487-bcdf-17e27578f44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985422565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2985422565
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3475715716
Short name T277
Test name
Test status
Simulation time 5731589805 ps
CPU time 12.78 seconds
Started Mar 28 12:52:26 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 212036 kb
Host smart-774534c3-f8f3-48cf-8f4d-bf0fd080aca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475715716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3475715716
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.964788902
Short name T322
Test name
Test status
Simulation time 10166202770 ps
CPU time 23.26 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:41:58 PM PDT 24
Peak memory 212732 kb
Host smart-dd6af17f-52bd-4584-b77a-5a1e35f589b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964788902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.964788902
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3700474738
Short name T581
Test name
Test status
Simulation time 141092120119 ps
CPU time 309.86 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:46:40 PM PDT 24
Peak memory 229028 kb
Host smart-e164e166-d9cd-469f-b2a6-8b5d6668b61b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700474738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3700474738
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4278157506
Short name T382
Test name
Test status
Simulation time 18845697222 ps
CPU time 178.11 seconds
Started Mar 28 12:52:26 PM PDT 24
Finished Mar 28 12:55:24 PM PDT 24
Peak memory 238084 kb
Host smart-614b92de-575a-4728-a739-b815ba7cd0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278157506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4278157506
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1368273945
Short name T237
Test name
Test status
Simulation time 85409507221 ps
CPU time 47.57 seconds
Started Mar 28 12:41:34 PM PDT 24
Finished Mar 28 12:42:22 PM PDT 24
Peak memory 215528 kb
Host smart-59d8e6ba-1ce7-44ba-9ff4-4c6c5b52c582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368273945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1368273945
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2761084763
Short name T351
Test name
Test status
Simulation time 1811795756 ps
CPU time 30.95 seconds
Started Mar 28 12:52:26 PM PDT 24
Finished Mar 28 12:52:57 PM PDT 24
Peak memory 213216 kb
Host smart-2239576c-5e49-46bf-9107-aa8c6b26d575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761084763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2761084763
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2142196544
Short name T615
Test name
Test status
Simulation time 8441301852 ps
CPU time 34.5 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 213328 kb
Host smart-2cc662fa-a896-41f4-b62e-d1cec73cefb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142196544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2142196544
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2567260856
Short name T524
Test name
Test status
Simulation time 2375576689 ps
CPU time 21.85 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 211832 kb
Host smart-f9baf5df-b7e6-477e-8b64-99c615070115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567260856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2567260856
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1145578071
Short name T344
Test name
Test status
Simulation time 19780432305 ps
CPU time 53.76 seconds
Started Mar 28 12:52:29 PM PDT 24
Finished Mar 28 12:53:23 PM PDT 24
Peak memory 217364 kb
Host smart-b9d0e2e2-d18d-4690-b111-8b35f05ce911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145578071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1145578071
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3100412911
Short name T564
Test name
Test status
Simulation time 693590098 ps
CPU time 19.49 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 218080 kb
Host smart-e7dfa1fd-666f-4d1c-941b-d852bd665f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100412911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3100412911
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2767698814
Short name T452
Test name
Test status
Simulation time 95463378776 ps
CPU time 111.28 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:54:19 PM PDT 24
Peak memory 219948 kb
Host smart-22155501-2c30-44db-95ed-b794a7c3824c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767698814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2767698814
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.834373389
Short name T335
Test name
Test status
Simulation time 5541388336 ps
CPU time 31.47 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:42:02 PM PDT 24
Peak memory 213064 kb
Host smart-fbac8462-e9b3-4036-99e8-bc0302f029e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834373389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.834373389
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1601259155
Short name T650
Test name
Test status
Simulation time 1005612395 ps
CPU time 15.08 seconds
Started Mar 28 12:41:33 PM PDT 24
Finished Mar 28 12:41:48 PM PDT 24
Peak memory 211808 kb
Host smart-b52c5359-7942-4d41-af4a-4138d1a9c80f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601259155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1601259155
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3912672816
Short name T666
Test name
Test status
Simulation time 8855690547 ps
CPU time 23.26 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:54 PM PDT 24
Peak memory 211980 kb
Host smart-06cc5686-d323-40c2-874c-78878c2aa18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912672816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3912672816
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2959793281
Short name T662
Test name
Test status
Simulation time 111418434499 ps
CPU time 264.86 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:45:55 PM PDT 24
Peak memory 217352 kb
Host smart-39060deb-759f-48d2-a3e7-d040c007c6c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959793281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2959793281
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.983760462
Short name T387
Test name
Test status
Simulation time 13698785944 ps
CPU time 241.32 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:56:26 PM PDT 24
Peak memory 235816 kb
Host smart-7b9e74f7-5b86-4b1e-8a1f-547a2a64bfa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983760462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.983760462
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2566781985
Short name T315
Test name
Test status
Simulation time 27428912247 ps
CPU time 54.61 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:53:21 PM PDT 24
Peak memory 214776 kb
Host smart-fcad6cad-f615-48d3-a9a5-8054d03a139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566781985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2566781985
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.332099132
Short name T267
Test name
Test status
Simulation time 6304088984 ps
CPU time 53.96 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:42:29 PM PDT 24
Peak memory 216152 kb
Host smart-8b8143b7-725c-4df4-8073-1a8342eeff1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332099132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.332099132
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2351138425
Short name T629
Test name
Test status
Simulation time 2668434239 ps
CPU time 25.63 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 211804 kb
Host smart-f43f7719-14be-45ec-b153-4dd8947e1ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351138425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2351138425
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.370247246
Short name T378
Test name
Test status
Simulation time 2585500371 ps
CPU time 18.99 seconds
Started Mar 28 12:52:32 PM PDT 24
Finished Mar 28 12:52:51 PM PDT 24
Peak memory 212864 kb
Host smart-6188df01-a348-4482-b223-c91ed1d68555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370247246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.370247246
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3171534212
Short name T493
Test name
Test status
Simulation time 19072382791 ps
CPU time 48.38 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 12:53:15 PM PDT 24
Peak memory 218092 kb
Host smart-4055bf1b-41e7-48e8-92b1-ba50e8fd65a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171534212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3171534212
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4178019454
Short name T173
Test name
Test status
Simulation time 26834188548 ps
CPU time 71.35 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:42:42 PM PDT 24
Peak memory 218972 kb
Host smart-3ddfec71-8dac-4ec5-a188-f157a6099c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178019454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4178019454
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3161273263
Short name T490
Test name
Test status
Simulation time 54509504376 ps
CPU time 62.05 seconds
Started Mar 28 12:41:34 PM PDT 24
Finished Mar 28 12:42:37 PM PDT 24
Peak memory 219960 kb
Host smart-ab0426e5-a941-4d0d-8db1-ecaa28b806ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161273263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3161273263
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3657005383
Short name T162
Test name
Test status
Simulation time 20807159651 ps
CPU time 110.56 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:54:18 PM PDT 24
Peak memory 221636 kb
Host smart-6713f513-f0e2-4e61-ab3c-041851fee58d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657005383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3657005383
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1114645646
Short name T278
Test name
Test status
Simulation time 4170535622 ps
CPU time 32.05 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:42:10 PM PDT 24
Peak memory 212436 kb
Host smart-d593037b-c1f6-4596-8b4d-d3e912ef2266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114645646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1114645646
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3849831977
Short name T287
Test name
Test status
Simulation time 5810693873 ps
CPU time 17.14 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 212040 kb
Host smart-05a43c09-b175-4cef-b599-10582cdd6864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849831977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3849831977
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1607061724
Short name T431
Test name
Test status
Simulation time 119398820723 ps
CPU time 719.42 seconds
Started Mar 28 12:52:27 PM PDT 24
Finished Mar 28 01:04:26 PM PDT 24
Peak memory 234888 kb
Host smart-6e05e210-8ad6-4974-9177-600b88f9cab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607061724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1607061724
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4238506807
Short name T461
Test name
Test status
Simulation time 18981481380 ps
CPU time 291.64 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:46:30 PM PDT 24
Peak memory 219136 kb
Host smart-89f879be-1b6b-44d6-af84-ce17df4f824e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238506807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4238506807
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1410877937
Short name T332
Test name
Test status
Simulation time 23275765605 ps
CPU time 56.64 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:42:34 PM PDT 24
Peak memory 215516 kb
Host smart-974602fa-e563-4dc2-aab4-f4aa2e7ccd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410877937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1410877937
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.428806450
Short name T637
Test name
Test status
Simulation time 4565967044 ps
CPU time 25.25 seconds
Started Mar 28 12:52:33 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 217616 kb
Host smart-b5a32a44-dcbb-4413-9b6c-f3760c970d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428806450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.428806450
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2070922803
Short name T160
Test name
Test status
Simulation time 1904381840 ps
CPU time 22.07 seconds
Started Mar 28 12:41:36 PM PDT 24
Finished Mar 28 12:41:58 PM PDT 24
Peak memory 212720 kb
Host smart-8f8fe97a-8c3f-4e8a-9dba-30007a4c2d0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070922803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2070922803
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2727110946
Short name T678
Test name
Test status
Simulation time 16419895894 ps
CPU time 24.58 seconds
Started Mar 28 12:52:32 PM PDT 24
Finished Mar 28 12:52:56 PM PDT 24
Peak memory 211928 kb
Host smart-a33bec3a-f58a-40ca-b3a5-4c62961781ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727110946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2727110946
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2848077187
Short name T86
Test name
Test status
Simulation time 355212915 ps
CPU time 19.77 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:52:48 PM PDT 24
Peak memory 216764 kb
Host smart-34b38770-9149-43d2-b0c5-1fdef08b80ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848077187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2848077187
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3903300218
Short name T258
Test name
Test status
Simulation time 9613543097 ps
CPU time 24.29 seconds
Started Mar 28 12:41:33 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 218764 kb
Host smart-89e9dee6-ab2a-450e-9a15-686fe2fc81ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903300218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3903300218
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3109571971
Short name T547
Test name
Test status
Simulation time 384204185 ps
CPU time 23.56 seconds
Started Mar 28 12:41:32 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 219252 kb
Host smart-0c99f8c1-6055-45bc-9583-ac8e498324eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109571971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3109571971
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.940055493
Short name T459
Test name
Test status
Simulation time 2226040545 ps
CPU time 30.32 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:52:55 PM PDT 24
Peak memory 219972 kb
Host smart-3f2ba3ba-667a-49c8-abd4-52802b0b9b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940055493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.940055493
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2494445591
Short name T455
Test name
Test status
Simulation time 1713798600 ps
CPU time 19.14 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:56 PM PDT 24
Peak memory 211820 kb
Host smart-438811a9-bc08-4854-9e10-411693c846e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494445591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2494445591
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3656896931
Short name T6
Test name
Test status
Simulation time 1628852586 ps
CPU time 13.86 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:52:44 PM PDT 24
Peak memory 211920 kb
Host smart-4c9677ab-01c0-4994-8050-063d36517c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656896931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3656896931
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2259878178
Short name T397
Test name
Test status
Simulation time 19065462787 ps
CPU time 261.65 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:46:00 PM PDT 24
Peak memory 238352 kb
Host smart-259b6f1f-b904-4082-9d68-4687cb08b23a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259878178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2259878178
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3741230812
Short name T353
Test name
Test status
Simulation time 201926235990 ps
CPU time 456.84 seconds
Started Mar 28 12:52:33 PM PDT 24
Finished Mar 28 01:00:10 PM PDT 24
Peak memory 238100 kb
Host smart-ae078490-8af3-40bd-9f4d-557d1519c203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741230812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3741230812
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1395697607
Short name T664
Test name
Test status
Simulation time 4118462679 ps
CPU time 18.9 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 215180 kb
Host smart-14d6dc46-3c1d-4af1-99fc-9cce11ef763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395697607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1395697607
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3993810797
Short name T482
Test name
Test status
Simulation time 9959183261 ps
CPU time 33.81 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:53:04 PM PDT 24
Peak memory 215916 kb
Host smart-0cf1b374-984d-4ec7-9756-6e87dde48698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993810797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3993810797
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.4288939462
Short name T19
Test name
Test status
Simulation time 38911102918 ps
CPU time 35.21 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:53:06 PM PDT 24
Peak memory 213508 kb
Host smart-8c9cee48-dbff-4fde-8341-371e9038157f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288939462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.4288939462
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.741665457
Short name T327
Test name
Test status
Simulation time 733459671 ps
CPU time 12.55 seconds
Started Mar 28 12:41:39 PM PDT 24
Finished Mar 28 12:41:52 PM PDT 24
Peak memory 211856 kb
Host smart-b08a613f-af67-4263-8f62-fe4faa7a5930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741665457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.741665457
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1065198367
Short name T110
Test name
Test status
Simulation time 23773804458 ps
CPU time 52.57 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:53:24 PM PDT 24
Peak memory 218548 kb
Host smart-91f17867-d0e7-4dbc-886f-29329b4cad84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065198367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1065198367
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1802582537
Short name T458
Test name
Test status
Simulation time 1499374122 ps
CPU time 19.58 seconds
Started Mar 28 12:41:35 PM PDT 24
Finished Mar 28 12:41:54 PM PDT 24
Peak memory 217068 kb
Host smart-33f8d9e7-5d73-4312-92d9-a104d53729c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802582537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1802582537
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3809046274
Short name T554
Test name
Test status
Simulation time 14531928088 ps
CPU time 67.4 seconds
Started Mar 28 12:52:30 PM PDT 24
Finished Mar 28 12:53:37 PM PDT 24
Peak memory 219956 kb
Host smart-0b7dfa2e-7690-4940-9390-7b8b44a8efa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809046274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3809046274
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4168844341
Short name T147
Test name
Test status
Simulation time 29071075721 ps
CPU time 178.19 seconds
Started Mar 28 12:41:29 PM PDT 24
Finished Mar 28 12:44:27 PM PDT 24
Peak memory 228528 kb
Host smart-f197dc48-0637-4be2-932c-d716649e8c17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168844341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4168844341
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2288080518
Short name T602
Test name
Test status
Simulation time 1648450993 ps
CPU time 8.4 seconds
Started Mar 28 12:52:35 PM PDT 24
Finished Mar 28 12:52:43 PM PDT 24
Peak memory 211820 kb
Host smart-44484e09-826f-4fbf-a8f5-a614ed3d6e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288080518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2288080518
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2695531468
Short name T244
Test name
Test status
Simulation time 1715395778 ps
CPU time 11.46 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:41:51 PM PDT 24
Peak memory 211828 kb
Host smart-620e73fc-b701-4b4d-95a4-e852a053f700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695531468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2695531468
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2257102774
Short name T462
Test name
Test status
Simulation time 50939033003 ps
CPU time 531.97 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:50:30 PM PDT 24
Peak memory 217588 kb
Host smart-583e42b9-a766-40c4-909a-f7d310ac5d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257102774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2257102774
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2846603402
Short name T667
Test name
Test status
Simulation time 375677816648 ps
CPU time 548.83 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 01:01:45 PM PDT 24
Peak memory 241048 kb
Host smart-fcd81ca6-e25b-475c-b3c8-e0d32e00a58d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846603402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2846603402
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3884963513
Short name T513
Test name
Test status
Simulation time 2357556134 ps
CPU time 18.87 seconds
Started Mar 28 12:52:36 PM PDT 24
Finished Mar 28 12:52:55 PM PDT 24
Peak memory 215312 kb
Host smart-8de0055a-a954-4e8e-a82a-65bf7e11b9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884963513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3884963513
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.741469911
Short name T521
Test name
Test status
Simulation time 1378059051 ps
CPU time 19.57 seconds
Started Mar 28 12:41:37 PM PDT 24
Finished Mar 28 12:41:57 PM PDT 24
Peak memory 215568 kb
Host smart-f71ecf17-4d00-4d19-a5ec-d092af25d30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741469911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.741469911
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1964354130
Short name T288
Test name
Test status
Simulation time 15124592937 ps
CPU time 33.49 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:42:12 PM PDT 24
Peak memory 211828 kb
Host smart-ca001202-3692-42dc-a20e-9bf418f9afa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964354130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1964354130
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3660217617
Short name T225
Test name
Test status
Simulation time 358853975 ps
CPU time 10.49 seconds
Started Mar 28 12:52:25 PM PDT 24
Finished Mar 28 12:52:36 PM PDT 24
Peak memory 212712 kb
Host smart-f31f9972-5a4e-4b42-863a-d8d652b6caf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660217617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3660217617
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2142395041
Short name T338
Test name
Test status
Simulation time 30838438622 ps
CPU time 78.37 seconds
Started Mar 28 12:52:29 PM PDT 24
Finished Mar 28 12:53:47 PM PDT 24
Peak memory 219124 kb
Host smart-49505d9b-eaee-4237-8725-b464d732bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142395041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2142395041
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.990050423
Short name T500
Test name
Test status
Simulation time 3033518636 ps
CPU time 29.77 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:42:08 PM PDT 24
Peak memory 216260 kb
Host smart-73208b1f-956d-430e-ac44-01f4f3b43a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990050423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.990050423
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3073128548
Short name T492
Test name
Test status
Simulation time 24883205775 ps
CPU time 157.97 seconds
Started Mar 28 12:52:29 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 219856 kb
Host smart-0b2789bb-a075-4655-9e8c-3ad092a70717
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073128548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3073128548
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.535558634
Short name T414
Test name
Test status
Simulation time 56952140221 ps
CPU time 42 seconds
Started Mar 28 12:41:41 PM PDT 24
Finished Mar 28 12:42:23 PM PDT 24
Peak memory 213516 kb
Host smart-4e546768-56a4-44d1-a558-c615d6a97f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535558634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.535558634
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1005215834
Short name T58
Test name
Test status
Simulation time 50926884267 ps
CPU time 2403.92 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 01:32:48 PM PDT 24
Peak memory 233364 kb
Host smart-320cc430-bea6-45a0-b6df-1723e2d5c0ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005215834 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1005215834
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1101354880
Short name T323
Test name
Test status
Simulation time 4277034652 ps
CPU time 15.2 seconds
Started Mar 28 12:41:39 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 211952 kb
Host smart-68955014-a078-4980-9ecf-bac52b954b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101354880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1101354880
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3213220004
Short name T520
Test name
Test status
Simulation time 5117044239 ps
CPU time 16.19 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:53:00 PM PDT 24
Peak memory 212012 kb
Host smart-481cfc34-e442-4c03-ba44-fd06a196e26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213220004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3213220004
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1444060454
Short name T293
Test name
Test status
Simulation time 23415086746 ps
CPU time 421.91 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:48:40 PM PDT 24
Peak memory 230140 kb
Host smart-cb40296d-e508-445c-9385-d47dd5d492e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444060454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1444060454
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3434733930
Short name T505
Test name
Test status
Simulation time 64872003257 ps
CPU time 627.25 seconds
Started Mar 28 12:52:35 PM PDT 24
Finished Mar 28 01:03:02 PM PDT 24
Peak memory 238448 kb
Host smart-19a27533-2dcb-4325-b468-c389bdec7741
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434733930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3434733930
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3123419476
Short name T187
Test name
Test status
Simulation time 24544162855 ps
CPU time 56.6 seconds
Started Mar 28 12:41:28 PM PDT 24
Finished Mar 28 12:42:25 PM PDT 24
Peak memory 215600 kb
Host smart-3d504bbd-b014-4899-ac20-312c5853b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123419476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3123419476
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3719961368
Short name T369
Test name
Test status
Simulation time 8712522854 ps
CPU time 69.28 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 12:53:48 PM PDT 24
Peak memory 215464 kb
Host smart-335e8427-7aed-4af5-8af8-35a7f2498717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719961368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3719961368
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1024639117
Short name T347
Test name
Test status
Simulation time 2800541455 ps
CPU time 27.07 seconds
Started Mar 28 12:52:31 PM PDT 24
Finished Mar 28 12:52:59 PM PDT 24
Peak memory 212000 kb
Host smart-dbc7d946-6495-419b-aab2-7b821d69580e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024639117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1024639117
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1135484352
Short name T377
Test name
Test status
Simulation time 14009382175 ps
CPU time 29.78 seconds
Started Mar 28 12:41:38 PM PDT 24
Finished Mar 28 12:42:08 PM PDT 24
Peak memory 212260 kb
Host smart-1ff76829-7a57-4f7c-bc0a-b31bed00da31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135484352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1135484352
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1892318461
Short name T620
Test name
Test status
Simulation time 4787463495 ps
CPU time 52.46 seconds
Started Mar 28 12:41:30 PM PDT 24
Finished Mar 28 12:42:22 PM PDT 24
Peak memory 217972 kb
Host smart-804d76d9-3382-4e6a-bbf8-6ee343d31614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892318461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1892318461
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.620655381
Short name T613
Test name
Test status
Simulation time 4782859038 ps
CPU time 35.59 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:53:09 PM PDT 24
Peak memory 218436 kb
Host smart-5a04b8c3-ef1c-4222-a58d-bf1421842f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620655381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.620655381
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1183662709
Short name T266
Test name
Test status
Simulation time 14398743714 ps
CPU time 84.84 seconds
Started Mar 28 12:52:34 PM PDT 24
Finished Mar 28 12:53:59 PM PDT 24
Peak memory 219860 kb
Host smart-f011a5a0-08e2-47fc-9fce-e5711cfbe305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183662709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1183662709
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2302200413
Short name T606
Test name
Test status
Simulation time 9866195904 ps
CPU time 28.15 seconds
Started Mar 28 12:41:40 PM PDT 24
Finished Mar 28 12:42:08 PM PDT 24
Peak memory 213348 kb
Host smart-fb1d1d5f-e3cf-4e95-a567-5dc796aaf7b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302200413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2302200413
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2969003807
Short name T209
Test name
Test status
Simulation time 993270278 ps
CPU time 9.91 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:41:55 PM PDT 24
Peak memory 211788 kb
Host smart-c0c6eff7-07e4-46c4-9d0b-4227041e33b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969003807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2969003807
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3138116853
Short name T154
Test name
Test status
Simulation time 661918713 ps
CPU time 8.51 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:52:37 PM PDT 24
Peak memory 211788 kb
Host smart-18c3df21-43f4-483b-ad5b-e71c2fea9f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138116853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3138116853
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.533110435
Short name T310
Test name
Test status
Simulation time 20805756366 ps
CPU time 228.97 seconds
Started Mar 28 12:52:43 PM PDT 24
Finished Mar 28 12:56:33 PM PDT 24
Peak memory 240572 kb
Host smart-453b6d73-a298-4767-ae54-a3b4d54db608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533110435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.533110435
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.910598277
Short name T13
Test name
Test status
Simulation time 33388125424 ps
CPU time 342.84 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:47:29 PM PDT 24
Peak memory 226108 kb
Host smart-cae233cc-fdc3-468b-aa75-e753cec8b666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910598277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.910598277
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2305202589
Short name T268
Test name
Test status
Simulation time 5427326966 ps
CPU time 53.39 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:42:40 PM PDT 24
Peak memory 214440 kb
Host smart-8c393db0-b54d-432c-b007-9c788f483f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305202589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2305202589
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3134355239
Short name T651
Test name
Test status
Simulation time 5125670148 ps
CPU time 35.21 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:53:20 PM PDT 24
Peak memory 215656 kb
Host smart-5b49bb64-e491-4f77-8c70-ceef532d698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134355239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3134355239
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3660581432
Short name T586
Test name
Test status
Simulation time 1197356987 ps
CPU time 14.11 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 211948 kb
Host smart-1021af26-4e71-4803-8200-5d6c3b1d2b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660581432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3660581432
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.940784414
Short name T656
Test name
Test status
Simulation time 3132773092 ps
CPU time 18.4 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:42:05 PM PDT 24
Peak memory 213028 kb
Host smart-14f773a4-492d-46b7-8a8b-4fae3721c259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940784414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.940784414
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2265379005
Short name T320
Test name
Test status
Simulation time 17774731024 ps
CPU time 46.21 seconds
Started Mar 28 12:52:43 PM PDT 24
Finished Mar 28 12:53:29 PM PDT 24
Peak memory 216900 kb
Host smart-f06f4486-46c9-4570-9914-921fe0a2b3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265379005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2265379005
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.548220334
Short name T680
Test name
Test status
Simulation time 2474097140 ps
CPU time 36.93 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:42:20 PM PDT 24
Peak memory 219212 kb
Host smart-3d4852a2-8121-48bd-abf6-8d0482fe2489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548220334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.548220334
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1105767689
Short name T663
Test name
Test status
Simulation time 6212545098 ps
CPU time 57.98 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 12:53:37 PM PDT 24
Peak memory 219960 kb
Host smart-71455534-140c-4338-829b-c2cf6f7bbd5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105767689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1105767689
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2220175128
Short name T339
Test name
Test status
Simulation time 11716005218 ps
CPU time 109.15 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 220776 kb
Host smart-343686a1-a987-4b78-ac19-da3095aaa0c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220175128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2220175128
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1347305911
Short name T202
Test name
Test status
Simulation time 13583505342 ps
CPU time 31.53 seconds
Started Mar 28 12:52:39 PM PDT 24
Finished Mar 28 12:53:11 PM PDT 24
Peak memory 212836 kb
Host smart-c4ac6ad0-bce1-4ee7-a761-da29631fe798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347305911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1347305911
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1934228827
Short name T568
Test name
Test status
Simulation time 3314726527 ps
CPU time 27.86 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:42:12 PM PDT 24
Peak memory 212604 kb
Host smart-f290434d-abb6-44e8-be5a-be276a9d60fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934228827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1934228827
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1133767207
Short name T352
Test name
Test status
Simulation time 14792061754 ps
CPU time 279.28 seconds
Started Mar 28 12:41:36 PM PDT 24
Finished Mar 28 12:46:15 PM PDT 24
Peak memory 228244 kb
Host smart-ec121d3e-596c-4fac-b9c6-cf9a2d5a4a09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133767207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1133767207
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4129494159
Short name T415
Test name
Test status
Simulation time 2750086390 ps
CPU time 198.99 seconds
Started Mar 28 12:52:39 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 240316 kb
Host smart-4cc606f9-f976-4023-80ab-677c52948d08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129494159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4129494159
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2195559015
Short name T420
Test name
Test status
Simulation time 1565215368 ps
CPU time 23 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:42:09 PM PDT 24
Peak memory 213952 kb
Host smart-46f3d10d-10f6-4faf-9d40-00bd06d22d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195559015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2195559015
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2855314944
Short name T65
Test name
Test status
Simulation time 48957402908 ps
CPU time 69.28 seconds
Started Mar 28 12:52:37 PM PDT 24
Finished Mar 28 12:53:47 PM PDT 24
Peak memory 214592 kb
Host smart-4fdda999-6708-4d87-90ab-4c2eff0b5158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855314944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2855314944
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1448845934
Short name T635
Test name
Test status
Simulation time 7292432893 ps
CPU time 29.74 seconds
Started Mar 28 12:52:43 PM PDT 24
Finished Mar 28 12:53:13 PM PDT 24
Peak memory 212268 kb
Host smart-675581c1-f2bd-451e-bec4-bf4cdf63ceaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448845934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1448845934
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.964684273
Short name T411
Test name
Test status
Simulation time 17051563282 ps
CPU time 33.65 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:42:18 PM PDT 24
Peak memory 213380 kb
Host smart-7a5b56ba-8a48-4686-8885-ed815461e3a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964684273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.964684273
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3093459039
Short name T186
Test name
Test status
Simulation time 362897674 ps
CPU time 19.79 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 214108 kb
Host smart-7505a887-2ac1-4575-a884-34877baac3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093459039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3093459039
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.813756508
Short name T583
Test name
Test status
Simulation time 54150786763 ps
CPU time 49.88 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:42:36 PM PDT 24
Peak memory 218120 kb
Host smart-bfcd8600-c18b-4bb6-8ad2-d6d5c2377429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813756508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.813756508
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1524498119
Short name T158
Test name
Test status
Simulation time 341459481 ps
CPU time 13.56 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:41:58 PM PDT 24
Peak memory 211624 kb
Host smart-41bf770f-8444-4e3b-a243-5cb45064370f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524498119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1524498119
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4080270418
Short name T456
Test name
Test status
Simulation time 24281150142 ps
CPU time 70.01 seconds
Started Mar 28 12:52:28 PM PDT 24
Finished Mar 28 12:53:39 PM PDT 24
Peak memory 220028 kb
Host smart-4a29675c-7ba4-44fe-b2ee-e721c748588f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080270418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4080270418
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1014038036
Short name T336
Test name
Test status
Simulation time 44669750802 ps
CPU time 3294.99 seconds
Started Mar 28 12:52:38 PM PDT 24
Finished Mar 28 01:47:34 PM PDT 24
Peak memory 232380 kb
Host smart-4abdef8c-9966-4cdb-9e93-f0e220c8f211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014038036 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1014038036
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.537603647
Short name T648
Test name
Test status
Simulation time 2123195238 ps
CPU time 21.38 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:42:06 PM PDT 24
Peak memory 212392 kb
Host smart-ba58532b-1604-4372-b069-87c9a0d17ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537603647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.537603647
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.646380974
Short name T210
Test name
Test status
Simulation time 21981109436 ps
CPU time 26.44 seconds
Started Mar 28 12:52:56 PM PDT 24
Finished Mar 28 12:53:24 PM PDT 24
Peak memory 212000 kb
Host smart-b1216f9b-6b28-46ca-b01c-5f8057e77076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646380974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.646380974
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1476396108
Short name T478
Test name
Test status
Simulation time 175777238767 ps
CPU time 516.02 seconds
Started Mar 28 12:52:33 PM PDT 24
Finished Mar 28 01:01:10 PM PDT 24
Peak memory 229172 kb
Host smart-7e5043dc-0fc2-4f11-b554-81b9e9cb7592
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476396108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1476396108
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.939687581
Short name T618
Test name
Test status
Simulation time 110869997857 ps
CPU time 1028.48 seconds
Started Mar 28 12:41:46 PM PDT 24
Finished Mar 28 12:58:55 PM PDT 24
Peak memory 225284 kb
Host smart-67dfba1b-0c36-4cbf-8d14-0d7f96a8871b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939687581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.939687581
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1468025190
Short name T659
Test name
Test status
Simulation time 3336971474 ps
CPU time 28.64 seconds
Started Mar 28 12:41:45 PM PDT 24
Finished Mar 28 12:42:14 PM PDT 24
Peak memory 214724 kb
Host smart-3c7cff4d-ce35-43ff-854c-9081d386b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468025190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1468025190
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4144182802
Short name T299
Test name
Test status
Simulation time 18935919914 ps
CPU time 49.26 seconds
Started Mar 28 12:52:57 PM PDT 24
Finished Mar 28 12:53:47 PM PDT 24
Peak memory 215720 kb
Host smart-61e8ef79-1a88-4a71-aac7-c58f394c5bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144182802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4144182802
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1617651367
Short name T441
Test name
Test status
Simulation time 7893935717 ps
CPU time 22.23 seconds
Started Mar 28 12:52:39 PM PDT 24
Finished Mar 28 12:53:01 PM PDT 24
Peak memory 212304 kb
Host smart-2e1d581b-20dd-4351-acb8-1b6a08ddcc05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617651367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1617651367
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2723639737
Short name T342
Test name
Test status
Simulation time 4201149522 ps
CPU time 22.56 seconds
Started Mar 28 12:41:42 PM PDT 24
Finished Mar 28 12:42:10 PM PDT 24
Peak memory 211904 kb
Host smart-ebea2e4d-1399-40c2-97d4-cac8c72dad00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723639737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2723639737
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2296714524
Short name T220
Test name
Test status
Simulation time 9538091922 ps
CPU time 31.4 seconds
Started Mar 28 12:52:49 PM PDT 24
Finished Mar 28 12:53:21 PM PDT 24
Peak memory 218560 kb
Host smart-3be4639b-77c3-49a3-8d79-b15d3fd30f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296714524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2296714524
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4081280349
Short name T190
Test name
Test status
Simulation time 705901141 ps
CPU time 20.09 seconds
Started Mar 28 12:41:43 PM PDT 24
Finished Mar 28 12:42:03 PM PDT 24
Peak memory 217964 kb
Host smart-5dad8253-88d8-4c13-a0c9-a7439363bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081280349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4081280349
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3025811096
Short name T115
Test name
Test status
Simulation time 948238298 ps
CPU time 15.94 seconds
Started Mar 28 12:41:44 PM PDT 24
Finished Mar 28 12:42:00 PM PDT 24
Peak memory 213016 kb
Host smart-9fc06096-d377-487d-bd95-afd8860d04f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025811096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3025811096
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3804072690
Short name T639
Test name
Test status
Simulation time 5196766729 ps
CPU time 101.26 seconds
Started Mar 28 12:52:44 PM PDT 24
Finished Mar 28 12:54:26 PM PDT 24
Peak memory 220412 kb
Host smart-ff3f16cd-a7a8-44be-a313-586ca7f66e4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804072690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3804072690
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1382709608
Short name T292
Test name
Test status
Simulation time 15430136508 ps
CPU time 30.55 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:05 PM PDT 24
Peak memory 212884 kb
Host smart-3b202c6d-e82d-4623-9170-1e1bfbf498d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382709608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1382709608
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3069880551
Short name T318
Test name
Test status
Simulation time 15312402611 ps
CPU time 30.66 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:41:09 PM PDT 24
Peak memory 212888 kb
Host smart-2edafcaa-4836-490c-8139-33df0593c3d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069880551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3069880551
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2198481646
Short name T533
Test name
Test status
Simulation time 110716424188 ps
CPU time 259.09 seconds
Started Mar 28 12:51:32 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 240400 kb
Host smart-0cef5362-997c-4d65-891f-516f73a61677
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198481646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2198481646
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2908390991
Short name T254
Test name
Test status
Simulation time 16767428596 ps
CPU time 271.37 seconds
Started Mar 28 12:40:34 PM PDT 24
Finished Mar 28 12:45:07 PM PDT 24
Peak memory 240728 kb
Host smart-8fbfd72a-7895-48b3-9487-4aca6b5a7a59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908390991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2908390991
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3325585807
Short name T29
Test name
Test status
Simulation time 10448147358 ps
CPU time 50.1 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:24 PM PDT 24
Peak memory 215852 kb
Host smart-fee0e2e1-ef06-4a1b-b034-045550ed7fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325585807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3325585807
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.892883520
Short name T231
Test name
Test status
Simulation time 8542032859 ps
CPU time 65.75 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:41:43 PM PDT 24
Peak memory 215780 kb
Host smart-ba3648ee-0786-44d3-8429-3bd3e54a0c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892883520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.892883520
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1381603841
Short name T125
Test name
Test status
Simulation time 21257219626 ps
CPU time 20.1 seconds
Started Mar 28 12:51:35 PM PDT 24
Finished Mar 28 12:51:55 PM PDT 24
Peak memory 213396 kb
Host smart-83bb60e3-e378-4d3c-919c-2c2caf7f56e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381603841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1381603841
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2235422330
Short name T373
Test name
Test status
Simulation time 19796545823 ps
CPU time 29.82 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:09 PM PDT 24
Peak memory 213300 kb
Host smart-1cd6973c-fda1-4736-8975-36ff8b13c780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235422330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2235422330
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3303537761
Short name T290
Test name
Test status
Simulation time 41656650474 ps
CPU time 60.87 seconds
Started Mar 28 12:51:32 PM PDT 24
Finished Mar 28 12:52:34 PM PDT 24
Peak memory 218436 kb
Host smart-3a96c649-fef6-49cc-822d-4f4ba6da5aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303537761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3303537761
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1166709076
Short name T240
Test name
Test status
Simulation time 8162420923 ps
CPU time 105.61 seconds
Started Mar 28 12:40:31 PM PDT 24
Finished Mar 28 12:42:17 PM PDT 24
Peak memory 219880 kb
Host smart-dc4a2c3d-c9fc-4d4c-82be-45ca9af9c39e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166709076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1166709076
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1367684544
Short name T233
Test name
Test status
Simulation time 3366693974 ps
CPU time 44.36 seconds
Started Mar 28 12:51:32 PM PDT 24
Finished Mar 28 12:52:17 PM PDT 24
Peak memory 220900 kb
Host smart-6b0a9717-ee50-41ab-963c-9f74521efa77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367684544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1367684544
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3016491485
Short name T151
Test name
Test status
Simulation time 23715408543 ps
CPU time 20.21 seconds
Started Mar 28 12:40:32 PM PDT 24
Finished Mar 28 12:40:53 PM PDT 24
Peak memory 212888 kb
Host smart-56f92a3b-35aa-462c-b9c7-da2a39ba4d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016491485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3016491485
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.982773743
Short name T591
Test name
Test status
Simulation time 339236709 ps
CPU time 8.26 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:51:42 PM PDT 24
Peak memory 211888 kb
Host smart-6933826b-5700-4444-85f0-a4a88284719a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982773743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.982773743
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1162029500
Short name T309
Test name
Test status
Simulation time 3447937952 ps
CPU time 189.29 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:54:43 PM PDT 24
Peak memory 238988 kb
Host smart-4ca45080-d8b7-464c-99d4-6fd9159a4feb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162029500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1162029500
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2316993312
Short name T394
Test name
Test status
Simulation time 83713555619 ps
CPU time 842.76 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:54:42 PM PDT 24
Peak memory 219584 kb
Host smart-3591226b-0390-4629-9d6d-e761caec690f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316993312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2316993312
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3697633472
Short name T408
Test name
Test status
Simulation time 6372171344 ps
CPU time 59.33 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 215592 kb
Host smart-a792195a-00d9-4521-9444-c03473cbcf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697633472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3697633472
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.563336475
Short name T599
Test name
Test status
Simulation time 12924109008 ps
CPU time 56.57 seconds
Started Mar 28 12:51:28 PM PDT 24
Finished Mar 28 12:52:25 PM PDT 24
Peak memory 215868 kb
Host smart-4aa3cebe-0cc2-4856-89a2-335edecedfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563336475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.563336475
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1655329739
Short name T312
Test name
Test status
Simulation time 3710436772 ps
CPU time 26.42 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:01 PM PDT 24
Peak memory 211884 kb
Host smart-08a47868-62a0-4238-b2be-8e3209672420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655329739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1655329739
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3757098487
Short name T354
Test name
Test status
Simulation time 664317182 ps
CPU time 10.63 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:40:48 PM PDT 24
Peak memory 212632 kb
Host smart-f2c4f97e-ecf8-4586-92cd-2546c0208424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757098487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3757098487
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2608557422
Short name T600
Test name
Test status
Simulation time 1359489610 ps
CPU time 29.07 seconds
Started Mar 28 12:40:40 PM PDT 24
Finished Mar 28 12:41:09 PM PDT 24
Peak memory 217588 kb
Host smart-5053ceed-4f97-4184-8766-d90b9aa94e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608557422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2608557422
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3229417127
Short name T531
Test name
Test status
Simulation time 4950167447 ps
CPU time 45.68 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:19 PM PDT 24
Peak memory 218220 kb
Host smart-6e39b145-80ed-43ba-9f7d-a0656fd87f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229417127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3229417127
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3168780480
Short name T608
Test name
Test status
Simulation time 16104794265 ps
CPU time 98.58 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:42:17 PM PDT 24
Peak memory 219352 kb
Host smart-03cf371e-07ce-4682-9b78-6426dd6bdedc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168780480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3168780480
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3913815464
Short name T515
Test name
Test status
Simulation time 5260043448 ps
CPU time 64.62 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:39 PM PDT 24
Peak memory 219536 kb
Host smart-ceb22cae-2664-497e-9f2d-8f42790c2803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913815464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3913815464
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3626193048
Short name T503
Test name
Test status
Simulation time 4090462554 ps
CPU time 15.7 seconds
Started Mar 28 12:40:35 PM PDT 24
Finished Mar 28 12:40:52 PM PDT 24
Peak memory 212448 kb
Host smart-1f699ece-28de-4e50-ab1c-990a47939f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626193048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3626193048
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4114719059
Short name T340
Test name
Test status
Simulation time 8868433624 ps
CPU time 22.3 seconds
Started Mar 28 12:51:37 PM PDT 24
Finished Mar 28 12:52:00 PM PDT 24
Peak memory 212908 kb
Host smart-5a3ae0c5-ad14-4d18-a6d3-a81495aff162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114719059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4114719059
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2914710491
Short name T390
Test name
Test status
Simulation time 44660797062 ps
CPU time 285.88 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:45:26 PM PDT 24
Peak memory 238384 kb
Host smart-98417d89-c4ac-4b19-9403-1d1e258943ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914710491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2914710491
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.452492352
Short name T145
Test name
Test status
Simulation time 6761014788 ps
CPU time 134.05 seconds
Started Mar 28 12:51:35 PM PDT 24
Finished Mar 28 12:53:49 PM PDT 24
Peak memory 240912 kb
Host smart-99a43e59-12ef-460d-b04c-5b8471c23271
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452492352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.452492352
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3237163433
Short name T195
Test name
Test status
Simulation time 1015273538 ps
CPU time 22.48 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:01 PM PDT 24
Peak memory 215328 kb
Host smart-48e1d66f-4762-4658-83d0-35a5b483635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237163433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3237163433
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.5032936
Short name T434
Test name
Test status
Simulation time 8199375626 ps
CPU time 32.26 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:06 PM PDT 24
Peak memory 216044 kb
Host smart-6eb56e8f-895f-4fd5-8cac-b2386832c306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5032936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.5032936
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1488041082
Short name T634
Test name
Test status
Simulation time 3023394987 ps
CPU time 27.74 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:08 PM PDT 24
Peak memory 213128 kb
Host smart-b10b9962-464f-4ba1-9a09-013ad94246d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488041082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1488041082
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2734586028
Short name T316
Test name
Test status
Simulation time 1356576215 ps
CPU time 14.32 seconds
Started Mar 28 12:51:36 PM PDT 24
Finished Mar 28 12:51:51 PM PDT 24
Peak memory 211808 kb
Host smart-2d2d6b8b-f827-4ded-9f8b-51d26931cd27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734586028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2734586028
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1420597047
Short name T276
Test name
Test status
Simulation time 7295939865 ps
CPU time 63.65 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:41:42 PM PDT 24
Peak memory 217864 kb
Host smart-77b3a710-4468-4144-af7b-c0e9f88e94df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420597047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1420597047
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.342247180
Short name T324
Test name
Test status
Simulation time 35579242797 ps
CPU time 67.72 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:52:42 PM PDT 24
Peak memory 218376 kb
Host smart-6dde55c3-6b1d-4837-be29-cd60efe22023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342247180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.342247180
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3757830253
Short name T71
Test name
Test status
Simulation time 54059861254 ps
CPU time 145 seconds
Started Mar 28 12:40:33 PM PDT 24
Finished Mar 28 12:42:59 PM PDT 24
Peak memory 222044 kb
Host smart-51065739-6cc0-4aff-893c-74558b4863a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757830253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3757830253
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.406716562
Short name T261
Test name
Test status
Simulation time 1090529138 ps
CPU time 61.49 seconds
Started Mar 28 12:51:33 PM PDT 24
Finished Mar 28 12:52:35 PM PDT 24
Peak memory 219816 kb
Host smart-ddaa7117-3440-4acf-b3d4-23eb3fb9737c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406716562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.406716562
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1706321821
Short name T211
Test name
Test status
Simulation time 7679853705 ps
CPU time 30.22 seconds
Started Mar 28 12:51:41 PM PDT 24
Finished Mar 28 12:52:11 PM PDT 24
Peak memory 212856 kb
Host smart-51f24e7c-2efa-4198-ad5a-6b8847c94a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706321821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1706321821
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3276218793
Short name T409
Test name
Test status
Simulation time 3316451173 ps
CPU time 27.64 seconds
Started Mar 28 12:40:33 PM PDT 24
Finished Mar 28 12:41:02 PM PDT 24
Peak memory 212036 kb
Host smart-46a2f9c6-c38c-47c8-b5fb-521da433e0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276218793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3276218793
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2728991541
Short name T46
Test name
Test status
Simulation time 21465102901 ps
CPU time 303.05 seconds
Started Mar 28 12:51:35 PM PDT 24
Finished Mar 28 12:56:39 PM PDT 24
Peak memory 237612 kb
Host smart-45ec3ed2-a16a-4237-8a28-be5fc70f9b53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728991541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2728991541
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.83469147
Short name T111
Test name
Test status
Simulation time 59930741409 ps
CPU time 426.07 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:47:46 PM PDT 24
Peak memory 236552 kb
Host smart-288ce5c8-9df2-474e-a61b-c8e9974b88f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83469147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_cor
rupt_sig_fatal_chk.83469147
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1462047470
Short name T329
Test name
Test status
Simulation time 17430297858 ps
CPU time 70.83 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 214560 kb
Host smart-40432231-5838-4d87-a84a-119918a89a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462047470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1462047470
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1947111414
Short name T422
Test name
Test status
Simulation time 37322470608 ps
CPU time 60.02 seconds
Started Mar 28 12:40:38 PM PDT 24
Finished Mar 28 12:41:39 PM PDT 24
Peak memory 215708 kb
Host smart-bbf92a59-f4b4-4a8e-b93c-7dc5e223ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947111414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1947111414
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1465945620
Short name T464
Test name
Test status
Simulation time 4934943245 ps
CPU time 24.82 seconds
Started Mar 28 12:51:36 PM PDT 24
Finished Mar 28 12:52:01 PM PDT 24
Peak memory 213432 kb
Host smart-1cd80b37-2ae4-47b0-a141-72b997675738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465945620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1465945620
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3219528015
Short name T509
Test name
Test status
Simulation time 2656023685 ps
CPU time 14.9 seconds
Started Mar 28 12:40:34 PM PDT 24
Finished Mar 28 12:40:49 PM PDT 24
Peak memory 212072 kb
Host smart-c4d25a7f-8f63-4a90-9f47-ac3908b88b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219528015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3219528015
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1328596967
Short name T665
Test name
Test status
Simulation time 1433396216 ps
CPU time 20.58 seconds
Started Mar 28 12:40:32 PM PDT 24
Finished Mar 28 12:40:53 PM PDT 24
Peak memory 217208 kb
Host smart-39ec973c-87a5-42b4-80c2-74f82e21ee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328596967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1328596967
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2847560672
Short name T570
Test name
Test status
Simulation time 1435927034 ps
CPU time 19.61 seconds
Started Mar 28 12:51:37 PM PDT 24
Finished Mar 28 12:51:57 PM PDT 24
Peak memory 218060 kb
Host smart-6640165f-081a-4ee1-99ed-2a4ac63604f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847560672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2847560672
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2022788030
Short name T418
Test name
Test status
Simulation time 3655136517 ps
CPU time 17.65 seconds
Started Mar 28 12:51:34 PM PDT 24
Finished Mar 28 12:51:52 PM PDT 24
Peak memory 214084 kb
Host smart-29dc80c5-3d70-470e-96cb-f8ea0ac43b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022788030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2022788030
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3363724332
Short name T412
Test name
Test status
Simulation time 2395792003 ps
CPU time 33.97 seconds
Started Mar 28 12:40:39 PM PDT 24
Finished Mar 28 12:41:14 PM PDT 24
Peak memory 219848 kb
Host smart-dd49cde0-0d2b-4c2f-a904-b8e20bb556cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363724332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3363724332
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3818408312
Short name T126
Test name
Test status
Simulation time 15494103996 ps
CPU time 581.33 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:50:20 PM PDT 24
Peak memory 229220 kb
Host smart-4145c926-4cc0-4116-9022-e2c78123f4ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818408312 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3818408312
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1475727063
Short name T76
Test name
Test status
Simulation time 331721483 ps
CPU time 8.29 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:40:45 PM PDT 24
Peak memory 211880 kb
Host smart-16c0157e-6c3b-4933-a47b-259693ebd7ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475727063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1475727063
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.434233782
Short name T7
Test name
Test status
Simulation time 3220932279 ps
CPU time 27.3 seconds
Started Mar 28 12:51:43 PM PDT 24
Finished Mar 28 12:52:11 PM PDT 24
Peak memory 212544 kb
Host smart-722de123-e728-4ebb-8f26-3231d005ae88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434233782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.434233782
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1834384317
Short name T15
Test name
Test status
Simulation time 181586206707 ps
CPU time 240.09 seconds
Started Mar 28 12:40:34 PM PDT 24
Finished Mar 28 12:44:36 PM PDT 24
Peak memory 237304 kb
Host smart-44f880ef-471a-4b06-a107-81666d800e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834384317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1834384317
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.809582466
Short name T257
Test name
Test status
Simulation time 225631274824 ps
CPU time 448.42 seconds
Started Mar 28 12:51:39 PM PDT 24
Finished Mar 28 12:59:08 PM PDT 24
Peak memory 228240 kb
Host smart-480bc911-55f9-4f3e-9c1b-01b2473728ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809582466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.809582466
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3459495756
Short name T660
Test name
Test status
Simulation time 134372394635 ps
CPU time 66.77 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:46 PM PDT 24
Peak memory 215628 kb
Host smart-695fec59-6763-48d6-844b-86353da61ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459495756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3459495756
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.696098945
Short name T331
Test name
Test status
Simulation time 17472596347 ps
CPU time 71.25 seconds
Started Mar 28 12:51:47 PM PDT 24
Finished Mar 28 12:52:58 PM PDT 24
Peak memory 214136 kb
Host smart-fdc418a1-36ef-4325-8ebf-99f69813cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696098945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.696098945
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2500658658
Short name T628
Test name
Test status
Simulation time 670848912 ps
CPU time 14.69 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:40:52 PM PDT 24
Peak memory 211780 kb
Host smart-25b8db2d-bca9-4dd8-b7c3-e7ec5c99857a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500658658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2500658658
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2904135061
Short name T487
Test name
Test status
Simulation time 4035225628 ps
CPU time 33.79 seconds
Started Mar 28 12:51:49 PM PDT 24
Finished Mar 28 12:52:23 PM PDT 24
Peak memory 211828 kb
Host smart-3dfd0d2b-cd5b-435f-a6eb-b8fbdb288702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904135061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2904135061
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1673517680
Short name T372
Test name
Test status
Simulation time 2333912335 ps
CPU time 35.16 seconds
Started Mar 28 12:51:41 PM PDT 24
Finished Mar 28 12:52:16 PM PDT 24
Peak memory 217712 kb
Host smart-27729330-a4d2-49e2-ac64-10f724cfa509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673517680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1673517680
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3827576675
Short name T264
Test name
Test status
Simulation time 19050441037 ps
CPU time 56.8 seconds
Started Mar 28 12:40:37 PM PDT 24
Finished Mar 28 12:41:35 PM PDT 24
Peak memory 217456 kb
Host smart-d8270259-cd00-4d48-945f-a37954915b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827576675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3827576675
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3479922303
Short name T263
Test name
Test status
Simulation time 919858726 ps
CPU time 57.32 seconds
Started Mar 28 12:40:36 PM PDT 24
Finished Mar 28 12:41:35 PM PDT 24
Peak memory 219812 kb
Host smart-ee883c9c-2a39-4970-a0a9-1e61e7fb0cb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479922303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3479922303
Directory /workspace/9.rom_ctrl_stress_all/latest
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