Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	141379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3568060

1

T3

4

T5

34

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	965133	1			T3	58		T5	349		T6	235
values[0x0]	1346934	1			T10	16988		T24	11674		T25	14154
values[0x1]	1397372	1			T10	17554		T24	12022		T25	14676

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	73942	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3635497

1

T3

31

T5

212

T6

139

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14871	1			T9	3		T10	169		T63	1
valid_sources[0x01]	15651	1			T3	10		T9	2		T10	181
valid_sources[0x02]	15779	1			T9	3		T10	168		T63	1
valid_sources[0x03]	12929	1			T9	1		T10	189		T11	1
valid_sources[0x04]	13958	1			T9	2		T10	165		T63	1
valid_sources[0x05]	12575	1			T5	31		T6	17		T9	1
valid_sources[0x06]	14458	1			T9	3		T10	166		T13	50
valid_sources[0x07]	13835	1			T9	5		T10	177		T46	1
valid_sources[0x08]	15709	1			T10	183		T46	2		T136	3
valid_sources[0x09]	13050	1			T10	181		T136	2		T86	1
valid_sources[0x0a]	14892	1			T9	3		T10	179		T11	1
valid_sources[0x0b]	12148	1			T9	2		T10	182		T119	3
valid_sources[0x0c]	15693	1			T6	34		T9	1		T10	190
valid_sources[0x0d]	13604	1			T9	1		T10	170		T63	1
valid_sources[0x0e]	13494	1			T9	1		T10	176		T12	14
valid_sources[0x0f]	14469	1			T9	4		T10	184		T11	1
valid_sources[0x10]	13503	1			T9	2		T10	163		T11	1
valid_sources[0x11]	15094	1			T10	198		T11	1		T46	2
valid_sources[0x12]	14156	1			T9	3		T10	203		T45	1
valid_sources[0x13]	12954	1			T9	3		T10	163		T13	40
valid_sources[0x14]	14982	1			T9	1		T10	179		T63	1
valid_sources[0x15]	14129	1			T9	1		T10	174		T12	3
valid_sources[0x16]	14647	1			T10	175		T11	2		T86	5
valid_sources[0x17]	15851	1			T10	175		T13	10		T14	1
valid_sources[0x18]	13425	1			T9	1		T10	187		T46	1
valid_sources[0x19]	13200	1			T3	4		T10	185		T70	2
valid_sources[0x1a]	12392	1			T9	2		T10	193		T14	1
valid_sources[0x1b]	14335	1			T9	3		T10	210		T46	2
valid_sources[0x1c]	13833	1			T10	186		T137	3		T136	1
valid_sources[0x1d]	13869	1			T9	2		T10	188		T138	1
valid_sources[0x1e]	14714	1			T6	19		T9	2		T10	181
valid_sources[0x1f]	15612	1			T9	1		T10	179		T11	3
valid_sources[0x20]	14645	1			T9	3		T10	178		T15	18
valid_sources[0x21]	14256	1			T3	2		T9	2		T10	188
valid_sources[0x22]	14376	1			T9	1		T10	192		T46	1
valid_sources[0x23]	15529	1			T9	1		T10	160		T11	1
valid_sources[0x24]	13979	1			T9	2		T10	173		T11	1
valid_sources[0x25]	14932	1			T9	2		T10	163		T136	1
valid_sources[0x26]	11976	1			T9	1		T10	188		T46	1
valid_sources[0x27]	15557	1			T9	1		T10	179		T44	24
valid_sources[0x28]	15165	1			T9	1		T10	196		T119	1
valid_sources[0x29]	11927	1			T9	2		T10	186		T46	2
valid_sources[0x2a]	13779	1			T9	3		T10	182		T119	1
valid_sources[0x2b]	13905	1			T9	3		T10	186		T45	6
valid_sources[0x2c]	13019	1			T10	200		T46	2		T136	1
valid_sources[0x2d]	14836	1			T9	1		T10	203		T11	1
valid_sources[0x2e]	14361	1			T9	1		T10	176		T46	2
valid_sources[0x2f]	13001	1			T9	2		T10	180		T11	1
valid_sources[0x30]	13841	1			T3	2		T9	3		T10	165
valid_sources[0x31]	14768	1			T9	1		T10	180		T45	3
valid_sources[0x32]	14008	1			T9	2		T10	207		T45	2
valid_sources[0x33]	13105	1			T5	16		T9	4		T10	197
valid_sources[0x34]	12529	1			T9	3		T10	195		T11	1
valid_sources[0x35]	13525	1			T9	1		T10	195		T46	2
valid_sources[0x36]	13979	1			T9	2		T10	147		T118	26
valid_sources[0x37]	13744	1			T9	3		T10	189		T46	1
valid_sources[0x38]	14326	1			T9	2		T10	185		T12	1
valid_sources[0x39]	13094	1			T9	4		T10	183		T46	2
valid_sources[0x3a]	14683	1			T9	1		T10	179		T136	2
valid_sources[0x3b]	13373	1			T9	1		T10	188		T138	1
valid_sources[0x3c]	14986	1			T9	6		T10	175		T63	1
valid_sources[0x3d]	14037	1			T3	4		T10	183		T11	1
valid_sources[0x3e]	13293	1			T9	1		T10	179		T63	1
valid_sources[0x3f]	12691	1			T5	73		T9	1		T10	162
valid_sources[0x40]	16122	1			T9	2		T10	188		T46	2
valid_sources[0x41]	15269	1			T9	1		T10	178		T14	1
valid_sources[0x42]	13950	1			T10	193		T12	6		T45	8
valid_sources[0x43]	14345	1			T9	1		T10	184		T45	2
valid_sources[0x44]	15655	1			T5	51		T9	1		T10	192
valid_sources[0x45]	14221	1			T9	3		T10	164		T11	1
valid_sources[0x46]	16534	1			T9	5		T10	159		T46	2
valid_sources[0x47]	13416	1			T10	184		T45	3		T46	2
valid_sources[0x48]	14381	1			T10	172		T86	1		T88	1
valid_sources[0x49]	13830	1			T9	1		T10	176		T13	11
valid_sources[0x4a]	12985	1			T9	1		T10	166		T11	1
valid_sources[0x4b]	14396	1			T5	57		T9	1		T10	178
valid_sources[0x4c]	14300	1			T10	169		T11	2		T45	3
valid_sources[0x4d]	15251	1			T10	191		T11	1		T46	1
valid_sources[0x4e]	15919	1			T9	2		T10	156		T11	1
valid_sources[0x4f]	15408	1			T9	1		T10	150		T118	31
valid_sources[0x50]	13020	1			T10	175		T46	2		T83	1
valid_sources[0x51]	14512	1			T10	182		T46	1		T138	1
valid_sources[0x52]	16772	1			T6	87		T9	5		T10	171
valid_sources[0x53]	14013	1			T10	185		T63	3		T46	2
valid_sources[0x54]	14350	1			T10	185		T46	1		T139	3
valid_sources[0x55]	15215	1			T9	2		T10	186		T11	1
valid_sources[0x56]	15542	1			T9	2		T10	152		T45	2
valid_sources[0x57]	19010	1			T9	1		T10	190		T118	2
valid_sources[0x58]	15600	1			T9	2		T10	187		T12	2
valid_sources[0x59]	14508	1			T9	1		T10	187		T63	2
valid_sources[0x5a]	13852	1			T10	192		T63	1		T46	2
valid_sources[0x5b]	14298	1			T9	1		T10	174		T11	2
valid_sources[0x5c]	17600	1			T9	1		T10	177		T45	1
valid_sources[0x5d]	16052	1			T9	1		T10	183		T11	1
valid_sources[0x5e]	13185	1			T9	6		T10	183		T11	1
valid_sources[0x5f]	13712	1			T9	2		T10	152		T45	1
valid_sources[0x60]	13795	1			T9	1		T10	173		T13	32
valid_sources[0x61]	13924	1			T9	1		T10	196		T139	6
valid_sources[0x62]	16360	1			T9	1		T10	190		T11	2
valid_sources[0x63]	14531	1			T9	3		T10	216		T63	1
valid_sources[0x64]	18173	1			T9	2		T10	182		T11	1
valid_sources[0x65]	16187	1			T3	23		T9	3		T10	199
valid_sources[0x66]	15394	1			T9	1		T10	193		T46	1
valid_sources[0x67]	16504	1			T9	1		T10	198		T46	2
valid_sources[0x68]	13486	1			T9	3		T10	172		T45	23
valid_sources[0x69]	13679	1			T9	1		T10	172		T11	1
valid_sources[0x6a]	15831	1			T9	2		T10	183		T46	1
valid_sources[0x6b]	14412	1			T9	3		T10	198		T14	1
valid_sources[0x6c]	13421	1			T9	1		T10	167		T63	1
valid_sources[0x6d]	15088	1			T9	4		T10	181		T44	9
valid_sources[0x6e]	14363	1			T9	1		T10	192		T63	3
valid_sources[0x6f]	15506	1			T10	180		T14	1		T74	41
valid_sources[0x70]	16093	1			T9	2		T10	175		T46	3
valid_sources[0x71]	13996	1			T9	1		T10	198		T70	4
valid_sources[0x72]	12904	1			T9	1		T10	179		T46	1
valid_sources[0x73]	15499	1			T3	3		T9	1		T10	170
valid_sources[0x74]	13637	1			T9	2		T10	166		T139	13
valid_sources[0x75]	16356	1			T9	3		T10	202		T45	2
valid_sources[0x76]	18150	1			T9	2		T10	199		T46	1
valid_sources[0x77]	17574	1			T9	1		T10	180		T11	1
valid_sources[0x78]	15296	1			T9	2		T10	154		T11	1
valid_sources[0x79]	13802	1			T9	1		T10	197		T44	4
valid_sources[0x7a]	13893	1			T10	197		T70	3		T46	1
valid_sources[0x7b]	16594	1			T9	2		T10	182		T86	3
valid_sources[0x7c]	14667	1			T9	2		T10	192		T12	3
valid_sources[0x7d]	13409	1			T6	15		T9	4		T10	176
valid_sources[0x7e]	14361	1			T9	2		T10	189		T70	2
valid_sources[0x7f]	14477	1			T9	1		T10	204		T11	1
valid_sources[0x80]	14147	1			T9	4		T10	168		T15	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

897226

1

T3

4

T5

34

T6

18

values[0x0]

all_enables

biggest_size

1334948

1

T10

16844

T24

11579

T25

14029

values[0x1]

all_enables

biggest_size

1335886

1

T10

16840

T24

11541

T25

14061

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	264107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2724991

1

T1

1

T2

1

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	745335	1			T1	1		T2	1		T3	32
values[0x0]	1040105	1			T10	12448		T33	2		T35	3
values[0x1]	1203658	1			T10	14355		T34	2		T35	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	117858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2871240

1

T1

1

T2

1

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12935	1			T10	137		T12	2		T72	1
valid_sources[0x01]	11726	1			T10	159		T24	90		T23	1
valid_sources[0x02]	11081	1			T10	128		T30	2		T24	68
valid_sources[0x03]	10816	1			T10	191		T140	2		T24	91
valid_sources[0x04]	12066	1			T10	102		T50	23		T24	101
valid_sources[0x05]	11539	1			T10	129		T24	85		T51	6
valid_sources[0x06]	12023	1			T10	212		T86	1		T24	122
valid_sources[0x07]	12822	1			T10	168		T30	2		T24	76
valid_sources[0x08]	11429	1			T10	126		T24	100		T25	118
valid_sources[0x09]	11214	1			T3	1		T4	3		T10	121
valid_sources[0x0a]	12879	1			T10	113		T20	1		T70	1
valid_sources[0x0b]	12883	1			T10	127		T70	1		T24	108
valid_sources[0x0c]	11159	1			T10	128		T24	106		T25	14
valid_sources[0x0d]	12425	1			T10	182		T138	1		T85	32
valid_sources[0x0e]	11741	1			T10	91		T12	2		T86	1
valid_sources[0x0f]	13226	1			T10	152		T86	1		T24	104
valid_sources[0x10]	11580	1			T10	151		T86	1		T24	108
valid_sources[0x11]	10735	1			T10	197		T15	1		T86	2
valid_sources[0x12]	11446	1			T10	163		T24	113		T141	1
valid_sources[0x13]	11034	1			T10	134		T138	1		T24	125
valid_sources[0x14]	10930	1			T10	134		T15	1		T70	1
valid_sources[0x15]	10903	1			T10	151		T22	1		T24	107
valid_sources[0x16]	13447	1			T10	102		T88	1		T24	88
valid_sources[0x17]	11968	1			T10	122		T86	1		T87	2
valid_sources[0x18]	11382	1			T10	112		T15	6		T70	2
valid_sources[0x19]	10328	1			T10	119		T86	1		T24	100
valid_sources[0x1a]	11155	1			T10	105		T12	5		T24	99
valid_sources[0x1b]	10472	1			T10	145		T70	1		T24	98
valid_sources[0x1c]	12344	1			T10	139		T140	4		T24	107
valid_sources[0x1d]	10268	1			T10	140		T18	1		T24	108
valid_sources[0x1e]	10990	1			T10	134		T24	96		T25	12
valid_sources[0x1f]	10457	1			T10	171		T48	1		T86	2
valid_sources[0x20]	11454	1			T10	149		T86	1		T24	123
valid_sources[0x21]	12982	1			T10	196		T24	94		T141	1
valid_sources[0x22]	11896	1			T10	114		T15	3		T86	1
valid_sources[0x23]	12014	1			T10	180		T15	1		T48	1
valid_sources[0x24]	10684	1			T3	2		T10	147		T33	2
valid_sources[0x25]	12088	1			T10	97		T142	1		T18	2
valid_sources[0x26]	10719	1			T10	156		T24	90		T25	16
valid_sources[0x27]	12235	1			T10	137		T47	1		T138	1
valid_sources[0x28]	10732	1			T10	173		T86	1		T88	3
valid_sources[0x29]	11496	1			T3	3		T10	105		T18	1
valid_sources[0x2a]	10698	1			T10	95		T48	1		T24	117
valid_sources[0x2b]	12508	1			T10	187		T18	1		T88	2
valid_sources[0x2c]	13400	1			T10	127		T18	1		T86	1
valid_sources[0x2d]	12540	1			T10	129		T86	1		T24	113
valid_sources[0x2e]	11850	1			T10	129		T86	2		T88	3
valid_sources[0x2f]	12840	1			T10	164		T88	2		T24	106
valid_sources[0x30]	11812	1			T10	164		T86	2		T87	1
valid_sources[0x31]	11667	1			T10	148		T24	127		T25	323
valid_sources[0x32]	12146	1			T10	153		T138	1		T68	1
valid_sources[0x33]	11840	1			T10	114		T86	1		T24	77
valid_sources[0x34]	11564	1			T10	187		T68	1		T24	83
valid_sources[0x35]	11915	1			T10	122		T48	1		T36	1
valid_sources[0x36]	12416	1			T10	169		T86	1		T24	106
valid_sources[0x37]	12597	1			T3	3		T10	140		T86	1
valid_sources[0x38]	12625	1			T3	3		T10	141		T11	15
valid_sources[0x39]	11070	1			T10	141		T70	1		T35	4
valid_sources[0x3a]	11198	1			T4	1		T10	108		T24	116
valid_sources[0x3b]	12110	1			T10	164		T140	6		T24	133
valid_sources[0x3c]	11794	1			T3	1		T10	119		T18	1
valid_sources[0x3d]	11292	1			T10	132		T70	2		T138	1
valid_sources[0x3e]	10983	1			T10	144		T86	1		T24	80
valid_sources[0x3f]	12078	1			T10	142		T86	2		T88	1
valid_sources[0x40]	11808	1			T10	144		T67	1		T88	1
valid_sources[0x41]	10922	1			T10	141		T15	2		T70	1
valid_sources[0x42]	11193	1			T10	140		T68	1		T84	4
valid_sources[0x43]	12208	1			T10	166		T138	1		T24	89
valid_sources[0x44]	12668	1			T10	101		T119	6		T138	1
valid_sources[0x45]	10314	1			T10	132		T24	139		T25	29
valid_sources[0x46]	11815	1			T4	2		T10	122		T15	3
valid_sources[0x47]	11388	1			T2	1		T10	122		T24	97
valid_sources[0x48]	11015	1			T3	1		T10	111		T119	32
valid_sources[0x49]	11885	1			T10	150		T24	118		T25	197
valid_sources[0x4a]	10886	1			T10	124		T138	1		T24	94
valid_sources[0x4b]	12137	1			T10	134		T86	1		T24	113
valid_sources[0x4c]	10989	1			T10	150		T48	1		T24	100
valid_sources[0x4d]	11709	1			T10	165		T86	1		T24	130
valid_sources[0x4e]	12085	1			T10	106		T12	4		T15	1
valid_sources[0x4f]	11095	1			T10	141		T67	2		T24	110
valid_sources[0x50]	12985	1			T10	155		T48	1		T138	1
valid_sources[0x51]	13296	1			T10	148		T86	2		T24	86
valid_sources[0x52]	11166	1			T10	151		T14	23		T18	1
valid_sources[0x53]	11840	1			T10	184		T15	1		T22	1
valid_sources[0x54]	12471	1			T10	131		T15	1		T24	95
valid_sources[0x55]	13197	1			T10	141		T48	1		T24	87
valid_sources[0x56]	11123	1			T10	173		T18	1		T86	3
valid_sources[0x57]	11890	1			T10	124		T70	1		T68	1
valid_sources[0x58]	12365	1			T10	134		T86	1		T24	89
valid_sources[0x59]	12620	1			T10	185		T22	2		T24	86
valid_sources[0x5a]	11785	1			T7	1		T10	161		T88	1
valid_sources[0x5b]	11045	1			T10	121		T24	98		T141	1
valid_sources[0x5c]	13264	1			T10	161		T86	1		T88	1
valid_sources[0x5d]	12272	1			T10	158		T140	1		T24	85
valid_sources[0x5e]	11822	1			T10	97		T86	1		T24	92
valid_sources[0x5f]	12147	1			T10	120		T18	1		T24	80
valid_sources[0x60]	12713	1			T10	138		T15	2		T86	3
valid_sources[0x61]	11070	1			T10	137		T86	1		T24	112
valid_sources[0x62]	11169	1			T10	181		T36	1		T86	1
valid_sources[0x63]	11085	1			T10	124		T48	1		T86	1
valid_sources[0x64]	11814	1			T10	175		T48	1		T86	1
valid_sources[0x65]	12286	1			T10	179		T70	1		T34	1
valid_sources[0x66]	13098	1			T10	158		T24	101		T25	74
valid_sources[0x67]	12421	1			T10	131		T86	1		T24	75
valid_sources[0x68]	11409	1			T10	176		T86	1		T88	4
valid_sources[0x69]	11385	1			T10	190		T86	1		T24	101
valid_sources[0x6a]	10999	1			T10	104		T22	2		T86	3
valid_sources[0x6b]	11589	1			T10	169		T24	104		T25	14
valid_sources[0x6c]	11470	1			T10	192		T24	79		T25	4
valid_sources[0x6d]	10908	1			T10	173		T86	1		T24	79
valid_sources[0x6e]	11976	1			T10	119		T70	1		T30	1
valid_sources[0x6f]	11452	1			T10	121		T86	2		T24	101
valid_sources[0x70]	12487	1			T10	166		T86	1		T88	1
valid_sources[0x71]	10773	1			T10	149		T30	4		T88	1
valid_sources[0x72]	11054	1			T10	118		T138	1		T86	1
valid_sources[0x73]	12504	1			T10	177		T24	103		T141	2
valid_sources[0x74]	11624	1			T10	144		T15	1		T86	1
valid_sources[0x75]	11673	1			T10	151		T15	1		T88	1
valid_sources[0x76]	12168	1			T10	155		T24	94		T25	20
valid_sources[0x77]	11100	1			T10	131		T15	1		T48	1
valid_sources[0x78]	11645	1			T10	128		T45	160		T24	77
valid_sources[0x79]	11634	1			T10	87		T11	6		T15	1
valid_sources[0x7a]	12554	1			T10	87		T86	2		T24	82
valid_sources[0x7b]	11567	1			T10	127		T48	1		T86	1
valid_sources[0x7c]	14315	1			T10	112		T15	1		T30	1
valid_sources[0x7d]	11504	1			T10	155		T86	2		T24	91
valid_sources[0x7e]	12025	1			T10	142		T24	71		T25	1
valid_sources[0x7f]	10366	1			T10	151		T18	1		T86	2
valid_sources[0x80]	11145	1			T10	172		T15	3		T48	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

687733

1

T1

1

T2

1

T3

14

values[0x0]

all_enables

biggest_size

1018931

1

T10

12188

T33

1

T35

2

values[0x1]

all_enables

biggest_size

1018327

1

T10

11987

T36

1

T67

2