Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6504037

1

T3

54

T5

315

T6

217

full_word

4161367

1

T3

4

T5

34

T6

18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	10664824	1			T3	58		T5	349		T6	235
auto[TlIntgErrCmd]	185	1			T60	1		T61	4		T62	2
auto[TlIntgErrData]	202	1			T60	6		T61	2		T62	2
auto[TlIntgErrBoth]	193	1			T60	3		T61	4		T62	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1682933

1

T3

58

T5

349

T6

235

auto[1]

8982471

1

T10

110365

T24

73227

T25

93022

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	699168	1			T3	54		T5	315		T6	217
auto[TlIntgErrNone]	partial	auto[1]	5804346	1			T10	70459		T24	46026		T25	59642
auto[TlIntgErrNone]	full_word	auto[0]	983504	1			T3	4		T5	34		T6	18
auto[TlIntgErrNone]	full_word	auto[1]	3177806	1			T10	39906		T24	27201		T25	33380
auto[TlIntgErrCmd]	partial	auto[0]	76	1			T61	2		T130	2		T125	2
auto[TlIntgErrCmd]	partial	auto[1]	87	1			T60	1		T61	1		T62	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T61	1		T125	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	15	1			T62	1		T130	1		T125	2
auto[TlIntgErrData]	partial	auto[0]	79	1			T62	2		T130	1		T125	2
auto[TlIntgErrData]	partial	auto[1]	101	1			T60	4		T61	1		T125	4
auto[TlIntgErrData]	full_word	auto[0]	13	1			T125	1		T132	1		T127	2
auto[TlIntgErrData]	full_word	auto[1]	9	1			T60	2		T61	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	80	1			T60	2		T61	1		T62	3
auto[TlIntgErrBoth]	partial	auto[1]	100	1			T60	1		T61	2		T62	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T61	1		T123	1		T133	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T131	1		T134	1		T135	1