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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 96.96 93.40 97.88 100.00 98.68 98.04 98.37


Total test records in report: 930
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T757 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2494252884 Mar 31 12:32:27 PM PDT 24 Mar 31 12:32:54 PM PDT 24 2322018268 ps
T758 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2727408434 Mar 31 12:32:53 PM PDT 24 Mar 31 12:32:58 PM PDT 24 333311110 ps
T759 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1959091921 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:14 PM PDT 24 382687470 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.906920797 Mar 31 12:32:26 PM PDT 24 Mar 31 12:33:17 PM PDT 24 6102013596 ps
T760 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3923478046 Mar 31 12:32:29 PM PDT 24 Mar 31 12:32:33 PM PDT 24 88962743 ps
T761 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1503944907 Mar 31 12:32:53 PM PDT 24 Mar 31 12:33:09 PM PDT 24 3429767078 ps
T762 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1949576590 Mar 31 12:23:51 PM PDT 24 Mar 31 12:24:03 PM PDT 24 1920765238 ps
T763 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.40128283 Mar 31 12:23:48 PM PDT 24 Mar 31 12:23:53 PM PDT 24 89110185 ps
T764 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.325442221 Mar 31 12:23:42 PM PDT 24 Mar 31 12:25:07 PM PDT 24 40016276576 ps
T765 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.646545236 Mar 31 12:23:47 PM PDT 24 Mar 31 12:24:07 PM PDT 24 13228154673 ps
T766 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1244908737 Mar 31 12:24:56 PM PDT 24 Mar 31 12:25:44 PM PDT 24 72587972415 ps
T767 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3115916348 Mar 31 12:23:58 PM PDT 24 Mar 31 12:24:10 PM PDT 24 2247728177 ps
T768 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3469535178 Mar 31 12:23:44 PM PDT 24 Mar 31 12:24:20 PM PDT 24 586969674 ps
T769 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2216252637 Mar 31 12:32:39 PM PDT 24 Mar 31 12:32:56 PM PDT 24 2027014692 ps
T132 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.64299105 Mar 31 12:32:45 PM PDT 24 Mar 31 12:33:30 PM PDT 24 1865739753 ps
T770 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3454676496 Mar 31 12:32:55 PM PDT 24 Mar 31 12:34:02 PM PDT 24 422758336 ps
T771 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4143965762 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:24 PM PDT 24 1903946052 ps
T772 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3903668065 Mar 31 12:23:52 PM PDT 24 Mar 31 12:24:01 PM PDT 24 931985638 ps
T127 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.870304215 Mar 31 12:32:48 PM PDT 24 Mar 31 12:34:06 PM PDT 24 1837810981 ps
T773 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1531338669 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:40 PM PDT 24 383893746 ps
T774 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1854438634 Mar 31 12:23:38 PM PDT 24 Mar 31 12:23:58 PM PDT 24 2056001715 ps
T775 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1997153483 Mar 31 12:26:05 PM PDT 24 Mar 31 12:26:14 PM PDT 24 1235880153 ps
T776 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4020783399 Mar 31 12:24:00 PM PDT 24 Mar 31 12:24:04 PM PDT 24 89835399 ps
T777 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3685948352 Mar 31 12:32:31 PM PDT 24 Mar 31 12:33:09 PM PDT 24 7031990774 ps
T778 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.317974503 Mar 31 12:32:40 PM PDT 24 Mar 31 12:32:45 PM PDT 24 517987520 ps
T779 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1154687581 Mar 31 12:32:41 PM PDT 24 Mar 31 12:32:48 PM PDT 24 1132218883 ps
T780 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.815700995 Mar 31 12:32:46 PM PDT 24 Mar 31 12:32:58 PM PDT 24 997338386 ps
T781 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.916856017 Mar 31 12:32:56 PM PDT 24 Mar 31 12:34:08 PM PDT 24 4310223396 ps
T782 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1699657783 Mar 31 12:23:58 PM PDT 24 Mar 31 12:24:07 PM PDT 24 1906379227 ps
T783 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.883438896 Mar 31 12:32:59 PM PDT 24 Mar 31 12:33:03 PM PDT 24 167883546 ps
T784 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.425417541 Mar 31 12:24:04 PM PDT 24 Mar 31 12:24:14 PM PDT 24 1005092785 ps
T785 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2314070361 Mar 31 12:23:48 PM PDT 24 Mar 31 12:24:03 PM PDT 24 12179891726 ps
T786 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2206679638 Mar 31 12:32:25 PM PDT 24 Mar 31 12:32:29 PM PDT 24 517900705 ps
T787 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2527287112 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:29 PM PDT 24 2196942286 ps
T788 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4206137856 Mar 31 12:23:50 PM PDT 24 Mar 31 12:24:00 PM PDT 24 1493701859 ps
T789 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.659698016 Mar 31 12:23:51 PM PDT 24 Mar 31 12:23:59 PM PDT 24 1173742464 ps
T790 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1125028197 Mar 31 12:32:47 PM PDT 24 Mar 31 12:32:51 PM PDT 24 378215216 ps
T791 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3525864558 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:03 PM PDT 24 1680679519 ps
T792 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.884928721 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:53 PM PDT 24 6877620177 ps
T793 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3518610761 Mar 31 12:23:42 PM PDT 24 Mar 31 12:23:46 PM PDT 24 332673942 ps
T794 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.72961389 Mar 31 12:23:42 PM PDT 24 Mar 31 12:23:53 PM PDT 24 7370881203 ps
T795 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.249869614 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:17 PM PDT 24 4427290064 ps
T796 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1812103551 Mar 31 12:32:40 PM PDT 24 Mar 31 12:32:47 PM PDT 24 352933051 ps
T797 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3755071490 Mar 31 12:32:36 PM PDT 24 Mar 31 12:32:49 PM PDT 24 1719673056 ps
T798 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.914885768 Mar 31 12:32:27 PM PDT 24 Mar 31 12:32:38 PM PDT 24 821673982 ps
T799 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.576184176 Mar 31 12:32:54 PM PDT 24 Mar 31 12:33:02 PM PDT 24 2864862800 ps
T800 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4241278874 Mar 31 12:32:26 PM PDT 24 Mar 31 12:32:41 PM PDT 24 7690550966 ps
T801 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.625339376 Mar 31 12:32:40 PM PDT 24 Mar 31 12:33:50 PM PDT 24 2333560881 ps
T802 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.995804969 Mar 31 12:32:36 PM PDT 24 Mar 31 12:32:50 PM PDT 24 6037035446 ps
T803 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.298873914 Mar 31 12:32:32 PM PDT 24 Mar 31 12:32:36 PM PDT 24 175590925 ps
T804 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3948435021 Mar 31 12:32:28 PM PDT 24 Mar 31 12:32:44 PM PDT 24 4538632398 ps
T805 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3340300840 Mar 31 12:23:32 PM PDT 24 Mar 31 12:23:49 PM PDT 24 11516166469 ps
T806 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.119409798 Mar 31 12:24:00 PM PDT 24 Mar 31 12:24:14 PM PDT 24 26975324905 ps
T807 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3019562397 Mar 31 12:32:47 PM PDT 24 Mar 31 12:32:57 PM PDT 24 934778266 ps
T808 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3769688567 Mar 31 12:32:40 PM PDT 24 Mar 31 12:32:48 PM PDT 24 201170092 ps
T809 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2639958943 Mar 31 12:32:40 PM PDT 24 Mar 31 12:32:56 PM PDT 24 7514794611 ps
T810 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4195861874 Mar 31 12:24:02 PM PDT 24 Mar 31 12:24:15 PM PDT 24 2147844764 ps
T135 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1243425354 Mar 31 12:32:39 PM PDT 24 Mar 31 12:33:26 PM PDT 24 5206396567 ps
T811 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1077485741 Mar 31 12:23:51 PM PDT 24 Mar 31 12:25:02 PM PDT 24 366685031 ps
T812 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1519777882 Mar 31 12:32:55 PM PDT 24 Mar 31 12:32:59 PM PDT 24 383889329 ps
T813 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2769364229 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:25 PM PDT 24 7297310827 ps
T814 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2821829477 Mar 31 12:32:48 PM PDT 24 Mar 31 12:33:01 PM PDT 24 1386643843 ps
T815 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.643913465 Mar 31 12:32:52 PM PDT 24 Mar 31 12:33:03 PM PDT 24 4288972343 ps
T816 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1399227545 Mar 31 12:23:53 PM PDT 24 Mar 31 12:24:04 PM PDT 24 1153175970 ps
T817 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1458281822 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:54 PM PDT 24 742620831 ps
T128 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.693052758 Mar 31 12:32:25 PM PDT 24 Mar 31 12:33:05 PM PDT 24 1139900764 ps
T818 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2845715974 Mar 31 12:23:53 PM PDT 24 Mar 31 12:24:29 PM PDT 24 297247717 ps
T819 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2880456449 Mar 31 12:32:56 PM PDT 24 Mar 31 12:33:15 PM PDT 24 386271040 ps
T820 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3049000586 Mar 31 12:23:58 PM PDT 24 Mar 31 12:24:11 PM PDT 24 1542513651 ps
T821 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3171286588 Mar 31 12:24:04 PM PDT 24 Mar 31 12:24:16 PM PDT 24 6532723463 ps
T822 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1269930655 Mar 31 12:23:32 PM PDT 24 Mar 31 12:23:47 PM PDT 24 1609985068 ps
T823 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.158140337 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:45 PM PDT 24 2398654791 ps
T824 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2003600952 Mar 31 12:24:09 PM PDT 24 Mar 31 12:24:20 PM PDT 24 3918508085 ps
T825 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1925927352 Mar 31 12:33:00 PM PDT 24 Mar 31 12:33:15 PM PDT 24 3432231309 ps
T826 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1719862376 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:11 PM PDT 24 661820780 ps
T827 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4102670214 Mar 31 12:32:40 PM PDT 24 Mar 31 12:32:45 PM PDT 24 1551153672 ps
T828 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2651533560 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:23 PM PDT 24 1278818333 ps
T829 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2650044214 Mar 31 12:23:40 PM PDT 24 Mar 31 12:24:07 PM PDT 24 1400153946 ps
T830 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3695329888 Mar 31 12:23:54 PM PDT 24 Mar 31 12:24:04 PM PDT 24 2140233818 ps
T831 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1157707005 Mar 31 12:32:25 PM PDT 24 Mar 31 12:32:33 PM PDT 24 2838800224 ps
T832 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.939847788 Mar 31 12:32:34 PM PDT 24 Mar 31 12:32:43 PM PDT 24 8714029214 ps
T833 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2132967902 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:45 PM PDT 24 7391483663 ps
T834 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.483795730 Mar 31 12:32:52 PM PDT 24 Mar 31 12:33:32 PM PDT 24 962523765 ps
T835 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1208844637 Mar 31 12:24:59 PM PDT 24 Mar 31 12:25:10 PM PDT 24 1122559574 ps
T836 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.991053934 Mar 31 12:32:34 PM PDT 24 Mar 31 12:32:41 PM PDT 24 1210912048 ps
T837 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2289999477 Mar 31 12:32:37 PM PDT 24 Mar 31 12:32:45 PM PDT 24 920958049 ps
T838 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2682495411 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:49 PM PDT 24 3420330994 ps
T839 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.801863682 Mar 31 12:32:53 PM PDT 24 Mar 31 12:34:31 PM PDT 24 24701944460 ps
T840 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2112800169 Mar 31 12:23:43 PM PDT 24 Mar 31 12:23:54 PM PDT 24 1040204269 ps
T841 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2663695493 Mar 31 12:24:07 PM PDT 24 Mar 31 12:24:18 PM PDT 24 1883986702 ps
T842 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2425079132 Mar 31 12:32:55 PM PDT 24 Mar 31 12:33:14 PM PDT 24 1439382255 ps
T843 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.975787201 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:48 PM PDT 24 5912643926 ps
T844 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3008747330 Mar 31 12:23:38 PM PDT 24 Mar 31 12:24:50 PM PDT 24 1047355745 ps
T845 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3211898458 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:53 PM PDT 24 2095864424 ps
T846 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.555318519 Mar 31 12:32:39 PM PDT 24 Mar 31 12:32:53 PM PDT 24 6499873020 ps
T847 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.40706269 Mar 31 12:32:54 PM PDT 24 Mar 31 12:34:11 PM PDT 24 15281664602 ps
T848 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4218188190 Mar 31 12:32:34 PM PDT 24 Mar 31 12:33:38 PM PDT 24 7860206577 ps
T849 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4049981480 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:17 PM PDT 24 2870296239 ps
T850 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1126938464 Mar 31 12:32:40 PM PDT 24 Mar 31 12:33:22 PM PDT 24 30326294016 ps
T851 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3807695660 Mar 31 12:23:48 PM PDT 24 Mar 31 12:24:29 PM PDT 24 1071698800 ps
T852 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1906531360 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:17 PM PDT 24 1511544069 ps
T853 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2055547415 Mar 31 12:23:41 PM PDT 24 Mar 31 12:23:53 PM PDT 24 453388057 ps
T854 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2434976143 Mar 31 12:23:57 PM PDT 24 Mar 31 12:25:05 PM PDT 24 494432768 ps
T855 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2781884181 Mar 31 12:24:56 PM PDT 24 Mar 31 12:25:07 PM PDT 24 689656988 ps
T856 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.212296814 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:21 PM PDT 24 1897183740 ps
T857 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2666211532 Mar 31 12:32:24 PM PDT 24 Mar 31 12:32:29 PM PDT 24 175258872 ps
T858 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2556006541 Mar 31 12:32:39 PM PDT 24 Mar 31 12:32:45 PM PDT 24 1434403193 ps
T859 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1563563028 Mar 31 12:23:43 PM PDT 24 Mar 31 12:23:56 PM PDT 24 1243694242 ps
T860 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3219406978 Mar 31 12:25:56 PM PDT 24 Mar 31 12:26:09 PM PDT 24 1731246350 ps
T861 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2561027685 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:29 PM PDT 24 4067532478 ps
T862 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1031016061 Mar 31 12:23:49 PM PDT 24 Mar 31 12:23:56 PM PDT 24 2608980989 ps
T863 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1501659604 Mar 31 12:23:43 PM PDT 24 Mar 31 12:23:53 PM PDT 24 5181763881 ps
T864 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3163535138 Mar 31 12:23:43 PM PDT 24 Mar 31 12:23:52 PM PDT 24 803755771 ps
T865 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1075264468 Mar 31 12:32:46 PM PDT 24 Mar 31 12:32:58 PM PDT 24 1245098035 ps
T866 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2427665888 Mar 31 12:23:46 PM PDT 24 Mar 31 12:23:55 PM PDT 24 2794200847 ps
T867 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2574971318 Mar 31 12:32:53 PM PDT 24 Mar 31 12:33:01 PM PDT 24 1725883886 ps
T868 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3229344085 Mar 31 12:32:28 PM PDT 24 Mar 31 12:32:42 PM PDT 24 7465610698 ps
T869 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2693395867 Mar 31 12:32:29 PM PDT 24 Mar 31 12:32:34 PM PDT 24 85450462 ps
T870 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.546206253 Mar 31 12:32:24 PM PDT 24 Mar 31 12:32:31 PM PDT 24 680576364 ps
T871 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1818056804 Mar 31 12:32:45 PM PDT 24 Mar 31 12:33:29 PM PDT 24 4177454653 ps
T872 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3952014469 Mar 31 12:32:56 PM PDT 24 Mar 31 12:33:43 PM PDT 24 19793005138 ps
T873 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.957380761 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:25 PM PDT 24 17619928739 ps
T874 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2003480861 Mar 31 12:24:10 PM PDT 24 Mar 31 12:25:25 PM PDT 24 5132087113 ps
T129 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4081616541 Mar 31 12:24:03 PM PDT 24 Mar 31 12:25:17 PM PDT 24 1644565756 ps
T875 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2845457512 Mar 31 12:24:00 PM PDT 24 Mar 31 12:24:06 PM PDT 24 89289038 ps
T876 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1210379776 Mar 31 12:32:49 PM PDT 24 Mar 31 12:32:56 PM PDT 24 768806402 ps
T877 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1274723142 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:17 PM PDT 24 1409356774 ps
T878 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1414658408 Mar 31 12:23:47 PM PDT 24 Mar 31 12:23:57 PM PDT 24 1345153666 ps
T879 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3146628203 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:02 PM PDT 24 1471697092 ps
T880 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3268711500 Mar 31 12:32:48 PM PDT 24 Mar 31 12:33:03 PM PDT 24 1528144215 ps
T881 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1240443991 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:14 PM PDT 24 626359110 ps
T882 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1128895575 Mar 31 12:26:04 PM PDT 24 Mar 31 12:26:10 PM PDT 24 214784626 ps
T883 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.348397609 Mar 31 12:24:56 PM PDT 24 Mar 31 12:25:35 PM PDT 24 6651708276 ps
T884 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.427446917 Mar 31 12:23:45 PM PDT 24 Mar 31 12:23:51 PM PDT 24 1040450440 ps
T885 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2959317781 Mar 31 12:32:58 PM PDT 24 Mar 31 12:33:47 PM PDT 24 13562107872 ps
T886 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.945418707 Mar 31 12:32:55 PM PDT 24 Mar 31 12:33:09 PM PDT 24 1703456827 ps
T887 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4066461202 Mar 31 12:32:34 PM PDT 24 Mar 31 12:32:44 PM PDT 24 2557356679 ps
T888 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2866212121 Mar 31 12:32:52 PM PDT 24 Mar 31 12:33:03 PM PDT 24 471261004 ps
T889 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1913988802 Mar 31 12:32:55 PM PDT 24 Mar 31 12:33:11 PM PDT 24 7863687556 ps
T890 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3916417228 Mar 31 12:23:45 PM PDT 24 Mar 31 12:24:02 PM PDT 24 1800472753 ps
T891 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3471274852 Mar 31 12:32:56 PM PDT 24 Mar 31 12:33:21 PM PDT 24 1041039364 ps
T892 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1030664913 Mar 31 12:32:38 PM PDT 24 Mar 31 12:33:13 PM PDT 24 2678762607 ps
T893 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3303014006 Mar 31 12:33:00 PM PDT 24 Mar 31 12:33:13 PM PDT 24 1131033478 ps
T894 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3696279077 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:21 PM PDT 24 175243320 ps
T895 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1056237793 Mar 31 12:32:40 PM PDT 24 Mar 31 12:32:45 PM PDT 24 168004164 ps
T896 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3934349549 Mar 31 12:23:34 PM PDT 24 Mar 31 12:23:50 PM PDT 24 19695650076 ps
T897 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2027860588 Mar 31 12:33:01 PM PDT 24 Mar 31 12:33:14 PM PDT 24 1421813666 ps
T898 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.566722801 Mar 31 12:23:59 PM PDT 24 Mar 31 12:24:08 PM PDT 24 457993991 ps
T899 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3073725432 Mar 31 12:32:26 PM PDT 24 Mar 31 12:32:41 PM PDT 24 5711628307 ps
T900 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3957233626 Mar 31 12:23:52 PM PDT 24 Mar 31 12:24:07 PM PDT 24 3742201898 ps
T901 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3810601499 Mar 31 12:32:32 PM PDT 24 Mar 31 12:32:39 PM PDT 24 748123141 ps
T902 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3303121166 Mar 31 12:32:52 PM PDT 24 Mar 31 12:32:58 PM PDT 24 187484097 ps
T903 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3282609848 Mar 31 12:32:54 PM PDT 24 Mar 31 12:33:02 PM PDT 24 2761080548 ps
T904 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1668439979 Mar 31 12:32:53 PM PDT 24 Mar 31 12:33:06 PM PDT 24 3752474520 ps
T905 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3963971345 Mar 31 12:23:43 PM PDT 24 Mar 31 12:23:53 PM PDT 24 975685143 ps
T906 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3358271380 Mar 31 12:32:48 PM PDT 24 Mar 31 12:33:02 PM PDT 24 2018965889 ps
T907 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2308687473 Mar 31 12:23:53 PM PDT 24 Mar 31 12:24:01 PM PDT 24 660670745 ps
T908 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3719703217 Mar 31 12:32:40 PM PDT 24 Mar 31 12:32:57 PM PDT 24 3768535541 ps
T909 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3128240030 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:07 PM PDT 24 347362705 ps
T910 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1769110391 Mar 31 12:32:46 PM PDT 24 Mar 31 12:33:05 PM PDT 24 4093468389 ps
T911 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.981295548 Mar 31 12:32:39 PM PDT 24 Mar 31 12:33:15 PM PDT 24 572043182 ps
T912 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1994014238 Mar 31 12:23:56 PM PDT 24 Mar 31 12:24:10 PM PDT 24 6343305569 ps
T913 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3287138407 Mar 31 12:32:34 PM PDT 24 Mar 31 12:32:44 PM PDT 24 655254618 ps
T914 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.983432519 Mar 31 12:23:59 PM PDT 24 Mar 31 12:25:14 PM PDT 24 7733598108 ps
T915 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2411614725 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:05 PM PDT 24 85391086 ps
T916 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3721905891 Mar 31 12:32:25 PM PDT 24 Mar 31 12:32:41 PM PDT 24 1633609649 ps
T917 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1633027076 Mar 31 12:32:52 PM PDT 24 Mar 31 12:33:01 PM PDT 24 617971088 ps
T918 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1055886080 Mar 31 12:23:42 PM PDT 24 Mar 31 12:23:57 PM PDT 24 1946116790 ps
T919 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1172822925 Mar 31 12:23:55 PM PDT 24 Mar 31 12:25:39 PM PDT 24 176317371667 ps
T920 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1389741383 Mar 31 12:32:34 PM PDT 24 Mar 31 12:32:38 PM PDT 24 829547878 ps
T921 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2603231865 Mar 31 12:25:12 PM PDT 24 Mar 31 12:25:19 PM PDT 24 105250599 ps
T922 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2063950468 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:11 PM PDT 24 857443327 ps
T923 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1071186847 Mar 31 12:24:56 PM PDT 24 Mar 31 12:25:16 PM PDT 24 2073618326 ps
T924 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1260591163 Mar 31 12:32:33 PM PDT 24 Mar 31 12:32:39 PM PDT 24 812405122 ps
T925 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3744612155 Mar 31 12:23:42 PM PDT 24 Mar 31 12:24:46 PM PDT 24 32868321608 ps
T926 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4282125845 Mar 31 12:23:36 PM PDT 24 Mar 31 12:23:40 PM PDT 24 114814820 ps
T927 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3482792227 Mar 31 12:32:46 PM PDT 24 Mar 31 12:32:55 PM PDT 24 602733559 ps
T928 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1702245142 Mar 31 12:32:47 PM PDT 24 Mar 31 12:33:18 PM PDT 24 6471460614 ps
T929 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3656479330 Mar 31 12:23:58 PM PDT 24 Mar 31 12:24:11 PM PDT 24 1214428167 ps
T930 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3343741624 Mar 31 12:32:55 PM PDT 24 Mar 31 12:33:11 PM PDT 24 1064859293 ps

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2468350708
Short name T10
Test name
Test status
Simulation time 50366431783 ps
CPU time 685.65 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:40:05 PM PDT 24
Peak memory 236092 kb
Host smart-ce64f3a7-0ce3-43d5-8975-0aa0623f0d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468350708 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2468350708
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3593808353
Short name T14
Test name
Test status
Simulation time 14372569533 ps
CPU time 202.18 seconds
Started Mar 31 12:28:52 PM PDT 24
Finished Mar 31 12:32:14 PM PDT 24
Peak memory 238344 kb
Host smart-05d8e6cd-c8df-409f-97a6-79afc40ee012
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593808353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3593808353
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.157400309
Short name T125
Test name
Test status
Simulation time 485696198 ps
CPU time 66.88 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 211612 kb
Host smart-5ec7d509-1b1c-4ef5-82a2-15d219194b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157400309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.157400309
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3239152202
Short name T3
Test name
Test status
Simulation time 188717349 ps
CPU time 9.94 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 219716 kb
Host smart-ce1eccec-3351-443b-99a2-e2aa9395ca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239152202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3239152202
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2755564378
Short name T30
Test name
Test status
Simulation time 6890964001 ps
CPU time 105.96 seconds
Started Mar 31 12:28:34 PM PDT 24
Finished Mar 31 12:30:20 PM PDT 24
Peak memory 237336 kb
Host smart-34fdb709-235d-4a08-9fcd-30cbf385df24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755564378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2755564378
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3615270510
Short name T65
Test name
Test status
Simulation time 4141114054 ps
CPU time 54.15 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:25:00 PM PDT 24
Peak memory 210840 kb
Host smart-64cb0fe7-5dd1-447c-84d9-f1eee6f6fd8b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615270510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3615270510
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4056477975
Short name T61
Test name
Test status
Simulation time 415962404 ps
CPU time 37.44 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:24:28 PM PDT 24
Peak memory 211600 kb
Host smart-10a717c2-5808-48b6-b0b8-af7b2e25c4d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056477975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4056477975
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1923188992
Short name T29
Test name
Test status
Simulation time 47840044963 ps
CPU time 4841.76 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 01:49:38 PM PDT 24
Peak memory 235832 kb
Host smart-be393b03-f809-434a-b5c9-589dca5812f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923188992 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1923188992
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2060927019
Short name T15
Test name
Test status
Simulation time 389157439 ps
CPU time 20.01 seconds
Started Mar 31 12:47:23 PM PDT 24
Finished Mar 31 12:47:43 PM PDT 24
Peak memory 215252 kb
Host smart-259900da-5be4-4ff9-aa39-225ec767abaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060927019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2060927019
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1028100218
Short name T1
Test name
Test status
Simulation time 16962286729 ps
CPU time 32.78 seconds
Started Mar 31 12:45:47 PM PDT 24
Finished Mar 31 12:46:20 PM PDT 24
Peak memory 212676 kb
Host smart-c7b941f9-9d8d-4d81-be67-2a12f3d6b7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028100218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1028100218
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.808017451
Short name T68
Test name
Test status
Simulation time 3760445082 ps
CPU time 9.98 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 211884 kb
Host smart-0232f504-c298-494b-b93a-1231f9a38c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808017451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.808017451
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3892236748
Short name T17
Test name
Test status
Simulation time 1843732712 ps
CPU time 9.12 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:28:53 PM PDT 24
Peak memory 212232 kb
Host smart-e33e7167-4edd-47b9-a2ce-672c0678629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892236748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3892236748
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4081616541
Short name T129
Test name
Test status
Simulation time 1644565756 ps
CPU time 74.03 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:25:17 PM PDT 24
Peak memory 211644 kb
Host smart-eca699c1-ca17-4f4c-9bba-9eb532012359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081616541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4081616541
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3769540366
Short name T95
Test name
Test status
Simulation time 48397237087 ps
CPU time 94.07 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:25:35 PM PDT 24
Peak memory 210840 kb
Host smart-7c90b5e9-a2b5-40ee-8da5-d400f0b5c0bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769540366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3769540366
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4050322408
Short name T207
Test name
Test status
Simulation time 1099925357 ps
CPU time 67.37 seconds
Started Mar 31 12:45:27 PM PDT 24
Finished Mar 31 12:46:35 PM PDT 24
Peak memory 224516 kb
Host smart-f44020e0-8aaa-4b53-9609-81d732402f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050322408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4050322408
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4237649464
Short name T78
Test name
Test status
Simulation time 3300069466 ps
CPU time 15.42 seconds
Started Mar 31 12:32:48 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 210976 kb
Host smart-7b424b88-0185-48c6-94d2-64a4599e270e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237649464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4237649464
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1669701292
Short name T102
Test name
Test status
Simulation time 938529000 ps
CPU time 7.93 seconds
Started Mar 31 12:46:47 PM PDT 24
Finished Mar 31 12:46:55 PM PDT 24
Peak memory 211672 kb
Host smart-39de4f2b-545b-4d3e-b761-f413c9e6a691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669701292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1669701292
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2179905878
Short name T26
Test name
Test status
Simulation time 131661268250 ps
CPU time 5135.1 seconds
Started Mar 31 12:45:54 PM PDT 24
Finished Mar 31 02:11:30 PM PDT 24
Peak memory 252756 kb
Host smart-97f6b651-6001-417c-a716-40748f9b2982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179905878 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2179905878
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3957233626
Short name T900
Test name
Test status
Simulation time 3742201898 ps
CPU time 14.88 seconds
Started Mar 31 12:23:52 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 210784 kb
Host smart-220928f2-8666-4896-9365-1ad3cea764b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957233626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3957233626
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4221597354
Short name T64
Test name
Test status
Simulation time 5050344642 ps
CPU time 11.2 seconds
Started Mar 31 12:32:33 PM PDT 24
Finished Mar 31 12:32:44 PM PDT 24
Peak memory 210976 kb
Host smart-2e3a3d94-c175-4bcf-b243-e2a964aa24ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221597354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4221597354
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2693395867
Short name T869
Test name
Test status
Simulation time 85450462 ps
CPU time 4.55 seconds
Started Mar 31 12:32:29 PM PDT 24
Finished Mar 31 12:32:34 PM PDT 24
Peak memory 210880 kb
Host smart-ebf324ea-aa5c-4e06-96a0-250a81c470d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693395867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2693395867
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.659698016
Short name T789
Test name
Test status
Simulation time 1173742464 ps
CPU time 7.86 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:23:59 PM PDT 24
Peak memory 210668 kb
Host smart-465bd2c9-a611-4b8f-ab20-7e48be8d7ac0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659698016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.659698016
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3646035946
Short name T750
Test name
Test status
Simulation time 3374026948 ps
CPU time 12.1 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:23:54 PM PDT 24
Peak memory 210748 kb
Host smart-de2d9d8e-fc65-4598-8c28-7c8e2de320f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646035946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3646035946
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.546206253
Short name T870
Test name
Test status
Simulation time 680576364 ps
CPU time 7.21 seconds
Started Mar 31 12:32:24 PM PDT 24
Finished Mar 31 12:32:31 PM PDT 24
Peak memory 210828 kb
Host smart-2018c854-09c7-4c4b-adef-622ba2ccd067
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546206253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.546206253
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1260591163
Short name T924
Test name
Test status
Simulation time 812405122 ps
CPU time 5.38 seconds
Started Mar 31 12:32:33 PM PDT 24
Finished Mar 31 12:32:39 PM PDT 24
Peak memory 219124 kb
Host smart-50d66ba4-01b2-46f3-a612-2e59d40c89fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260591163 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1260591163
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1269930655
Short name T822
Test name
Test status
Simulation time 1609985068 ps
CPU time 14.41 seconds
Started Mar 31 12:23:32 PM PDT 24
Finished Mar 31 12:23:47 PM PDT 24
Peak memory 218904 kb
Host smart-bc5072fa-b3bd-4b2c-bad0-1e76fd4e6717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269930655 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1269930655
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2206679638
Short name T786
Test name
Test status
Simulation time 517900705 ps
CPU time 4.05 seconds
Started Mar 31 12:32:25 PM PDT 24
Finished Mar 31 12:32:29 PM PDT 24
Peak memory 210876 kb
Host smart-ae5b442d-09d5-4f2c-a451-501256009009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206679638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2206679638
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3709581122
Short name T718
Test name
Test status
Simulation time 7361451398 ps
CPU time 15.4 seconds
Started Mar 31 12:23:45 PM PDT 24
Finished Mar 31 12:24:01 PM PDT 24
Peak memory 210728 kb
Host smart-b2a914c8-18f8-4910-bb9c-55c11fa85fbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709581122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3709581122
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.330855927
Short name T713
Test name
Test status
Simulation time 831632786 ps
CPU time 4.06 seconds
Started Mar 31 12:23:40 PM PDT 24
Finished Mar 31 12:23:45 PM PDT 24
Peak memory 210536 kb
Host smart-ab879ca5-1c7d-4b1e-bf47-6a67b6c755bc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330855927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.330855927
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3923478046
Short name T760
Test name
Test status
Simulation time 88962743 ps
CPU time 3.99 seconds
Started Mar 31 12:32:29 PM PDT 24
Finished Mar 31 12:32:33 PM PDT 24
Peak memory 210776 kb
Host smart-428dbe2b-8429-48d9-bea6-1dc92b9bbeb9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923478046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3923478046
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3229344085
Short name T868
Test name
Test status
Simulation time 7465610698 ps
CPU time 13.69 seconds
Started Mar 31 12:32:28 PM PDT 24
Finished Mar 31 12:32:42 PM PDT 24
Peak memory 210904 kb
Host smart-1c4d3015-05d4-44c2-b9ef-3b6e7a7a1dbc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229344085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3229344085
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.324622078
Short name T702
Test name
Test status
Simulation time 693307529 ps
CPU time 4 seconds
Started Mar 31 12:23:31 PM PDT 24
Finished Mar 31 12:23:36 PM PDT 24
Peak memory 210536 kb
Host smart-10277d30-3e68-4637-84f3-4e09e7bc96b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324622078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
324622078
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2650044214
Short name T829
Test name
Test status
Simulation time 1400153946 ps
CPU time 26.56 seconds
Started Mar 31 12:23:40 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 210724 kb
Host smart-d5e6517f-215b-4b00-bdd4-a371f99ddced
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650044214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2650044214
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.658337881
Short name T725
Test name
Test status
Simulation time 51315022467 ps
CPU time 97.45 seconds
Started Mar 31 12:32:25 PM PDT 24
Finished Mar 31 12:34:02 PM PDT 24
Peak memory 210964 kb
Host smart-25640008-36df-495f-bbd3-1f676ccdd74c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658337881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.658337881
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1203205873
Short name T754
Test name
Test status
Simulation time 1397170979 ps
CPU time 14.29 seconds
Started Mar 31 12:23:52 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 210748 kb
Host smart-22b9de61-84d2-458a-afbd-e0227259dbac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203205873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1203205873
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.201151675
Short name T736
Test name
Test status
Simulation time 1629799627 ps
CPU time 13.14 seconds
Started Mar 31 12:32:25 PM PDT 24
Finished Mar 31 12:32:38 PM PDT 24
Peak memory 211160 kb
Host smart-dbdd7ce9-89dc-430a-a06f-b11b6858a68a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201151675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.201151675
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1854438634
Short name T774
Test name
Test status
Simulation time 2056001715 ps
CPU time 19.28 seconds
Started Mar 31 12:23:38 PM PDT 24
Finished Mar 31 12:23:58 PM PDT 24
Peak memory 218940 kb
Host smart-ad799cd8-1f39-4f09-b292-16b295bd04e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854438634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1854438634
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1933095240
Short name T687
Test name
Test status
Simulation time 5170829144 ps
CPU time 12.9 seconds
Started Mar 31 12:32:27 PM PDT 24
Finished Mar 31 12:32:40 PM PDT 24
Peak memory 219212 kb
Host smart-21237e2a-dc34-4399-aedf-b44733c07f80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933095240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1933095240
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1408869301
Short name T133
Test name
Test status
Simulation time 5504273524 ps
CPU time 72.59 seconds
Started Mar 31 12:32:27 PM PDT 24
Finished Mar 31 12:33:40 PM PDT 24
Peak memory 211184 kb
Host smart-c8b1b54a-7de6-41b4-8d27-392ea9e1f828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408869301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1408869301
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3008747330
Short name T844
Test name
Test status
Simulation time 1047355745 ps
CPU time 72.19 seconds
Started Mar 31 12:23:38 PM PDT 24
Finished Mar 31 12:24:50 PM PDT 24
Peak memory 212436 kb
Host smart-be83d9f7-2e5a-488b-b1af-df666a5edc01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008747330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3008747330
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3621632382
Short name T698
Test name
Test status
Simulation time 1479766295 ps
CPU time 9.81 seconds
Started Mar 31 12:23:50 PM PDT 24
Finished Mar 31 12:24:00 PM PDT 24
Peak memory 210752 kb
Host smart-0ecd38f1-05aa-4a4d-9602-217cc0f84082
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621632382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3621632382
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3948435021
Short name T804
Test name
Test status
Simulation time 4538632398 ps
CPU time 15.84 seconds
Started Mar 31 12:32:28 PM PDT 24
Finished Mar 31 12:32:44 PM PDT 24
Peak memory 210888 kb
Host smart-6493bbee-6086-49e0-8afe-587cabd5962a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948435021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3948435021
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1250896122
Short name T704
Test name
Test status
Simulation time 7374389367 ps
CPU time 15.61 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:18 PM PDT 24
Peak memory 210812 kb
Host smart-ea0d459e-8df3-4513-a861-ed20542bbbae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250896122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1250896122
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2666211532
Short name T857
Test name
Test status
Simulation time 175258872 ps
CPU time 4.37 seconds
Started Mar 31 12:32:24 PM PDT 24
Finished Mar 31 12:32:29 PM PDT 24
Peak memory 210872 kb
Host smart-9e3795e5-1933-4321-a671-5ea6fa009156
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666211532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2666211532
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3721905891
Short name T916
Test name
Test status
Simulation time 1633609649 ps
CPU time 16.12 seconds
Started Mar 31 12:32:25 PM PDT 24
Finished Mar 31 12:32:41 PM PDT 24
Peak memory 210832 kb
Host smart-5f71a45e-6faa-405a-aefc-b1f640311151
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721905891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3721905891
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4143965762
Short name T771
Test name
Test status
Simulation time 1903946052 ps
CPU time 18.73 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 210700 kb
Host smart-52fedda2-2662-4733-92f8-46e517b6a0c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143965762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4143965762
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3340300840
Short name T805
Test name
Test status
Simulation time 11516166469 ps
CPU time 17.52 seconds
Started Mar 31 12:23:32 PM PDT 24
Finished Mar 31 12:23:49 PM PDT 24
Peak memory 218936 kb
Host smart-2924bcc9-65d5-4d74-b468-bee60b23c747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340300840 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3340300840
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3810601499
Short name T901
Test name
Test status
Simulation time 748123141 ps
CPU time 6.83 seconds
Started Mar 31 12:32:32 PM PDT 24
Finished Mar 31 12:32:39 PM PDT 24
Peak memory 211384 kb
Host smart-1bd2345f-4a2c-4008-8f55-ca3f9e152e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810601499 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3810601499
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3235064837
Short name T746
Test name
Test status
Simulation time 949153439 ps
CPU time 10.1 seconds
Started Mar 31 12:32:24 PM PDT 24
Finished Mar 31 12:32:34 PM PDT 24
Peak memory 210812 kb
Host smart-2d819818-13a4-46fa-9ff6-134f5a4508ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235064837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3235064837
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3963971345
Short name T905
Test name
Test status
Simulation time 975685143 ps
CPU time 10.17 seconds
Started Mar 31 12:23:43 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 210712 kb
Host smart-ec91f47e-ee65-48e8-b8c9-704b53989ff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963971345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3963971345
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3073725432
Short name T899
Test name
Test status
Simulation time 5711628307 ps
CPU time 15.35 seconds
Started Mar 31 12:32:26 PM PDT 24
Finished Mar 31 12:32:41 PM PDT 24
Peak memory 210796 kb
Host smart-01d1ea51-b33c-4a5e-878d-b2942f71fa25
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073725432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3073725432
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4282125845
Short name T926
Test name
Test status
Simulation time 114814820 ps
CPU time 4.03 seconds
Started Mar 31 12:23:36 PM PDT 24
Finished Mar 31 12:23:40 PM PDT 24
Peak memory 210588 kb
Host smart-58319700-6fde-4a95-8bb3-74b98faf4dde
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282125845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4282125845
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2411614725
Short name T915
Test name
Test status
Simulation time 85391086 ps
CPU time 4.15 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:05 PM PDT 24
Peak memory 210644 kb
Host smart-58d60b9c-69c6-40cc-bee4-bff94a746544
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411614725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2411614725
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4241278874
Short name T800
Test name
Test status
Simulation time 7690550966 ps
CPU time 15.09 seconds
Started Mar 31 12:32:26 PM PDT 24
Finished Mar 31 12:32:41 PM PDT 24
Peak memory 210868 kb
Host smart-415fb3eb-d4d1-444d-872d-c7d9f67f9cc2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241278874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4241278874
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1490101512
Short name T117
Test name
Test status
Simulation time 3044758527 ps
CPU time 36.24 seconds
Started Mar 31 12:23:49 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 210800 kb
Host smart-b7cf37a0-3179-4a6e-9800-f0ab01f52002
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490101512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1490101512
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2494252884
Short name T757
Test name
Test status
Simulation time 2322018268 ps
CPU time 26.67 seconds
Started Mar 31 12:32:27 PM PDT 24
Finished Mar 31 12:32:54 PM PDT 24
Peak memory 210880 kb
Host smart-b11f74d1-6d4b-46a2-9cfb-8af8b4329264
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494252884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2494252884
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1157707005
Short name T831
Test name
Test status
Simulation time 2838800224 ps
CPU time 8.16 seconds
Started Mar 31 12:32:25 PM PDT 24
Finished Mar 31 12:32:33 PM PDT 24
Peak memory 210952 kb
Host smart-092a4d76-4276-4ee6-ba1c-8e8f908edb0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157707005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1157707005
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.175810966
Short name T756
Test name
Test status
Simulation time 936627780 ps
CPU time 6.72 seconds
Started Mar 31 12:23:44 PM PDT 24
Finished Mar 31 12:23:51 PM PDT 24
Peak memory 210660 kb
Host smart-a1a0e35a-8b15-496d-8040-561da47953a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175810966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.175810966
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.253233268
Short name T701
Test name
Test status
Simulation time 992102772 ps
CPU time 12.52 seconds
Started Mar 31 12:32:27 PM PDT 24
Finished Mar 31 12:32:40 PM PDT 24
Peak memory 219112 kb
Host smart-bc1fa23a-3839-4306-b3be-afb3d6cf38df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253233268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.253233268
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.566722801
Short name T898
Test name
Test status
Simulation time 457993991 ps
CPU time 9.39 seconds
Started Mar 31 12:23:59 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 218984 kb
Host smart-23100402-cc1d-41a2-b26d-9527917c3a90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566722801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.566722801
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.340084418
Short name T126
Test name
Test status
Simulation time 956577856 ps
CPU time 40.01 seconds
Started Mar 31 12:23:35 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 212496 kb
Host smart-e7ebc526-659b-4dac-98ff-1598d0b85695
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340084418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.340084418
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.344240911
Short name T134
Test name
Test status
Simulation time 580617888 ps
CPU time 37.84 seconds
Started Mar 31 12:32:24 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 211464 kb
Host smart-ef44e8e9-3307-4f22-bbed-720207d3a293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344240911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.344240911
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.212296814
Short name T856
Test name
Test status
Simulation time 1897183740 ps
CPU time 15.07 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 218956 kb
Host smart-4b6e851f-8da9-41bc-8d31-4f30a6c24c95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212296814 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.212296814
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3019562397
Short name T807
Test name
Test status
Simulation time 934778266 ps
CPU time 10.34 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:32:57 PM PDT 24
Peak memory 219148 kb
Host smart-03966502-2328-4210-9abe-ba86ea5e4691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019562397 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3019562397
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2821829477
Short name T814
Test name
Test status
Simulation time 1386643843 ps
CPU time 12.28 seconds
Started Mar 31 12:32:48 PM PDT 24
Finished Mar 31 12:33:01 PM PDT 24
Peak memory 210768 kb
Host smart-6269eafe-1b1e-40ae-af92-e8b051b50171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821829477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2821829477
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3696279077
Short name T894
Test name
Test status
Simulation time 175243320 ps
CPU time 4.17 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 210724 kb
Host smart-222fb844-b857-456a-9e81-c5af1ee8173e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696279077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3696279077
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2132967902
Short name T833
Test name
Test status
Simulation time 7391483663 ps
CPU time 57.84 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:45 PM PDT 24
Peak memory 210972 kb
Host smart-744fec1f-60a1-425a-9a34-d9d0fbc401fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132967902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2132967902
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2561027685
Short name T861
Test name
Test status
Simulation time 4067532478 ps
CPU time 23.07 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 210828 kb
Host smart-6d8af6c9-3da1-4f35-ad4b-38376af2ee7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561027685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2561027685
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2769364229
Short name T813
Test name
Test status
Simulation time 7297310827 ps
CPU time 15.65 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 210768 kb
Host smart-63191c56-2659-4f38-8692-40333fa29017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769364229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2769364229
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1769110391
Short name T910
Test name
Test status
Simulation time 4093468389 ps
CPU time 18.62 seconds
Started Mar 31 12:32:46 PM PDT 24
Finished Mar 31 12:33:05 PM PDT 24
Peak memory 219220 kb
Host smart-ebfa647c-5351-48d9-a767-fd2b0e1f0491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769110391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1769110391
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.527587353
Short name T720
Test name
Test status
Simulation time 2006410374 ps
CPU time 19.22 seconds
Started Mar 31 12:23:40 PM PDT 24
Finished Mar 31 12:23:59 PM PDT 24
Peak memory 218932 kb
Host smart-693f6196-6704-4de3-9629-072d38ee9ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527587353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.527587353
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3168498613
Short name T60
Test name
Test status
Simulation time 7456566138 ps
CPU time 44.69 seconds
Started Mar 31 12:23:46 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 210932 kb
Host smart-70fc43dc-201b-46b9-befb-b3ab9299ac2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168498613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3168498613
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.870304215
Short name T127
Test name
Test status
Simulation time 1837810981 ps
CPU time 77.38 seconds
Started Mar 31 12:32:48 PM PDT 24
Finished Mar 31 12:34:06 PM PDT 24
Peak memory 219088 kb
Host smart-d9903dbf-0720-4d68-a26f-16310db99a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870304215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.870304215
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1627360587
Short name T699
Test name
Test status
Simulation time 156553745 ps
CPU time 4.87 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:32:52 PM PDT 24
Peak memory 218944 kb
Host smart-a46ed55c-445c-412c-8a32-ad7da4701c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627360587 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1627360587
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4206137856
Short name T788
Test name
Test status
Simulation time 1493701859 ps
CPU time 9.72 seconds
Started Mar 31 12:23:50 PM PDT 24
Finished Mar 31 12:24:00 PM PDT 24
Peak memory 218940 kb
Host smart-c7f70156-118c-4899-89cc-cd466d2349ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206137856 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4206137856
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1125028197
Short name T790
Test name
Test status
Simulation time 378215216 ps
CPU time 4.11 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:32:51 PM PDT 24
Peak memory 210880 kb
Host smart-508bad28-56b8-436f-bf7f-5793c93c9141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125028197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1125028197
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2604587126
Short name T77
Test name
Test status
Simulation time 825656355 ps
CPU time 5.6 seconds
Started Mar 31 12:23:56 PM PDT 24
Finished Mar 31 12:24:02 PM PDT 24
Peak memory 210744 kb
Host smart-9ff27f35-0203-4cc2-8d1a-e2f16fe3cd07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604587126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2604587126
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2633785186
Short name T90
Test name
Test status
Simulation time 24669883596 ps
CPU time 57.03 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 210792 kb
Host smart-6e5c6d49-391f-4cfc-b86e-b496fe9a8371
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633785186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2633785186
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2651533560
Short name T828
Test name
Test status
Simulation time 1278818333 ps
CPU time 36.07 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:23 PM PDT 24
Peak memory 210756 kb
Host smart-6d52b4fa-6e26-447b-920d-3dad8780a8a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651533560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2651533560
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1949576590
Short name T762
Test name
Test status
Simulation time 1920765238 ps
CPU time 11.46 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:24:03 PM PDT 24
Peak memory 210740 kb
Host smart-f05a698e-e7fc-4c73-bab7-faa328e0c2a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949576590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1949576590
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3358271380
Short name T906
Test name
Test status
Simulation time 2018965889 ps
CPU time 14.34 seconds
Started Mar 31 12:32:48 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 210784 kb
Host smart-4ee38ef4-c54f-4465-8581-06920cdceef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358271380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3358271380
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.119409798
Short name T806
Test name
Test status
Simulation time 26975324905 ps
CPU time 13.92 seconds
Started Mar 31 12:24:00 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 219048 kb
Host smart-f70914b6-8ef9-402b-9fa8-0bc9575a8be9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119409798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.119409798
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3525864558
Short name T791
Test name
Test status
Simulation time 1680679519 ps
CPU time 16.37 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 219136 kb
Host smart-745d232b-f8f7-469a-a5e2-5b88dcbeef7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525864558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3525864558
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1458281822
Short name T817
Test name
Test status
Simulation time 742620831 ps
CPU time 66.94 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:54 PM PDT 24
Peak memory 211012 kb
Host smart-97998f9e-514a-4477-84ca-4e357787868a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458281822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1458281822
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2878454737
Short name T741
Test name
Test status
Simulation time 3266396059 ps
CPU time 43.09 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:25:41 PM PDT 24
Peak memory 218600 kb
Host smart-0148d74b-9e41-4eac-86ed-57541ed7fce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878454737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2878454737
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1994014238
Short name T912
Test name
Test status
Simulation time 6343305569 ps
CPU time 13.21 seconds
Started Mar 31 12:23:56 PM PDT 24
Finished Mar 31 12:24:10 PM PDT 24
Peak memory 219008 kb
Host smart-2c27c5ee-fa49-47c8-962d-559defda9fca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994014238 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1994014238
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3303121166
Short name T902
Test name
Test status
Simulation time 187484097 ps
CPU time 5.73 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:32:58 PM PDT 24
Peak memory 218964 kb
Host smart-7d0cc67d-798b-4742-a5da-09b85f409ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303121166 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3303121166
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3897395962
Short name T700
Test name
Test status
Simulation time 1775567146 ps
CPU time 13.85 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:23:55 PM PDT 24
Peak memory 210728 kb
Host smart-3adec8e2-9ba9-4b7f-a45f-4eff52907281
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897395962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3897395962
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.576184176
Short name T799
Test name
Test status
Simulation time 2864862800 ps
CPU time 8.28 seconds
Started Mar 31 12:32:54 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 210880 kb
Host smart-cdb2d3fc-4538-493d-8308-db17895339b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576184176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.576184176
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1244908737
Short name T766
Test name
Test status
Simulation time 72587972415 ps
CPU time 48.01 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:44 PM PDT 24
Peak memory 208204 kb
Host smart-d8b7d68a-fde5-4d4a-a824-9971402180b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244908737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1244908737
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.975787201
Short name T843
Test name
Test status
Simulation time 5912643926 ps
CPU time 60.75 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:48 PM PDT 24
Peak memory 210896 kb
Host smart-309160d9-f518-45f3-868f-c0f12284df71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975787201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.975787201
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2223716776
Short name T747
Test name
Test status
Simulation time 1179388952 ps
CPU time 10.59 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:33:04 PM PDT 24
Peak memory 210816 kb
Host smart-ea26816c-7c83-4800-9616-1685854d6f4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223716776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2223716776
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.846570493
Short name T76
Test name
Test status
Simulation time 178760791 ps
CPU time 4.31 seconds
Started Mar 31 12:23:57 PM PDT 24
Finished Mar 31 12:24:01 PM PDT 24
Peak memory 210688 kb
Host smart-82ddca0c-c8dc-4c7d-bb85-3a76fc6c3154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846570493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.846570493
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1668439979
Short name T904
Test name
Test status
Simulation time 3752474520 ps
CPU time 13.01 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 219176 kb
Host smart-39f21ca0-3f1f-4948-8854-527aa94c2240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668439979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1668439979
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2308687473
Short name T907
Test name
Test status
Simulation time 660670745 ps
CPU time 7.77 seconds
Started Mar 31 12:23:53 PM PDT 24
Finished Mar 31 12:24:01 PM PDT 24
Peak memory 219008 kb
Host smart-e3453224-c3ba-43e3-8bdd-ff6177cdefaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308687473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2308687473
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3469535178
Short name T768
Test name
Test status
Simulation time 586969674 ps
CPU time 35.95 seconds
Started Mar 31 12:23:44 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 211560 kb
Host smart-f4ad6bf5-e2f2-4647-bef6-56b6d6a1e8cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469535178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3469535178
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.483795730
Short name T834
Test name
Test status
Simulation time 962523765 ps
CPU time 39.44 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:32 PM PDT 24
Peak memory 210896 kb
Host smart-df767826-8d42-4abd-84e7-24382ad7c593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483795730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.483795730
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1519777882
Short name T812
Test name
Test status
Simulation time 383889329 ps
CPU time 4.61 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:32:59 PM PDT 24
Peak memory 219012 kb
Host smart-0ccb38d9-0d2b-44b1-9cc7-614111d25cae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519777882 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1519777882
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1699657783
Short name T782
Test name
Test status
Simulation time 1906379227 ps
CPU time 8.98 seconds
Started Mar 31 12:23:58 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 218948 kb
Host smart-39bf4152-5838-4cd5-b301-9058aa4562a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699657783 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1699657783
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1208844637
Short name T835
Test name
Test status
Simulation time 1122559574 ps
CPU time 10.61 seconds
Started Mar 31 12:24:59 PM PDT 24
Finished Mar 31 12:25:10 PM PDT 24
Peak memory 210756 kb
Host smart-bc6719b5-6e37-45df-93fa-c5cd1b87feb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208844637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1208844637
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1913988802
Short name T889
Test name
Test status
Simulation time 7863687556 ps
CPU time 15.68 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:11 PM PDT 24
Peak memory 210836 kb
Host smart-82ac4a36-1cc1-4605-998e-631d5602fb07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913988802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1913988802
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3780519803
Short name T719
Test name
Test status
Simulation time 7757587986 ps
CPU time 26.46 seconds
Started Mar 31 12:32:56 PM PDT 24
Finished Mar 31 12:33:22 PM PDT 24
Peak memory 211012 kb
Host smart-b7662db8-d912-4dd8-8760-5d28365f9546
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780519803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3780519803
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.788643399
Short name T731
Test name
Test status
Simulation time 27867189486 ps
CPU time 66.79 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:25:18 PM PDT 24
Peak memory 210808 kb
Host smart-9bba7aa3-37e2-4a8c-ab87-aca3dfb9e3d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788643399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.788643399
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3499419041
Short name T745
Test name
Test status
Simulation time 1042610423 ps
CPU time 11.58 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 210832 kb
Host smart-6b69ee50-60ab-4f63-a5bf-0dd837c209bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499419041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3499419041
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.40128283
Short name T763
Test name
Test status
Simulation time 89110185 ps
CPU time 4.26 seconds
Started Mar 31 12:23:48 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 210720 kb
Host smart-1ab9a772-3223-4864-92df-7fce91a1a58f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40128283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ct
rl_same_csr_outstanding.40128283
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2781884181
Short name T855
Test name
Test status
Simulation time 689656988 ps
CPU time 10 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 217864 kb
Host smart-4eba882c-9668-4e1a-92e4-4d57eff35218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781884181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2781884181
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2840686193
Short name T697
Test name
Test status
Simulation time 145128083 ps
CPU time 9.26 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 219148 kb
Host smart-31d82981-6b08-4277-849f-5021a498a0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840686193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2840686193
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3454676496
Short name T770
Test name
Test status
Simulation time 422758336 ps
CPU time 66.91 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:34:02 PM PDT 24
Peak memory 211876 kb
Host smart-82019711-692f-454f-aa6f-359998318dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454676496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3454676496
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.884928721
Short name T792
Test name
Test status
Simulation time 6877620177 ps
CPU time 47.97 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:53 PM PDT 24
Peak memory 212748 kb
Host smart-bba819b5-b678-4bdb-8aa1-8b82d404d7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884928721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.884928721
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1563563028
Short name T859
Test name
Test status
Simulation time 1243694242 ps
CPU time 12.04 seconds
Started Mar 31 12:23:43 PM PDT 24
Finished Mar 31 12:23:56 PM PDT 24
Peak memory 219004 kb
Host smart-e62c729c-f619-429d-b7b8-aaf6911d5304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563563028 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1563563028
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2574971318
Short name T867
Test name
Test status
Simulation time 1725883886 ps
CPU time 7.22 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:33:01 PM PDT 24
Peak memory 212024 kb
Host smart-f8d55797-c32b-4a2b-bc89-ec0ff3df0c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574971318 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2574971318
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4198377383
Short name T696
Test name
Test status
Simulation time 1674660794 ps
CPU time 13.18 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:25:10 PM PDT 24
Peak memory 210412 kb
Host smart-9cbb2b47-6b1e-4ed4-9b62-aede64d87c48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198377383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4198377383
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.643913465
Short name T815
Test name
Test status
Simulation time 4288972343 ps
CPU time 10.74 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 210988 kb
Host smart-af87c609-440a-4d14-8171-31b94600e408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643913465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.643913465
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2425079132
Short name T842
Test name
Test status
Simulation time 1439382255 ps
CPU time 18.52 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:14 PM PDT 24
Peak memory 210820 kb
Host smart-9637c925-5b0d-4daf-b55c-0d179ec63f77
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425079132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2425079132
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.348397609
Short name T883
Test name
Test status
Simulation time 6651708276 ps
CPU time 38.01 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:35 PM PDT 24
Peak memory 208424 kb
Host smart-a34320c2-d4ed-4f23-b59c-dde91beb7bc0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348397609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.348397609
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2063950468
Short name T922
Test name
Test status
Simulation time 857443327 ps
CPU time 9.45 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 210708 kb
Host smart-5323e875-f505-4f73-90d2-a54fc0ba60fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063950468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2063950468
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3539972690
Short name T722
Test name
Test status
Simulation time 6818588323 ps
CPU time 16 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:08 PM PDT 24
Peak memory 210888 kb
Host smart-b3c32a56-ecdb-46f6-9a64-681c82379cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539972690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3539972690
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1071186847
Short name T923
Test name
Test status
Simulation time 2073618326 ps
CPU time 19.35 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:16 PM PDT 24
Peak memory 217052 kb
Host smart-cc4b91d3-342c-4c78-ad27-698318d03b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071186847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1071186847
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1665363470
Short name T753
Test name
Test status
Simulation time 145200134 ps
CPU time 6.21 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 218452 kb
Host smart-cd86c8db-0e76-4433-a51d-40a3d3486682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665363470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1665363470
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1077485741
Short name T811
Test name
Test status
Simulation time 366685031 ps
CPU time 70.92 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:25:02 PM PDT 24
Peak memory 218908 kb
Host smart-f02cd3c2-ad33-4532-b069-e33f63bb8819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077485741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1077485741
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2959317781
Short name T885
Test name
Test status
Simulation time 13562107872 ps
CPU time 48.86 seconds
Started Mar 31 12:32:58 PM PDT 24
Finished Mar 31 12:33:47 PM PDT 24
Peak memory 211776 kb
Host smart-49653c22-12b3-4a95-ab1c-e928ca6083b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959317781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2959317781
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3258860537
Short name T743
Test name
Test status
Simulation time 1113250601 ps
CPU time 11.4 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 218896 kb
Host smart-6bfd1c2f-abcc-4f69-8cf8-d484b61467e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258860537 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3258860537
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3748025260
Short name T735
Test name
Test status
Simulation time 1894383731 ps
CPU time 4.8 seconds
Started Mar 31 12:32:54 PM PDT 24
Finished Mar 31 12:32:59 PM PDT 24
Peak memory 219100 kb
Host smart-c1005c08-b96e-4149-b130-55df1e7bf89f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748025260 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3748025260
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1874739597
Short name T715
Test name
Test status
Simulation time 1735630890 ps
CPU time 14.26 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:07 PM PDT 24
Peak memory 210868 kb
Host smart-08a3241e-b65e-488c-a37a-260bcab55cf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874739597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1874739597
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2751954787
Short name T744
Test name
Test status
Simulation time 773569932 ps
CPU time 9.02 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:10 PM PDT 24
Peak memory 210728 kb
Host smart-d82fdb9c-b64d-4137-ba2e-e4ce5dd275b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751954787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2751954787
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.801863682
Short name T839
Test name
Test status
Simulation time 24701944460 ps
CPU time 97.38 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:34:31 PM PDT 24
Peak memory 211028 kb
Host smart-34a8924f-300f-4d42-b0b9-1c73686c47eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801863682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.801863682
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1633027076
Short name T917
Test name
Test status
Simulation time 617971088 ps
CPU time 8.32 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:01 PM PDT 24
Peak memory 210844 kb
Host smart-57c66adf-652a-48c3-8326-701d35dd9979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633027076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1633027076
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2953776567
Short name T66
Test name
Test status
Simulation time 259835597 ps
CPU time 6.09 seconds
Started Mar 31 12:23:53 PM PDT 24
Finished Mar 31 12:23:59 PM PDT 24
Peak memory 210764 kb
Host smart-c57add55-c53a-429e-a240-f60c0f37fc67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953776567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2953776567
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2866212121
Short name T888
Test name
Test status
Simulation time 471261004 ps
CPU time 10.6 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 219012 kb
Host smart-c72fb272-9907-42fa-82fa-8c9d97870508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866212121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2866212121
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3903668065
Short name T772
Test name
Test status
Simulation time 931985638 ps
CPU time 9.43 seconds
Started Mar 31 12:23:52 PM PDT 24
Finished Mar 31 12:24:01 PM PDT 24
Peak memory 219008 kb
Host smart-63a689d5-7723-434a-aafb-256a5b80643b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903668065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3903668065
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2434976143
Short name T854
Test name
Test status
Simulation time 494432768 ps
CPU time 67.63 seconds
Started Mar 31 12:23:57 PM PDT 24
Finished Mar 31 12:25:05 PM PDT 24
Peak memory 211760 kb
Host smart-d7d2061a-39b0-4a6d-83c7-02c3728eb864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434976143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2434976143
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.40706269
Short name T847
Test name
Test status
Simulation time 15281664602 ps
CPU time 76.93 seconds
Started Mar 31 12:32:54 PM PDT 24
Finished Mar 31 12:34:11 PM PDT 24
Peak memory 211876 kb
Host smart-c4a06c20-5915-4083-bcf4-118455e6f5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40706269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_int
g_err.40706269
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2603231865
Short name T921
Test name
Test status
Simulation time 105250599 ps
CPU time 6.29 seconds
Started Mar 31 12:25:12 PM PDT 24
Finished Mar 31 12:25:19 PM PDT 24
Peak memory 218892 kb
Host smart-020f5aad-3ca3-44b1-8eec-82ee8c9798cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603231865 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2603231865
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3282609848
Short name T903
Test name
Test status
Simulation time 2761080548 ps
CPU time 8.15 seconds
Started Mar 31 12:32:54 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 219104 kb
Host smart-4ac0766d-348d-4f86-97f2-3be7a6b11a6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282609848 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3282609848
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1128895575
Short name T882
Test name
Test status
Simulation time 214784626 ps
CPU time 5.61 seconds
Started Mar 31 12:26:04 PM PDT 24
Finished Mar 31 12:26:10 PM PDT 24
Peak memory 210728 kb
Host smart-0be13cdf-a524-4a27-bd19-2e66d5d3016e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128895575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1128895575
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2930355276
Short name T115
Test name
Test status
Simulation time 174713744 ps
CPU time 4.29 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:00 PM PDT 24
Peak memory 210800 kb
Host smart-80c601bf-adcf-490f-a451-e481fcd0d4bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930355276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2930355276
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.190112230
Short name T89
Test name
Test status
Simulation time 1150216300 ps
CPU time 26.87 seconds
Started Mar 31 12:23:57 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 210728 kb
Host smart-bcb58ca7-d660-4b69-bdc9-aad3a7de4d8c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190112230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.190112230
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3952014469
Short name T872
Test name
Test status
Simulation time 19793005138 ps
CPU time 47.8 seconds
Started Mar 31 12:32:56 PM PDT 24
Finished Mar 31 12:33:43 PM PDT 24
Peak memory 210980 kb
Host smart-12190f0b-d57a-43f9-b5ee-4be7e884145a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952014469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3952014469
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.232452469
Short name T112
Test name
Test status
Simulation time 1666341088 ps
CPU time 13.43 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 210868 kb
Host smart-295a41bd-7782-48cf-a46f-c579ac6ff4fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232452469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.232452469
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2584297833
Short name T80
Test name
Test status
Simulation time 825633578 ps
CPU time 5.58 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:25:03 PM PDT 24
Peak memory 210392 kb
Host smart-1f2f4be0-e252-4505-a8d4-bc80637e3be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584297833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2584297833
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3343741624
Short name T930
Test name
Test status
Simulation time 1064859293 ps
CPU time 15.36 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:11 PM PDT 24
Peak memory 219080 kb
Host smart-6bb0174c-e654-4012-acab-32de0c547ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343741624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3343741624
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.957380761
Short name T873
Test name
Test status
Simulation time 17619928739 ps
CPU time 13.78 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 219036 kb
Host smart-6fcded29-d634-4118-9041-97e0ae88dbb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957380761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.957380761
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2845715974
Short name T818
Test name
Test status
Simulation time 297247717 ps
CPU time 36.41 seconds
Started Mar 31 12:23:53 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 210748 kb
Host smart-458edd24-b8a4-4047-8ba6-86b26135ab2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845715974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2845715974
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3258294163
Short name T124
Test name
Test status
Simulation time 4327680925 ps
CPU time 72.41 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:34:06 PM PDT 24
Peak memory 212200 kb
Host smart-598a2667-2579-4069-bb52-c4456b615bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258294163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3258294163
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1069163418
Short name T692
Test name
Test status
Simulation time 224079059 ps
CPU time 4.71 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 218900 kb
Host smart-93630567-e16a-46b9-ac2c-4a75e6f64fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069163418 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1069163418
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2229983315
Short name T733
Test name
Test status
Simulation time 1430670258 ps
CPU time 12.43 seconds
Started Mar 31 12:32:56 PM PDT 24
Finished Mar 31 12:33:08 PM PDT 24
Peak memory 219056 kb
Host smart-8474c521-a0ef-4d1e-a6b2-20eeda3c81a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229983315 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2229983315
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2369522185
Short name T693
Test name
Test status
Simulation time 348209634 ps
CPU time 4.05 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 210724 kb
Host smart-dde7d6ae-eda9-4611-81a2-d6c17b81dd69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369522185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2369522185
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.945418707
Short name T886
Test name
Test status
Simulation time 1703456827 ps
CPU time 13.24 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 210192 kb
Host smart-26b0191a-5a96-42cf-8da2-d7b125845d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945418707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.945418707
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2880456449
Short name T819
Test name
Test status
Simulation time 386271040 ps
CPU time 18.55 seconds
Started Mar 31 12:32:56 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 210812 kb
Host smart-465f4535-6baa-4294-9cfb-9fc11f7a4ce1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880456449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2880456449
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4153650648
Short name T721
Test name
Test status
Simulation time 6124819518 ps
CPU time 44.43 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:41 PM PDT 24
Peak memory 208412 kb
Host smart-2aacca95-944c-4fc7-85ca-8a42f328ff8e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153650648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4153650648
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1959091921
Short name T759
Test name
Test status
Simulation time 382687470 ps
CPU time 6.01 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 210700 kb
Host smart-392edbef-6e67-410b-8212-cda83639ea4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959091921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1959091921
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2727408434
Short name T758
Test name
Test status
Simulation time 333311110 ps
CPU time 4.4 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:32:58 PM PDT 24
Peak memory 211008 kb
Host smart-9df39cbd-c5ee-442d-aa4b-82b152d89168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727408434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2727408434
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2778090898
Short name T716
Test name
Test status
Simulation time 4899436104 ps
CPU time 14.61 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:33:08 PM PDT 24
Peak memory 219244 kb
Host smart-41829866-f1ba-42c9-93aa-1b87967fdc75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778090898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2778090898
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3103723785
Short name T711
Test name
Test status
Simulation time 1322014404 ps
CPU time 15.09 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 216652 kb
Host smart-a1c8ae93-59bd-4721-a177-af76a06f111f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103723785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3103723785
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.264111757
Short name T130
Test name
Test status
Simulation time 1723843395 ps
CPU time 39.56 seconds
Started Mar 31 12:32:55 PM PDT 24
Finished Mar 31 12:33:34 PM PDT 24
Peak memory 210768 kb
Host smart-5657a149-9abe-43e9-ab7f-1b23970b0ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264111757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.264111757
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2527287112
Short name T787
Test name
Test status
Simulation time 2196942286 ps
CPU time 16.22 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 219016 kb
Host smart-b4e2c3aa-32c8-414f-b286-f2f00a098bc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527287112 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2527287112
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4256174541
Short name T714
Test name
Test status
Simulation time 742884544 ps
CPU time 4.28 seconds
Started Mar 31 12:32:52 PM PDT 24
Finished Mar 31 12:32:57 PM PDT 24
Peak memory 213040 kb
Host smart-242b1096-9981-47c9-9631-0d47395872e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256174541 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4256174541
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1886932083
Short name T710
Test name
Test status
Simulation time 168559648 ps
CPU time 4.22 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 210744 kb
Host smart-b4deae09-f4b6-4212-8d67-f26666c69a6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886932083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1886932083
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3018470508
Short name T75
Test name
Test status
Simulation time 7760921836 ps
CPU time 12.42 seconds
Started Mar 31 12:32:54 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 210880 kb
Host smart-e167a377-8baa-4765-bf68-e6e97e17b637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018470508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3018470508
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3044189897
Short name T707
Test name
Test status
Simulation time 1446850338 ps
CPU time 18.64 seconds
Started Mar 31 12:24:00 PM PDT 24
Finished Mar 31 12:24:19 PM PDT 24
Peak memory 210704 kb
Host smart-aa8d1b21-acba-4c1b-9466-c7300eaea70f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044189897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3044189897
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3471274852
Short name T891
Test name
Test status
Simulation time 1041039364 ps
CPU time 25.28 seconds
Started Mar 31 12:32:56 PM PDT 24
Finished Mar 31 12:33:21 PM PDT 24
Peak memory 210852 kb
Host smart-f0695fac-0824-4a9a-b7e6-d24a96ced77d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471274852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3471274852
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1648109794
Short name T740
Test name
Test status
Simulation time 1180402965 ps
CPU time 4.13 seconds
Started Mar 31 12:32:58 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 210872 kb
Host smart-5d6d4b03-c075-47e9-83cd-a43630c1af13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648109794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1648109794
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2528113061
Short name T732
Test name
Test status
Simulation time 1183464637 ps
CPU time 12.76 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 210796 kb
Host smart-0d3d1ae8-5019-4ad6-bb10-891b9779e1ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528113061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2528113061
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1503944907
Short name T761
Test name
Test status
Simulation time 3429767078 ps
CPU time 16.66 seconds
Started Mar 31 12:32:53 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 215180 kb
Host smart-f2317e9b-252b-4684-9e1a-9bfb2e874393
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503944907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1503944907
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2867498334
Short name T730
Test name
Test status
Simulation time 1654266440 ps
CPU time 15.82 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 218928 kb
Host smart-2611a64c-6fd8-4c86-a570-6393063faaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867498334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2867498334
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2682495411
Short name T838
Test name
Test status
Simulation time 3420330994 ps
CPU time 44.47 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:49 PM PDT 24
Peak memory 212688 kb
Host smart-2a3b624f-c1bf-40b7-8871-ab264bac2229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682495411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2682495411
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.916856017
Short name T781
Test name
Test status
Simulation time 4310223396 ps
CPU time 72.25 seconds
Started Mar 31 12:32:56 PM PDT 24
Finished Mar 31 12:34:08 PM PDT 24
Peak memory 219072 kb
Host smart-7e364ca0-406e-4b61-bdaf-6dc7e899566a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916856017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.916856017
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2027860588
Short name T897
Test name
Test status
Simulation time 1421813666 ps
CPU time 13.02 seconds
Started Mar 31 12:33:01 PM PDT 24
Finished Mar 31 12:33:14 PM PDT 24
Peak memory 212776 kb
Host smart-639443c5-4743-473b-8aa1-c217fa80b18e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027860588 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2027860588
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3695329888
Short name T830
Test name
Test status
Simulation time 2140233818 ps
CPU time 10.59 seconds
Started Mar 31 12:23:54 PM PDT 24
Finished Mar 31 12:24:04 PM PDT 24
Peak memory 212500 kb
Host smart-339a54cb-d065-4f8a-9cd5-cb6bcdd1b7db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695329888 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3695329888
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1906531360
Short name T852
Test name
Test status
Simulation time 1511544069 ps
CPU time 12.67 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 210728 kb
Host smart-653bfc97-aa6b-4271-b5cd-d58d4baa387d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906531360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1906531360
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.883438896
Short name T783
Test name
Test status
Simulation time 167883546 ps
CPU time 4.15 seconds
Started Mar 31 12:32:59 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 210696 kb
Host smart-8d0efe9a-86ad-4685-b908-3e9796df20b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883438896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.883438896
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2153635743
Short name T97
Test name
Test status
Simulation time 8391460719 ps
CPU time 76.02 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:25:22 PM PDT 24
Peak memory 210804 kb
Host smart-076aba65-e744-4d58-a949-d2d31c1283cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153635743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2153635743
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3977903933
Short name T92
Test name
Test status
Simulation time 12816210606 ps
CPU time 54.49 seconds
Started Mar 31 12:32:54 PM PDT 24
Finished Mar 31 12:33:48 PM PDT 24
Peak memory 210972 kb
Host smart-28a78c84-41f4-4c10-8fab-bfd31785a486
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977903933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3977903933
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1925927352
Short name T825
Test name
Test status
Simulation time 3432231309 ps
CPU time 14.56 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 210892 kb
Host smart-74f6f6ab-7f59-4a4c-80d0-554e629220ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925927352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1925927352
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3957615912
Short name T81
Test name
Test status
Simulation time 1807201307 ps
CPU time 15.15 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 210744 kb
Host smart-34ab62ce-0044-4067-8b6b-915ed113f939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957615912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3957615912
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2663695493
Short name T841
Test name
Test status
Simulation time 1883986702 ps
CPU time 11.71 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:18 PM PDT 24
Peak memory 218972 kb
Host smart-ef3b27a8-44ed-422a-9ba3-c720e15734cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663695493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2663695493
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3303014006
Short name T893
Test name
Test status
Simulation time 1131033478 ps
CPU time 13.17 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:33:13 PM PDT 24
Peak memory 219016 kb
Host smart-fee220d8-fcfc-44c2-99b4-ee6d44d55794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303014006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3303014006
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1122641205
Short name T123
Test name
Test status
Simulation time 2129384018 ps
CPU time 75.44 seconds
Started Mar 31 12:33:00 PM PDT 24
Finished Mar 31 12:34:15 PM PDT 24
Peak memory 211712 kb
Host smart-9766f5a0-6470-4df8-a322-f9be2e9c42cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122641205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1122641205
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2003480861
Short name T874
Test name
Test status
Simulation time 5132087113 ps
CPU time 75.03 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:25:25 PM PDT 24
Peak memory 218984 kb
Host smart-035c9f6b-701b-4585-abb4-cfbedad5a088
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003480861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2003480861
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1399227545
Short name T816
Test name
Test status
Simulation time 1153175970 ps
CPU time 11.3 seconds
Started Mar 31 12:23:53 PM PDT 24
Finished Mar 31 12:24:04 PM PDT 24
Peak memory 210712 kb
Host smart-4268444a-017a-40b1-bb97-b22e44fd6d33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399227545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1399227545
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.995804969
Short name T802
Test name
Test status
Simulation time 6037035446 ps
CPU time 13.72 seconds
Started Mar 31 12:32:36 PM PDT 24
Finished Mar 31 12:32:50 PM PDT 24
Peak memory 210892 kb
Host smart-f3327a0d-bd23-4ed6-89e8-b3bf7ea40b14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995804969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.995804969
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3128240030
Short name T909
Test name
Test status
Simulation time 347362705 ps
CPU time 4.61 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 210696 kb
Host smart-6ddb2e75-3946-45c0-b194-77953ce9f71a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128240030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3128240030
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3755071490
Short name T797
Test name
Test status
Simulation time 1719673056 ps
CPU time 13.73 seconds
Started Mar 31 12:32:36 PM PDT 24
Finished Mar 31 12:32:49 PM PDT 24
Peak memory 210824 kb
Host smart-b1233b7b-f175-4b5d-8bc7-7bc8908403b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755071490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3755071490
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1753175025
Short name T116
Test name
Test status
Simulation time 169241768 ps
CPU time 6.93 seconds
Started Mar 31 12:32:36 PM PDT 24
Finished Mar 31 12:32:43 PM PDT 24
Peak memory 210828 kb
Host smart-676bcaf0-cabb-4d42-b900-95b4182b6f24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753175025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1753175025
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1969748369
Short name T98
Test name
Test status
Simulation time 4283303729 ps
CPU time 19.51 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:24:01 PM PDT 24
Peak memory 210748 kb
Host smart-4ed506b5-5d14-4fbb-86d4-dc47e6bc54c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969748369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1969748369
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2808958313
Short name T729
Test name
Test status
Simulation time 645672949 ps
CPU time 8.27 seconds
Started Mar 31 12:32:32 PM PDT 24
Finished Mar 31 12:32:40 PM PDT 24
Peak memory 219124 kb
Host smart-3120a275-5f88-48be-9b38-68d389408bff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808958313 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2808958313
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3934349549
Short name T896
Test name
Test status
Simulation time 19695650076 ps
CPU time 15.87 seconds
Started Mar 31 12:23:34 PM PDT 24
Finished Mar 31 12:23:50 PM PDT 24
Peak memory 219080 kb
Host smart-91619a09-5a5a-414f-9482-c8a9bc9753b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934349549 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3934349549
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.298873914
Short name T803
Test name
Test status
Simulation time 175590925 ps
CPU time 4.12 seconds
Started Mar 31 12:32:32 PM PDT 24
Finished Mar 31 12:32:36 PM PDT 24
Peak memory 210900 kb
Host smart-0a3673c9-144e-446e-94f8-117b18d91062
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298873914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.298873914
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.83351953
Short name T94
Test name
Test status
Simulation time 903041658 ps
CPU time 9.67 seconds
Started Mar 31 12:23:48 PM PDT 24
Finished Mar 31 12:23:58 PM PDT 24
Peak memory 210708 kb
Host smart-315732f8-13fe-4408-94a4-fad91d81b574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83351953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.83351953
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.378285797
Short name T726
Test name
Test status
Simulation time 167796815 ps
CPU time 3.88 seconds
Started Mar 31 12:32:35 PM PDT 24
Finished Mar 31 12:32:39 PM PDT 24
Peak memory 210660 kb
Host smart-a450e2f5-cc73-47be-b46d-64ab4330ff12
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378285797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.378285797
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.747493510
Short name T751
Test name
Test status
Simulation time 8042245249 ps
CPU time 15.61 seconds
Started Mar 31 12:23:46 PM PDT 24
Finished Mar 31 12:24:01 PM PDT 24
Peak memory 210644 kb
Host smart-2d7d1987-30ce-4cc0-aec1-b25faf35dd83
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747493510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.747493510
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1389741383
Short name T920
Test name
Test status
Simulation time 829547878 ps
CPU time 3.98 seconds
Started Mar 31 12:32:34 PM PDT 24
Finished Mar 31 12:32:38 PM PDT 24
Peak memory 210756 kb
Host smart-3c241bb2-324e-4d2b-9bc4-888f87a17a17
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389741383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1389741383
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3163535138
Short name T864
Test name
Test status
Simulation time 803755771 ps
CPU time 8.74 seconds
Started Mar 31 12:23:43 PM PDT 24
Finished Mar 31 12:23:52 PM PDT 24
Peak memory 210660 kb
Host smart-601af9e1-6033-4fa3-96e5-66524ee37e05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163535138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3163535138
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4194097033
Short name T82
Test name
Test status
Simulation time 32301528148 ps
CPU time 65.51 seconds
Started Mar 31 12:23:51 PM PDT 24
Finished Mar 31 12:24:56 PM PDT 24
Peak memory 210856 kb
Host smart-a2dc19ee-8959-4a3c-9bb9-148ef8c2cb40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194097033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4194097033
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.906920797
Short name T101
Test name
Test status
Simulation time 6102013596 ps
CPU time 51.12 seconds
Started Mar 31 12:32:26 PM PDT 24
Finished Mar 31 12:33:17 PM PDT 24
Peak memory 210916 kb
Host smart-ed88eea7-7127-4069-a432-b14a99754306
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906920797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.906920797
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1201279491
Short name T79
Test name
Test status
Simulation time 3063615116 ps
CPU time 10.11 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:23:57 PM PDT 24
Peak memory 210820 kb
Host smart-30509ef7-2aa9-4083-8b44-4c2ef92ee2c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201279491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1201279491
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.939847788
Short name T832
Test name
Test status
Simulation time 8714029214 ps
CPU time 8.75 seconds
Started Mar 31 12:32:34 PM PDT 24
Finished Mar 31 12:32:43 PM PDT 24
Peak memory 210980 kb
Host smart-8c14a4d2-b9ec-4fc9-a60c-57c267f68a17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939847788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.939847788
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3916417228
Short name T890
Test name
Test status
Simulation time 1800472753 ps
CPU time 16.8 seconds
Started Mar 31 12:23:45 PM PDT 24
Finished Mar 31 12:24:02 PM PDT 24
Peak memory 218916 kb
Host smart-52cc8dbb-b1f8-4e5f-a300-47fcd38a5493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916417228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3916417228
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.914885768
Short name T798
Test name
Test status
Simulation time 821673982 ps
CPU time 11.29 seconds
Started Mar 31 12:32:27 PM PDT 24
Finished Mar 31 12:32:38 PM PDT 24
Peak memory 219080 kb
Host smart-3fb4597f-6531-4c66-aadc-1ce26df96122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914885768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.914885768
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3807695660
Short name T851
Test name
Test status
Simulation time 1071698800 ps
CPU time 41.22 seconds
Started Mar 31 12:23:48 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 211320 kb
Host smart-0edd15f0-e57b-4a04-98af-b448fa02c42e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807695660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3807695660
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.693052758
Short name T128
Test name
Test status
Simulation time 1139900764 ps
CPU time 39.53 seconds
Started Mar 31 12:32:25 PM PDT 24
Finished Mar 31 12:33:05 PM PDT 24
Peak memory 210724 kb
Host smart-e239a5fe-a747-4518-b86f-1f915aff2495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693052758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.693052758
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1055886080
Short name T918
Test name
Test status
Simulation time 1946116790 ps
CPU time 15.04 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:23:57 PM PDT 24
Peak memory 210760 kb
Host smart-08d2e765-31c9-4e5d-b587-4f80af60eaa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055886080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1055886080
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3309461319
Short name T114
Test name
Test status
Simulation time 1293168841 ps
CPU time 12.2 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:53 PM PDT 24
Peak memory 210872 kb
Host smart-13a0e475-a1da-432e-83da-48208b952ae1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309461319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3309461319
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4066461202
Short name T887
Test name
Test status
Simulation time 2557356679 ps
CPU time 10.01 seconds
Started Mar 31 12:32:34 PM PDT 24
Finished Mar 31 12:32:44 PM PDT 24
Peak memory 210944 kb
Host smart-8f460127-b30a-44cf-8c9b-bfe7a120dfe9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066461202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4066461202
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.427446917
Short name T884
Test name
Test status
Simulation time 1040450440 ps
CPU time 6.13 seconds
Started Mar 31 12:23:45 PM PDT 24
Finished Mar 31 12:23:51 PM PDT 24
Peak memory 210744 kb
Host smart-5d4e9202-6e9a-4d5b-9bd1-0809f1b930a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427446917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.427446917
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3287138407
Short name T913
Test name
Test status
Simulation time 655254618 ps
CPU time 9.77 seconds
Started Mar 31 12:32:34 PM PDT 24
Finished Mar 31 12:32:44 PM PDT 24
Peak memory 211044 kb
Host smart-30404fab-eeaf-4a09-afed-77683cd5160a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287138407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3287138407
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.646545236
Short name T765
Test name
Test status
Simulation time 13228154673 ps
CPU time 19.65 seconds
Started Mar 31 12:23:47 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 210824 kb
Host smart-280a867e-bd6a-4dd7-b36f-ded6b2e61ab6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646545236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.646545236
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1154687581
Short name T779
Test name
Test status
Simulation time 1132218883 ps
CPU time 6.87 seconds
Started Mar 31 12:32:41 PM PDT 24
Finished Mar 31 12:32:48 PM PDT 24
Peak memory 219136 kb
Host smart-77cb4d62-390b-407e-9e17-26d12c6a2c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154687581 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1154687581
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1719862376
Short name T826
Test name
Test status
Simulation time 661820780 ps
CPU time 5.03 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 218952 kb
Host smart-6d7b8168-e5c0-4b25-b9fa-053112803ac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719862376 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1719862376
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3115916348
Short name T767
Test name
Test status
Simulation time 2247728177 ps
CPU time 11.56 seconds
Started Mar 31 12:23:58 PM PDT 24
Finished Mar 31 12:24:10 PM PDT 24
Peak memory 210812 kb
Host smart-ed71f90b-0dcf-4320-945f-d5f6e6be4d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115916348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3115916348
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.991053934
Short name T836
Test name
Test status
Simulation time 1210912048 ps
CPU time 6.08 seconds
Started Mar 31 12:32:34 PM PDT 24
Finished Mar 31 12:32:41 PM PDT 24
Peak memory 210792 kb
Host smart-90bd997f-3ae3-47df-aad7-f218e175b97d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991053934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.991053934
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.127964143
Short name T690
Test name
Test status
Simulation time 2732275958 ps
CPU time 10.65 seconds
Started Mar 31 12:32:32 PM PDT 24
Finished Mar 31 12:32:43 PM PDT 24
Peak memory 210680 kb
Host smart-bf68d20c-78fb-4a8e-994e-179d47182dc9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127964143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.127964143
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2398386258
Short name T689
Test name
Test status
Simulation time 261035742 ps
CPU time 3.99 seconds
Started Mar 31 12:23:46 PM PDT 24
Finished Mar 31 12:23:50 PM PDT 24
Peak memory 210624 kb
Host smart-c7df0291-d62e-474c-b815-44df96603646
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398386258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2398386258
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2624808207
Short name T748
Test name
Test status
Simulation time 1202245975 ps
CPU time 11.23 seconds
Started Mar 31 12:32:34 PM PDT 24
Finished Mar 31 12:32:46 PM PDT 24
Peak memory 210752 kb
Host smart-30ddac38-50b3-4675-a654-6da3cbed72c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624808207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2624808207
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4020783399
Short name T776
Test name
Test status
Simulation time 89835399 ps
CPU time 4.05 seconds
Started Mar 31 12:24:00 PM PDT 24
Finished Mar 31 12:24:04 PM PDT 24
Peak memory 210608 kb
Host smart-82f83e93-badb-4e57-af4f-9c8c668ae040
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020783399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4020783399
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1172822925
Short name T919
Test name
Test status
Simulation time 176317371667 ps
CPU time 103.96 seconds
Started Mar 31 12:23:55 PM PDT 24
Finished Mar 31 12:25:39 PM PDT 24
Peak memory 210856 kb
Host smart-50d75fd3-72e5-47ae-92ca-26785907c56c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172822925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1172822925
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4218188190
Short name T848
Test name
Test status
Simulation time 7860206577 ps
CPU time 63.92 seconds
Started Mar 31 12:32:34 PM PDT 24
Finished Mar 31 12:33:38 PM PDT 24
Peak memory 210860 kb
Host smart-1209edfb-674f-449d-bf1c-2fbaab9e0ba5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218188190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4218188190
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2314070361
Short name T785
Test name
Test status
Simulation time 12179891726 ps
CPU time 15.29 seconds
Started Mar 31 12:23:48 PM PDT 24
Finished Mar 31 12:24:03 PM PDT 24
Peak memory 210820 kb
Host smart-789878ac-2257-4d96-a9dd-7661bec1c68b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314070361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2314070361
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2556006541
Short name T858
Test name
Test status
Simulation time 1434403193 ps
CPU time 6.2 seconds
Started Mar 31 12:32:39 PM PDT 24
Finished Mar 31 12:32:45 PM PDT 24
Peak memory 210716 kb
Host smart-086243f0-bf6a-471a-b4aa-4c90eee9973a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556006541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2556006541
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4247034452
Short name T755
Test name
Test status
Simulation time 15151357476 ps
CPU time 18.72 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 219036 kb
Host smart-89eecf8f-10b6-401d-b1d5-fdee0dbaeeb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247034452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4247034452
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4259947698
Short name T705
Test name
Test status
Simulation time 1284575677 ps
CPU time 14.62 seconds
Started Mar 31 12:32:32 PM PDT 24
Finished Mar 31 12:32:47 PM PDT 24
Peak memory 219100 kb
Host smart-0ba2e608-53d5-46e4-b912-d1787aad702f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259947698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4259947698
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3169947213
Short name T62
Test name
Test status
Simulation time 10654446229 ps
CPU time 42.53 seconds
Started Mar 31 12:23:50 PM PDT 24
Finished Mar 31 12:24:33 PM PDT 24
Peak memory 211948 kb
Host smart-fcab22fb-b491-4e82-8c46-0a5188be1ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169947213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3169947213
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3685948352
Short name T777
Test name
Test status
Simulation time 7031990774 ps
CPU time 38.37 seconds
Started Mar 31 12:32:31 PM PDT 24
Finished Mar 31 12:33:09 PM PDT 24
Peak memory 210984 kb
Host smart-a29c7d00-234d-46f0-b6d4-245134447ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685948352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3685948352
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3223278104
Short name T717
Test name
Test status
Simulation time 4123455803 ps
CPU time 15.87 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 210888 kb
Host smart-ce023764-92aa-4669-a83e-e9f363182cc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223278104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3223278104
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3518610761
Short name T793
Test name
Test status
Simulation time 332673942 ps
CPU time 4.03 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:23:46 PM PDT 24
Peak memory 210740 kb
Host smart-d369b420-2000-42aa-b8bf-c885c453e99a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518610761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3518610761
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.425417541
Short name T784
Test name
Test status
Simulation time 1005092785 ps
CPU time 10.12 seconds
Started Mar 31 12:24:04 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 210736 kb
Host smart-eb3707fa-464a-4984-9f76-e60d31ffc168
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425417541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.425417541
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.555318519
Short name T846
Test name
Test status
Simulation time 6499873020 ps
CPU time 13.9 seconds
Started Mar 31 12:32:39 PM PDT 24
Finished Mar 31 12:32:53 PM PDT 24
Peak memory 210872 kb
Host smart-6862620b-e410-4cb6-8201-da0ccf9b1fcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555318519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.555318519
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1812103551
Short name T796
Test name
Test status
Simulation time 352933051 ps
CPU time 7.24 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:47 PM PDT 24
Peak memory 210832 kb
Host smart-33b00e51-83e5-4246-b856-e1101f867046
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812103551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1812103551
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2845457512
Short name T875
Test name
Test status
Simulation time 89289038 ps
CPU time 5.52 seconds
Started Mar 31 12:24:00 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 210708 kb
Host smart-232eec11-3c4e-4fc2-9e6c-ff8340a2856d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845457512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2845457512
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1274723142
Short name T877
Test name
Test status
Simulation time 1409356774 ps
CPU time 12.68 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 218984 kb
Host smart-0486aea6-6cfe-4d1c-9242-5221037a72bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274723142 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1274723142
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4102670214
Short name T827
Test name
Test status
Simulation time 1551153672 ps
CPU time 4.75 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:45 PM PDT 24
Peak memory 214048 kb
Host smart-d81f22d6-355d-421a-bb28-aa2ec39ead28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102670214 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4102670214
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1414658408
Short name T878
Test name
Test status
Simulation time 1345153666 ps
CPU time 9.59 seconds
Started Mar 31 12:23:47 PM PDT 24
Finished Mar 31 12:23:57 PM PDT 24
Peak memory 210676 kb
Host smart-40f6c1ea-04f6-454a-aac3-698d78e0d1b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414658408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1414658408
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3201562289
Short name T724
Test name
Test status
Simulation time 1638738814 ps
CPU time 9.06 seconds
Started Mar 31 12:32:39 PM PDT 24
Finished Mar 31 12:32:48 PM PDT 24
Peak memory 210816 kb
Host smart-97951190-a752-49d4-8ed0-d6735a80ce94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201562289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3201562289
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1056237793
Short name T895
Test name
Test status
Simulation time 168004164 ps
CPU time 4.08 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:45 PM PDT 24
Peak memory 210660 kb
Host smart-3c3bebc4-12ce-4002-969a-a11c0d2abd41
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056237793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1056237793
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.697785321
Short name T708
Test name
Test status
Simulation time 1030834384 ps
CPU time 9.99 seconds
Started Mar 31 12:23:44 PM PDT 24
Finished Mar 31 12:23:54 PM PDT 24
Peak memory 210600 kb
Host smart-c401fc92-c42d-4b01-a269-77ac256afc1f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697785321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.697785321
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1735159925
Short name T686
Test name
Test status
Simulation time 7045793730 ps
CPU time 14.48 seconds
Started Mar 31 12:23:43 PM PDT 24
Finished Mar 31 12:23:58 PM PDT 24
Peak memory 210700 kb
Host smart-3ed01e51-5a4c-4ed9-8ff1-570ee1e217ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735159925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1735159925
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.473581785
Short name T688
Test name
Test status
Simulation time 1663834564 ps
CPU time 13.22 seconds
Started Mar 31 12:32:41 PM PDT 24
Finished Mar 31 12:32:54 PM PDT 24
Peak memory 210836 kb
Host smart-3ec2d09c-e1e4-4549-842d-ff564557dc30
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473581785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
473581785
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1126938464
Short name T850
Test name
Test status
Simulation time 30326294016 ps
CPU time 41.41 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:33:22 PM PDT 24
Peak memory 210820 kb
Host smart-05b9c1fa-48f7-4e77-95a1-6cde9621f716
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126938464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1126938464
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3744612155
Short name T925
Test name
Test status
Simulation time 32868321608 ps
CPU time 63.45 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:24:46 PM PDT 24
Peak memory 210820 kb
Host smart-4b8834ea-276a-4fea-9440-b88a7bd9b274
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744612155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3744612155
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2003600952
Short name T824
Test name
Test status
Simulation time 3918508085 ps
CPU time 10.34 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 210824 kb
Host smart-1828b30c-da0b-410f-8e85-3d87fa2b970d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003600952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2003600952
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2037273670
Short name T727
Test name
Test status
Simulation time 1066089647 ps
CPU time 10.61 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:51 PM PDT 24
Peak memory 210912 kb
Host smart-c53f3760-5f13-4a63-a670-a68bb4a33dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037273670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2037273670
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3146628203
Short name T879
Test name
Test status
Simulation time 1471697092 ps
CPU time 15.13 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 219048 kb
Host smart-6ce8b9da-076a-4e8b-bc80-7df7892c02a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146628203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3146628203
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3979743085
Short name T709
Test name
Test status
Simulation time 348231884 ps
CPU time 6.52 seconds
Started Mar 31 12:23:49 PM PDT 24
Finished Mar 31 12:23:56 PM PDT 24
Peak memory 214984 kb
Host smart-381de87f-aa03-44f0-8d1f-4670eec148bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979743085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3979743085
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1487095619
Short name T734
Test name
Test status
Simulation time 713099997 ps
CPU time 69.18 seconds
Started Mar 31 12:23:46 PM PDT 24
Finished Mar 31 12:24:56 PM PDT 24
Peak memory 211732 kb
Host smart-8e4a5e19-532e-4cf2-a9d2-06d9be4e050e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487095619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1487095619
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3786400355
Short name T131
Test name
Test status
Simulation time 1886645954 ps
CPU time 74.45 seconds
Started Mar 31 12:32:38 PM PDT 24
Finished Mar 31 12:33:53 PM PDT 24
Peak memory 211620 kb
Host smart-b7478242-417b-44ca-848c-0c47bec02e34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786400355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3786400355
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2427665888
Short name T866
Test name
Test status
Simulation time 2794200847 ps
CPU time 8.44 seconds
Started Mar 31 12:23:46 PM PDT 24
Finished Mar 31 12:23:55 PM PDT 24
Peak memory 219016 kb
Host smart-d85eb0a4-114f-48ed-9c72-b65b08275111
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427665888 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2427665888
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.310789151
Short name T691
Test name
Test status
Simulation time 4579245277 ps
CPU time 9.73 seconds
Started Mar 31 12:32:38 PM PDT 24
Finished Mar 31 12:32:48 PM PDT 24
Peak memory 211632 kb
Host smart-43f870df-eb06-4f80-970d-fa5c47845ade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310789151 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.310789151
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2639958943
Short name T809
Test name
Test status
Simulation time 7514794611 ps
CPU time 15.32 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:56 PM PDT 24
Peak memory 210880 kb
Host smart-d96a2025-9ef8-4b7d-b1da-3b86b49606d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639958943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2639958943
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.72961389
Short name T794
Test name
Test status
Simulation time 7370881203 ps
CPU time 10.69 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 210800 kb
Host smart-993d4e3e-8978-485f-a90e-f9bf99743c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72961389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.72961389
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.158140337
Short name T823
Test name
Test status
Simulation time 2398654791 ps
CPU time 32.01 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:45 PM PDT 24
Peak memory 210828 kb
Host smart-00c4980d-b7a1-45e2-8fb6-01de542ea207
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158140337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.158140337
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3988359011
Short name T91
Test name
Test status
Simulation time 725053335 ps
CPU time 27.41 seconds
Started Mar 31 12:32:38 PM PDT 24
Finished Mar 31 12:33:06 PM PDT 24
Peak memory 210936 kb
Host smart-8fb28f40-7e9e-414d-a073-2717123604ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988359011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3988359011
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.317974503
Short name T778
Test name
Test status
Simulation time 517987520 ps
CPU time 4.31 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:45 PM PDT 24
Peak memory 210844 kb
Host smart-8f880292-ce5c-467d-9d9c-202b14a0287d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317974503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.317974503
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4049981480
Short name T849
Test name
Test status
Simulation time 2870296239 ps
CPU time 12.19 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 210824 kb
Host smart-c61ff10a-30e6-446d-aa29-4d52e6a0f206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049981480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4049981480
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2055547415
Short name T853
Test name
Test status
Simulation time 453388057 ps
CPU time 11.49 seconds
Started Mar 31 12:23:41 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 218976 kb
Host smart-8ad26177-b373-432f-95c8-52b43ed0ed0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055547415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2055547415
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3769688567
Short name T808
Test name
Test status
Simulation time 201170092 ps
CPU time 7.8 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:48 PM PDT 24
Peak memory 219000 kb
Host smart-3fa93eed-7ca0-423c-a505-bd6d9f62862c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769688567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3769688567
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1531338669
Short name T773
Test name
Test status
Simulation time 383893746 ps
CPU time 35.11 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:40 PM PDT 24
Peak memory 210768 kb
Host smart-61344c18-56b6-4bec-8d7f-ec571ff0b156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531338669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1531338669
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.625339376
Short name T801
Test name
Test status
Simulation time 2333560881 ps
CPU time 69.33 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:33:50 PM PDT 24
Peak memory 210940 kb
Host smart-5689ee3e-ca4b-4ecf-bb7a-36d3fe2c0995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625339376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.625339376
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1031016061
Short name T862
Test name
Test status
Simulation time 2608980989 ps
CPU time 6.85 seconds
Started Mar 31 12:23:49 PM PDT 24
Finished Mar 31 12:23:56 PM PDT 24
Peak memory 219060 kb
Host smart-74ea30dd-8424-430c-872b-d32a339cdf3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031016061 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1031016061
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1172660001
Short name T695
Test name
Test status
Simulation time 101591626 ps
CPU time 4.44 seconds
Started Mar 31 12:32:37 PM PDT 24
Finished Mar 31 12:32:42 PM PDT 24
Peak memory 213044 kb
Host smart-bc844509-565a-4c72-aaa2-986b9e0599a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172660001 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1172660001
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2234187686
Short name T712
Test name
Test status
Simulation time 2750052185 ps
CPU time 8.57 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:49 PM PDT 24
Peak memory 210832 kb
Host smart-ad0e7dec-3467-415c-a98e-263fe1ac96a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234187686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2234187686
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.988518406
Short name T752
Test name
Test status
Simulation time 3901877120 ps
CPU time 15.51 seconds
Started Mar 31 12:23:37 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 210792 kb
Host smart-37a0bb92-98ad-43a4-951f-d50d25889f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988518406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.988518406
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1030664913
Short name T892
Test name
Test status
Simulation time 2678762607 ps
CPU time 34.84 seconds
Started Mar 31 12:32:38 PM PDT 24
Finished Mar 31 12:33:13 PM PDT 24
Peak memory 210956 kb
Host smart-20213e13-2ed8-4d6b-9855-b3b68982ce2d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030664913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1030664913
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.325442221
Short name T764
Test name
Test status
Simulation time 40016276576 ps
CPU time 84.8 seconds
Started Mar 31 12:23:42 PM PDT 24
Finished Mar 31 12:25:07 PM PDT 24
Peak memory 210712 kb
Host smart-70e90dbe-65a9-4b89-830e-dfd5ed4784ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325442221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.325442221
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2216252637
Short name T769
Test name
Test status
Simulation time 2027014692 ps
CPU time 16.26 seconds
Started Mar 31 12:32:39 PM PDT 24
Finished Mar 31 12:32:56 PM PDT 24
Peak memory 210912 kb
Host smart-e32c36a1-8f0f-4ba5-9b6e-4e213f5743e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216252637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2216252637
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3049000586
Short name T820
Test name
Test status
Simulation time 1542513651 ps
CPU time 12.92 seconds
Started Mar 31 12:23:58 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 210732 kb
Host smart-dc2d4486-cf0a-4c86-97cf-affb9070d27d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049000586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3049000586
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2289999477
Short name T837
Test name
Test status
Simulation time 920958049 ps
CPU time 7.58 seconds
Started Mar 31 12:32:37 PM PDT 24
Finished Mar 31 12:32:45 PM PDT 24
Peak memory 219152 kb
Host smart-4b34a18e-4f05-431e-a74a-7b0afd933db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289999477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2289999477
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.926165288
Short name T706
Test name
Test status
Simulation time 4718486125 ps
CPU time 15.69 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:18 PM PDT 24
Peak memory 219076 kb
Host smart-bddd68de-063f-40b0-b96b-830755e026a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926165288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.926165288
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.981295548
Short name T911
Test name
Test status
Simulation time 572043182 ps
CPU time 36.02 seconds
Started Mar 31 12:32:39 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 211776 kb
Host smart-ce8afc20-f901-4803-960e-fdf1b22bf43a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981295548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.981295548
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1075264468
Short name T865
Test name
Test status
Simulation time 1245098035 ps
CPU time 11.14 seconds
Started Mar 31 12:32:46 PM PDT 24
Finished Mar 31 12:32:58 PM PDT 24
Peak memory 219140 kb
Host smart-e3e78ca2-3d15-4f07-b726-9ac99db37bf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075264468 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1075264468
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2112800169
Short name T840
Test name
Test status
Simulation time 1040204269 ps
CPU time 10.5 seconds
Started Mar 31 12:23:43 PM PDT 24
Finished Mar 31 12:23:54 PM PDT 24
Peak memory 218924 kb
Host smart-51ea3945-6fd5-44b5-893a-0f0ce61ae93d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112800169 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2112800169
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1501659604
Short name T863
Test name
Test status
Simulation time 5181763881 ps
CPU time 9.53 seconds
Started Mar 31 12:23:43 PM PDT 24
Finished Mar 31 12:23:53 PM PDT 24
Peak memory 210796 kb
Host smart-045cdcf3-eba6-4456-85a1-b55a63cfecc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501659604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1501659604
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1658247733
Short name T96
Test name
Test status
Simulation time 1241004567 ps
CPU time 9.66 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:50 PM PDT 24
Peak memory 210836 kb
Host smart-44982b90-17ee-43de-aacf-28e081e7439b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658247733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1658247733
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1240443991
Short name T881
Test name
Test status
Simulation time 626359110 ps
CPU time 27.03 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:14 PM PDT 24
Peak memory 210852 kb
Host smart-653e65b4-2c30-4502-b162-d80405182e60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240443991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1240443991
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.248879403
Short name T100
Test name
Test status
Simulation time 2178753165 ps
CPU time 26.64 seconds
Started Mar 31 12:23:47 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 210820 kb
Host smart-6805490b-f4ca-4d61-bc2e-0114a194cc0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248879403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.248879403
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1069574669
Short name T739
Test name
Test status
Simulation time 23390371678 ps
CPU time 17.18 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:57 PM PDT 24
Peak memory 210844 kb
Host smart-94545470-ca88-42c1-8e34-25dbeaf5f84a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069574669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1069574669
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3656479330
Short name T929
Test name
Test status
Simulation time 1214428167 ps
CPU time 13.05 seconds
Started Mar 31 12:23:58 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 210704 kb
Host smart-c92209c6-d861-4156-83d1-7dedc7c301c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656479330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3656479330
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3219406978
Short name T860
Test name
Test status
Simulation time 1731246350 ps
CPU time 12.82 seconds
Started Mar 31 12:25:56 PM PDT 24
Finished Mar 31 12:26:09 PM PDT 24
Peak memory 218952 kb
Host smart-1c10ed78-5a73-4472-8ae4-ce5ee537d988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219406978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3219406978
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3719703217
Short name T908
Test name
Test status
Simulation time 3768535541 ps
CPU time 17.12 seconds
Started Mar 31 12:32:40 PM PDT 24
Finished Mar 31 12:32:57 PM PDT 24
Peak memory 219100 kb
Host smart-6a08348a-2995-47c6-b003-99b808d4895b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719703217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3719703217
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1243425354
Short name T135
Test name
Test status
Simulation time 5206396567 ps
CPU time 47.59 seconds
Started Mar 31 12:32:39 PM PDT 24
Finished Mar 31 12:33:26 PM PDT 24
Peak memory 211728 kb
Host smart-c74926fc-1ec1-4319-89a6-8f3276b55e75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243425354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1243425354
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1098471380
Short name T749
Test name
Test status
Simulation time 906440464 ps
CPU time 6.27 seconds
Started Mar 31 12:32:48 PM PDT 24
Finished Mar 31 12:32:54 PM PDT 24
Peak memory 218996 kb
Host smart-3f9f1e41-c90a-4650-a4ec-9c19d16f8e0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098471380 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1098471380
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1654659075
Short name T694
Test name
Test status
Simulation time 1479682491 ps
CPU time 12.69 seconds
Started Mar 31 12:24:57 PM PDT 24
Finished Mar 31 12:25:10 PM PDT 24
Peak memory 218980 kb
Host smart-99b01077-ab66-4e63-8d7c-21454029ff06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654659075 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1654659075
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1192056554
Short name T93
Test name
Test status
Simulation time 12972226890 ps
CPU time 12.63 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:32:59 PM PDT 24
Peak memory 210888 kb
Host smart-3bef082b-947c-4be9-9124-aa74d0373c9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192056554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1192056554
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1997153483
Short name T775
Test name
Test status
Simulation time 1235880153 ps
CPU time 8.04 seconds
Started Mar 31 12:26:05 PM PDT 24
Finished Mar 31 12:26:14 PM PDT 24
Peak memory 210748 kb
Host smart-a1248b5c-d142-43f2-afa3-845900168258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997153483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1997153483
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2636816822
Short name T99
Test name
Test status
Simulation time 547347963 ps
CPU time 27.24 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:15 PM PDT 24
Peak memory 210856 kb
Host smart-d4ae47a2-6a26-4f8a-814a-a328b68decba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636816822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2636816822
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3121066729
Short name T738
Test name
Test status
Simulation time 1197778427 ps
CPU time 13.29 seconds
Started Mar 31 12:32:49 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 210824 kb
Host smart-27a242f8-3504-4cae-a06e-4d6424595de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121066729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3121066729
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3171286588
Short name T821
Test name
Test status
Simulation time 6532723463 ps
CPU time 11.18 seconds
Started Mar 31 12:24:04 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 210820 kb
Host smart-f992777c-6bd4-4f83-a6eb-778e77e47af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171286588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3171286588
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3482792227
Short name T927
Test name
Test status
Simulation time 602733559 ps
CPU time 8.83 seconds
Started Mar 31 12:32:46 PM PDT 24
Finished Mar 31 12:32:55 PM PDT 24
Peak memory 219032 kb
Host smart-59a219e1-d397-40ad-902f-81ea8cb3d1dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482792227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3482792227
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4195861874
Short name T810
Test name
Test status
Simulation time 2147844764 ps
CPU time 13.33 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 219068 kb
Host smart-7ccbdd56-09e3-4e90-84f5-d4c4a179e4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195861874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4195861874
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1818056804
Short name T871
Test name
Test status
Simulation time 4177454653 ps
CPU time 43.4 seconds
Started Mar 31 12:32:45 PM PDT 24
Finished Mar 31 12:33:29 PM PDT 24
Peak memory 211376 kb
Host smart-6c4f4ab0-ffa1-436c-a565-1cf0eb9ba2fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818056804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1818056804
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.983432519
Short name T914
Test name
Test status
Simulation time 7733598108 ps
CPU time 74.56 seconds
Started Mar 31 12:23:59 PM PDT 24
Finished Mar 31 12:25:14 PM PDT 24
Peak memory 218960 kb
Host smart-c47eb2e0-7644-49dc-b804-f5a72db32aef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983432519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.983432519
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2059739948
Short name T742
Test name
Test status
Simulation time 362975643 ps
CPU time 5.22 seconds
Started Mar 31 12:23:50 PM PDT 24
Finished Mar 31 12:23:55 PM PDT 24
Peak memory 218964 kb
Host smart-29b72fa6-1bce-4ff0-8ecd-70f0d6132cf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059739948 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2059739948
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.815700995
Short name T780
Test name
Test status
Simulation time 997338386 ps
CPU time 11.35 seconds
Started Mar 31 12:32:46 PM PDT 24
Finished Mar 31 12:32:58 PM PDT 24
Peak memory 219056 kb
Host smart-7465eed0-582f-4c15-947f-7d0e8a06fba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815700995 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.815700995
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.169558450
Short name T703
Test name
Test status
Simulation time 3956921386 ps
CPU time 15.49 seconds
Started Mar 31 12:32:48 PM PDT 24
Finished Mar 31 12:33:04 PM PDT 24
Peak memory 210832 kb
Host smart-77cf6ae1-7e62-4611-a1d0-29c7a82e68b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169558450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.169558450
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.249869614
Short name T795
Test name
Test status
Simulation time 4427290064 ps
CPU time 11.07 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 210828 kb
Host smart-778d762a-086e-4acd-bb1e-6f59ef2fe978
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249869614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.249869614
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1303116670
Short name T723
Test name
Test status
Simulation time 368602070 ps
CPU time 17.94 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 210760 kb
Host smart-924dbeee-6a25-4e9a-860d-5d15e1acf83b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303116670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1303116670
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1702245142
Short name T928
Test name
Test status
Simulation time 6471460614 ps
CPU time 31.58 seconds
Started Mar 31 12:32:47 PM PDT 24
Finished Mar 31 12:33:18 PM PDT 24
Peak memory 211000 kb
Host smart-53e3c6a8-a7f1-4e7c-84fa-0212103e7196
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702245142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1702245142
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1210379776
Short name T876
Test name
Test status
Simulation time 768806402 ps
CPU time 6.72 seconds
Started Mar 31 12:32:49 PM PDT 24
Finished Mar 31 12:32:56 PM PDT 24
Peak memory 210792 kb
Host smart-4c731f05-7a96-457c-91e4-4ab5195d5eb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210379776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1210379776
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2049420183
Short name T737
Test name
Test status
Simulation time 8703925771 ps
CPU time 15.61 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:25:12 PM PDT 24
Peak memory 209384 kb
Host smart-87e65e12-41a0-450f-b3fd-505c440d8286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049420183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2049420183
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3268711500
Short name T880
Test name
Test status
Simulation time 1528144215 ps
CPU time 14.96 seconds
Started Mar 31 12:32:48 PM PDT 24
Finished Mar 31 12:33:03 PM PDT 24
Peak memory 219060 kb
Host smart-71f70451-14d6-452a-bc7a-752c2b30bd55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268711500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3268711500
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.488434015
Short name T728
Test name
Test status
Simulation time 525860193 ps
CPU time 8.46 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 218968 kb
Host smart-9e7de78e-2759-485e-9eb9-3e4306747f47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488434015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.488434015
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3211898458
Short name T845
Test name
Test status
Simulation time 2095864424 ps
CPU time 36.67 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:53 PM PDT 24
Peak memory 211304 kb
Host smart-39ae8736-a505-4486-a4e6-350bda5b65dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211898458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3211898458
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.64299105
Short name T132
Test name
Test status
Simulation time 1865739753 ps
CPU time 45.01 seconds
Started Mar 31 12:32:45 PM PDT 24
Finished Mar 31 12:33:30 PM PDT 24
Peak memory 211424 kb
Host smart-eb43ef31-2aba-486d-9205-0e7f5dbc9c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64299105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg
_err.64299105
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1223206698
Short name T495
Test name
Test status
Simulation time 690621658 ps
CPU time 4.21 seconds
Started Mar 31 12:28:27 PM PDT 24
Finished Mar 31 12:28:31 PM PDT 24
Peak memory 211672 kb
Host smart-8a83a69a-6ca0-4a7c-9132-bcc2877af539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223206698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1223206698
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2523620315
Short name T226
Test name
Test status
Simulation time 8413418077 ps
CPU time 15.07 seconds
Started Mar 31 12:45:25 PM PDT 24
Finished Mar 31 12:45:40 PM PDT 24
Peak memory 211864 kb
Host smart-eadf5419-4b66-4f9e-9298-cb028a2ce682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523620315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2523620315
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.723030203
Short name T578
Test name
Test status
Simulation time 56029149211 ps
CPU time 136.11 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:30:45 PM PDT 24
Peak memory 229228 kb
Host smart-0f0614cc-dcf9-46bd-9e6d-c12c693b0275
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723030203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.723030203
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1904378375
Short name T269
Test name
Test status
Simulation time 1670898660 ps
CPU time 10.71 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:56 PM PDT 24
Peak memory 212356 kb
Host smart-7888d663-57d6-43a2-8630-9f1dc529e1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904378375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1904378375
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4037389135
Short name T504
Test name
Test status
Simulation time 1458330526 ps
CPU time 10.66 seconds
Started Mar 31 12:45:25 PM PDT 24
Finished Mar 31 12:45:36 PM PDT 24
Peak memory 212288 kb
Host smart-58b89b7b-2fe0-44c5-b5fa-e81f2bea1ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037389135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4037389135
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1355257327
Short name T381
Test name
Test status
Simulation time 380319514 ps
CPU time 5.3 seconds
Started Mar 31 12:28:16 PM PDT 24
Finished Mar 31 12:28:21 PM PDT 24
Peak memory 211552 kb
Host smart-054628de-293d-45aa-afe3-cc921c4d5edf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355257327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1355257327
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.176961118
Short name T342
Test name
Test status
Simulation time 2249274673 ps
CPU time 11.97 seconds
Started Mar 31 12:45:29 PM PDT 24
Finished Mar 31 12:45:41 PM PDT 24
Peak memory 211772 kb
Host smart-c5c42716-ac32-4cf2-a761-f67e39d879c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176961118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.176961118
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.46771880
Short name T39
Test name
Test status
Simulation time 1001064130 ps
CPU time 106.39 seconds
Started Mar 31 12:45:25 PM PDT 24
Finished Mar 31 12:47:12 PM PDT 24
Peak memory 237268 kb
Host smart-2080a761-378c-4b14-9195-7246670a0244
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46771880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.46771880
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.816574354
Short name T37
Test name
Test status
Simulation time 418485668 ps
CPU time 97.87 seconds
Started Mar 31 12:28:32 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 237164 kb
Host smart-20e52fae-6ea4-4cc8-9493-bc832e701849
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816574354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.816574354
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3004195892
Short name T325
Test name
Test status
Simulation time 3959064159 ps
CPU time 24.98 seconds
Started Mar 31 12:45:24 PM PDT 24
Finished Mar 31 12:45:50 PM PDT 24
Peak memory 213888 kb
Host smart-7983ea34-827c-4f2f-a4c4-9c969a57b46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004195892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3004195892
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3801936814
Short name T236
Test name
Test status
Simulation time 2538125859 ps
CPU time 17.91 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:48 PM PDT 24
Peak memory 214088 kb
Host smart-5a9447f9-3f3d-4682-abd3-749ed3ac31c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801936814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3801936814
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.130378310
Short name T230
Test name
Test status
Simulation time 16501674469 ps
CPU time 36.79 seconds
Started Mar 31 12:45:26 PM PDT 24
Finished Mar 31 12:46:03 PM PDT 24
Peak memory 219888 kb
Host smart-f3b751c1-2b1f-4762-a70f-80e0fe2e1b10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130378310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.130378310
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3356073531
Short name T290
Test name
Test status
Simulation time 109573765 ps
CPU time 5.77 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:36 PM PDT 24
Peak memory 211552 kb
Host smart-65b9d979-2ee1-4087-bb02-f226cbc4d6f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356073531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3356073531
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.153209544
Short name T556
Test name
Test status
Simulation time 2886898260 ps
CPU time 12.62 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:42 PM PDT 24
Peak memory 211764 kb
Host smart-422a5e34-5a48-40a4-9b44-dae345aee02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153209544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.153209544
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.440401995
Short name T106
Test name
Test status
Simulation time 165222022 ps
CPU time 4.17 seconds
Started Mar 31 12:45:36 PM PDT 24
Finished Mar 31 12:45:40 PM PDT 24
Peak memory 211732 kb
Host smart-fc8b47c4-c89d-44a3-a75d-2e98723c8f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440401995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.440401995
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1652642124
Short name T386
Test name
Test status
Simulation time 111177527697 ps
CPU time 358.08 seconds
Started Mar 31 12:45:26 PM PDT 24
Finished Mar 31 12:51:24 PM PDT 24
Peak memory 230612 kb
Host smart-b9fe319b-1f5d-4893-b02a-515766ec1b5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652642124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1652642124
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2488249972
Short name T665
Test name
Test status
Simulation time 40773205879 ps
CPU time 388.07 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:35:12 PM PDT 24
Peak memory 232248 kb
Host smart-6d8111ba-1256-4eba-ba3b-7936af4d85c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488249972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2488249972
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2192065110
Short name T622
Test name
Test status
Simulation time 29810780211 ps
CPU time 28.49 seconds
Started Mar 31 12:28:01 PM PDT 24
Finished Mar 31 12:28:30 PM PDT 24
Peak memory 211788 kb
Host smart-9458c6bf-3b21-4acf-b008-1d55f292097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192065110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2192065110
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2701780233
Short name T164
Test name
Test status
Simulation time 30529193934 ps
CPU time 35.12 seconds
Started Mar 31 12:45:25 PM PDT 24
Finished Mar 31 12:46:01 PM PDT 24
Peak memory 212644 kb
Host smart-f0cc2765-429a-4375-bc37-af813caf0adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701780233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2701780233
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3822340482
Short name T139
Test name
Test status
Simulation time 2065937033 ps
CPU time 11.74 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:28:41 PM PDT 24
Peak memory 211576 kb
Host smart-37ad636d-bcec-4c10-b7df-bd8de923b352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822340482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3822340482
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.568202463
Short name T314
Test name
Test status
Simulation time 1833167583 ps
CPU time 15.44 seconds
Started Mar 31 12:45:25 PM PDT 24
Finished Mar 31 12:45:41 PM PDT 24
Peak memory 211640 kb
Host smart-b9ecaa9a-90e4-4e7e-b0c9-18b6629b0cdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568202463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.568202463
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1413727858
Short name T41
Test name
Test status
Simulation time 2426429124 ps
CPU time 105.7 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:30:10 PM PDT 24
Peak memory 237308 kb
Host smart-b1d32d7a-5825-4bfa-bf89-5e9b5feb45bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413727858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1413727858
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4189662403
Short name T42
Test name
Test status
Simulation time 1470369575 ps
CPU time 98.25 seconds
Started Mar 31 12:45:38 PM PDT 24
Finished Mar 31 12:47:16 PM PDT 24
Peak memory 237224 kb
Host smart-9193573e-0ba3-4f19-8dd4-eeb344c4737e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189662403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4189662403
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1119694790
Short name T626
Test name
Test status
Simulation time 7521746485 ps
CPU time 31.36 seconds
Started Mar 31 12:45:26 PM PDT 24
Finished Mar 31 12:45:58 PM PDT 24
Peak memory 219944 kb
Host smart-7ab4975c-4638-4fe6-8007-759f33ff44e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119694790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1119694790
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2245713672
Short name T192
Test name
Test status
Simulation time 2053173836 ps
CPU time 23.78 seconds
Started Mar 31 12:45:28 PM PDT 24
Finished Mar 31 12:45:52 PM PDT 24
Peak memory 213780 kb
Host smart-f3803c0f-fc18-40e7-a28f-4d0ce4ee0973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245713672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2245713672
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2941710343
Short name T634
Test name
Test status
Simulation time 5924292889 ps
CPU time 32.66 seconds
Started Mar 31 12:28:34 PM PDT 24
Finished Mar 31 12:29:07 PM PDT 24
Peak memory 213968 kb
Host smart-58b2536e-02a0-4744-8f86-dfefc0a05f55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941710343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2941710343
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1179849986
Short name T379
Test name
Test status
Simulation time 10050221278 ps
CPU time 12.29 seconds
Started Mar 31 12:28:38 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 211804 kb
Host smart-e90db2f1-9c31-44c7-bd5a-351402f0ba77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179849986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1179849986
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3037210797
Short name T584
Test name
Test status
Simulation time 4291235471 ps
CPU time 10.5 seconds
Started Mar 31 12:45:50 PM PDT 24
Finished Mar 31 12:46:01 PM PDT 24
Peak memory 211884 kb
Host smart-d254a4c3-14d4-46f8-9ef3-f1dd494a464f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037210797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3037210797
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3166183495
Short name T561
Test name
Test status
Simulation time 136153374962 ps
CPU time 383.94 seconds
Started Mar 31 12:45:48 PM PDT 24
Finished Mar 31 12:52:12 PM PDT 24
Peak memory 230888 kb
Host smart-836d1b53-8056-4f4f-b51e-e0ba391cffd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166183495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3166183495
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.858324788
Short name T311
Test name
Test status
Simulation time 70693178838 ps
CPU time 668.2 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:39:52 PM PDT 24
Peak memory 226260 kb
Host smart-04469d6c-021b-4e5b-a316-98df7e22e671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858324788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.858324788
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2438486739
Short name T257
Test name
Test status
Simulation time 347096187 ps
CPU time 9.47 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:53 PM PDT 24
Peak memory 212196 kb
Host smart-c67530ec-07dc-44b7-a277-94d9daa81e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438486739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2438486739
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1358194784
Short name T592
Test name
Test status
Simulation time 2178708795 ps
CPU time 17.71 seconds
Started Mar 31 12:28:36 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 211720 kb
Host smart-ab60b3ec-05f1-4404-ac87-2d37ed94c338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358194784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1358194784
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1523204018
Short name T5
Test name
Test status
Simulation time 919608794 ps
CPU time 8.42 seconds
Started Mar 31 12:45:46 PM PDT 24
Finished Mar 31 12:45:55 PM PDT 24
Peak memory 211652 kb
Host smart-5afea7b1-a1f3-4639-aa3a-72d6aa484c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523204018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1523204018
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1388550006
Short name T489
Test name
Test status
Simulation time 11018744007 ps
CPU time 21.76 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 219844 kb
Host smart-4f453a30-094d-470c-a5ee-6364cf69d170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388550006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1388550006
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3757372617
Short name T573
Test name
Test status
Simulation time 5681806582 ps
CPU time 26.92 seconds
Started Mar 31 12:45:50 PM PDT 24
Finished Mar 31 12:46:17 PM PDT 24
Peak memory 213768 kb
Host smart-b4386802-e2f1-4ff2-964e-47200639748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757372617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3757372617
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1482321401
Short name T476
Test name
Test status
Simulation time 5992312482 ps
CPU time 26.98 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:29:11 PM PDT 24
Peak memory 219868 kb
Host smart-911dbbc9-d8d2-49d5-8a44-97032f4bca2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482321401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1482321401
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.765526594
Short name T601
Test name
Test status
Simulation time 6481459921 ps
CPU time 18.7 seconds
Started Mar 31 12:45:49 PM PDT 24
Finished Mar 31 12:46:08 PM PDT 24
Peak memory 211620 kb
Host smart-0c3c43af-9d2d-4406-97f9-dce7349d7118
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765526594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.765526594
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1749255457
Short name T470
Test name
Test status
Simulation time 4339015701 ps
CPU time 15.16 seconds
Started Mar 31 12:28:32 PM PDT 24
Finished Mar 31 12:28:48 PM PDT 24
Peak memory 211688 kb
Host smart-194a60ea-a8b3-41ae-8992-81869a74b56e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749255457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1749255457
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.588437821
Short name T632
Test name
Test status
Simulation time 1191146022 ps
CPU time 11.64 seconds
Started Mar 31 12:45:55 PM PDT 24
Finished Mar 31 12:46:07 PM PDT 24
Peak memory 211684 kb
Host smart-5abe13d9-3bb1-4ac7-9061-051b2d4cf1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588437821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.588437821
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3360669878
Short name T154
Test name
Test status
Simulation time 22662813637 ps
CPU time 121.9 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:30:34 PM PDT 24
Peak memory 229036 kb
Host smart-25f35525-c98b-4a80-8522-0d8ce1b1dfc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360669878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3360669878
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3594276927
Short name T308
Test name
Test status
Simulation time 132243436162 ps
CPU time 342.38 seconds
Started Mar 31 12:45:56 PM PDT 24
Finished Mar 31 12:51:39 PM PDT 24
Peak memory 226084 kb
Host smart-e2d64436-d578-4c1b-a45f-9eb133f619d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594276927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3594276927
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2513006654
Short name T434
Test name
Test status
Simulation time 2985551260 ps
CPU time 14.26 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 212540 kb
Host smart-81d2f409-2e59-4a96-9ee6-68246d2a7732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513006654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2513006654
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4028745215
Short name T549
Test name
Test status
Simulation time 2871097185 ps
CPU time 26.63 seconds
Started Mar 31 12:45:53 PM PDT 24
Finished Mar 31 12:46:19 PM PDT 24
Peak memory 212536 kb
Host smart-825d9e0b-e268-4fb5-aa27-e8cf72f550e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028745215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4028745215
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2041260707
Short name T496
Test name
Test status
Simulation time 96616897 ps
CPU time 5.32 seconds
Started Mar 31 12:45:53 PM PDT 24
Finished Mar 31 12:45:58 PM PDT 24
Peak memory 211672 kb
Host smart-17f7e7c3-ba9d-4531-8320-e3ab440437a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041260707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2041260707
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3723487167
Short name T205
Test name
Test status
Simulation time 1524298406 ps
CPU time 6.65 seconds
Started Mar 31 12:28:34 PM PDT 24
Finished Mar 31 12:28:41 PM PDT 24
Peak memory 211572 kb
Host smart-830b65f7-a605-412c-bf64-8ef198773735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3723487167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3723487167
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2418344649
Short name T87
Test name
Test status
Simulation time 21539346499 ps
CPU time 33.71 seconds
Started Mar 31 12:45:55 PM PDT 24
Finished Mar 31 12:46:29 PM PDT 24
Peak memory 215020 kb
Host smart-86cde1d9-4d01-4f58-a140-077da460fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418344649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2418344649
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.881426159
Short name T633
Test name
Test status
Simulation time 1205112288 ps
CPU time 12.23 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:51 PM PDT 24
Peak memory 214244 kb
Host smart-334ece74-13ba-46cc-aea1-ef499ba0af34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881426159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.881426159
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3006736674
Short name T462
Test name
Test status
Simulation time 1352726707 ps
CPU time 14.1 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 211484 kb
Host smart-bad323b1-9317-43c4-8607-543a6d4bf774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006736674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3006736674
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.867564098
Short name T307
Test name
Test status
Simulation time 830927605 ps
CPU time 13.86 seconds
Started Mar 31 12:45:53 PM PDT 24
Finished Mar 31 12:46:07 PM PDT 24
Peak memory 211652 kb
Host smart-55ead71f-7067-4013-9e60-13e9949878c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867564098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.867564098
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2875727844
Short name T518
Test name
Test status
Simulation time 1038379062 ps
CPU time 10.16 seconds
Started Mar 31 12:45:54 PM PDT 24
Finished Mar 31 12:46:04 PM PDT 24
Peak memory 211692 kb
Host smart-f1dae322-502f-484c-bc25-a860739258fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875727844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2875727844
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3504029475
Short name T391
Test name
Test status
Simulation time 4778557945 ps
CPU time 11.81 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:28:47 PM PDT 24
Peak memory 211736 kb
Host smart-d1b1bb31-94b4-4f17-a539-752582f13f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504029475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3504029475
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1772258008
Short name T468
Test name
Test status
Simulation time 16768267497 ps
CPU time 162.78 seconds
Started Mar 31 12:45:53 PM PDT 24
Finished Mar 31 12:48:36 PM PDT 24
Peak memory 225448 kb
Host smart-b0551a3b-bb29-483c-887f-a07821fab29d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772258008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1772258008
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2417010620
Short name T361
Test name
Test status
Simulation time 44975874075 ps
CPU time 198.78 seconds
Started Mar 31 12:28:37 PM PDT 24
Finished Mar 31 12:31:56 PM PDT 24
Peak memory 235304 kb
Host smart-c7267799-ce53-4b99-8472-e20ed9d3ad24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417010620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2417010620
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1552498620
Short name T155
Test name
Test status
Simulation time 6216381594 ps
CPU time 19.03 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 213184 kb
Host smart-d57538d3-ab02-41bb-aee4-f85d1e0fad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552498620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1552498620
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1692554886
Short name T7
Test name
Test status
Simulation time 29242816938 ps
CPU time 33.22 seconds
Started Mar 31 12:45:54 PM PDT 24
Finished Mar 31 12:46:27 PM PDT 24
Peak memory 212648 kb
Host smart-7224cfb8-c00e-43d5-8363-403f00c9feff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692554886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1692554886
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2610356631
Short name T568
Test name
Test status
Simulation time 1013486362 ps
CPU time 11.45 seconds
Started Mar 31 12:45:55 PM PDT 24
Finished Mar 31 12:46:07 PM PDT 24
Peak memory 211656 kb
Host smart-01b24682-bc40-4e3e-b613-48f0d9dd1ed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610356631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2610356631
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3434108249
Short name T397
Test name
Test status
Simulation time 10076713401 ps
CPU time 12.19 seconds
Started Mar 31 12:28:42 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 211684 kb
Host smart-9c7ca1de-f115-4654-aa18-b74921def8fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434108249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3434108249
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2941111245
Short name T263
Test name
Test status
Simulation time 7805485459 ps
CPU time 20.05 seconds
Started Mar 31 12:28:34 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 219832 kb
Host smart-e7bffc0b-eab5-472b-80dd-237c7126405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941111245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2941111245
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3502069978
Short name T84
Test name
Test status
Simulation time 13263702715 ps
CPU time 24.96 seconds
Started Mar 31 12:45:53 PM PDT 24
Finished Mar 31 12:46:18 PM PDT 24
Peak memory 219828 kb
Host smart-f51d880c-2cee-4d08-acfc-58dac1ca3601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502069978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3502069978
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1234551745
Short name T352
Test name
Test status
Simulation time 2050719725 ps
CPU time 17.38 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:29:03 PM PDT 24
Peak memory 215564 kb
Host smart-5584ebda-aaaf-4b41-aa14-7e36d6ecb3f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234551745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1234551745
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1500997156
Short name T365
Test name
Test status
Simulation time 3402833680 ps
CPU time 30.86 seconds
Started Mar 31 12:45:55 PM PDT 24
Finished Mar 31 12:46:26 PM PDT 24
Peak memory 214012 kb
Host smart-64fd9698-3b1f-4824-b5c1-34b7d1ea443c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500997156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1500997156
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.324121606
Short name T516
Test name
Test status
Simulation time 24419699203 ps
CPU time 2780.71 seconds
Started Mar 31 12:45:54 PM PDT 24
Finished Mar 31 01:32:15 PM PDT 24
Peak memory 234048 kb
Host smart-8d8f4d47-33e2-4004-b6e1-4caa11b08dd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324121606 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.324121606
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2447977328
Short name T657
Test name
Test status
Simulation time 10666083383 ps
CPU time 12.32 seconds
Started Mar 31 12:28:41 PM PDT 24
Finished Mar 31 12:28:53 PM PDT 24
Peak memory 211752 kb
Host smart-f0096236-f0de-4a25-a354-4f842c7110be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447977328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2447977328
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2683361697
Short name T336
Test name
Test status
Simulation time 1517634396 ps
CPU time 13.73 seconds
Started Mar 31 12:46:03 PM PDT 24
Finished Mar 31 12:46:18 PM PDT 24
Peak memory 211764 kb
Host smart-47778dca-351d-426a-a395-fa45a1a6908b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683361697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2683361697
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2818196911
Short name T662
Test name
Test status
Simulation time 17147447259 ps
CPU time 118.98 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:30:30 PM PDT 24
Peak memory 225052 kb
Host smart-ff489e8d-f83b-4b2b-a3e9-33ccafb616f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818196911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2818196911
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3076199928
Short name T560
Test name
Test status
Simulation time 27967948633 ps
CPU time 333.9 seconds
Started Mar 31 12:45:55 PM PDT 24
Finished Mar 31 12:51:29 PM PDT 24
Peak memory 228884 kb
Host smart-78c30ab7-4b19-4429-bfbf-2a3d4c0195bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076199928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3076199928
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2341216231
Short name T643
Test name
Test status
Simulation time 6900538506 ps
CPU time 31.03 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 12:29:31 PM PDT 24
Peak memory 212660 kb
Host smart-5a8ecfe4-c6db-476b-8585-dcbeaff1ba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341216231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2341216231
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.420437088
Short name T8
Test name
Test status
Simulation time 1440106679 ps
CPU time 11.6 seconds
Started Mar 31 12:45:54 PM PDT 24
Finished Mar 31 12:46:06 PM PDT 24
Peak memory 211792 kb
Host smart-fb4ce24c-1b40-4a7c-93a5-73bb68d85bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420437088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.420437088
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1966806217
Short name T349
Test name
Test status
Simulation time 141554613 ps
CPU time 6.15 seconds
Started Mar 31 12:28:36 PM PDT 24
Finished Mar 31 12:28:43 PM PDT 24
Peak memory 211572 kb
Host smart-27e52dbd-4965-45e2-b083-d3f9c53797d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966806217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1966806217
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2161132771
Short name T458
Test name
Test status
Simulation time 6688493069 ps
CPU time 13.35 seconds
Started Mar 31 12:46:05 PM PDT 24
Finished Mar 31 12:46:19 PM PDT 24
Peak memory 211772 kb
Host smart-f1e271c1-6126-45c1-b24c-735e9fa7678e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161132771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2161132771
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2624520301
Short name T211
Test name
Test status
Simulation time 1684800995 ps
CPU time 11.84 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:52 PM PDT 24
Peak memory 219696 kb
Host smart-48e81bcc-7371-4d8e-b278-521d471e3f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624520301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2624520301
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3316483876
Short name T63
Test name
Test status
Simulation time 10326213563 ps
CPU time 23.23 seconds
Started Mar 31 12:45:53 PM PDT 24
Finished Mar 31 12:46:16 PM PDT 24
Peak memory 215024 kb
Host smart-2f3910a4-8a62-4ce7-bc70-53d573d40002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316483876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3316483876
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1199615485
Short name T623
Test name
Test status
Simulation time 5103845695 ps
CPU time 53.79 seconds
Started Mar 31 12:28:32 PM PDT 24
Finished Mar 31 12:29:26 PM PDT 24
Peak memory 219860 kb
Host smart-bae587c9-3488-45a6-a345-ff1026bfe854
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199615485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1199615485
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.755014361
Short name T19
Test name
Test status
Simulation time 6038616413 ps
CPU time 32.87 seconds
Started Mar 31 12:45:51 PM PDT 24
Finished Mar 31 12:46:24 PM PDT 24
Peak memory 216892 kb
Host smart-c83d0fb9-3352-4816-9bf2-26309fac99db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755014361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.755014361
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3012528300
Short name T186
Test name
Test status
Simulation time 7088377313 ps
CPU time 14.57 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:46:16 PM PDT 24
Peak memory 211868 kb
Host smart-4401b08a-0c3c-47d3-81ec-1c3c67b54877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012528300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3012528300
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3017877549
Short name T359
Test name
Test status
Simulation time 516253352 ps
CPU time 5.92 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:28:56 PM PDT 24
Peak memory 211756 kb
Host smart-c8df1a98-b8c0-46a1-a366-8d37b701037d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017877549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3017877549
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1619774994
Short name T228
Test name
Test status
Simulation time 32494940069 ps
CPU time 299.78 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:51:01 PM PDT 24
Peak memory 231780 kb
Host smart-f5953b64-3359-4aa4-9b54-8dfcba7b1e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619774994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1619774994
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3044806117
Short name T574
Test name
Test status
Simulation time 193165343249 ps
CPU time 495.42 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:36:59 PM PDT 24
Peak memory 247712 kb
Host smart-ca369e83-35c7-4697-a9b4-886ba155c269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044806117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3044806117
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2031616071
Short name T401
Test name
Test status
Simulation time 334712961 ps
CPU time 11.7 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:46:13 PM PDT 24
Peak memory 212692 kb
Host smart-6ca82da8-13e8-4385-a794-f606b7f1589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031616071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2031616071
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2309019031
Short name T72
Test name
Test status
Simulation time 258215923 ps
CPU time 10.57 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 212292 kb
Host smart-d15411cb-bcea-4b25-b4e4-10ddd500a1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309019031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2309019031
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1031758817
Short name T419
Test name
Test status
Simulation time 1618665310 ps
CPU time 10.48 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:28:45 PM PDT 24
Peak memory 211528 kb
Host smart-a83e9207-e117-440a-82fe-6d9de102cc6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031758817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1031758817
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2785353510
Short name T145
Test name
Test status
Simulation time 5105961232 ps
CPU time 12.56 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:46:14 PM PDT 24
Peak memory 211748 kb
Host smart-316757d3-a1d0-4fa5-a51a-7c27a17ceef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785353510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2785353510
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2922485450
Short name T252
Test name
Test status
Simulation time 3403862093 ps
CPU time 29.91 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:46:32 PM PDT 24
Peak memory 219856 kb
Host smart-91f149ef-31b7-48ba-8488-100428749f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922485450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2922485450
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.825939277
Short name T368
Test name
Test status
Simulation time 14565431846 ps
CPU time 32.15 seconds
Started Mar 31 12:28:42 PM PDT 24
Finished Mar 31 12:29:14 PM PDT 24
Peak memory 214504 kb
Host smart-a0d81b0c-faa6-4160-8deb-a0e627afa43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825939277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.825939277
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1770005683
Short name T312
Test name
Test status
Simulation time 33768297791 ps
CPU time 61.45 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 219820 kb
Host smart-93100cd3-79e2-479b-a9ac-59ae9a05dfbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770005683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1770005683
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.895972547
Short name T242
Test name
Test status
Simulation time 1821628150 ps
CPU time 31.52 seconds
Started Mar 31 12:46:04 PM PDT 24
Finished Mar 31 12:46:36 PM PDT 24
Peak memory 214856 kb
Host smart-1738154b-a7bd-4293-86be-e5ad5abfaa26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895972547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.895972547
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.588374978
Short name T122
Test name
Test status
Simulation time 32828114795 ps
CPU time 1372.01 seconds
Started Mar 31 12:46:02 PM PDT 24
Finished Mar 31 01:08:54 PM PDT 24
Peak memory 228548 kb
Host smart-1702f3f1-3807-41b1-9dd3-36a03a576944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588374978 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.588374978
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.413052615
Short name T575
Test name
Test status
Simulation time 99180614 ps
CPU time 4.16 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:28:47 PM PDT 24
Peak memory 211676 kb
Host smart-71106d88-4c35-433a-b3be-9404e46773c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413052615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.413052615
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.560473035
Short name T544
Test name
Test status
Simulation time 925175870 ps
CPU time 10.05 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:46:11 PM PDT 24
Peak memory 211704 kb
Host smart-1088393f-5f41-4dbe-b18e-48e412bcb35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560473035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.560473035
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1017348885
Short name T520
Test name
Test status
Simulation time 108334757800 ps
CPU time 298.25 seconds
Started Mar 31 12:46:02 PM PDT 24
Finished Mar 31 12:51:02 PM PDT 24
Peak memory 234320 kb
Host smart-a2760bb4-a7bd-40fd-886d-fb7deba07528
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017348885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1017348885
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4224828006
Short name T321
Test name
Test status
Simulation time 9416932655 ps
CPU time 103.97 seconds
Started Mar 31 12:28:42 PM PDT 24
Finished Mar 31 12:30:26 PM PDT 24
Peak memory 219096 kb
Host smart-4267427b-4cc0-4bb0-a423-e6396051ea5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224828006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4224828006
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1467170361
Short name T674
Test name
Test status
Simulation time 5934304217 ps
CPU time 29.85 seconds
Started Mar 31 12:46:03 PM PDT 24
Finished Mar 31 12:46:34 PM PDT 24
Peak memory 213168 kb
Host smart-584fcf55-36a7-4897-8e51-20084a815f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467170361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1467170361
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1807360903
Short name T136
Test name
Test status
Simulation time 4256978913 ps
CPU time 11.67 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:46:13 PM PDT 24
Peak memory 211776 kb
Host smart-94b9a139-028a-48c8-a968-e14895e1bcc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807360903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1807360903
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3979908113
Short name T6
Test name
Test status
Simulation time 5652608673 ps
CPU time 12.93 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:28:57 PM PDT 24
Peak memory 211668 kb
Host smart-1a3ee195-09b9-43f8-8e03-168ca4f72c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979908113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3979908113
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1752422612
Short name T267
Test name
Test status
Simulation time 4426666795 ps
CPU time 33.36 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:29:13 PM PDT 24
Peak memory 219768 kb
Host smart-6d5c819f-8ac2-4b65-abf6-8917fe5a1a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752422612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1752422612
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2486462103
Short name T285
Test name
Test status
Simulation time 7097494990 ps
CPU time 21.72 seconds
Started Mar 31 12:46:00 PM PDT 24
Finished Mar 31 12:46:22 PM PDT 24
Peak memory 219836 kb
Host smart-16a61702-c1aa-4dea-a3e5-fe75f03c5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486462103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2486462103
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.226296776
Short name T540
Test name
Test status
Simulation time 34804101067 ps
CPU time 40.96 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:29:27 PM PDT 24
Peak memory 214520 kb
Host smart-c3610ca1-27fb-401a-bc6f-ff3c503289b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226296776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.226296776
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3517933230
Short name T565
Test name
Test status
Simulation time 50599438026 ps
CPU time 48.75 seconds
Started Mar 31 12:46:02 PM PDT 24
Finished Mar 31 12:46:51 PM PDT 24
Peak memory 219908 kb
Host smart-759da6cd-2469-4187-8526-04fba5d0f7fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517933230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3517933230
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2296487474
Short name T616
Test name
Test status
Simulation time 3917099304 ps
CPU time 15.74 seconds
Started Mar 31 12:46:12 PM PDT 24
Finished Mar 31 12:46:29 PM PDT 24
Peak memory 211900 kb
Host smart-8f809dfe-fb1b-4f86-aebe-273583ce575c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296487474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2296487474
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2858057720
Short name T620
Test name
Test status
Simulation time 88950886 ps
CPU time 4.34 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:28:51 PM PDT 24
Peak memory 211656 kb
Host smart-8bf3a8e8-b3c6-4727-a008-7c96cf77e12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858057720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2858057720
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1120221263
Short name T345
Test name
Test status
Simulation time 5391503389 ps
CPU time 139.73 seconds
Started Mar 31 12:46:02 PM PDT 24
Finished Mar 31 12:48:23 PM PDT 24
Peak memory 230320 kb
Host smart-35ff5a5c-aa58-42f6-bf49-1ce61f5a384d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120221263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1120221263
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2405314487
Short name T630
Test name
Test status
Simulation time 293382633773 ps
CPU time 281.72 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:33:29 PM PDT 24
Peak memory 221476 kb
Host smart-11564b4b-4732-4492-ab16-840873cdc88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405314487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2405314487
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2861034619
Short name T426
Test name
Test status
Simulation time 11208809484 ps
CPU time 25.71 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:29:09 PM PDT 24
Peak memory 212684 kb
Host smart-7177974a-c224-47b6-8865-48e6395a5c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861034619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2861034619
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3343935483
Short name T111
Test name
Test status
Simulation time 173780608 ps
CPU time 9.19 seconds
Started Mar 31 12:46:04 PM PDT 24
Finished Mar 31 12:46:13 PM PDT 24
Peak memory 212420 kb
Host smart-86630cfd-17ad-464c-b3c6-70372f73474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343935483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3343935483
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1240739868
Short name T383
Test name
Test status
Simulation time 745126544 ps
CPU time 6.43 seconds
Started Mar 31 12:46:02 PM PDT 24
Finished Mar 31 12:46:08 PM PDT 24
Peak memory 211672 kb
Host smart-4a4177a0-1f09-423a-b912-4aa160ba8465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1240739868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1240739868
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2520905852
Short name T235
Test name
Test status
Simulation time 530609323 ps
CPU time 6.21 seconds
Started Mar 31 12:28:41 PM PDT 24
Finished Mar 31 12:28:47 PM PDT 24
Peak memory 211524 kb
Host smart-9cdca7db-67b2-443d-971a-7b253104fa8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520905852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2520905852
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.115323792
Short name T162
Test name
Test status
Simulation time 188558395 ps
CPU time 10.12 seconds
Started Mar 31 12:28:27 PM PDT 24
Finished Mar 31 12:28:38 PM PDT 24
Peak memory 213308 kb
Host smart-c4a8cdc8-be4f-48e4-8b77-f8fdbdfe31d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115323792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.115323792
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4291838981
Short name T234
Test name
Test status
Simulation time 3536939497 ps
CPU time 34.55 seconds
Started Mar 31 12:46:06 PM PDT 24
Finished Mar 31 12:46:41 PM PDT 24
Peak memory 213280 kb
Host smart-24738bee-6b31-4a52-8e84-31166c7f4f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291838981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4291838981
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.152303640
Short name T161
Test name
Test status
Simulation time 14222694385 ps
CPU time 58.1 seconds
Started Mar 31 12:46:01 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 219928 kb
Host smart-e073588f-85a2-4adb-bc93-6a1e9622360f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152303640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.152303640
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1571212617
Short name T243
Test name
Test status
Simulation time 182719786 ps
CPU time 7.79 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:52 PM PDT 24
Peak memory 211564 kb
Host smart-70136282-3cf7-4ad4-9e6d-a7ce0d4738aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571212617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1571212617
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3684019526
Short name T459
Test name
Test status
Simulation time 7555264983 ps
CPU time 13.97 seconds
Started Mar 31 12:46:14 PM PDT 24
Finished Mar 31 12:46:28 PM PDT 24
Peak memory 211812 kb
Host smart-04cce829-0386-46a5-9549-21365e254468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684019526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3684019526
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.881810064
Short name T439
Test name
Test status
Simulation time 778278249 ps
CPU time 9.14 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:29:00 PM PDT 24
Peak memory 211636 kb
Host smart-bd1107af-0e76-4b89-8848-0b12b5c5dbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881810064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.881810064
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1468971313
Short name T609
Test name
Test status
Simulation time 24119409083 ps
CPU time 242.26 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:32:51 PM PDT 24
Peak memory 230324 kb
Host smart-5578aa08-d2d2-4d9b-800c-367242625e27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468971313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1468971313
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4085663263
Short name T21
Test name
Test status
Simulation time 4184123108 ps
CPU time 62.99 seconds
Started Mar 31 12:46:10 PM PDT 24
Finished Mar 31 12:47:13 PM PDT 24
Peak memory 238248 kb
Host smart-1d61b111-5a5f-424c-aa38-c44fedb7fa65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085663263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4085663263
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3686542699
Short name T503
Test name
Test status
Simulation time 1384149246 ps
CPU time 9.31 seconds
Started Mar 31 12:46:08 PM PDT 24
Finished Mar 31 12:46:18 PM PDT 24
Peak memory 212292 kb
Host smart-a1f6b74c-06d4-4427-abb8-5f352b995ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686542699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3686542699
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.833146153
Short name T535
Test name
Test status
Simulation time 168820489 ps
CPU time 9.17 seconds
Started Mar 31 12:28:41 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 212312 kb
Host smart-62f1f7ae-97a8-49b6-a265-59d14d4bbeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833146153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.833146153
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1479867757
Short name T387
Test name
Test status
Simulation time 7310423830 ps
CPU time 15.25 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:29:00 PM PDT 24
Peak memory 211680 kb
Host smart-39a3a224-0bb7-4d32-9d2e-0fc5415e335f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479867757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1479867757
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3285245866
Short name T508
Test name
Test status
Simulation time 11411414903 ps
CPU time 15.4 seconds
Started Mar 31 12:46:08 PM PDT 24
Finished Mar 31 12:46:23 PM PDT 24
Peak memory 211752 kb
Host smart-d280eb45-d941-487d-ab32-da5df48c13e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285245866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3285245866
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1042853417
Short name T502
Test name
Test status
Simulation time 5288599480 ps
CPU time 19.69 seconds
Started Mar 31 12:46:10 PM PDT 24
Finished Mar 31 12:46:30 PM PDT 24
Peak memory 219964 kb
Host smart-91f50349-4a75-49ab-8b72-1ca52354a42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042853417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1042853417
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3490742255
Short name T83
Test name
Test status
Simulation time 7151741665 ps
CPU time 33.43 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:21 PM PDT 24
Peak memory 214464 kb
Host smart-8da6c92f-2678-4e45-9e39-1cf01f11c2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490742255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3490742255
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2093802399
Short name T492
Test name
Test status
Simulation time 1356553417 ps
CPU time 22.97 seconds
Started Mar 31 12:46:14 PM PDT 24
Finished Mar 31 12:46:37 PM PDT 24
Peak memory 215208 kb
Host smart-3023ba88-a9b3-4bc3-918a-3ee13d471a74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093802399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2093802399
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.835802584
Short name T624
Test name
Test status
Simulation time 1388169950 ps
CPU time 29.06 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 12:29:23 PM PDT 24
Peak memory 215488 kb
Host smart-ac78f0b6-f8d2-474e-bee3-fdb12d73f2ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835802584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.835802584
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3293750013
Short name T498
Test name
Test status
Simulation time 799786462 ps
CPU time 8.81 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:28:56 PM PDT 24
Peak memory 211656 kb
Host smart-2e5932e9-465d-4a8a-b9ed-76c5e9d01e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293750013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3293750013
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3954049224
Short name T398
Test name
Test status
Simulation time 2126167928 ps
CPU time 16.42 seconds
Started Mar 31 12:46:10 PM PDT 24
Finished Mar 31 12:46:27 PM PDT 24
Peak memory 211784 kb
Host smart-eedc6b70-2158-41ea-8521-72f2413f81ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954049224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3954049224
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3207751854
Short name T467
Test name
Test status
Simulation time 27929344463 ps
CPU time 236.92 seconds
Started Mar 31 12:46:15 PM PDT 24
Finished Mar 31 12:50:12 PM PDT 24
Peak memory 238300 kb
Host smart-d96e1e59-d993-41e1-9b14-86a6b5fa1005
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207751854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3207751854
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.423456475
Short name T218
Test name
Test status
Simulation time 2173602960 ps
CPU time 65.31 seconds
Started Mar 31 12:28:56 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 219048 kb
Host smart-9a0e62ba-19af-4653-bab1-d9c830a0299d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423456475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.423456475
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1425288571
Short name T415
Test name
Test status
Simulation time 4156576455 ps
CPU time 33.59 seconds
Started Mar 31 12:46:08 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 212608 kb
Host smart-a36d06c8-8713-407a-933b-61f87125d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425288571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1425288571
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1700986327
Short name T558
Test name
Test status
Simulation time 7035700119 ps
CPU time 29.63 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:16 PM PDT 24
Peak memory 213008 kb
Host smart-825235c8-f8b2-4845-a107-f8d20719808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700986327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1700986327
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1771011086
Short name T348
Test name
Test status
Simulation time 826854328 ps
CPU time 10.07 seconds
Started Mar 31 12:46:08 PM PDT 24
Finished Mar 31 12:46:18 PM PDT 24
Peak memory 211652 kb
Host smart-cc9e5d9e-0753-4d18-9312-9ef4130fb336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771011086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1771011086
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1954480044
Short name T513
Test name
Test status
Simulation time 572777892 ps
CPU time 7.97 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:28:58 PM PDT 24
Peak memory 211660 kb
Host smart-f76a1c69-d804-480b-a99b-56e3c0b83a69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954480044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1954480044
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2699253596
Short name T484
Test name
Test status
Simulation time 3636639503 ps
CPU time 25.56 seconds
Started Mar 31 12:29:10 PM PDT 24
Finished Mar 31 12:29:36 PM PDT 24
Peak memory 219816 kb
Host smart-403ef45b-e4d2-40f8-b153-dfc253135e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699253596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2699253596
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3906458797
Short name T244
Test name
Test status
Simulation time 693582092 ps
CPU time 13.85 seconds
Started Mar 31 12:46:14 PM PDT 24
Finished Mar 31 12:46:28 PM PDT 24
Peak memory 213372 kb
Host smart-b58bfcb9-28fd-4416-8729-7b485513db0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906458797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3906458797
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3746545075
Short name T523
Test name
Test status
Simulation time 5147262377 ps
CPU time 27.09 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:29:10 PM PDT 24
Peak memory 217456 kb
Host smart-307c167e-ec44-4fc4-87bb-a0d92b829a4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746545075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3746545075
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.753518017
Short name T477
Test name
Test status
Simulation time 7707436014 ps
CPU time 22.19 seconds
Started Mar 31 12:46:14 PM PDT 24
Finished Mar 31 12:46:36 PM PDT 24
Peak memory 215848 kb
Host smart-7d3c3ec0-d368-41b2-9510-3dbce275ac54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753518017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.753518017
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.941770171
Short name T282
Test name
Test status
Simulation time 185545659637 ps
CPU time 1932.69 seconds
Started Mar 31 12:46:10 PM PDT 24
Finished Mar 31 01:18:23 PM PDT 24
Peak memory 235544 kb
Host smart-8569a62e-da0d-4d44-805a-f1bdbd84c126
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941770171 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.941770171
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1431777377
Short name T280
Test name
Test status
Simulation time 1032487516 ps
CPU time 10.27 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:56 PM PDT 24
Peak memory 211652 kb
Host smart-65017ff0-5e6a-4728-8fb9-9c7ddacbb026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431777377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1431777377
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2111253602
Short name T483
Test name
Test status
Simulation time 293428029 ps
CPU time 6.45 seconds
Started Mar 31 12:46:21 PM PDT 24
Finished Mar 31 12:46:28 PM PDT 24
Peak memory 211792 kb
Host smart-af1eeee5-e2ec-4ef9-b21d-1443e24fbb21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111253602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2111253602
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.357826728
Short name T202
Test name
Test status
Simulation time 274926409527 ps
CPU time 323.86 seconds
Started Mar 31 12:46:12 PM PDT 24
Finished Mar 31 12:51:36 PM PDT 24
Peak memory 225264 kb
Host smart-7fd07409-d3cf-4a4b-b47a-e9de31b0fe6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357826728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.357826728
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.839013562
Short name T304
Test name
Test status
Simulation time 29228868327 ps
CPU time 136.33 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:31:05 PM PDT 24
Peak memory 212992 kb
Host smart-95f1ae60-6a45-4366-8563-7ec1e883efb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839013562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.839013562
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1437336206
Short name T382
Test name
Test status
Simulation time 3384427634 ps
CPU time 26.17 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 212412 kb
Host smart-80b711a5-5df9-44eb-a95c-5bc19dd20108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437336206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1437336206
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2493732536
Short name T552
Test name
Test status
Simulation time 26658643737 ps
CPU time 27.64 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:29:11 PM PDT 24
Peak memory 213472 kb
Host smart-a3422291-331f-404f-9a84-5e0e6dfdecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493732536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2493732536
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1379307376
Short name T446
Test name
Test status
Simulation time 7202319361 ps
CPU time 15.17 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:29:01 PM PDT 24
Peak memory 211684 kb
Host smart-66cf8baf-ddee-44ec-8514-f4b8d2376ef1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379307376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1379307376
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1432759707
Short name T249
Test name
Test status
Simulation time 206111992 ps
CPU time 5.43 seconds
Started Mar 31 12:46:13 PM PDT 24
Finished Mar 31 12:46:19 PM PDT 24
Peak memory 211668 kb
Host smart-92a51b2a-0f12-43b9-9c59-65493a6ee901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432759707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1432759707
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1765214522
Short name T550
Test name
Test status
Simulation time 2789475076 ps
CPU time 25.89 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:29:12 PM PDT 24
Peak memory 213320 kb
Host smart-1c3f24e1-bf60-4bf6-a524-edf1fc207ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765214522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1765214522
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.58104680
Short name T284
Test name
Test status
Simulation time 4283695315 ps
CPU time 33.87 seconds
Started Mar 31 12:46:09 PM PDT 24
Finished Mar 31 12:46:43 PM PDT 24
Peak memory 219856 kb
Host smart-0fd9a95e-d0af-4db4-bb3f-92b193ad6e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58104680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.58104680
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1635830820
Short name T514
Test name
Test status
Simulation time 1388328933 ps
CPU time 16.49 seconds
Started Mar 31 12:46:13 PM PDT 24
Finished Mar 31 12:46:29 PM PDT 24
Peak memory 219832 kb
Host smart-9cc4e31a-cbfb-4a28-8c69-963000064f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635830820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1635830820
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3126024265
Short name T596
Test name
Test status
Simulation time 6761040773 ps
CPU time 17.38 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:29:02 PM PDT 24
Peak memory 212808 kb
Host smart-4de34f14-ffbf-428e-bdeb-6bc2086a8f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126024265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3126024265
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1117380024
Short name T637
Test name
Test status
Simulation time 121786110474 ps
CPU time 1672.51 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 01:14:10 PM PDT 24
Peak memory 235728 kb
Host smart-531ae055-8f0d-469c-af6a-d7ce36cde3a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117380024 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1117380024
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1941389787
Short name T103
Test name
Test status
Simulation time 33209372255 ps
CPU time 1355.93 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:51:24 PM PDT 24
Peak memory 236312 kb
Host smart-29119881-7da4-4576-b477-cec1f125f06b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941389787 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1941389787
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1732707490
Short name T156
Test name
Test status
Simulation time 2923668546 ps
CPU time 13.3 seconds
Started Mar 31 12:45:34 PM PDT 24
Finished Mar 31 12:45:47 PM PDT 24
Peak memory 211884 kb
Host smart-314d3032-c19e-4245-b34f-603210566465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732707490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1732707490
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.90483101
Short name T247
Test name
Test status
Simulation time 21635290104 ps
CPU time 13.14 seconds
Started Mar 31 12:28:41 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 211892 kb
Host smart-5af4488f-cfad-4f72-a9c6-268b959827f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90483101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.90483101
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3551014843
Short name T443
Test name
Test status
Simulation time 80914467750 ps
CPU time 176.92 seconds
Started Mar 31 12:28:19 PM PDT 24
Finished Mar 31 12:31:16 PM PDT 24
Peak memory 237032 kb
Host smart-814f236e-10a8-4588-96d7-fe22e22891ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551014843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3551014843
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.531408060
Short name T599
Test name
Test status
Simulation time 13262759127 ps
CPU time 175.03 seconds
Started Mar 31 12:45:34 PM PDT 24
Finished Mar 31 12:48:29 PM PDT 24
Peak memory 229400 kb
Host smart-53cdd324-7e0b-45ed-b2a8-314f6ebea4c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531408060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.531408060
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3999468140
Short name T480
Test name
Test status
Simulation time 2388618524 ps
CPU time 13.45 seconds
Started Mar 31 12:45:35 PM PDT 24
Finished Mar 31 12:45:49 PM PDT 24
Peak memory 211876 kb
Host smart-54d2c90e-f8c6-4789-bec8-a53f50769638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999468140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3999468140
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.456106275
Short name T227
Test name
Test status
Simulation time 13928290161 ps
CPU time 29.85 seconds
Started Mar 31 12:28:27 PM PDT 24
Finished Mar 31 12:28:57 PM PDT 24
Peak memory 212908 kb
Host smart-79ccce00-db33-4806-bc8c-08417541948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456106275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.456106275
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4050350848
Short name T488
Test name
Test status
Simulation time 2819688638 ps
CPU time 16.5 seconds
Started Mar 31 12:45:33 PM PDT 24
Finished Mar 31 12:45:50 PM PDT 24
Peak memory 211804 kb
Host smart-17430725-117d-4783-be6e-ad95b98bbbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050350848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4050350848
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.598392389
Short name T277
Test name
Test status
Simulation time 369772540 ps
CPU time 5.45 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:28:36 PM PDT 24
Peak memory 211544 kb
Host smart-bd5803b3-dceb-482e-800b-793861018393
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598392389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.598392389
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1274534331
Short name T38
Test name
Test status
Simulation time 582009227 ps
CPU time 101.24 seconds
Started Mar 31 12:45:32 PM PDT 24
Finished Mar 31 12:47:13 PM PDT 24
Peak memory 238468 kb
Host smart-81eabd5e-c8d8-472e-a3a5-eddb81033120
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274534331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1274534331
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3588464459
Short name T40
Test name
Test status
Simulation time 6225141557 ps
CPU time 106.73 seconds
Started Mar 31 12:28:37 PM PDT 24
Finished Mar 31 12:30:24 PM PDT 24
Peak memory 237320 kb
Host smart-55927811-4cd4-43e5-bdf8-5f99d5c7bec5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588464459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3588464459
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2697561358
Short name T231
Test name
Test status
Simulation time 189990751 ps
CPU time 9.94 seconds
Started Mar 31 12:45:33 PM PDT 24
Finished Mar 31 12:45:43 PM PDT 24
Peak memory 219788 kb
Host smart-57f9b1da-8b02-4808-b487-afce532924b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697561358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2697561358
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.83104632
Short name T364
Test name
Test status
Simulation time 504672515 ps
CPU time 10.5 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:28:46 PM PDT 24
Peak memory 219716 kb
Host smart-09437a38-c6fe-4e73-bba1-ee40e5b4de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83104632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.83104632
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1044061917
Short name T430
Test name
Test status
Simulation time 3980873745 ps
CPU time 45.15 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:29:18 PM PDT 24
Peak memory 219832 kb
Host smart-20260d2e-c8f3-4c5a-817e-c7969c0fa36a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044061917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1044061917
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2012315945
Short name T631
Test name
Test status
Simulation time 13790722342 ps
CPU time 42.72 seconds
Started Mar 31 12:45:33 PM PDT 24
Finished Mar 31 12:46:16 PM PDT 24
Peak memory 219928 kb
Host smart-808f510c-1db1-4fd1-9415-dc58f4dd1ef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012315945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2012315945
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3883698643
Short name T559
Test name
Test status
Simulation time 329827986191 ps
CPU time 1807.97 seconds
Started Mar 31 12:45:33 PM PDT 24
Finished Mar 31 01:15:41 PM PDT 24
Peak memory 236616 kb
Host smart-db9cccef-e4e6-4976-9a04-3ae8fbe7fce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883698643 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3883698643
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1157273726
Short name T588
Test name
Test status
Simulation time 942287758 ps
CPU time 10.37 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:46:27 PM PDT 24
Peak memory 211780 kb
Host smart-0040ff80-2b60-42ef-88fb-fb6d2183f885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157273726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1157273726
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.479975323
Short name T152
Test name
Test status
Simulation time 303296200 ps
CPU time 6.19 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:28:57 PM PDT 24
Peak memory 211648 kb
Host smart-211cba8d-1cef-451b-bdaa-3cd40a040393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479975323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.479975323
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1234162690
Short name T669
Test name
Test status
Simulation time 260130728827 ps
CPU time 342.35 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:34:25 PM PDT 24
Peak memory 225552 kb
Host smart-afe56360-4905-4090-8d4f-ed19979ea17d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234162690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1234162690
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.722836864
Short name T547
Test name
Test status
Simulation time 34709000576 ps
CPU time 346.33 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:52:03 PM PDT 24
Peak memory 228360 kb
Host smart-125329a2-8f5b-4b5c-b735-fc1ffd8e19a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722836864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.722836864
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2097281762
Short name T350
Test name
Test status
Simulation time 4478524959 ps
CPU time 33.68 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 12:29:36 PM PDT 24
Peak memory 212656 kb
Host smart-60a5eac7-5db6-423e-b01b-f9f4719e54d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097281762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2097281762
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.700618766
Short name T185
Test name
Test status
Simulation time 175672564 ps
CPU time 9.37 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:34 PM PDT 24
Peak memory 211676 kb
Host smart-c4679c67-669f-4188-9410-5ccea63bcde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700618766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.700618766
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2366410159
Short name T668
Test name
Test status
Simulation time 3600619776 ps
CPU time 16.1 seconds
Started Mar 31 12:28:42 PM PDT 24
Finished Mar 31 12:28:58 PM PDT 24
Peak memory 211692 kb
Host smart-f753a29c-69aa-43ba-9b55-ea7e54822c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366410159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2366410159
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.283623216
Short name T193
Test name
Test status
Simulation time 2406956497 ps
CPU time 17.71 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 211688 kb
Host smart-b08e2c06-2674-491c-9fcf-4ca9058711de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283623216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.283623216
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2007544592
Short name T402
Test name
Test status
Simulation time 16208109625 ps
CPU time 34.01 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:46:51 PM PDT 24
Peak memory 214624 kb
Host smart-cb5b7162-922d-477d-b792-8c888e9b401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007544592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2007544592
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2494819428
Short name T621
Test name
Test status
Simulation time 669567189 ps
CPU time 9.95 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 213864 kb
Host smart-2fbd0961-bab6-49cc-8655-e0841a982fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494819428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2494819428
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3511456775
Short name T166
Test name
Test status
Simulation time 7952063963 ps
CPU time 64.05 seconds
Started Mar 31 12:46:15 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 219876 kb
Host smart-a8cd9172-29b3-4050-8ab6-ce6caa205d26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511456775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3511456775
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4010157374
Short name T650
Test name
Test status
Simulation time 14773984676 ps
CPU time 76.61 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 219832 kb
Host smart-5a19ff1c-5235-4d86-a727-73cf9e7f8442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010157374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4010157374
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3369880945
Short name T291
Test name
Test status
Simulation time 6867313174 ps
CPU time 14.44 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:39 PM PDT 24
Peak memory 211800 kb
Host smart-f3facf87-7e30-440b-8e0f-92f2b8e687ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369880945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3369880945
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2213814120
Short name T23
Test name
Test status
Simulation time 5098656931 ps
CPU time 177.64 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:31:41 PM PDT 24
Peak memory 233544 kb
Host smart-a4227e78-325c-4689-965e-105db02305c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213814120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2213814120
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3482880923
Short name T506
Test name
Test status
Simulation time 49714996471 ps
CPU time 140.55 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:48:37 PM PDT 24
Peak memory 229052 kb
Host smart-da6a93ab-0556-4f9a-92f0-c22a7682b608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482880923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3482880923
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1463173478
Short name T146
Test name
Test status
Simulation time 693590366 ps
CPU time 9.22 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:46:25 PM PDT 24
Peak memory 212508 kb
Host smart-146cbabf-36a3-4478-add5-7914e29bdc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463173478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1463173478
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1529478777
Short name T187
Test name
Test status
Simulation time 168454402 ps
CPU time 9.34 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 212160 kb
Host smart-a0e0320b-8c0e-42b4-8b31-cf328f78ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529478777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1529478777
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4157179971
Short name T465
Test name
Test status
Simulation time 1844382307 ps
CPU time 16.2 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:29:07 PM PDT 24
Peak memory 211536 kb
Host smart-9f0b7ba2-37e7-45b4-bf00-434446d6a550
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157179971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4157179971
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4157906791
Short name T685
Test name
Test status
Simulation time 3935126441 ps
CPU time 14.54 seconds
Started Mar 31 12:46:17 PM PDT 24
Finished Mar 31 12:46:31 PM PDT 24
Peak memory 211776 kb
Host smart-a21465b1-bd3a-4f80-ab51-b81087d549d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157906791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4157906791
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2296625549
Short name T515
Test name
Test status
Simulation time 9229820502 ps
CPU time 23.5 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:29:11 PM PDT 24
Peak memory 219820 kb
Host smart-1e194294-9b31-4d02-9ff2-da69625cc318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296625549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2296625549
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2437210770
Short name T245
Test name
Test status
Simulation time 17745270852 ps
CPU time 41.29 seconds
Started Mar 31 12:46:17 PM PDT 24
Finished Mar 31 12:46:58 PM PDT 24
Peak memory 214744 kb
Host smart-c0704493-d530-48ce-afe5-af59a20ee99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437210770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2437210770
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2446008437
Short name T408
Test name
Test status
Simulation time 594964857 ps
CPU time 14.75 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 215588 kb
Host smart-75ef4640-dc51-411e-a7fd-1957dcebc041
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446008437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2446008437
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3278989437
Short name T355
Test name
Test status
Simulation time 18429005922 ps
CPU time 46.42 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:47:11 PM PDT 24
Peak memory 219856 kb
Host smart-9577142a-dbad-4be3-b5ea-35efb7df01af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278989437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3278989437
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.316757364
Short name T270
Test name
Test status
Simulation time 8068342486 ps
CPU time 15.44 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:28:58 PM PDT 24
Peak memory 211804 kb
Host smart-304b790f-5ef2-4a1d-baed-b2a6df960db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316757364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.316757364
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.768174485
Short name T206
Test name
Test status
Simulation time 1278678141 ps
CPU time 11.75 seconds
Started Mar 31 12:46:23 PM PDT 24
Finished Mar 31 12:46:35 PM PDT 24
Peak memory 211796 kb
Host smart-3a2744ec-9888-4943-a933-b7b2d7d34649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768174485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.768174485
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1215400478
Short name T261
Test name
Test status
Simulation time 1086503081 ps
CPU time 62.14 seconds
Started Mar 31 12:46:21 PM PDT 24
Finished Mar 31 12:47:24 PM PDT 24
Peak memory 230232 kb
Host smart-6c90a1ab-d0e7-499f-82ba-982de09733cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215400478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1215400478
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2505443227
Short name T546
Test name
Test status
Simulation time 443270976770 ps
CPU time 414.51 seconds
Started Mar 31 12:28:42 PM PDT 24
Finished Mar 31 12:35:36 PM PDT 24
Peak memory 214104 kb
Host smart-87e739c6-e234-4b26-84c6-90e81d5b426e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505443227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2505443227
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1623074892
Short name T59
Test name
Test status
Simulation time 1105004608 ps
CPU time 9.24 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:28:56 PM PDT 24
Peak memory 212188 kb
Host smart-9b7269f7-570d-4fe4-b49e-f4933c7b0984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623074892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1623074892
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2472176390
Short name T536
Test name
Test status
Simulation time 3840714726 ps
CPU time 19.1 seconds
Started Mar 31 12:46:21 PM PDT 24
Finished Mar 31 12:46:41 PM PDT 24
Peak memory 212824 kb
Host smart-5ff4c634-ac02-49cc-a778-34a4b546fc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472176390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2472176390
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1642513529
Short name T659
Test name
Test status
Simulation time 1736403887 ps
CPU time 14.72 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:46:32 PM PDT 24
Peak memory 211568 kb
Host smart-93d9d84b-55ce-4682-85d7-3e368b350d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642513529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1642513529
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.528837195
Short name T581
Test name
Test status
Simulation time 7619552250 ps
CPU time 16.37 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:29:00 PM PDT 24
Peak memory 211788 kb
Host smart-bde82127-7130-4ce2-b47d-bde6f978a897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528837195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.528837195
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2377060860
Short name T328
Test name
Test status
Simulation time 11632720787 ps
CPU time 31.97 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:29:16 PM PDT 24
Peak memory 215048 kb
Host smart-a851e671-7de8-4be2-a608-1bd7f4e517fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377060860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2377060860
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.52151375
Short name T390
Test name
Test status
Simulation time 20969904868 ps
CPU time 27.08 seconds
Started Mar 31 12:46:16 PM PDT 24
Finished Mar 31 12:46:43 PM PDT 24
Peak memory 219928 kb
Host smart-734a3788-4ab4-477e-a69a-21c0b844a93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52151375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.52151375
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1484730129
Short name T322
Test name
Test status
Simulation time 14845483716 ps
CPU time 23.07 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:29:11 PM PDT 24
Peak memory 217368 kb
Host smart-68d1c491-3beb-4a0c-8421-a225042a8200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484730129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1484730129
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.551143075
Short name T448
Test name
Test status
Simulation time 4143271976 ps
CPU time 40.62 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:47:05 PM PDT 24
Peak memory 219832 kb
Host smart-74710dff-7d38-4352-a6fa-2838ac18821c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551143075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.551143075
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2820244964
Short name T24
Test name
Test status
Simulation time 43158654081 ps
CPU time 470.8 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 233464 kb
Host smart-6dff3f0b-e5ef-4ce4-8353-37bc6c771e60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820244964 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2820244964
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.420742496
Short name T120
Test name
Test status
Simulation time 253529632456 ps
CPU time 10040.7 seconds
Started Mar 31 12:46:27 PM PDT 24
Finished Mar 31 03:33:48 PM PDT 24
Peak memory 239968 kb
Host smart-499b4814-b960-4008-a070-27b3f4afdb4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420742496 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.420742496
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1262316987
Short name T346
Test name
Test status
Simulation time 3737191393 ps
CPU time 8.94 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:34 PM PDT 24
Peak memory 211888 kb
Host smart-3e04e9d4-4bf4-46e0-9180-2a7ee7cf11b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262316987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1262316987
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3701740478
Short name T67
Test name
Test status
Simulation time 1337026826 ps
CPU time 12.76 seconds
Started Mar 31 12:28:42 PM PDT 24
Finished Mar 31 12:28:55 PM PDT 24
Peak memory 211620 kb
Host smart-59644dc1-6459-4f10-91b3-071490973901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701740478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3701740478
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3739103091
Short name T174
Test name
Test status
Simulation time 1685463250 ps
CPU time 101.26 seconds
Started Mar 31 12:29:10 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 230856 kb
Host smart-505f6e29-712b-45cf-bf77-c9b9dc8a22cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739103091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3739103091
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3740324173
Short name T635
Test name
Test status
Simulation time 35333843810 ps
CPU time 302.2 seconds
Started Mar 31 12:46:23 PM PDT 24
Finished Mar 31 12:51:25 PM PDT 24
Peak memory 229296 kb
Host smart-32a4f38b-1dd1-4144-ad36-531feea74a19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740324173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3740324173
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1974026396
Short name T589
Test name
Test status
Simulation time 1385471035 ps
CPU time 11.3 seconds
Started Mar 31 12:46:28 PM PDT 24
Finished Mar 31 12:46:39 PM PDT 24
Peak memory 212768 kb
Host smart-0022a7a1-bec2-44bd-abb1-74f4abd4c5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974026396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1974026396
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2229169382
Short name T572
Test name
Test status
Simulation time 10509083307 ps
CPU time 22.09 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:12 PM PDT 24
Peak memory 211696 kb
Host smart-bc234da3-3615-4ad9-a450-119ece0a72ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229169382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2229169382
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3609492428
Short name T239
Test name
Test status
Simulation time 1083283033 ps
CPU time 11.99 seconds
Started Mar 31 12:29:21 PM PDT 24
Finished Mar 31 12:29:34 PM PDT 24
Peak memory 211652 kb
Host smart-09a04f22-8724-473b-bf16-b0f8127dd1e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609492428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3609492428
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.648025742
Short name T427
Test name
Test status
Simulation time 790851121 ps
CPU time 8 seconds
Started Mar 31 12:46:27 PM PDT 24
Finished Mar 31 12:46:35 PM PDT 24
Peak memory 211628 kb
Host smart-677b4685-787f-4f25-9621-d944ec99853b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648025742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.648025742
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1426764250
Short name T172
Test name
Test status
Simulation time 701841265 ps
CPU time 15.34 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:40 PM PDT 24
Peak memory 213980 kb
Host smart-c0a4b726-3e70-4cd1-9413-aae69def3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426764250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1426764250
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2438795989
Short name T320
Test name
Test status
Simulation time 6610611556 ps
CPU time 40.42 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:29:25 PM PDT 24
Peak memory 214672 kb
Host smart-174a8c93-de01-48e4-87a8-529a372573cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438795989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2438795989
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3559144327
Short name T566
Test name
Test status
Simulation time 5917147614 ps
CPU time 54.28 seconds
Started Mar 31 12:46:25 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 217032 kb
Host smart-0755607c-c2d9-4b6f-8de5-0d7a40a900ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559144327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3559144327
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3466184639
Short name T653
Test name
Test status
Simulation time 114768387384 ps
CPU time 1035.63 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 01:03:39 PM PDT 24
Peak memory 232620 kb
Host smart-a9050684-4f27-4b93-ba02-274b155a615c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466184639 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3466184639
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1513930714
Short name T151
Test name
Test status
Simulation time 171422344 ps
CPU time 4.15 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:28:53 PM PDT 24
Peak memory 211700 kb
Host smart-29786caa-28cd-4b61-a6b4-7ce0523e5f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513930714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1513930714
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3465067715
Short name T414
Test name
Test status
Simulation time 1453316301 ps
CPU time 12.5 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:37 PM PDT 24
Peak memory 211776 kb
Host smart-aff3d508-5f5a-41bc-b590-60ed0c729eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465067715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3465067715
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3928369429
Short name T339
Test name
Test status
Simulation time 123523358455 ps
CPU time 304.48 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:33:54 PM PDT 24
Peak memory 235352 kb
Host smart-41931af0-10de-4871-97c6-2306b7741439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928369429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3928369429
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.646632784
Short name T638
Test name
Test status
Simulation time 136439994042 ps
CPU time 212.67 seconds
Started Mar 31 12:46:26 PM PDT 24
Finished Mar 31 12:49:59 PM PDT 24
Peak memory 219508 kb
Host smart-800c2956-e44d-4dcb-a911-bd226a715c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646632784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.646632784
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1026608279
Short name T639
Test name
Test status
Simulation time 25171805680 ps
CPU time 31.58 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:29:23 PM PDT 24
Peak memory 212712 kb
Host smart-737e06b2-5adc-40b7-ae7c-d7ed8d40d32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026608279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1026608279
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3871528796
Short name T332
Test name
Test status
Simulation time 2085474546 ps
CPU time 21.39 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:45 PM PDT 24
Peak memory 212348 kb
Host smart-36d1ff69-3607-4cc9-90c4-b5facaad0d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871528796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3871528796
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2716178269
Short name T316
Test name
Test status
Simulation time 349211259 ps
CPU time 6.33 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:28:58 PM PDT 24
Peak memory 211540 kb
Host smart-b37e78ac-af77-4630-a6ab-85c8f5458cc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716178269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2716178269
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.280136229
Short name T378
Test name
Test status
Simulation time 3447576343 ps
CPU time 10.49 seconds
Started Mar 31 12:46:25 PM PDT 24
Finished Mar 31 12:46:35 PM PDT 24
Peak memory 211696 kb
Host smart-af8576a6-d45e-484f-b7d4-3bd332677b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280136229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.280136229
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1848023438
Short name T661
Test name
Test status
Simulation time 18937343573 ps
CPU time 21.62 seconds
Started Mar 31 12:46:26 PM PDT 24
Finished Mar 31 12:46:48 PM PDT 24
Peak memory 214472 kb
Host smart-85fa16db-7be8-4044-93d4-b2c6df7d61bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848023438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1848023438
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4115635785
Short name T429
Test name
Test status
Simulation time 1376818357 ps
CPU time 12.44 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:29:01 PM PDT 24
Peak memory 213640 kb
Host smart-48abbc85-79d7-4bef-85da-85e61e4b37b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115635785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4115635785
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.141221963
Short name T534
Test name
Test status
Simulation time 1485087153 ps
CPU time 21.15 seconds
Started Mar 31 12:46:23 PM PDT 24
Finished Mar 31 12:46:45 PM PDT 24
Peak memory 219844 kb
Host smart-e54bce79-1733-4f5b-8f20-81beb741e798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141221963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.141221963
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3259687734
Short name T464
Test name
Test status
Simulation time 1431884621 ps
CPU time 13.53 seconds
Started Mar 31 12:29:11 PM PDT 24
Finished Mar 31 12:29:25 PM PDT 24
Peak memory 212124 kb
Host smart-ee037b47-a818-4f34-964d-5e559cedd05d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259687734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3259687734
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1895878324
Short name T204
Test name
Test status
Simulation time 1624291532 ps
CPU time 10.6 seconds
Started Mar 31 12:46:31 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 211596 kb
Host smart-2b8bfc9a-e8a4-4327-ba64-2629eb541325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895878324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1895878324
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.904524044
Short name T412
Test name
Test status
Simulation time 1808073169 ps
CPU time 14.66 seconds
Started Mar 31 12:29:06 PM PDT 24
Finished Mar 31 12:29:21 PM PDT 24
Peak memory 211592 kb
Host smart-c9ed658d-e314-4093-855b-f5f66f1eb9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904524044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.904524044
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3783202238
Short name T209
Test name
Test status
Simulation time 7315103044 ps
CPU time 106.29 seconds
Started Mar 31 12:46:26 PM PDT 24
Finished Mar 31 12:48:13 PM PDT 24
Peak memory 238476 kb
Host smart-052381c4-0580-4cdf-963b-9a72e41c0d6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783202238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3783202238
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.926901512
Short name T333
Test name
Test status
Simulation time 107132902969 ps
CPU time 466.34 seconds
Started Mar 31 12:29:43 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 219112 kb
Host smart-a1f00845-e84c-467b-838e-492567684f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926901512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.926901512
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.134493153
Short name T256
Test name
Test status
Simulation time 15670921804 ps
CPU time 30.97 seconds
Started Mar 31 12:46:27 PM PDT 24
Finished Mar 31 12:46:58 PM PDT 24
Peak memory 211856 kb
Host smart-073cabf8-721f-4505-a3c3-33c50b79c0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134493153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.134493153
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3994699051
Short name T505
Test name
Test status
Simulation time 2415505772 ps
CPU time 13.18 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:58 PM PDT 24
Peak memory 212164 kb
Host smart-5f7dc172-0a2f-48fa-a9b5-a1491fc37209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994699051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3994699051
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.21760675
Short name T435
Test name
Test status
Simulation time 1164393323 ps
CPU time 12.68 seconds
Started Mar 31 12:28:56 PM PDT 24
Finished Mar 31 12:29:09 PM PDT 24
Peak memory 211508 kb
Host smart-35cb1217-0d37-4aa8-909b-a483d2747792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21760675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.21760675
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3633895818
Short name T422
Test name
Test status
Simulation time 1712135157 ps
CPU time 14.06 seconds
Started Mar 31 12:46:27 PM PDT 24
Finished Mar 31 12:46:41 PM PDT 24
Peak memory 211684 kb
Host smart-f981390b-f434-4f9c-8512-b7e846728754
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633895818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3633895818
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.200876707
Short name T473
Test name
Test status
Simulation time 35858932040 ps
CPU time 31.93 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:22 PM PDT 24
Peak memory 219832 kb
Host smart-80910ba1-8728-48a7-ae06-c0519a1fccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200876707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.200876707
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2990925862
Short name T373
Test name
Test status
Simulation time 20270359737 ps
CPU time 23.59 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:48 PM PDT 24
Peak memory 214732 kb
Host smart-8b214f5a-547d-4194-9101-fcbb08f58a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990925862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2990925862
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1712129692
Short name T180
Test name
Test status
Simulation time 8011914019 ps
CPU time 26.84 seconds
Started Mar 31 12:28:59 PM PDT 24
Finished Mar 31 12:29:27 PM PDT 24
Peak memory 217072 kb
Host smart-507551ee-a88b-4935-ab2c-0b05ffeccc61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712129692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1712129692
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2827036398
Short name T157
Test name
Test status
Simulation time 837584937 ps
CPU time 21.95 seconds
Started Mar 31 12:46:24 PM PDT 24
Finished Mar 31 12:46:46 PM PDT 24
Peak memory 215456 kb
Host smart-ca256a7e-9f29-4d13-b845-e11fdefa01ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827036398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2827036398
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1785449564
Short name T69
Test name
Test status
Simulation time 320361550 ps
CPU time 4.22 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 211648 kb
Host smart-13157e92-32b9-48ae-8df3-2b2cc1e8eccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785449564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1785449564
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3851139686
Short name T104
Test name
Test status
Simulation time 1201864287 ps
CPU time 11.18 seconds
Started Mar 31 12:46:30 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 211764 kb
Host smart-e1b4e1f8-93c5-4956-8cb2-47b5b18dd880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851139686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3851139686
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.16348450
Short name T449
Test name
Test status
Simulation time 179126744832 ps
CPU time 371.82 seconds
Started Mar 31 12:29:36 PM PDT 24
Finished Mar 31 12:35:48 PM PDT 24
Peak memory 234252 kb
Host smart-91a97e44-2630-42cc-84a9-a5a14b709d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_co
rrupt_sig_fatal_chk.16348450
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2051954463
Short name T341
Test name
Test status
Simulation time 39799218895 ps
CPU time 395.36 seconds
Started Mar 31 12:46:32 PM PDT 24
Finished Mar 31 12:53:08 PM PDT 24
Peak memory 231352 kb
Host smart-3157c82a-3be6-4c3c-9de9-06558e03aa19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051954463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2051954463
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2063559734
Short name T169
Test name
Test status
Simulation time 6310752154 ps
CPU time 28.32 seconds
Started Mar 31 12:46:31 PM PDT 24
Finished Mar 31 12:47:00 PM PDT 24
Peak memory 213080 kb
Host smart-593859e1-b0f2-4053-8f29-b4104d80bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063559734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2063559734
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2107419596
Short name T251
Test name
Test status
Simulation time 4403446810 ps
CPU time 33.09 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:29:21 PM PDT 24
Peak memory 212488 kb
Host smart-3da6bd5f-93bd-41fd-82b4-a14bf9b6d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107419596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2107419596
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2327221295
Short name T108
Test name
Test status
Simulation time 1961295109 ps
CPU time 16.31 seconds
Started Mar 31 12:29:10 PM PDT 24
Finished Mar 31 12:29:26 PM PDT 24
Peak memory 211528 kb
Host smart-3703c8a8-aae1-42aa-b998-2596b0c55d8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327221295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2327221295
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2683602274
Short name T323
Test name
Test status
Simulation time 1024629887 ps
CPU time 7.02 seconds
Started Mar 31 12:46:30 PM PDT 24
Finished Mar 31 12:46:38 PM PDT 24
Peak memory 211644 kb
Host smart-5adefe6f-5d51-433b-9725-355b294e46de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683602274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2683602274
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3122112095
Short name T466
Test name
Test status
Simulation time 447733167 ps
CPU time 11.17 seconds
Started Mar 31 12:46:31 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 219820 kb
Host smart-b074c13e-e0a9-4587-94c5-a2c10cf3999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122112095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3122112095
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3664887153
Short name T138
Test name
Test status
Simulation time 364207285 ps
CPU time 9.39 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:28:52 PM PDT 24
Peak memory 214328 kb
Host smart-f7dd03e9-2832-44cb-981c-444fa52874bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664887153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3664887153
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2799898779
Short name T198
Test name
Test status
Simulation time 28418321801 ps
CPU time 37.23 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:29:23 PM PDT 24
Peak memory 215020 kb
Host smart-22520166-e1f3-42d1-90b5-4d2aa58e93fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799898779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2799898779
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.855168055
Short name T532
Test name
Test status
Simulation time 424715907 ps
CPU time 12.83 seconds
Started Mar 31 12:46:30 PM PDT 24
Finished Mar 31 12:46:43 PM PDT 24
Peak memory 219688 kb
Host smart-489d6d68-649b-4133-b41f-612e01d9d97c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855168055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.855168055
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.852920485
Short name T197
Test name
Test status
Simulation time 12520239108 ps
CPU time 14.83 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 211808 kb
Host smart-e7c3b574-b908-4e96-9187-244b19308ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852920485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.852920485
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.9263844
Short name T287
Test name
Test status
Simulation time 3696098519 ps
CPU time 14.61 seconds
Started Mar 31 12:46:42 PM PDT 24
Finished Mar 31 12:46:57 PM PDT 24
Peak memory 211856 kb
Host smart-97f34bab-ca70-4740-bcc1-1bc6f7d03e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9263844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.9263844
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.116413944
Short name T318
Test name
Test status
Simulation time 80186238528 ps
CPU time 268.51 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:51:09 PM PDT 24
Peak memory 238480 kb
Host smart-a9df8502-4a92-4592-9ba1-616afc05ef15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116413944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.116413944
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4244634394
Short name T337
Test name
Test status
Simulation time 24814302457 ps
CPU time 188.82 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 12:31:55 PM PDT 24
Peak memory 231208 kb
Host smart-9128fc67-91db-4ab7-a8d5-bcccce86a54f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244634394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4244634394
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4263301907
Short name T262
Test name
Test status
Simulation time 2647224889 ps
CPU time 23.28 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:29:09 PM PDT 24
Peak memory 212508 kb
Host smart-dc0e6f1f-c331-434c-b7fd-c68a28bdfc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263301907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4263301907
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.641715492
Short name T189
Test name
Test status
Simulation time 15500289054 ps
CPU time 18.73 seconds
Started Mar 31 12:46:40 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 212588 kb
Host smart-14ae3c27-175e-4748-b3d6-275979782840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641715492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.641715492
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2204498289
Short name T74
Test name
Test status
Simulation time 5919013983 ps
CPU time 17.36 seconds
Started Mar 31 12:29:11 PM PDT 24
Finished Mar 31 12:29:28 PM PDT 24
Peak memory 211660 kb
Host smart-1cf1a67c-2b8e-4f51-b826-4e58ef333a1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204498289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2204498289
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3738694636
Short name T563
Test name
Test status
Simulation time 96926670 ps
CPU time 5.61 seconds
Started Mar 31 12:46:31 PM PDT 24
Finished Mar 31 12:46:37 PM PDT 24
Peak memory 211684 kb
Host smart-7d7f8c76-1515-4864-8c44-99ba22977c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738694636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3738694636
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1316630565
Short name T583
Test name
Test status
Simulation time 1399362029 ps
CPU time 9.9 seconds
Started Mar 31 12:46:29 PM PDT 24
Finished Mar 31 12:46:39 PM PDT 24
Peak memory 219748 kb
Host smart-328318d1-dd39-4403-a66a-bb869fbe8ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316630565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1316630565
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1572088942
Short name T595
Test name
Test status
Simulation time 2385162006 ps
CPU time 23.71 seconds
Started Mar 31 12:28:59 PM PDT 24
Finished Mar 31 12:29:24 PM PDT 24
Peak memory 219816 kb
Host smart-9976c280-7c2b-45e3-91eb-b3939e1dec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572088942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1572088942
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.219666135
Short name T452
Test name
Test status
Simulation time 160496944035 ps
CPU time 132.8 seconds
Started Mar 31 12:28:58 PM PDT 24
Finished Mar 31 12:31:12 PM PDT 24
Peak memory 219796 kb
Host smart-dad30aa9-0959-42ce-a49b-a77ddfa85819
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219666135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.219666135
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4243298841
Short name T170
Test name
Test status
Simulation time 199109479 ps
CPU time 10.41 seconds
Started Mar 31 12:46:31 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 219768 kb
Host smart-48f2421b-0749-4177-b58b-e8f4fd907831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243298841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4243298841
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1003339233
Short name T327
Test name
Test status
Simulation time 21416729209 ps
CPU time 16.6 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:46:58 PM PDT 24
Peak memory 211884 kb
Host smart-befac2f3-676e-40ca-be32-62cf54d2504a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003339233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1003339233
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3802491946
Short name T522
Test name
Test status
Simulation time 794798714 ps
CPU time 5.84 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:51 PM PDT 24
Peak memory 211668 kb
Host smart-b8df077b-4562-4fa1-bfd2-ab59a34af259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802491946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3802491946
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2422121528
Short name T215
Test name
Test status
Simulation time 73025481004 ps
CPU time 224.08 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:50:25 PM PDT 24
Peak memory 238268 kb
Host smart-a97be759-1603-47c2-a1fc-81b46b572c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422121528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2422121528
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2653779646
Short name T409
Test name
Test status
Simulation time 32054268555 ps
CPU time 126.27 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:30:51 PM PDT 24
Peak memory 241492 kb
Host smart-b58b503b-55b6-4759-baa6-808868265a60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653779646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2653779646
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1465263579
Short name T181
Test name
Test status
Simulation time 694725312 ps
CPU time 9.19 seconds
Started Mar 31 12:46:40 PM PDT 24
Finished Mar 31 12:46:50 PM PDT 24
Peak memory 212340 kb
Host smart-ee3cfac8-0cb1-41a7-a325-dd874333b479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465263579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1465263579
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3280199973
Short name T271
Test name
Test status
Simulation time 1803808824 ps
CPU time 20.38 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 212316 kb
Host smart-5ccdb54e-6eb8-4f26-817a-89261d1cfaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280199973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3280199973
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1907659742
Short name T562
Test name
Test status
Simulation time 3475223244 ps
CPU time 14.97 seconds
Started Mar 31 12:29:41 PM PDT 24
Finished Mar 31 12:29:56 PM PDT 24
Peak memory 211708 kb
Host smart-74268646-f85d-4217-997c-fbffd80e6af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907659742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1907659742
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4232491060
Short name T537
Test name
Test status
Simulation time 1738042394 ps
CPU time 10.11 seconds
Started Mar 31 12:46:40 PM PDT 24
Finished Mar 31 12:46:51 PM PDT 24
Peak memory 211628 kb
Host smart-8871da5a-442f-4615-9a2f-fee09f960a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232491060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4232491060
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2491276864
Short name T137
Test name
Test status
Simulation time 715281480 ps
CPU time 9.81 seconds
Started Mar 31 12:28:38 PM PDT 24
Finished Mar 31 12:28:47 PM PDT 24
Peak memory 219728 kb
Host smart-a6ae601a-ab87-4efc-8351-e0d8738ffbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491276864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2491276864
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.787591639
Short name T420
Test name
Test status
Simulation time 929402461 ps
CPU time 17.26 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:46:58 PM PDT 24
Peak memory 219736 kb
Host smart-4761cb8a-c963-48e4-9d57-059a3845b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787591639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.787591639
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3545244777
Short name T579
Test name
Test status
Simulation time 2544694951 ps
CPU time 34.09 seconds
Started Mar 31 12:29:10 PM PDT 24
Finished Mar 31 12:29:45 PM PDT 24
Peak memory 213224 kb
Host smart-6a22b44c-54f8-4112-95c3-c7536d5bee1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545244777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3545244777
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1053862721
Short name T330
Test name
Test status
Simulation time 220859734152 ps
CPU time 2091.42 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 01:03:46 PM PDT 24
Peak memory 236364 kb
Host smart-3e9f353e-32c1-4400-863e-d89bead10304
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053862721 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1053862721
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1493795153
Short name T229
Test name
Test status
Simulation time 173961997 ps
CPU time 5.43 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:46:47 PM PDT 24
Peak memory 211732 kb
Host smart-50ab6e38-4229-454e-8ba2-6e8a27f279fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493795153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1493795153
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.772186573
Short name T585
Test name
Test status
Simulation time 168695282 ps
CPU time 4.19 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:49 PM PDT 24
Peak memory 211668 kb
Host smart-3c49759c-bc70-465d-b91b-c3675a845aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772186573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.772186573
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1946198941
Short name T675
Test name
Test status
Simulation time 46562560808 ps
CPU time 451.82 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:54:13 PM PDT 24
Peak memory 237380 kb
Host smart-d33dcf9f-c46b-4441-8f61-2b3098f454c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946198941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1946198941
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2845609845
Short name T679
Test name
Test status
Simulation time 8027619989 ps
CPU time 90.75 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:30:15 PM PDT 24
Peak memory 233504 kb
Host smart-44b075e3-92d0-4094-8f93-b939e6ebe220
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845609845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2845609845
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2678701725
Short name T403
Test name
Test status
Simulation time 1571045161 ps
CPU time 19.36 seconds
Started Mar 31 12:46:40 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 211756 kb
Host smart-87c57ec4-c1f1-4775-9bf5-e1fd3115ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678701725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2678701725
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3607364679
Short name T570
Test name
Test status
Simulation time 695305079 ps
CPU time 13.68 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:03 PM PDT 24
Peak memory 211964 kb
Host smart-052aef10-6012-44cf-80f3-98c60fad38de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607364679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3607364679
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1858163624
Short name T46
Test name
Test status
Simulation time 11811644002 ps
CPU time 15.89 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:46:57 PM PDT 24
Peak memory 211668 kb
Host smart-dab0b81f-4151-484a-a04d-7ebd22bc8d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858163624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1858163624
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3456151249
Short name T105
Test name
Test status
Simulation time 2145457515 ps
CPU time 14.3 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:02 PM PDT 24
Peak memory 211580 kb
Host smart-f1995925-26a7-48f6-8e4c-99bfbfd2031d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456151249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3456151249
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2443950255
Short name T286
Test name
Test status
Simulation time 1733881396 ps
CPU time 14.76 seconds
Started Mar 31 12:46:39 PM PDT 24
Finished Mar 31 12:46:54 PM PDT 24
Peak memory 219848 kb
Host smart-3cc60d27-843f-4369-a293-cccf63e45a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443950255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2443950255
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3496111055
Short name T612
Test name
Test status
Simulation time 6119615592 ps
CPU time 29.15 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:19 PM PDT 24
Peak memory 214172 kb
Host smart-c482db2d-a189-41cd-ac1b-1d63c329c0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496111055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3496111055
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2688608994
Short name T660
Test name
Test status
Simulation time 132859260 ps
CPU time 6.81 seconds
Started Mar 31 12:46:39 PM PDT 24
Finished Mar 31 12:46:46 PM PDT 24
Peak memory 211648 kb
Host smart-8eca4a63-0df9-483c-8fa0-50be2f289a22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688608994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2688608994
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3280421112
Short name T664
Test name
Test status
Simulation time 1975144342 ps
CPU time 19.64 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:29:07 PM PDT 24
Peak memory 211504 kb
Host smart-c9e18b5c-c846-4d35-a3e7-5daf0323423c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280421112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3280421112
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3974075124
Short name T440
Test name
Test status
Simulation time 95041773390 ps
CPU time 852.47 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:43:03 PM PDT 24
Peak memory 236308 kb
Host smart-694fb1f2-a533-464d-948f-521ed59735bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974075124 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3974075124
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.914769835
Short name T490
Test name
Test status
Simulation time 31298916998 ps
CPU time 4217 seconds
Started Mar 31 12:46:40 PM PDT 24
Finished Mar 31 01:56:58 PM PDT 24
Peak memory 235404 kb
Host smart-408073f7-4403-4237-9b93-104c6ce48895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914769835 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.914769835
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1004761392
Short name T296
Test name
Test status
Simulation time 3169873613 ps
CPU time 13.82 seconds
Started Mar 31 12:45:36 PM PDT 24
Finished Mar 31 12:45:50 PM PDT 24
Peak memory 211900 kb
Host smart-ae36b4b2-5f46-4b60-802f-ff00cb864f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004761392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1004761392
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3320000444
Short name T551
Test name
Test status
Simulation time 1102117410 ps
CPU time 9.48 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:43 PM PDT 24
Peak memory 211636 kb
Host smart-f14d81cb-5d51-4eb2-a44f-5455a8ed3d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320000444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3320000444
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1020733276
Short name T517
Test name
Test status
Simulation time 69467652163 ps
CPU time 335.79 seconds
Started Mar 31 12:45:35 PM PDT 24
Finished Mar 31 12:51:11 PM PDT 24
Peak memory 238316 kb
Host smart-5db4cd86-7e95-477c-8422-422e68587402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020733276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1020733276
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1632144757
Short name T309
Test name
Test status
Simulation time 38830442932 ps
CPU time 234.15 seconds
Started Mar 31 12:28:21 PM PDT 24
Finished Mar 31 12:32:15 PM PDT 24
Peak memory 237524 kb
Host smart-2c08bc7c-671c-4ad9-aa26-08fd21f23ea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632144757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1632144757
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2426265452
Short name T394
Test name
Test status
Simulation time 229721861 ps
CPU time 9.18 seconds
Started Mar 31 12:45:37 PM PDT 24
Finished Mar 31 12:45:47 PM PDT 24
Peak memory 212200 kb
Host smart-e40c2c33-3c2a-4be2-af78-806cdf590b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426265452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2426265452
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2539980346
Short name T310
Test name
Test status
Simulation time 364099880 ps
CPU time 9.3 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:49 PM PDT 24
Peak memory 211988 kb
Host smart-92b3ec93-d72a-424f-ad68-5a5ebf6919be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539980346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2539980346
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1507205076
Short name T567
Test name
Test status
Simulation time 4159338303 ps
CPU time 11.36 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:38 PM PDT 24
Peak memory 211676 kb
Host smart-fa1ec420-f18d-4c8e-ae9e-569e80a5aee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507205076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1507205076
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2043204958
Short name T652
Test name
Test status
Simulation time 97029787 ps
CPU time 5.36 seconds
Started Mar 31 12:45:34 PM PDT 24
Finished Mar 31 12:45:39 PM PDT 24
Peak memory 211604 kb
Host smart-5b25bfd4-2f60-43c4-a5ea-12da1f57513c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043204958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2043204958
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3068039720
Short name T31
Test name
Test status
Simulation time 29856455937 ps
CPU time 106.73 seconds
Started Mar 31 12:45:32 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 234600 kb
Host smart-9275cebb-2f68-4210-8096-2905a1f1c122
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068039720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3068039720
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1636967015
Short name T461
Test name
Test status
Simulation time 370042677 ps
CPU time 9.99 seconds
Started Mar 31 12:45:34 PM PDT 24
Finished Mar 31 12:45:44 PM PDT 24
Peak memory 219668 kb
Host smart-0755eaa2-cfca-415d-8f26-b940c2d6d073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636967015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1636967015
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2540239310
Short name T372
Test name
Test status
Simulation time 2638430505 ps
CPU time 31.92 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:28:58 PM PDT 24
Peak memory 214008 kb
Host smart-57fcba3f-3261-4e93-83c2-8eaf07797bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540239310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2540239310
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2959473586
Short name T45
Test name
Test status
Simulation time 2138585177 ps
CPU time 32.9 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:29:03 PM PDT 24
Peak memory 219692 kb
Host smart-022d6ecc-abb5-457a-a445-d3502ce19c99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959473586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2959473586
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.519923544
Short name T667
Test name
Test status
Simulation time 5635702307 ps
CPU time 18.15 seconds
Started Mar 31 12:45:35 PM PDT 24
Finished Mar 31 12:45:53 PM PDT 24
Peak memory 211736 kb
Host smart-81e0a859-1eda-4b9c-8f26-6c695faa06e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519923544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.519923544
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1701729483
Short name T219
Test name
Test status
Simulation time 883524027 ps
CPU time 9.39 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:55 PM PDT 24
Peak memory 211668 kb
Host smart-836585a1-8447-4dbe-9251-0afdbc9c65e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701729483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1701729483
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.620594880
Short name T529
Test name
Test status
Simulation time 171998250 ps
CPU time 4.13 seconds
Started Mar 31 12:46:41 PM PDT 24
Finished Mar 31 12:46:45 PM PDT 24
Peak memory 211676 kb
Host smart-5203525b-c56b-46b0-a110-67ed1dc4c3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620594880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.620594880
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.165750249
Short name T676
Test name
Test status
Simulation time 7410203383 ps
CPU time 162.56 seconds
Started Mar 31 12:46:43 PM PDT 24
Finished Mar 31 12:49:25 PM PDT 24
Peak memory 234524 kb
Host smart-31d90aba-e670-4dfe-b862-3744ab290567
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165750249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.165750249
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3625663948
Short name T18
Test name
Test status
Simulation time 124916770817 ps
CPU time 355.02 seconds
Started Mar 31 12:29:17 PM PDT 24
Finished Mar 31 12:35:12 PM PDT 24
Peak memory 233144 kb
Host smart-205ed7c3-2646-42c1-8fca-defe7be5561a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625663948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3625663948
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2382400417
Short name T182
Test name
Test status
Simulation time 15722150929 ps
CPU time 31.86 seconds
Started Mar 31 12:28:52 PM PDT 24
Finished Mar 31 12:29:24 PM PDT 24
Peak memory 212704 kb
Host smart-a424e118-0758-47ed-8e99-7d5aed31b2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382400417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2382400417
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2874959357
Short name T481
Test name
Test status
Simulation time 4119338404 ps
CPU time 33 seconds
Started Mar 31 12:46:42 PM PDT 24
Finished Mar 31 12:47:15 PM PDT 24
Peak memory 212404 kb
Host smart-f0912966-19cb-4c45-84bf-e4f535d5c48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874959357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2874959357
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1314659490
Short name T195
Test name
Test status
Simulation time 5130776217 ps
CPU time 17.23 seconds
Started Mar 31 12:46:40 PM PDT 24
Finished Mar 31 12:46:58 PM PDT 24
Peak memory 211788 kb
Host smart-fdb86b64-f658-4a61-acf1-ac921a4d9387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314659490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1314659490
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3190017244
Short name T605
Test name
Test status
Simulation time 1076046444 ps
CPU time 11.4 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 12:29:06 PM PDT 24
Peak memory 211592 kb
Host smart-9efd9394-4952-47b6-93ef-3633b2e93cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190017244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3190017244
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1716381199
Short name T577
Test name
Test status
Simulation time 4572432654 ps
CPU time 23.88 seconds
Started Mar 31 12:46:40 PM PDT 24
Finished Mar 31 12:47:04 PM PDT 24
Peak memory 219952 kb
Host smart-bf2d8bcf-9fc6-44aa-9d5e-4205c3a15aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716381199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1716381199
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3796340933
Short name T283
Test name
Test status
Simulation time 6235467050 ps
CPU time 20.41 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:29:06 PM PDT 24
Peak memory 219752 kb
Host smart-e7f7f19f-bf7e-4a34-8959-9f124d9817c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796340933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3796340933
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2475009393
Short name T191
Test name
Test status
Simulation time 17372944394 ps
CPU time 46.56 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:33 PM PDT 24
Peak memory 219848 kb
Host smart-bbf751e1-6776-45c2-93f3-96e5853c4f76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475009393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2475009393
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.439048453
Short name T384
Test name
Test status
Simulation time 30475654050 ps
CPU time 119.39 seconds
Started Mar 31 12:46:39 PM PDT 24
Finished Mar 31 12:48:39 PM PDT 24
Peak memory 219856 kb
Host smart-30534b2f-c167-43e3-bd62-38e8dc2a36ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439048453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.439048453
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.96293572
Short name T57
Test name
Test status
Simulation time 139711127487 ps
CPU time 2656.59 seconds
Started Mar 31 12:28:46 PM PDT 24
Finished Mar 31 01:13:03 PM PDT 24
Peak memory 245932 kb
Host smart-aeb7a5af-4644-47ae-971f-0cddc02a6e5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96293572 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.96293572
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.19785716
Short name T424
Test name
Test status
Simulation time 838532101 ps
CPU time 9.26 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:05 PM PDT 24
Peak memory 211672 kb
Host smart-cee29b48-ad20-40ec-909a-81ba16244e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19785716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.19785716
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3082860049
Short name T222
Test name
Test status
Simulation time 7518371109 ps
CPU time 14.31 seconds
Started Mar 31 12:46:46 PM PDT 24
Finished Mar 31 12:47:01 PM PDT 24
Peak memory 211772 kb
Host smart-87b4db08-0a61-4797-9918-dc93c0ed5d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082860049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3082860049
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3102673561
Short name T369
Test name
Test status
Simulation time 6709858280 ps
CPU time 119.27 seconds
Started Mar 31 12:46:45 PM PDT 24
Finished Mar 31 12:48:44 PM PDT 24
Peak memory 231296 kb
Host smart-f76ddb8e-21e1-4c8d-aaa1-b6d439fa2b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102673561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3102673561
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3903889504
Short name T450
Test name
Test status
Simulation time 195613673750 ps
CPU time 230.79 seconds
Started Mar 31 12:28:52 PM PDT 24
Finished Mar 31 12:32:43 PM PDT 24
Peak memory 232232 kb
Host smart-fbe9590c-b777-4432-8d06-5450a8833b08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903889504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3903889504
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1134590860
Short name T416
Test name
Test status
Simulation time 4066109332 ps
CPU time 30.65 seconds
Started Mar 31 12:29:05 PM PDT 24
Finished Mar 31 12:29:36 PM PDT 24
Peak memory 212780 kb
Host smart-a1a99b21-39bd-4f18-b664-3f20e910bff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134590860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1134590860
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3413749399
Short name T553
Test name
Test status
Simulation time 14527091724 ps
CPU time 33.33 seconds
Started Mar 31 12:46:45 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 212692 kb
Host smart-43ba0772-7d97-42f9-9e59-838db6381de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413749399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3413749399
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1810016617
Short name T604
Test name
Test status
Simulation time 95986839 ps
CPU time 5.53 seconds
Started Mar 31 12:46:45 PM PDT 24
Finished Mar 31 12:46:52 PM PDT 24
Peak memory 211612 kb
Host smart-b4c33d1d-381a-4538-b8a8-6264b02dffc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810016617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1810016617
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.709784756
Short name T533
Test name
Test status
Simulation time 428605998 ps
CPU time 5.45 seconds
Started Mar 31 12:28:57 PM PDT 24
Finished Mar 31 12:29:03 PM PDT 24
Peak memory 211588 kb
Host smart-fd929554-3317-47f3-9749-bce08cbd4985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709784756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.709784756
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3742823796
Short name T388
Test name
Test status
Simulation time 2148278589 ps
CPU time 22.78 seconds
Started Mar 31 12:46:45 PM PDT 24
Finished Mar 31 12:47:08 PM PDT 24
Peak memory 214384 kb
Host smart-17cd1b58-f6a1-4814-b878-bb5ab02a1c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742823796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3742823796
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.720584463
Short name T292
Test name
Test status
Simulation time 790593172 ps
CPU time 9.46 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 219556 kb
Host smart-2158591e-b705-4e06-9a59-7db8c9101f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720584463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.720584463
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.336890098
Short name T542
Test name
Test status
Simulation time 17870476906 ps
CPU time 53.44 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:43 PM PDT 24
Peak memory 219412 kb
Host smart-b762452a-75f4-456c-b875-6612256dda88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336890098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.336890098
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.391352522
Short name T360
Test name
Test status
Simulation time 46420439692 ps
CPU time 99.43 seconds
Started Mar 31 12:46:46 PM PDT 24
Finished Mar 31 12:48:26 PM PDT 24
Peak memory 219860 kb
Host smart-311dea2d-d459-475f-b959-12116058636d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391352522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.391352522
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2159300053
Short name T55
Test name
Test status
Simulation time 25091125055 ps
CPU time 1685.62 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:58:00 PM PDT 24
Peak memory 225968 kb
Host smart-fac945e1-026e-4b74-9215-9fc9dde4e123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159300053 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2159300053
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2165546612
Short name T463
Test name
Test status
Simulation time 122753306224 ps
CPU time 2479.46 seconds
Started Mar 31 12:46:44 PM PDT 24
Finished Mar 31 01:28:05 PM PDT 24
Peak memory 244660 kb
Host smart-180ac24a-4c5c-4698-b635-6fda1ffa7e3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165546612 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2165546612
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1287068239
Short name T253
Test name
Test status
Simulation time 171579499 ps
CPU time 4.29 seconds
Started Mar 31 12:46:46 PM PDT 24
Finished Mar 31 12:46:51 PM PDT 24
Peak memory 211652 kb
Host smart-b96d1b5d-b6af-41d4-9451-0b11cbbdce93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287068239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1287068239
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2453075020
Short name T371
Test name
Test status
Simulation time 498884556 ps
CPU time 7.41 seconds
Started Mar 31 12:28:57 PM PDT 24
Finished Mar 31 12:29:05 PM PDT 24
Peak memory 211624 kb
Host smart-ae49d47f-fc6e-4cc9-99ed-1c256bd383e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453075020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2453075020
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.395882975
Short name T109
Test name
Test status
Simulation time 202423239014 ps
CPU time 448.6 seconds
Started Mar 31 12:46:45 PM PDT 24
Finished Mar 31 12:54:14 PM PDT 24
Peak memory 220212 kb
Host smart-cb49e22a-2290-421f-baa6-0d6669e7f086
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395882975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.395882975
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.746383076
Short name T418
Test name
Test status
Simulation time 9689531381 ps
CPU time 103.12 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:31:41 PM PDT 24
Peak memory 212708 kb
Host smart-2391f4fe-271e-409c-acc9-5fa5113b4667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746383076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.746383076
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1670784804
Short name T299
Test name
Test status
Simulation time 3065520201 ps
CPU time 18.08 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:30:12 PM PDT 24
Peak memory 212016 kb
Host smart-18d1b163-1f27-4fbc-afd4-0fbbc7c4920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670784804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1670784804
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.275164978
Short name T682
Test name
Test status
Simulation time 13162403200 ps
CPU time 27.88 seconds
Started Mar 31 12:46:47 PM PDT 24
Finished Mar 31 12:47:15 PM PDT 24
Peak memory 213888 kb
Host smart-bc92b7e0-a3a8-49d9-8b28-8948f0eeb4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275164978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.275164978
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2676288284
Short name T607
Test name
Test status
Simulation time 7544296925 ps
CPU time 17.5 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:05 PM PDT 24
Peak memory 211660 kb
Host smart-5e07a404-7343-4440-bbc7-19dd59d15fb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676288284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2676288284
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4107083581
Short name T437
Test name
Test status
Simulation time 8595120499 ps
CPU time 21.42 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:17 PM PDT 24
Peak memory 219572 kb
Host smart-38fe71dc-2c93-40f5-bc14-bdb5a397a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107083581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4107083581
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.815283467
Short name T153
Test name
Test status
Simulation time 716525109 ps
CPU time 10.04 seconds
Started Mar 31 12:46:44 PM PDT 24
Finished Mar 31 12:46:54 PM PDT 24
Peak memory 213552 kb
Host smart-339ddfc0-3741-4b4a-913e-9d9baca31d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815283467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.815283467
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1184388852
Short name T628
Test name
Test status
Simulation time 1834357244 ps
CPU time 22.34 seconds
Started Mar 31 12:28:55 PM PDT 24
Finished Mar 31 12:29:17 PM PDT 24
Peak memory 219724 kb
Host smart-5d27ae23-63c5-4700-bf51-c7d91e26e63c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184388852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1184388852
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2634278281
Short name T531
Test name
Test status
Simulation time 9447757466 ps
CPU time 82.55 seconds
Started Mar 31 12:46:46 PM PDT 24
Finished Mar 31 12:48:09 PM PDT 24
Peak memory 218588 kb
Host smart-f7b44049-6083-4c9e-bedc-e6c157ba865b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634278281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2634278281
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3751527029
Short name T358
Test name
Test status
Simulation time 14866447040 ps
CPU time 539.27 seconds
Started Mar 31 12:29:07 PM PDT 24
Finished Mar 31 12:38:07 PM PDT 24
Peak memory 228152 kb
Host smart-b00f20c7-23fd-4536-b567-bd6e21aa0ac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751527029 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3751527029
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.416906684
Short name T272
Test name
Test status
Simulation time 200312065865 ps
CPU time 3916.56 seconds
Started Mar 31 12:46:46 PM PDT 24
Finished Mar 31 01:52:04 PM PDT 24
Peak memory 248712 kb
Host smart-a1b805f1-a0b4-43a4-b0e0-13a2de08dcd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416906684 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.416906684
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3334771399
Short name T627
Test name
Test status
Simulation time 1678799944 ps
CPU time 14.41 seconds
Started Mar 31 12:46:52 PM PDT 24
Finished Mar 31 12:47:06 PM PDT 24
Peak memory 211776 kb
Host smart-2d2171d9-78a4-4da0-8c84-4735db47ebba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334771399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3334771399
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.497769666
Short name T248
Test name
Test status
Simulation time 827814361 ps
CPU time 4.27 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:28:52 PM PDT 24
Peak memory 211656 kb
Host smart-80d3e5cb-e6cc-409b-ac04-a92556e55c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497769666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.497769666
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1279151334
Short name T528
Test name
Test status
Simulation time 5159409438 ps
CPU time 111.28 seconds
Started Mar 31 12:46:46 PM PDT 24
Finished Mar 31 12:48:38 PM PDT 24
Peak memory 238396 kb
Host smart-301b78d3-e743-4217-8479-df1aa8b10575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279151334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1279151334
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2257959341
Short name T500
Test name
Test status
Simulation time 10217217105 ps
CPU time 233.59 seconds
Started Mar 31 12:29:09 PM PDT 24
Finished Mar 31 12:33:02 PM PDT 24
Peak memory 228676 kb
Host smart-6b38c095-e1a1-40ef-977d-9b04b6eab281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257959341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2257959341
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1186676732
Short name T396
Test name
Test status
Simulation time 4973308063 ps
CPU time 25.09 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:29:16 PM PDT 24
Peak memory 212600 kb
Host smart-b8e74c7f-b3a1-4bf5-9c4d-5c2c80e9848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186676732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1186676732
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3113557118
Short name T214
Test name
Test status
Simulation time 1394188474 ps
CPU time 17.92 seconds
Started Mar 31 12:46:44 PM PDT 24
Finished Mar 31 12:47:02 PM PDT 24
Peak memory 212376 kb
Host smart-980edf7f-f63e-47e5-8eab-92cd4310565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113557118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3113557118
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1857949221
Short name T213
Test name
Test status
Simulation time 1218272373 ps
CPU time 12.41 seconds
Started Mar 31 12:46:46 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 211672 kb
Host smart-a04f4ff8-1e42-4517-8c68-b61ad4d3a71e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857949221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1857949221
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2057157897
Short name T554
Test name
Test status
Simulation time 102420919 ps
CPU time 5.5 seconds
Started Mar 31 12:28:56 PM PDT 24
Finished Mar 31 12:29:02 PM PDT 24
Peak memory 211556 kb
Host smart-9b9560be-2bc8-421f-8555-353e15dc381a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057157897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2057157897
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2691319719
Short name T85
Test name
Test status
Simulation time 843015336 ps
CPU time 16.46 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 12:29:17 PM PDT 24
Peak memory 219820 kb
Host smart-64b13f8f-899a-4c92-a594-fd2888fb8303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691319719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2691319719
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.4156647327
Short name T188
Test name
Test status
Simulation time 510031661 ps
CPU time 14.52 seconds
Started Mar 31 12:46:45 PM PDT 24
Finished Mar 31 12:47:00 PM PDT 24
Peak memory 213840 kb
Host smart-1173144a-b9b5-4d08-85ff-e99f8257e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156647327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4156647327
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1562363376
Short name T281
Test name
Test status
Simulation time 5284978057 ps
CPU time 54.1 seconds
Started Mar 31 12:46:45 PM PDT 24
Finished Mar 31 12:47:40 PM PDT 24
Peak memory 219960 kb
Host smart-9a84adf2-b2a5-4049-9a1e-a1384e062ae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562363376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1562363376
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2001811358
Short name T259
Test name
Test status
Simulation time 5660052936 ps
CPU time 13.58 seconds
Started Mar 31 12:28:59 PM PDT 24
Finished Mar 31 12:29:14 PM PDT 24
Peak memory 212712 kb
Host smart-fa614b1d-3865-4366-856c-08b74a966a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001811358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2001811358
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3306533874
Short name T555
Test name
Test status
Simulation time 101495454170 ps
CPU time 3980.45 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 01:35:08 PM PDT 24
Peak memory 246688 kb
Host smart-aab6ccb6-ef18-4e8c-b38b-651096c20d32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306533874 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3306533874
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3032704209
Short name T167
Test name
Test status
Simulation time 361647008 ps
CPU time 3.91 seconds
Started Mar 31 12:28:58 PM PDT 24
Finished Mar 31 12:29:03 PM PDT 24
Peak memory 211504 kb
Host smart-5d46f90d-f884-4f62-8ca3-edfdc8219948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032704209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3032704209
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3390534033
Short name T268
Test name
Test status
Simulation time 215249278 ps
CPU time 4.15 seconds
Started Mar 31 12:46:51 PM PDT 24
Finished Mar 31 12:46:55 PM PDT 24
Peak memory 211676 kb
Host smart-1f76e1f1-17fd-4f7d-957b-4de76eaeef3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390534033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3390534033
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1106369850
Short name T4
Test name
Test status
Simulation time 7271453577 ps
CPU time 106.54 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:31:43 PM PDT 24
Peak memory 221080 kb
Host smart-c2d4bd4c-a429-4fa0-9568-474baba1f2ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106369850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1106369850
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3142644961
Short name T353
Test name
Test status
Simulation time 4559377833 ps
CPU time 149.37 seconds
Started Mar 31 12:46:52 PM PDT 24
Finished Mar 31 12:49:21 PM PDT 24
Peak memory 237432 kb
Host smart-f8ea01c9-e23c-45dc-b43f-8914ef72da66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142644961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3142644961
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.787435197
Short name T619
Test name
Test status
Simulation time 14374397639 ps
CPU time 34.58 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:22 PM PDT 24
Peak memory 212640 kb
Host smart-f39af645-b2de-40a4-8f9c-ff9fe72f9051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787435197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.787435197
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.999056665
Short name T524
Test name
Test status
Simulation time 1376435078 ps
CPU time 17.81 seconds
Started Mar 31 12:46:51 PM PDT 24
Finished Mar 31 12:47:09 PM PDT 24
Peak memory 212432 kb
Host smart-83c1a5dd-c584-4a9d-b520-ca177e5e13a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999056665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.999056665
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2725884496
Short name T564
Test name
Test status
Simulation time 1795229659 ps
CPU time 15.14 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 211584 kb
Host smart-38e66495-e468-45fc-8884-d895440196d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725884496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2725884496
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4111630671
Short name T246
Test name
Test status
Simulation time 105627311 ps
CPU time 5.66 seconds
Started Mar 31 12:46:54 PM PDT 24
Finished Mar 31 12:47:00 PM PDT 24
Peak memory 211632 kb
Host smart-f9ef7308-e56b-4748-8722-ab9602b9ea02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111630671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4111630671
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1108883034
Short name T329
Test name
Test status
Simulation time 1583923829 ps
CPU time 18.71 seconds
Started Mar 31 12:46:52 PM PDT 24
Finished Mar 31 12:47:11 PM PDT 24
Peak memory 213692 kb
Host smart-f73704c3-991b-45eb-ad41-1502a48d16b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108883034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1108883034
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2737510338
Short name T210
Test name
Test status
Simulation time 768362262 ps
CPU time 14.84 seconds
Started Mar 31 12:28:59 PM PDT 24
Finished Mar 31 12:29:14 PM PDT 24
Peak memory 219724 kb
Host smart-a75f7d69-2ea5-4940-b86d-74e695449d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737510338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2737510338
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2775510125
Short name T107
Test name
Test status
Simulation time 33324907164 ps
CPU time 92.62 seconds
Started Mar 31 12:46:54 PM PDT 24
Finished Mar 31 12:48:27 PM PDT 24
Peak memory 219884 kb
Host smart-486644bd-3d2b-4352-a4fd-40df77c12ef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775510125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2775510125
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4180804941
Short name T684
Test name
Test status
Simulation time 19986057105 ps
CPU time 49.22 seconds
Started Mar 31 12:28:57 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 216888 kb
Host smart-2a0d2837-8f10-47c9-b75b-21903d850dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180804941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4180804941
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2773995911
Short name T681
Test name
Test status
Simulation time 248761207982 ps
CPU time 2347.2 seconds
Started Mar 31 12:46:53 PM PDT 24
Finished Mar 31 01:26:00 PM PDT 24
Peak memory 238164 kb
Host smart-e6e867a1-b384-4126-8bc4-a83ef6e3e2ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773995911 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2773995911
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1455175486
Short name T395
Test name
Test status
Simulation time 6271466552 ps
CPU time 13.26 seconds
Started Mar 31 12:46:54 PM PDT 24
Finished Mar 31 12:47:07 PM PDT 24
Peak memory 211756 kb
Host smart-7f3ccac6-ac3a-4d7c-8edd-f5e1827420df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455175486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1455175486
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2732243753
Short name T597
Test name
Test status
Simulation time 1969382792 ps
CPU time 6.87 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 211364 kb
Host smart-b0bc86d2-a146-460b-9fd7-0668d05a5891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732243753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2732243753
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1556392040
Short name T50
Test name
Test status
Simulation time 248840474255 ps
CPU time 285.53 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 12:33:47 PM PDT 24
Peak memory 225116 kb
Host smart-2c84fa5d-ba48-465a-a16f-220e4f13f02a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556392040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1556392040
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3096005753
Short name T598
Test name
Test status
Simulation time 73732926361 ps
CPU time 168.83 seconds
Started Mar 31 12:46:52 PM PDT 24
Finished Mar 31 12:49:41 PM PDT 24
Peak memory 212392 kb
Host smart-b4239ccd-0abe-48a9-85ea-0595ebc34733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096005753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3096005753
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.611586496
Short name T519
Test name
Test status
Simulation time 7867854248 ps
CPU time 20.96 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 211400 kb
Host smart-b4263eaa-3ce4-47ab-9747-51412b253729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611586496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.611586496
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.733271892
Short name T442
Test name
Test status
Simulation time 7146266547 ps
CPU time 29.81 seconds
Started Mar 31 12:46:54 PM PDT 24
Finished Mar 31 12:47:24 PM PDT 24
Peak memory 212592 kb
Host smart-a316983f-cc8f-4854-a090-cf71d94958fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733271892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.733271892
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1288444573
Short name T44
Test name
Test status
Simulation time 8126975648 ps
CPU time 16.16 seconds
Started Mar 31 12:28:57 PM PDT 24
Finished Mar 31 12:29:14 PM PDT 24
Peak memory 211612 kb
Host smart-7fb05fd5-295b-4ea1-8209-360fa41e2f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288444573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1288444573
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2936673789
Short name T380
Test name
Test status
Simulation time 2956845429 ps
CPU time 9.88 seconds
Started Mar 31 12:46:51 PM PDT 24
Finished Mar 31 12:47:01 PM PDT 24
Peak memory 211772 kb
Host smart-facdc220-c0f4-434c-b65c-2b014ee017d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936673789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2936673789
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3145442709
Short name T425
Test name
Test status
Simulation time 14807053860 ps
CPU time 29.87 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 12:29:25 PM PDT 24
Peak memory 214540 kb
Host smart-ba6a8f5d-23bc-4034-8a66-4867e6b8b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145442709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3145442709
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3811162569
Short name T293
Test name
Test status
Simulation time 49258100028 ps
CPU time 35.31 seconds
Started Mar 31 12:46:51 PM PDT 24
Finished Mar 31 12:47:27 PM PDT 24
Peak memory 219928 kb
Host smart-04587b42-39ae-4773-bdfc-150485473bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811162569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3811162569
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1043861019
Short name T611
Test name
Test status
Simulation time 1747348954 ps
CPU time 18.8 seconds
Started Mar 31 12:28:55 PM PDT 24
Finished Mar 31 12:29:14 PM PDT 24
Peak memory 219680 kb
Host smart-3b234b88-a148-4389-a26e-33b5d0a6afd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043861019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1043861019
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3655036383
Short name T586
Test name
Test status
Simulation time 36232434160 ps
CPU time 50.02 seconds
Started Mar 31 12:46:52 PM PDT 24
Finished Mar 31 12:47:42 PM PDT 24
Peak memory 219880 kb
Host smart-60a0cfe5-227a-4dec-969f-c9bf4c730178
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655036383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3655036383
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3112550689
Short name T54
Test name
Test status
Simulation time 72615764639 ps
CPU time 1534.92 seconds
Started Mar 31 12:46:54 PM PDT 24
Finished Mar 31 01:12:29 PM PDT 24
Peak memory 238672 kb
Host smart-213994aa-2a30-4f71-a703-43821f37787f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112550689 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3112550689
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1503758886
Short name T150
Test name
Test status
Simulation time 232961924 ps
CPU time 4.24 seconds
Started Mar 31 12:46:53 PM PDT 24
Finished Mar 31 12:46:57 PM PDT 24
Peak memory 211704 kb
Host smart-ab30ff18-55ef-4490-b6d0-c46820e8e2cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503758886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1503758886
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4128449989
Short name T501
Test name
Test status
Simulation time 7906180194 ps
CPU time 15.25 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 211804 kb
Host smart-b94b04ee-9d10-4317-ab6e-d1b5e31d0b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128449989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4128449989
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1110471994
Short name T301
Test name
Test status
Simulation time 18896087667 ps
CPU time 249.19 seconds
Started Mar 31 12:46:56 PM PDT 24
Finished Mar 31 12:51:05 PM PDT 24
Peak memory 230312 kb
Host smart-f3ee3d01-eb4a-4532-9dea-c755fab63102
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110471994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1110471994
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1244857009
Short name T600
Test name
Test status
Simulation time 5743507872 ps
CPU time 88.76 seconds
Started Mar 31 12:29:15 PM PDT 24
Finished Mar 31 12:30:44 PM PDT 24
Peak memory 220132 kb
Host smart-918c5d9e-85f1-4303-9e08-116ae3b8cd32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244857009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1244857009
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1247432927
Short name T338
Test name
Test status
Simulation time 4332192093 ps
CPU time 22.21 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 12:29:16 PM PDT 24
Peak memory 212680 kb
Host smart-53c60771-a157-41c2-af87-0bf80f2c8683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247432927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1247432927
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3506866217
Short name T331
Test name
Test status
Simulation time 170365219 ps
CPU time 9.58 seconds
Started Mar 31 12:46:54 PM PDT 24
Finished Mar 31 12:47:03 PM PDT 24
Peak memory 212328 kb
Host smart-d75fd8cd-fae6-4890-aeea-7010a3ec87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506866217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3506866217
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.316010783
Short name T683
Test name
Test status
Simulation time 5894556159 ps
CPU time 17.08 seconds
Started Mar 31 12:46:51 PM PDT 24
Finished Mar 31 12:47:08 PM PDT 24
Peak memory 211636 kb
Host smart-75ef44d9-6860-4dcd-ab19-12e4afd957b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316010783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.316010783
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3254030113
Short name T194
Test name
Test status
Simulation time 2836466660 ps
CPU time 13.32 seconds
Started Mar 31 12:29:14 PM PDT 24
Finished Mar 31 12:29:27 PM PDT 24
Peak memory 211680 kb
Host smart-ea21455c-e64e-4340-8ffa-a5f01f67e04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254030113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3254030113
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1211333982
Short name T677
Test name
Test status
Simulation time 4554655038 ps
CPU time 30.11 seconds
Started Mar 31 12:46:55 PM PDT 24
Finished Mar 31 12:47:25 PM PDT 24
Peak memory 213804 kb
Host smart-7b7b6299-4044-4ed4-ba5e-a6a51f30376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211333982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1211333982
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3543293648
Short name T666
Test name
Test status
Simulation time 4028877226 ps
CPU time 38.22 seconds
Started Mar 31 12:29:09 PM PDT 24
Finished Mar 31 12:29:48 PM PDT 24
Peak memory 213028 kb
Host smart-8276dfc5-e161-4647-abc8-3cd87b531a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543293648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3543293648
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1325964504
Short name T71
Test name
Test status
Simulation time 2271339507 ps
CPU time 12.67 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:09 PM PDT 24
Peak memory 211340 kb
Host smart-cd1737b1-2d3b-42d1-b59d-2914b58ce41c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325964504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1325964504
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2847939056
Short name T149
Test name
Test status
Simulation time 908553805 ps
CPU time 16.76 seconds
Started Mar 31 12:46:51 PM PDT 24
Finished Mar 31 12:47:08 PM PDT 24
Peak memory 213136 kb
Host smart-fc89bad9-c1d0-4766-8243-f214329df810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847939056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2847939056
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2786750939
Short name T34
Test name
Test status
Simulation time 4094528582 ps
CPU time 10.43 seconds
Started Mar 31 12:47:00 PM PDT 24
Finished Mar 31 12:47:10 PM PDT 24
Peak memory 211772 kb
Host smart-5ed4df9d-36f9-4c09-ac31-586169b70f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786750939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2786750939
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3189237197
Short name T298
Test name
Test status
Simulation time 168184876 ps
CPU time 4.2 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:28:53 PM PDT 24
Peak memory 211728 kb
Host smart-45391c3d-7b9f-49d0-a6db-b99025e0b1ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189237197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3189237197
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3045987200
Short name T165
Test name
Test status
Simulation time 33154282452 ps
CPU time 274.92 seconds
Started Mar 31 12:29:57 PM PDT 24
Finished Mar 31 12:34:32 PM PDT 24
Peak memory 214020 kb
Host smart-ec3a6393-6168-436a-b2df-a8c4e1a1be84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045987200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3045987200
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3559649582
Short name T423
Test name
Test status
Simulation time 4028584892 ps
CPU time 117.8 seconds
Started Mar 31 12:47:04 PM PDT 24
Finished Mar 31 12:49:02 PM PDT 24
Peak memory 212080 kb
Host smart-c324fc9c-076e-4c5a-a6af-659941c47db3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559649582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3559649582
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2485646107
Short name T433
Test name
Test status
Simulation time 1544780066 ps
CPU time 14.46 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 211720 kb
Host smart-80f053d3-5b84-4e6d-a6cc-7e25077d14f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485646107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2485646107
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2565855786
Short name T507
Test name
Test status
Simulation time 696885568 ps
CPU time 13.89 seconds
Started Mar 31 12:47:01 PM PDT 24
Finished Mar 31 12:47:15 PM PDT 24
Peak memory 212240 kb
Host smart-3ab8aed0-a959-4eea-bcd9-6c1ae9554ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565855786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2565855786
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3042743880
Short name T240
Test name
Test status
Simulation time 2562428142 ps
CPU time 13.47 seconds
Started Mar 31 12:47:03 PM PDT 24
Finished Mar 31 12:47:17 PM PDT 24
Peak memory 211752 kb
Host smart-ad07d775-5f55-45ec-bbe6-d558e8a4fdad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042743880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3042743880
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4083547041
Short name T13
Test name
Test status
Simulation time 389051394 ps
CPU time 5.68 seconds
Started Mar 31 12:29:19 PM PDT 24
Finished Mar 31 12:29:25 PM PDT 24
Peak memory 211672 kb
Host smart-18264030-c57d-45bc-9ce1-92d1de4abfb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083547041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4083547041
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3208670062
Short name T324
Test name
Test status
Simulation time 3626573750 ps
CPU time 21.1 seconds
Started Mar 31 12:29:58 PM PDT 24
Finished Mar 31 12:30:21 PM PDT 24
Peak memory 219584 kb
Host smart-563b78b6-454f-4fbd-a391-522993fc0be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208670062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3208670062
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.961710212
Short name T582
Test name
Test status
Simulation time 181065834 ps
CPU time 9.55 seconds
Started Mar 31 12:46:52 PM PDT 24
Finished Mar 31 12:47:01 PM PDT 24
Peak memory 219804 kb
Host smart-36e86c7d-b30f-41f8-883a-cda3655e8571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961710212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.961710212
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2366389965
Short name T212
Test name
Test status
Simulation time 9487550174 ps
CPU time 75.6 seconds
Started Mar 31 12:47:00 PM PDT 24
Finished Mar 31 12:48:16 PM PDT 24
Peak memory 217188 kb
Host smart-bbd41580-f3c5-4aa4-b8b1-f661fe0d39b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366389965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2366389965
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2516959899
Short name T255
Test name
Test status
Simulation time 3821600126 ps
CPU time 43.44 seconds
Started Mar 31 12:29:48 PM PDT 24
Finished Mar 31 12:30:33 PM PDT 24
Peak memory 219056 kb
Host smart-6f79c71d-624e-47e3-9141-9cfc124be5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516959899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2516959899
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2003511547
Short name T494
Test name
Test status
Simulation time 2403601070 ps
CPU time 6.31 seconds
Started Mar 31 12:47:00 PM PDT 24
Finished Mar 31 12:47:07 PM PDT 24
Peak memory 211888 kb
Host smart-c9577d19-76d8-45ee-a33d-b598be02decd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003511547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2003511547
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2849776988
Short name T175
Test name
Test status
Simulation time 920095964 ps
CPU time 3.89 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:00 PM PDT 24
Peak memory 211360 kb
Host smart-f833868d-cac9-431e-a87f-973eeea070bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849776988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2849776988
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1166941840
Short name T658
Test name
Test status
Simulation time 34313646528 ps
CPU time 65.38 seconds
Started Mar 31 12:47:00 PM PDT 24
Finished Mar 31 12:48:05 PM PDT 24
Peak memory 229040 kb
Host smart-ebbaf9c5-63fd-49d1-92ba-5187e727f4cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166941840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1166941840
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4021458742
Short name T576
Test name
Test status
Simulation time 65269150585 ps
CPU time 357.09 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:34:43 PM PDT 24
Peak memory 221044 kb
Host smart-a4bd0174-c408-4792-a88d-52501dc0d9f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021458742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4021458742
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2020498700
Short name T200
Test name
Test status
Simulation time 5843679289 ps
CPU time 19.97 seconds
Started Mar 31 12:29:25 PM PDT 24
Finished Mar 31 12:29:45 PM PDT 24
Peak memory 212976 kb
Host smart-e655b8a4-92a4-44a7-bf19-edfc86ab8719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020498700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2020498700
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.936085253
Short name T160
Test name
Test status
Simulation time 3879920979 ps
CPU time 30.1 seconds
Started Mar 31 12:47:02 PM PDT 24
Finished Mar 31 12:47:32 PM PDT 24
Peak memory 212672 kb
Host smart-974e475b-50bb-4ef2-bcbe-d88fd6b01954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936085253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.936085253
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2621378327
Short name T680
Test name
Test status
Simulation time 343692419 ps
CPU time 7.69 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 12:29:07 PM PDT 24
Peak memory 211632 kb
Host smart-b59eeadb-ee3e-4810-a324-57682041ed26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621378327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2621378327
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4169378374
Short name T587
Test name
Test status
Simulation time 4365209723 ps
CPU time 13.49 seconds
Started Mar 31 12:47:00 PM PDT 24
Finished Mar 31 12:47:14 PM PDT 24
Peak memory 211772 kb
Host smart-6d45c882-27cf-464b-86dc-c7b471c01ab1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169378374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4169378374
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.280627494
Short name T438
Test name
Test status
Simulation time 2397927674 ps
CPU time 22.68 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:10 PM PDT 24
Peak memory 214180 kb
Host smart-1fe99d2c-620b-4cfd-8cf4-6f84467343bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280627494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.280627494
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3153774811
Short name T11
Test name
Test status
Simulation time 4373886519 ps
CPU time 23.75 seconds
Started Mar 31 12:47:02 PM PDT 24
Finished Mar 31 12:47:26 PM PDT 24
Peak memory 214828 kb
Host smart-46706583-61ea-4f56-b4ab-5ba6e077ce3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153774811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3153774811
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.121428368
Short name T606
Test name
Test status
Simulation time 1928514328 ps
CPU time 39.12 seconds
Started Mar 31 12:47:00 PM PDT 24
Finished Mar 31 12:47:39 PM PDT 24
Peak memory 217016 kb
Host smart-0712e492-2896-4b68-93e1-e03d0dd56bce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121428368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.121428368
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.246582205
Short name T405
Test name
Test status
Simulation time 1550445827 ps
CPU time 22.61 seconds
Started Mar 31 12:28:57 PM PDT 24
Finished Mar 31 12:29:19 PM PDT 24
Peak memory 213432 kb
Host smart-2b75db36-7caa-4bb6-a123-8936872f1885
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246582205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.246582205
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2092542419
Short name T25
Test name
Test status
Simulation time 32461451088 ps
CPU time 7206.04 seconds
Started Mar 31 12:47:00 PM PDT 24
Finished Mar 31 02:47:07 PM PDT 24
Peak memory 232896 kb
Host smart-d4758be8-ce6f-4b0c-9459-abee3130553d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092542419 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2092542419
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2059285010
Short name T497
Test name
Test status
Simulation time 3321068734 ps
CPU time 14.16 seconds
Started Mar 31 12:47:10 PM PDT 24
Finished Mar 31 12:47:24 PM PDT 24
Peak memory 211888 kb
Host smart-417a8531-7a80-4138-94da-9b6028f333de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059285010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2059285010
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2625536670
Short name T436
Test name
Test status
Simulation time 333755565 ps
CPU time 4.19 seconds
Started Mar 31 12:29:26 PM PDT 24
Finished Mar 31 12:29:30 PM PDT 24
Peak memory 211672 kb
Host smart-06ba6243-8f42-432b-a4ca-dbe49876a892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625536670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2625536670
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2374374713
Short name T472
Test name
Test status
Simulation time 260963773092 ps
CPU time 247.77 seconds
Started Mar 31 12:28:56 PM PDT 24
Finished Mar 31 12:33:05 PM PDT 24
Peak memory 220196 kb
Host smart-142c6ef1-7f24-495d-b87f-9ecd6394d396
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374374713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2374374713
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4201529712
Short name T613
Test name
Test status
Simulation time 1552334169 ps
CPU time 105.95 seconds
Started Mar 31 12:47:08 PM PDT 24
Finished Mar 31 12:48:54 PM PDT 24
Peak memory 229216 kb
Host smart-43a738a1-6ac9-466c-b6fc-ff3cafd02c83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201529712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4201529712
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3359289765
Short name T208
Test name
Test status
Simulation time 3736835876 ps
CPU time 30.61 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:30:25 PM PDT 24
Peak memory 211988 kb
Host smart-0abea29d-9f44-4d59-9afb-e01fc91bfaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359289765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3359289765
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3842328447
Short name T482
Test name
Test status
Simulation time 13390740984 ps
CPU time 30.25 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:45 PM PDT 24
Peak memory 211920 kb
Host smart-e05a2858-84f0-4c70-8327-324c16f85b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842328447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3842328447
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.253535746
Short name T144
Test name
Test status
Simulation time 195410482 ps
CPU time 5.5 seconds
Started Mar 31 12:29:03 PM PDT 24
Finished Mar 31 12:29:09 PM PDT 24
Peak memory 211576 kb
Host smart-f9615e29-e418-41a4-8646-35f8b3deb5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253535746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.253535746
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.538148704
Short name T196
Test name
Test status
Simulation time 675980547 ps
CPU time 9.65 seconds
Started Mar 31 12:47:12 PM PDT 24
Finished Mar 31 12:47:21 PM PDT 24
Peak memory 211672 kb
Host smart-57d7d1ce-6f18-4b8e-aa78-da391ae780fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538148704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.538148704
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2705740262
Short name T273
Test name
Test status
Simulation time 1908977317 ps
CPU time 17.9 seconds
Started Mar 31 12:47:01 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 214192 kb
Host smart-a247fe16-a8a9-466a-ba7c-aa4719d3a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705740262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2705740262
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4127442762
Short name T399
Test name
Test status
Simulation time 849014550 ps
CPU time 12.1 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:08 PM PDT 24
Peak memory 219452 kb
Host smart-3cb7f34c-ac9c-449f-9244-556defba5741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127442762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4127442762
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3282033067
Short name T417
Test name
Test status
Simulation time 101904104 ps
CPU time 6.73 seconds
Started Mar 31 12:29:10 PM PDT 24
Finished Mar 31 12:29:17 PM PDT 24
Peak memory 211484 kb
Host smart-4f4d37a2-b61f-4915-a9e9-fc9047b153d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282033067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3282033067
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.551047106
Short name T475
Test name
Test status
Simulation time 11191492756 ps
CPU time 51.76 seconds
Started Mar 31 12:47:01 PM PDT 24
Finished Mar 31 12:47:53 PM PDT 24
Peak memory 216596 kb
Host smart-3839bc1c-535f-43ce-a128-48c0f58f82b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551047106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.551047106
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.356519709
Short name T274
Test name
Test status
Simulation time 1680895517 ps
CPU time 14.05 seconds
Started Mar 31 12:28:42 PM PDT 24
Finished Mar 31 12:28:56 PM PDT 24
Peak memory 211652 kb
Host smart-502d7ee2-085e-45ea-803b-bb7cf7ee337d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356519709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.356519709
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.539748862
Short name T469
Test name
Test status
Simulation time 182703147 ps
CPU time 3.95 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:45:43 PM PDT 24
Peak memory 211692 kb
Host smart-89d83c0a-2c34-4270-917f-b696ef9a378d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539748862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.539748862
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1758198439
Short name T176
Test name
Test status
Simulation time 5102932352 ps
CPU time 84.47 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:29:52 PM PDT 24
Peak memory 221040 kb
Host smart-df5063d1-814a-4a10-8800-66975c363afd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758198439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1758198439
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1987209142
Short name T647
Test name
Test status
Simulation time 323728066088 ps
CPU time 324.19 seconds
Started Mar 31 12:45:38 PM PDT 24
Finished Mar 31 12:51:02 PM PDT 24
Peak memory 229100 kb
Host smart-a7565ea2-f103-4a7c-a4aa-0b1d5ddacc06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987209142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1987209142
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.340843718
Short name T374
Test name
Test status
Simulation time 521307863 ps
CPU time 9.4 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:33 PM PDT 24
Peak memory 212212 kb
Host smart-94a94ae7-9547-40b7-8f23-9e16a2c51a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340843718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.340843718
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3523559615
Short name T279
Test name
Test status
Simulation time 4262798294 ps
CPU time 33.51 seconds
Started Mar 31 12:45:40 PM PDT 24
Finished Mar 31 12:46:14 PM PDT 24
Peak memory 212340 kb
Host smart-7822bc58-4e42-45dc-896e-a18d93cc24be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523559615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3523559615
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.36796965
Short name T184
Test name
Test status
Simulation time 1330273370 ps
CPU time 12.82 seconds
Started Mar 31 12:28:34 PM PDT 24
Finished Mar 31 12:28:48 PM PDT 24
Peak memory 211552 kb
Host smart-f396229b-d81a-4c00-8c80-c95a6743356f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36796965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.36796965
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.81449903
Short name T608
Test name
Test status
Simulation time 95413505 ps
CPU time 5.5 seconds
Started Mar 31 12:45:34 PM PDT 24
Finished Mar 31 12:45:39 PM PDT 24
Peak memory 211672 kb
Host smart-abdc743e-6958-4858-8f49-63e50c50a100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81449903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.81449903
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1997597549
Short name T32
Test name
Test status
Simulation time 245816098 ps
CPU time 53.53 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:46:33 PM PDT 24
Peak memory 233432 kb
Host smart-bfee0219-c2cd-4fca-8935-74e23d894707
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997597549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1997597549
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3054040507
Short name T43
Test name
Test status
Simulation time 7119570994 ps
CPU time 106.6 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:30:18 PM PDT 24
Peak memory 231520 kb
Host smart-e770a5aa-bae0-4903-a65d-406f52262c75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054040507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3054040507
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3709253718
Short name T451
Test name
Test status
Simulation time 8566697919 ps
CPU time 26.23 seconds
Started Mar 31 12:45:32 PM PDT 24
Finished Mar 31 12:45:59 PM PDT 24
Peak memory 215060 kb
Host smart-a3cd4ee1-a72f-4632-8de2-7da8214f281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709253718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3709253718
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.798768907
Short name T225
Test name
Test status
Simulation time 784782430 ps
CPU time 10.01 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 213528 kb
Host smart-ad1231d0-0e6f-4339-a4d1-2012d9017979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798768907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.798768907
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1610622208
Short name T356
Test name
Test status
Simulation time 905909106 ps
CPU time 10.98 seconds
Started Mar 31 12:45:32 PM PDT 24
Finished Mar 31 12:45:43 PM PDT 24
Peak memory 215124 kb
Host smart-2a7654fb-df1e-49ed-a952-701b6ba5905f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610622208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1610622208
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2340947363
Short name T288
Test name
Test status
Simulation time 353646962 ps
CPU time 8.83 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 211548 kb
Host smart-e8aa2284-1e22-4f85-9884-53351961cf9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340947363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2340947363
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1108996859
Short name T266
Test name
Test status
Simulation time 1364774978 ps
CPU time 12.04 seconds
Started Mar 31 12:47:12 PM PDT 24
Finished Mar 31 12:47:24 PM PDT 24
Peak memory 211680 kb
Host smart-64f7ada4-e43c-4292-8c7a-ab3cda02d745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108996859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1108996859
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1634691986
Short name T491
Test name
Test status
Simulation time 3938385870 ps
CPU time 15.4 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 211448 kb
Host smart-53eb2117-f55e-4253-8e90-f3b5dcf66df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634691986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1634691986
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1278850747
Short name T527
Test name
Test status
Simulation time 44200893014 ps
CPU time 402.99 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:36:39 PM PDT 24
Peak memory 219848 kb
Host smart-da1afe14-9860-4101-be6c-dce80b5422aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278850747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1278850747
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2427053800
Short name T53
Test name
Test status
Simulation time 1390748025 ps
CPU time 86.55 seconds
Started Mar 31 12:47:12 PM PDT 24
Finished Mar 31 12:48:38 PM PDT 24
Peak memory 230112 kb
Host smart-7dad8630-e0cc-4195-b7dd-c752ebdb67ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427053800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2427053800
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2797553819
Short name T641
Test name
Test status
Simulation time 5276463712 ps
CPU time 17.92 seconds
Started Mar 31 12:29:44 PM PDT 24
Finished Mar 31 12:30:02 PM PDT 24
Peak memory 211876 kb
Host smart-d8acdf98-cc7f-4eac-8480-9edfa7d6063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797553819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2797553819
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.7490295
Short name T479
Test name
Test status
Simulation time 72206943988 ps
CPU time 32.15 seconds
Started Mar 31 12:47:07 PM PDT 24
Finished Mar 31 12:47:40 PM PDT 24
Peak memory 212808 kb
Host smart-847333e4-6d68-4ed8-a90e-ff7911e4c39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7490295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.7490295
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1617620140
Short name T453
Test name
Test status
Simulation time 546243760 ps
CPU time 8.16 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:04 PM PDT 24
Peak memory 211280 kb
Host smart-d7b07b23-3ce5-4413-baf0-7981f0ce8e51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617620140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1617620140
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.769857429
Short name T313
Test name
Test status
Simulation time 2998712168 ps
CPU time 10.09 seconds
Started Mar 31 12:47:12 PM PDT 24
Finished Mar 31 12:47:23 PM PDT 24
Peak memory 211788 kb
Host smart-24e258c6-12fd-4d2e-870a-e01823bd5e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769857429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.769857429
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.141606279
Short name T521
Test name
Test status
Simulation time 3674447156 ps
CPU time 30.83 seconds
Started Mar 31 12:28:58 PM PDT 24
Finished Mar 31 12:29:29 PM PDT 24
Peak memory 213724 kb
Host smart-a64d287b-e9e7-4c26-9ea6-995d7bfe405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141606279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.141606279
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3137642751
Short name T644
Test name
Test status
Simulation time 2799228417 ps
CPU time 30.11 seconds
Started Mar 31 12:47:08 PM PDT 24
Finished Mar 31 12:47:38 PM PDT 24
Peak memory 219944 kb
Host smart-d7d07aa5-9222-4057-8f95-5da9431bb0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137642751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3137642751
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1744055191
Short name T171
Test name
Test status
Simulation time 6837625483 ps
CPU time 35.61 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:31 PM PDT 24
Peak memory 219576 kb
Host smart-7e9c4cbd-bd66-4e6e-9143-ad0f8165200e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744055191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1744055191
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3155309172
Short name T250
Test name
Test status
Simulation time 5839199366 ps
CPU time 33.29 seconds
Started Mar 31 12:47:08 PM PDT 24
Finished Mar 31 12:47:41 PM PDT 24
Peak memory 219856 kb
Host smart-47290d5e-62c1-4230-b9aa-afee884db495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155309172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3155309172
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3330080686
Short name T121
Test name
Test status
Simulation time 32292977359 ps
CPU time 843.78 seconds
Started Mar 31 12:29:12 PM PDT 24
Finished Mar 31 12:43:16 PM PDT 24
Peak memory 236272 kb
Host smart-1e55d8d7-9378-4a37-9911-bbe196e572c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330080686 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3330080686
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1582549641
Short name T276
Test name
Test status
Simulation time 5443672258 ps
CPU time 9.69 seconds
Started Mar 31 12:29:19 PM PDT 24
Finished Mar 31 12:29:29 PM PDT 24
Peak memory 211848 kb
Host smart-b26e9046-14a4-4221-941f-7c5c6daabde3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582549641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1582549641
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3750028808
Short name T671
Test name
Test status
Simulation time 3573471242 ps
CPU time 14.12 seconds
Started Mar 31 12:47:09 PM PDT 24
Finished Mar 31 12:47:23 PM PDT 24
Peak memory 211884 kb
Host smart-114cf576-fb62-42ea-af67-090174b7f508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750028808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3750028808
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2825522129
Short name T232
Test name
Test status
Simulation time 496178320332 ps
CPU time 219.92 seconds
Started Mar 31 12:29:14 PM PDT 24
Finished Mar 31 12:32:54 PM PDT 24
Peak memory 237216 kb
Host smart-14ef7839-5efb-4f56-86a4-f6f347d62b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825522129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2825522129
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.795137871
Short name T275
Test name
Test status
Simulation time 1975932985 ps
CPU time 104.87 seconds
Started Mar 31 12:47:10 PM PDT 24
Finished Mar 31 12:48:55 PM PDT 24
Peak memory 220132 kb
Host smart-a69e178a-4dcb-42da-9474-9f68c2246b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795137871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.795137871
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2341380971
Short name T73
Test name
Test status
Simulation time 3093027090 ps
CPU time 28.04 seconds
Started Mar 31 12:47:11 PM PDT 24
Finished Mar 31 12:47:39 PM PDT 24
Peak memory 212532 kb
Host smart-d1b3e966-869f-4997-8015-e913eb7ace8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341380971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2341380971
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4261540417
Short name T392
Test name
Test status
Simulation time 7001348909 ps
CPU time 15.55 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:11 PM PDT 24
Peak memory 212720 kb
Host smart-a73b9f65-6a31-47a1-9f11-3220eeae78d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261540417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4261540417
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2659286189
Short name T460
Test name
Test status
Simulation time 3843073417 ps
CPU time 10.9 seconds
Started Mar 31 12:47:08 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 211792 kb
Host smart-274e0540-70af-4f0d-b741-e0ba346caa87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659286189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2659286189
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4263755001
Short name T147
Test name
Test status
Simulation time 15035268156 ps
CPU time 15.83 seconds
Started Mar 31 12:29:24 PM PDT 24
Finished Mar 31 12:29:40 PM PDT 24
Peak memory 211776 kb
Host smart-e5d60f01-d263-4fdc-8750-b77e755fbab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263755001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4263755001
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3518737038
Short name T48
Test name
Test status
Simulation time 6189363657 ps
CPU time 30.72 seconds
Started Mar 31 12:47:12 PM PDT 24
Finished Mar 31 12:47:43 PM PDT 24
Peak memory 219952 kb
Host smart-1bf22b40-5eca-41ac-a06b-36a9af3139b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518737038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3518737038
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3644902964
Short name T294
Test name
Test status
Simulation time 715963673 ps
CPU time 9.35 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:05 PM PDT 24
Peak memory 213396 kb
Host smart-596c85fd-ab17-47a3-aa11-4de436f1d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644902964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3644902964
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.296264444
Short name T593
Test name
Test status
Simulation time 1589255471 ps
CPU time 13.16 seconds
Started Mar 31 12:29:08 PM PDT 24
Finished Mar 31 12:29:21 PM PDT 24
Peak memory 219744 kb
Host smart-a987c17d-e6d5-4480-8b76-c234f0eb522a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296264444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.296264444
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3784879167
Short name T179
Test name
Test status
Simulation time 16606856921 ps
CPU time 39.17 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:53 PM PDT 24
Peak memory 219956 kb
Host smart-b2d1cd24-610c-462f-b7ba-bf0c5e3cbb14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784879167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3784879167
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2709504087
Short name T362
Test name
Test status
Simulation time 81202711620 ps
CPU time 1440.17 seconds
Started Mar 31 12:29:54 PM PDT 24
Finished Mar 31 12:53:55 PM PDT 24
Peak memory 236092 kb
Host smart-27ccbb92-fb8c-42c7-b34c-07be3dabf83e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709504087 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2709504087
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.560164661
Short name T28
Test name
Test status
Simulation time 276491090034 ps
CPU time 5100.16 seconds
Started Mar 31 12:47:09 PM PDT 24
Finished Mar 31 02:12:10 PM PDT 24
Peak memory 251040 kb
Host smart-25283b4c-f1ea-46e5-b1e4-44b27e346e67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560164661 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.560164661
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2519325950
Short name T366
Test name
Test status
Simulation time 132253201 ps
CPU time 5.09 seconds
Started Mar 31 12:29:21 PM PDT 24
Finished Mar 31 12:29:26 PM PDT 24
Peak memory 211660 kb
Host smart-bd4ed31a-5ba7-4bf6-a3ba-3b3cc29fe652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519325950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2519325950
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.794184043
Short name T499
Test name
Test status
Simulation time 2767307787 ps
CPU time 5.69 seconds
Started Mar 31 12:47:10 PM PDT 24
Finished Mar 31 12:47:16 PM PDT 24
Peak memory 211904 kb
Host smart-f54c5e22-8615-4086-87bd-9e0ace4c558c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794184043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.794184043
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1506353187
Short name T625
Test name
Test status
Simulation time 328774419246 ps
CPU time 297.02 seconds
Started Mar 31 12:47:11 PM PDT 24
Finished Mar 31 12:52:09 PM PDT 24
Peak memory 233672 kb
Host smart-9eb432b2-cd39-4991-abec-00108171af94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506353187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1506353187
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3395456444
Short name T545
Test name
Test status
Simulation time 68860595665 ps
CPU time 142.96 seconds
Started Mar 31 12:29:04 PM PDT 24
Finished Mar 31 12:31:27 PM PDT 24
Peak memory 235364 kb
Host smart-08ab945e-2418-4390-8e1e-fe9deada821e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395456444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3395456444
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1301720274
Short name T672
Test name
Test status
Simulation time 396941716 ps
CPU time 9.41 seconds
Started Mar 31 12:47:09 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 212268 kb
Host smart-e0707c00-ab8f-4c49-9bd9-24b7e8e52932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301720274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1301720274
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3021474488
Short name T651
Test name
Test status
Simulation time 10070582433 ps
CPU time 17.13 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:30:13 PM PDT 24
Peak memory 212440 kb
Host smart-59a499bf-dc78-40ae-ba5f-16ce0dc3f9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021474488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3021474488
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1269427055
Short name T571
Test name
Test status
Simulation time 389536223 ps
CPU time 7.69 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:03 PM PDT 24
Peak memory 211248 kb
Host smart-99f0fdd5-f78c-4dc1-9926-c18735b600d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269427055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1269427055
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1362380767
Short name T525
Test name
Test status
Simulation time 984923174 ps
CPU time 11.24 seconds
Started Mar 31 12:47:11 PM PDT 24
Finished Mar 31 12:47:23 PM PDT 24
Peak memory 211628 kb
Host smart-c50cb5ed-7ef3-49f4-9328-54262b0f82fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362380767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1362380767
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3985820962
Short name T254
Test name
Test status
Simulation time 717095768 ps
CPU time 9.63 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 12:29:11 PM PDT 24
Peak memory 219712 kb
Host smart-05c1e68e-0d71-442d-9444-975962e2e03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985820962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3985820962
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.685874226
Short name T649
Test name
Test status
Simulation time 11928917309 ps
CPU time 32.05 seconds
Started Mar 31 12:47:10 PM PDT 24
Finished Mar 31 12:47:43 PM PDT 24
Peak memory 219856 kb
Host smart-024edbd1-e63d-4f66-ab4b-eff15fce53f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685874226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.685874226
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1946551661
Short name T615
Test name
Test status
Simulation time 37774517418 ps
CPU time 78.29 seconds
Started Mar 31 12:47:10 PM PDT 24
Finished Mar 31 12:48:28 PM PDT 24
Peak memory 219836 kb
Host smart-dd3189a8-1f63-4111-8531-ab7c9a5f7933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946551661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1946551661
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3580260713
Short name T377
Test name
Test status
Simulation time 8101571509 ps
CPU time 23.78 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:19 PM PDT 24
Peak memory 219552 kb
Host smart-005b2022-fa7c-4b98-948a-f108354d2e67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580260713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3580260713
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3943447647
Short name T580
Test name
Test status
Simulation time 1552708580 ps
CPU time 13.15 seconds
Started Mar 31 12:28:58 PM PDT 24
Finished Mar 31 12:29:12 PM PDT 24
Peak memory 211656 kb
Host smart-de3c3d4d-c961-4557-a4eb-f695b18d542e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943447647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3943447647
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.427592431
Short name T36
Test name
Test status
Simulation time 4742767785 ps
CPU time 14.44 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:28 PM PDT 24
Peak memory 211824 kb
Host smart-ba4da4f7-8a94-4237-bbbd-3b95215cdb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427592431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.427592431
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2129579413
Short name T654
Test name
Test status
Simulation time 72013010880 ps
CPU time 168.64 seconds
Started Mar 31 12:47:17 PM PDT 24
Finished Mar 31 12:50:06 PM PDT 24
Peak memory 212084 kb
Host smart-f6be684e-b1e6-4253-8cc4-41cbc82d608f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129579413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2129579413
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4172725499
Short name T315
Test name
Test status
Simulation time 49524694040 ps
CPU time 433.58 seconds
Started Mar 31 12:29:16 PM PDT 24
Finished Mar 31 12:36:30 PM PDT 24
Peak memory 220108 kb
Host smart-4a030122-c9b6-47bd-95a8-32097de50bd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172725499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4172725499
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2210152046
Short name T673
Test name
Test status
Simulation time 14318667062 ps
CPU time 29.41 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:20 PM PDT 24
Peak memory 212704 kb
Host smart-94e60e2f-4825-444d-ae77-af3681ac9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210152046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2210152046
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3284731539
Short name T20
Test name
Test status
Simulation time 10414794662 ps
CPU time 25.67 seconds
Started Mar 31 12:47:19 PM PDT 24
Finished Mar 31 12:47:44 PM PDT 24
Peak memory 212788 kb
Host smart-5799ba28-3994-49d0-8886-9e6956f6ccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284731539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3284731539
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1536463538
Short name T221
Test name
Test status
Simulation time 1487937237 ps
CPU time 13.64 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:29:05 PM PDT 24
Peak memory 211540 kb
Host smart-bf50aadc-66af-4878-8489-6455424154df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536463538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1536463538
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1583307021
Short name T354
Test name
Test status
Simulation time 6241594833 ps
CPU time 8.56 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:23 PM PDT 24
Peak memory 211744 kb
Host smart-ba41f1d6-f8f0-42d6-b795-30195fe24645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583307021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1583307021
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.672466828
Short name T441
Test name
Test status
Simulation time 3801812594 ps
CPU time 16.7 seconds
Started Mar 31 12:47:10 PM PDT 24
Finished Mar 31 12:47:27 PM PDT 24
Peak memory 219824 kb
Host smart-137b603f-fe76-4d1b-954b-f3971ea1ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672466828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.672466828
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.209672575
Short name T326
Test name
Test status
Simulation time 28699970381 ps
CPU time 61.97 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:52 PM PDT 24
Peak memory 219836 kb
Host smart-9b32aff7-15fb-4e96-bd5d-8d216c6bd44e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209672575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.209672575
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.405063495
Short name T260
Test name
Test status
Simulation time 35486844925 ps
CPU time 83.7 seconds
Started Mar 31 12:47:17 PM PDT 24
Finished Mar 31 12:48:41 PM PDT 24
Peak memory 219956 kb
Host smart-335fdeba-2380-426f-bf88-89837951f734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405063495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.405063495
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.4233550497
Short name T58
Test name
Test status
Simulation time 73183459383 ps
CPU time 2079.49 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 01:03:42 PM PDT 24
Peak memory 236424 kb
Host smart-ce6fc84d-d636-4347-9d86-825a32180e97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233550497 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.4233550497
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1182443719
Short name T646
Test name
Test status
Simulation time 846842348 ps
CPU time 6.97 seconds
Started Mar 31 12:29:10 PM PDT 24
Finished Mar 31 12:29:17 PM PDT 24
Peak memory 211700 kb
Host smart-c885fefa-8012-42e7-b6c2-3e8d0e74ddcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182443719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1182443719
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1287799906
Short name T530
Test name
Test status
Simulation time 6641647472 ps
CPU time 13.89 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:28 PM PDT 24
Peak memory 211904 kb
Host smart-2c5ff79f-b4af-4f60-9409-5d43ababed43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287799906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1287799906
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1054836667
Short name T603
Test name
Test status
Simulation time 60178532024 ps
CPU time 222.3 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:50:56 PM PDT 24
Peak memory 237632 kb
Host smart-ff23ad05-fe32-4586-8454-2da9e5b4015f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054836667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1054836667
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.522003499
Short name T177
Test name
Test status
Simulation time 7702417066 ps
CPU time 78.96 seconds
Started Mar 31 12:29:19 PM PDT 24
Finished Mar 31 12:30:38 PM PDT 24
Peak memory 229320 kb
Host smart-a2352638-1438-4a93-b22f-cdc6262b51bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522003499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.522003499
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1407138132
Short name T148
Test name
Test status
Simulation time 7085424394 ps
CPU time 22.81 seconds
Started Mar 31 12:47:17 PM PDT 24
Finished Mar 31 12:47:40 PM PDT 24
Peak memory 212900 kb
Host smart-9f396993-d2bd-4bc6-b5e5-3eb437fcef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407138132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1407138132
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3153968496
Short name T400
Test name
Test status
Simulation time 3774841682 ps
CPU time 30.79 seconds
Started Mar 31 12:28:48 PM PDT 24
Finished Mar 31 12:29:19 PM PDT 24
Peak memory 212464 kb
Host smart-1fdd7248-7fc0-4297-9dbc-e0c54377cac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153968496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3153968496
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1637746865
Short name T413
Test name
Test status
Simulation time 334539387 ps
CPU time 7.45 seconds
Started Mar 31 12:47:18 PM PDT 24
Finished Mar 31 12:47:26 PM PDT 24
Peak memory 211624 kb
Host smart-09e558ef-307c-4235-a373-9ecad40b0229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637746865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1637746865
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2242046394
Short name T344
Test name
Test status
Simulation time 1108458541 ps
CPU time 11.36 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 211548 kb
Host smart-3b5f4b31-8e46-45c1-9c5a-39d984bd9125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242046394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2242046394
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3481704277
Short name T110
Test name
Test status
Simulation time 724042940 ps
CPU time 9.68 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 219696 kb
Host smart-12bb43eb-0443-44fa-b2b2-15a35fdd3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481704277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3481704277
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.40558038
Short name T357
Test name
Test status
Simulation time 16469920167 ps
CPU time 33.27 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:47 PM PDT 24
Peak memory 219904 kb
Host smart-41433826-22f5-4629-a5ca-af0e72d9d2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40558038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.40558038
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2926538231
Short name T119
Test name
Test status
Simulation time 5778137105 ps
CPU time 52.07 seconds
Started Mar 31 12:47:15 PM PDT 24
Finished Mar 31 12:48:07 PM PDT 24
Peak memory 219952 kb
Host smart-359d603b-2548-48ca-ac08-26810e9ad44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926538231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2926538231
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3724427489
Short name T404
Test name
Test status
Simulation time 2968232294 ps
CPU time 16.79 seconds
Started Mar 31 12:28:52 PM PDT 24
Finished Mar 31 12:29:09 PM PDT 24
Peak memory 211584 kb
Host smart-2f46229c-465f-4d00-b716-8a185917218e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724427489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3724427489
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1467716390
Short name T238
Test name
Test status
Simulation time 20534412717 ps
CPU time 12.18 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:26 PM PDT 24
Peak memory 211860 kb
Host smart-5621ec83-f42a-4af9-8aab-97de719cf2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467716390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1467716390
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4006895535
Short name T183
Test name
Test status
Simulation time 16983810854 ps
CPU time 13.71 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 211680 kb
Host smart-699a3930-c06a-4da2-8e1a-9d6b6440ba72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006895535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4006895535
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2441683485
Short name T493
Test name
Test status
Simulation time 1926021223 ps
CPU time 114.9 seconds
Started Mar 31 12:29:56 PM PDT 24
Finished Mar 31 12:31:51 PM PDT 24
Peak memory 229848 kb
Host smart-56feb70a-ea98-48da-bc76-90772d257f9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441683485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2441683485
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.339129428
Short name T163
Test name
Test status
Simulation time 20363058988 ps
CPU time 122.21 seconds
Started Mar 31 12:47:15 PM PDT 24
Finished Mar 31 12:49:18 PM PDT 24
Peak memory 229908 kb
Host smart-f7b0681a-2a7d-431b-b660-3e33f73d34e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339129428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.339129428
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1616410718
Short name T305
Test name
Test status
Simulation time 2056838568 ps
CPU time 21.33 seconds
Started Mar 31 12:29:24 PM PDT 24
Finished Mar 31 12:29:46 PM PDT 24
Peak memory 212416 kb
Host smart-cfff867a-9804-4df3-ac17-e86a3f7994d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616410718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1616410718
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2658079856
Short name T217
Test name
Test status
Simulation time 2516282798 ps
CPU time 23.62 seconds
Started Mar 31 12:47:15 PM PDT 24
Finished Mar 31 12:47:38 PM PDT 24
Peak memory 212424 kb
Host smart-fb6c5332-a5ab-41b4-a045-fb50612cd3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658079856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2658079856
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1909035425
Short name T428
Test name
Test status
Simulation time 738334475 ps
CPU time 9.67 seconds
Started Mar 31 12:29:11 PM PDT 24
Finished Mar 31 12:29:20 PM PDT 24
Peak memory 211556 kb
Host smart-9238cf25-b865-44d1-9744-d238d4fbf790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909035425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1909035425
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3070678677
Short name T173
Test name
Test status
Simulation time 1167732691 ps
CPU time 11.65 seconds
Started Mar 31 12:47:17 PM PDT 24
Finished Mar 31 12:47:29 PM PDT 24
Peak memory 211584 kb
Host smart-5ad4471c-65ef-4c1e-af96-06b46a658070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070678677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3070678677
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1150908426
Short name T543
Test name
Test status
Simulation time 730742797 ps
CPU time 9.85 seconds
Started Mar 31 12:47:16 PM PDT 24
Finished Mar 31 12:47:26 PM PDT 24
Peak memory 219800 kb
Host smart-23ab6afe-d32b-4e7f-902b-b42c210f1459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150908426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1150908426
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1545755123
Short name T351
Test name
Test status
Simulation time 795081068 ps
CPU time 10.11 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:00 PM PDT 24
Peak memory 213968 kb
Host smart-0e2d1c8b-15c0-4f12-965f-15a664aa62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545755123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1545755123
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2851168829
Short name T86
Test name
Test status
Simulation time 6467586118 ps
CPU time 32.09 seconds
Started Mar 31 12:29:55 PM PDT 24
Finished Mar 31 12:30:27 PM PDT 24
Peak memory 216332 kb
Host smart-853a2d48-30fb-404e-b36e-2dd5fb3cb305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851168829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2851168829
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.352405162
Short name T141
Test name
Test status
Simulation time 5618073227 ps
CPU time 31.28 seconds
Started Mar 31 12:47:17 PM PDT 24
Finished Mar 31 12:47:48 PM PDT 24
Peak memory 216744 kb
Host smart-b5a04d5f-95dc-4525-81af-ab6ae526cafa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352405162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.352405162
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2582817645
Short name T478
Test name
Test status
Simulation time 32152794957 ps
CPU time 608.13 seconds
Started Mar 31 12:47:19 PM PDT 24
Finished Mar 31 12:57:27 PM PDT 24
Peak memory 235472 kb
Host smart-5e80585c-30c8-4558-bcaf-4e8bd40a4911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582817645 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2582817645
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1201893016
Short name T220
Test name
Test status
Simulation time 862622702 ps
CPU time 9.48 seconds
Started Mar 31 12:29:03 PM PDT 24
Finished Mar 31 12:29:13 PM PDT 24
Peak memory 211688 kb
Host smart-4df0d26a-f058-4fd5-a10b-da943a7bacbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201893016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1201893016
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1871319644
Short name T591
Test name
Test status
Simulation time 7774468801 ps
CPU time 12.78 seconds
Started Mar 31 12:47:16 PM PDT 24
Finished Mar 31 12:47:30 PM PDT 24
Peak memory 211884 kb
Host smart-e02dbf52-8502-4a6c-a2bc-1dcf0b3785c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871319644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1871319644
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3433898589
Short name T306
Test name
Test status
Simulation time 123935659112 ps
CPU time 286.88 seconds
Started Mar 31 12:29:03 PM PDT 24
Finished Mar 31 12:33:50 PM PDT 24
Peak memory 231028 kb
Host smart-799d11e5-dd0b-4da4-b678-7a6153c5a2a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433898589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3433898589
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.673885401
Short name T389
Test name
Test status
Simulation time 49564359941 ps
CPU time 141.51 seconds
Started Mar 31 12:47:15 PM PDT 24
Finished Mar 31 12:49:37 PM PDT 24
Peak memory 213120 kb
Host smart-dee9fa98-85b7-411e-8183-2cdc38a3a0dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673885401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.673885401
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2011470748
Short name T143
Test name
Test status
Simulation time 756773635 ps
CPU time 9.32 seconds
Started Mar 31 12:47:17 PM PDT 24
Finished Mar 31 12:47:26 PM PDT 24
Peak memory 212368 kb
Host smart-38103152-ce72-47c7-9efa-54d9d70e92df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011470748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2011470748
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.526218047
Short name T302
Test name
Test status
Simulation time 5898946565 ps
CPU time 18.68 seconds
Started Mar 31 12:29:05 PM PDT 24
Finished Mar 31 12:29:24 PM PDT 24
Peak memory 213048 kb
Host smart-cc240b65-d11b-44a3-9054-20be441510b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526218047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.526218047
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1435690638
Short name T295
Test name
Test status
Simulation time 7937307290 ps
CPU time 16.24 seconds
Started Mar 31 12:47:14 PM PDT 24
Finished Mar 31 12:47:31 PM PDT 24
Peak memory 211732 kb
Host smart-21af346e-4aa7-429d-a310-4ae5fd96a0d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435690638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1435690638
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3505743632
Short name T201
Test name
Test status
Simulation time 3113734611 ps
CPU time 9.99 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 211612 kb
Host smart-e2329217-93d3-4525-b7cb-a8d7086e2cfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505743632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3505743632
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2129689354
Short name T12
Test name
Test status
Simulation time 188165094 ps
CPU time 9.83 seconds
Started Mar 31 12:28:57 PM PDT 24
Finished Mar 31 12:29:07 PM PDT 24
Peak memory 219696 kb
Host smart-f9b09f1b-94d1-4ee9-91ae-d2fdb7bf37fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129689354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2129689354
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3233495088
Short name T487
Test name
Test status
Simulation time 6895656757 ps
CPU time 29.24 seconds
Started Mar 31 12:47:16 PM PDT 24
Finished Mar 31 12:47:46 PM PDT 24
Peak memory 214356 kb
Host smart-423354de-4f70-4fcf-b29e-27d7fe44c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233495088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3233495088
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3864462606
Short name T113
Test name
Test status
Simulation time 435008253 ps
CPU time 10.6 seconds
Started Mar 31 12:47:16 PM PDT 24
Finished Mar 31 12:47:27 PM PDT 24
Peak memory 219852 kb
Host smart-31742db1-9b1c-40f8-a19d-8632eac2e4f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864462606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3864462606
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.430336915
Short name T278
Test name
Test status
Simulation time 3693104042 ps
CPU time 18.74 seconds
Started Mar 31 12:28:55 PM PDT 24
Finished Mar 31 12:29:20 PM PDT 24
Peak memory 212752 kb
Host smart-270c7f21-35d6-446b-905f-b77542796798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430336915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.430336915
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1106057448
Short name T317
Test name
Test status
Simulation time 1107653370 ps
CPU time 11.07 seconds
Started Mar 31 12:47:23 PM PDT 24
Finished Mar 31 12:47:34 PM PDT 24
Peak memory 211748 kb
Host smart-eb054f53-7ad0-4ed1-9fcd-ba85bfdfcd23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106057448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1106057448
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1938696178
Short name T33
Test name
Test status
Simulation time 175148661 ps
CPU time 4.18 seconds
Started Mar 31 12:29:02 PM PDT 24
Finished Mar 31 12:29:06 PM PDT 24
Peak memory 211612 kb
Host smart-2d24e7c2-b9ef-418d-a38e-8056b84150ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938696178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1938696178
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3729011276
Short name T376
Test name
Test status
Simulation time 17825408359 ps
CPU time 130.29 seconds
Started Mar 31 12:28:51 PM PDT 24
Finished Mar 31 12:31:01 PM PDT 24
Peak memory 230140 kb
Host smart-f7820062-07f2-4082-a861-17be1fda7894
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729011276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3729011276
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.721644657
Short name T199
Test name
Test status
Simulation time 34271513427 ps
CPU time 349.64 seconds
Started Mar 31 12:47:21 PM PDT 24
Finished Mar 31 12:53:11 PM PDT 24
Peak memory 228932 kb
Host smart-930e10be-0a0e-4a05-a354-30c02863bd42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721644657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.721644657
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2952041733
Short name T569
Test name
Test status
Simulation time 14505038606 ps
CPU time 32.98 seconds
Started Mar 31 12:29:04 PM PDT 24
Finished Mar 31 12:29:38 PM PDT 24
Peak memory 212716 kb
Host smart-46f8082a-2109-496f-a965-4b1d05e092d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952041733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2952041733
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4033732809
Short name T142
Test name
Test status
Simulation time 1318179354 ps
CPU time 11.62 seconds
Started Mar 31 12:47:21 PM PDT 24
Finished Mar 31 12:47:34 PM PDT 24
Peak memory 212228 kb
Host smart-9e3cb981-bbe7-4d71-930c-10e6f0191605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033732809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4033732809
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3455661137
Short name T421
Test name
Test status
Simulation time 192846585 ps
CPU time 5.5 seconds
Started Mar 31 12:47:24 PM PDT 24
Finished Mar 31 12:47:30 PM PDT 24
Peak memory 211636 kb
Host smart-c898f04e-ba90-463b-b995-2b8f5565a401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455661137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3455661137
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.438695806
Short name T233
Test name
Test status
Simulation time 10177986008 ps
CPU time 14.52 seconds
Started Mar 31 12:28:47 PM PDT 24
Finished Mar 31 12:29:01 PM PDT 24
Peak memory 211576 kb
Host smart-c65257ee-6866-4ec4-8e0d-e84930c16e2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438695806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.438695806
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3312334007
Short name T444
Test name
Test status
Simulation time 9596911410 ps
CPU time 31.9 seconds
Started Mar 31 12:28:55 PM PDT 24
Finished Mar 31 12:29:27 PM PDT 24
Peak memory 219880 kb
Host smart-cb925625-d845-49d1-b2c5-9008105cebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312334007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3312334007
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3511793199
Short name T410
Test name
Test status
Simulation time 2025332076 ps
CPU time 12.66 seconds
Started Mar 31 12:47:18 PM PDT 24
Finished Mar 31 12:47:31 PM PDT 24
Peak memory 214148 kb
Host smart-2ab617a9-96a1-4bf2-acb8-8ea59b7e54b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511793199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3511793199
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2000886906
Short name T645
Test name
Test status
Simulation time 2943469960 ps
CPU time 27.76 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:28 PM PDT 24
Peak memory 213972 kb
Host smart-022f1c71-f94c-4acc-b630-e38aa903e4ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000886906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2000886906
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2435187001
Short name T343
Test name
Test status
Simulation time 3851610670 ps
CPU time 15.56 seconds
Started Mar 31 12:47:16 PM PDT 24
Finished Mar 31 12:47:32 PM PDT 24
Peak memory 214928 kb
Host smart-72821f37-6f3c-48b0-86cb-5e9d295373e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435187001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2435187001
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3002718002
Short name T367
Test name
Test status
Simulation time 38698172959 ps
CPU time 968.25 seconds
Started Mar 31 12:47:24 PM PDT 24
Finished Mar 31 01:03:32 PM PDT 24
Peak memory 235244 kb
Host smart-e3a8753a-0885-458b-ab3d-8a878451b50c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002718002 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3002718002
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2010055434
Short name T49
Test name
Test status
Simulation time 7271240133 ps
CPU time 15.52 seconds
Started Mar 31 12:47:22 PM PDT 24
Finished Mar 31 12:47:38 PM PDT 24
Peak memory 211736 kb
Host smart-404bbe61-03fa-4391-85d4-b0eea3240137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010055434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2010055434
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.383665469
Short name T511
Test name
Test status
Simulation time 1848917510 ps
CPU time 15.03 seconds
Started Mar 31 12:28:56 PM PDT 24
Finished Mar 31 12:29:11 PM PDT 24
Peak memory 211684 kb
Host smart-764b1167-a9e4-4dc6-901e-b9229a20d970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383665469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.383665469
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2216153389
Short name T52
Test name
Test status
Simulation time 22351228726 ps
CPU time 132.17 seconds
Started Mar 31 12:47:29 PM PDT 24
Finished Mar 31 12:49:42 PM PDT 24
Peak memory 219120 kb
Host smart-798cffb8-eb6f-4186-903f-94d223c18d2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216153389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2216153389
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3432813872
Short name T670
Test name
Test status
Simulation time 16472714003 ps
CPU time 238.08 seconds
Started Mar 31 12:29:18 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 229324 kb
Host smart-802b3eab-968b-46e7-8a35-5b2289b4533f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432813872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3432813872
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2102320969
Short name T431
Test name
Test status
Simulation time 1319627348 ps
CPU time 11.61 seconds
Started Mar 31 12:28:54 PM PDT 24
Finished Mar 31 12:29:06 PM PDT 24
Peak memory 213028 kb
Host smart-90be10e4-9ab0-47c7-9ecd-2e330d807153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102320969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2102320969
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3737562004
Short name T16
Test name
Test status
Simulation time 4080719693 ps
CPU time 21.56 seconds
Started Mar 31 12:47:23 PM PDT 24
Finished Mar 31 12:47:45 PM PDT 24
Peak memory 212404 kb
Host smart-ff9f23eb-ed4c-4183-a1e8-1542c490d210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737562004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3737562004
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1236640132
Short name T486
Test name
Test status
Simulation time 4119761972 ps
CPU time 11.15 seconds
Started Mar 31 12:29:14 PM PDT 24
Finished Mar 31 12:29:25 PM PDT 24
Peak memory 211680 kb
Host smart-00f3258a-af3b-40fe-a70d-253da58053ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236640132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1236640132
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2748626241
Short name T375
Test name
Test status
Simulation time 757161200 ps
CPU time 9.9 seconds
Started Mar 31 12:47:22 PM PDT 24
Finished Mar 31 12:47:32 PM PDT 24
Peak memory 211516 kb
Host smart-0345f121-5a34-4135-bf46-6e1dda518c78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2748626241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2748626241
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1364908494
Short name T602
Test name
Test status
Simulation time 593154397 ps
CPU time 13.8 seconds
Started Mar 31 12:29:05 PM PDT 24
Finished Mar 31 12:29:19 PM PDT 24
Peak memory 214044 kb
Host smart-dd1c85f8-daed-4ae4-b2f9-677052a51f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364908494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1364908494
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2381276261
Short name T509
Test name
Test status
Simulation time 4196515437 ps
CPU time 37.93 seconds
Started Mar 31 12:47:21 PM PDT 24
Finished Mar 31 12:47:59 PM PDT 24
Peak memory 213536 kb
Host smart-e0d95acf-9fcf-4f99-b54b-669db73d1b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381276261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2381276261
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2791314334
Short name T445
Test name
Test status
Simulation time 5812995441 ps
CPU time 49.91 seconds
Started Mar 31 12:28:56 PM PDT 24
Finished Mar 31 12:29:46 PM PDT 24
Peak memory 219852 kb
Host smart-da1dd827-a504-4667-af03-b18478dbeba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791314334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2791314334
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2142116818
Short name T678
Test name
Test status
Simulation time 3339257817 ps
CPU time 9.22 seconds
Started Mar 31 12:47:23 PM PDT 24
Finished Mar 31 12:47:32 PM PDT 24
Peak memory 211884 kb
Host smart-c7dcb778-bf03-48d8-a678-bf0b357cb747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142116818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2142116818
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3679475533
Short name T303
Test name
Test status
Simulation time 2441223486 ps
CPU time 16.23 seconds
Started Mar 31 12:29:17 PM PDT 24
Finished Mar 31 12:29:34 PM PDT 24
Peak memory 211772 kb
Host smart-340a22c1-0043-4acc-a625-42e04672943d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679475533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3679475533
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1363492090
Short name T642
Test name
Test status
Simulation time 2605146815 ps
CPU time 131.98 seconds
Started Mar 31 12:47:22 PM PDT 24
Finished Mar 31 12:49:34 PM PDT 24
Peak memory 239400 kb
Host smart-97575844-d166-4e36-a135-52c1c33b0f9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363492090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1363492090
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3258210515
Short name T216
Test name
Test status
Simulation time 135600220952 ps
CPU time 255.85 seconds
Started Mar 31 12:29:00 PM PDT 24
Finished Mar 31 12:33:16 PM PDT 24
Peak memory 234172 kb
Host smart-64aa2b25-d556-4d44-a634-76a43251ec8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258210515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3258210515
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1969001724
Short name T2
Test name
Test status
Simulation time 168748712 ps
CPU time 9.42 seconds
Started Mar 31 12:47:29 PM PDT 24
Finished Mar 31 12:47:39 PM PDT 24
Peak memory 212372 kb
Host smart-879e84c4-ed1d-4c4a-a323-3bcf73ff265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969001724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1969001724
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2910228506
Short name T617
Test name
Test status
Simulation time 4316423991 ps
CPU time 34.67 seconds
Started Mar 31 12:28:49 PM PDT 24
Finished Mar 31 12:29:23 PM PDT 24
Peak memory 212696 kb
Host smart-997ae34d-2828-4f0f-b60d-f7b3b3005387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910228506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2910228506
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2271432049
Short name T471
Test name
Test status
Simulation time 101351205 ps
CPU time 5.46 seconds
Started Mar 31 12:29:17 PM PDT 24
Finished Mar 31 12:29:23 PM PDT 24
Peak memory 211556 kb
Host smart-af826fc4-6eee-4f84-9dbc-2b33bcbc32b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271432049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2271432049
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2371446167
Short name T118
Test name
Test status
Simulation time 2766075992 ps
CPU time 9.7 seconds
Started Mar 31 12:47:23 PM PDT 24
Finished Mar 31 12:47:33 PM PDT 24
Peak memory 211768 kb
Host smart-38c62174-f8e1-41cc-b15d-549f27894758
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371446167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2371446167
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2498338551
Short name T241
Test name
Test status
Simulation time 742883445 ps
CPU time 9.86 seconds
Started Mar 31 12:28:55 PM PDT 24
Finished Mar 31 12:29:05 PM PDT 24
Peak memory 219716 kb
Host smart-ec59d852-419b-47ef-9311-9265331e95b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498338551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2498338551
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2661409567
Short name T411
Test name
Test status
Simulation time 255526378 ps
CPU time 10.35 seconds
Started Mar 31 12:47:21 PM PDT 24
Finished Mar 31 12:47:32 PM PDT 24
Peak memory 213764 kb
Host smart-15e52bb8-c521-43f9-a948-6e3c2efe3dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661409567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2661409567
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2476545668
Short name T590
Test name
Test status
Simulation time 1308112364 ps
CPU time 10.27 seconds
Started Mar 31 12:47:24 PM PDT 24
Finished Mar 31 12:47:34 PM PDT 24
Peak memory 211536 kb
Host smart-5c884474-b506-4e77-a901-4b7b82b486cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476545668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2476545668
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.399789104
Short name T237
Test name
Test status
Simulation time 23550494095 ps
CPU time 29.74 seconds
Started Mar 31 12:28:53 PM PDT 24
Finished Mar 31 12:29:28 PM PDT 24
Peak memory 213336 kb
Host smart-884d0a23-b797-4284-94dc-5a3365b255a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399789104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.399789104
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1660682600
Short name T510
Test name
Test status
Simulation time 82125929016 ps
CPU time 869.25 seconds
Started Mar 31 12:47:22 PM PDT 24
Finished Mar 31 01:01:52 PM PDT 24
Peak memory 232728 kb
Host smart-d9d784c0-b1c1-44f7-a178-0e3e62c17c64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660682600 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1660682600
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1115562846
Short name T203
Test name
Test status
Simulation time 1038044695 ps
CPU time 4.21 seconds
Started Mar 31 12:28:41 PM PDT 24
Finished Mar 31 12:28:45 PM PDT 24
Peak memory 211728 kb
Host smart-912cdbcc-5f00-4478-8dd8-60cf78e92855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115562846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1115562846
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1608971274
Short name T363
Test name
Test status
Simulation time 181016422 ps
CPU time 5.39 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:45:44 PM PDT 24
Peak memory 211700 kb
Host smart-d46e0094-9ffe-4615-a124-ceec1e1d3ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608971274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1608971274
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1130666608
Short name T548
Test name
Test status
Simulation time 12371283029 ps
CPU time 85.2 seconds
Started Mar 31 12:45:40 PM PDT 24
Finished Mar 31 12:47:05 PM PDT 24
Peak memory 220848 kb
Host smart-8f6fd4ec-03c1-4913-b122-9ba6807081dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130666608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1130666608
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.860033536
Short name T347
Test name
Test status
Simulation time 18689525654 ps
CPU time 162.08 seconds
Started Mar 31 12:28:34 PM PDT 24
Finished Mar 31 12:31:17 PM PDT 24
Peak memory 230316 kb
Host smart-81ed590d-db94-4de8-92c7-0688bf344efb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860033536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.860033536
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3697440370
Short name T47
Test name
Test status
Simulation time 4303277469 ps
CPU time 32.74 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:46:12 PM PDT 24
Peak memory 214464 kb
Host smart-eb12a1b8-3255-4104-904a-5b7f6a6f14ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697440370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3697440370
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.847944859
Short name T178
Test name
Test status
Simulation time 15452278479 ps
CPU time 25.02 seconds
Started Mar 31 12:28:35 PM PDT 24
Finished Mar 31 12:29:00 PM PDT 24
Peak memory 213156 kb
Host smart-c81490af-a567-458e-a4bc-de0156ac8653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847944859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.847944859
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2121906735
Short name T456
Test name
Test status
Simulation time 433366176 ps
CPU time 5.33 seconds
Started Mar 31 12:28:36 PM PDT 24
Finished Mar 31 12:28:41 PM PDT 24
Peak memory 211572 kb
Host smart-f69c08af-11c8-4311-b46e-b64c2f027969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121906735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2121906735
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3295768940
Short name T538
Test name
Test status
Simulation time 183760766 ps
CPU time 5.28 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:45:44 PM PDT 24
Peak memory 211656 kb
Host smart-58359465-9a75-4f5c-a8ff-fa3915baa690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295768940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3295768940
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1712704853
Short name T655
Test name
Test status
Simulation time 4049613991 ps
CPU time 37.59 seconds
Started Mar 31 12:28:30 PM PDT 24
Finished Mar 31 12:29:08 PM PDT 24
Peak memory 219812 kb
Host smart-d25bf089-3771-4f49-be7f-eb106f7bbeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712704853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1712704853
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2257777381
Short name T526
Test name
Test status
Simulation time 2829921260 ps
CPU time 30.61 seconds
Started Mar 31 12:45:40 PM PDT 24
Finished Mar 31 12:46:11 PM PDT 24
Peak memory 219448 kb
Host smart-24a79f61-3108-4e37-a960-d32c56d2b224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257777381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2257777381
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2311328878
Short name T158
Test name
Test status
Simulation time 1673872449 ps
CPU time 23.12 seconds
Started Mar 31 12:28:23 PM PDT 24
Finished Mar 31 12:28:46 PM PDT 24
Peak memory 215904 kb
Host smart-591c7e7e-065e-4554-b82c-5dd52cb5dbcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311328878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2311328878
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2667401020
Short name T265
Test name
Test status
Simulation time 194370042 ps
CPU time 10 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:45:49 PM PDT 24
Peak memory 213240 kb
Host smart-abdd3f4f-3795-46ab-b355-9ed441de4473
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667401020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2667401020
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1408261395
Short name T56
Test name
Test status
Simulation time 126907078584 ps
CPU time 2650.48 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 01:12:40 PM PDT 24
Peak memory 246136 kb
Host smart-ed124833-6d17-438f-944b-92a3c9c4eba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408261395 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1408261395
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1832510193
Short name T610
Test name
Test status
Simulation time 409041090 ps
CPU time 7.17 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:48 PM PDT 24
Peak memory 211756 kb
Host smart-a9ce2b27-9e31-4269-8380-52e6d6ab1230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832510193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1832510193
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4060786981
Short name T393
Test name
Test status
Simulation time 1313337801 ps
CPU time 9.75 seconds
Started Mar 31 12:45:41 PM PDT 24
Finished Mar 31 12:45:51 PM PDT 24
Peak memory 211740 kb
Host smart-ea52cf49-10b5-41d5-9547-a80205661b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060786981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4060786981
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3295114155
Short name T557
Test name
Test status
Simulation time 4465123099 ps
CPU time 111.06 seconds
Started Mar 31 12:45:42 PM PDT 24
Finished Mar 31 12:47:33 PM PDT 24
Peak memory 213064 kb
Host smart-6612dee8-d872-42b2-9965-083d5ccd1861
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295114155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3295114155
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4138022696
Short name T457
Test name
Test status
Simulation time 35549413322 ps
CPU time 145.36 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:31:10 PM PDT 24
Peak memory 220108 kb
Host smart-788746a0-7113-4f36-b7a2-64d8cb419e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138022696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4138022696
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2060869598
Short name T289
Test name
Test status
Simulation time 250346479 ps
CPU time 9.3 seconds
Started Mar 31 12:28:44 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 212228 kb
Host smart-d0e48998-5bf7-4b0c-8de0-e53320e54b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060869598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2060869598
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3161651562
Short name T224
Test name
Test status
Simulation time 15413214705 ps
CPU time 32.78 seconds
Started Mar 31 12:45:40 PM PDT 24
Finished Mar 31 12:46:13 PM PDT 24
Peak memory 212612 kb
Host smart-009d2e52-f6de-40a7-9c64-40441065d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161651562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3161651562
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1476057039
Short name T454
Test name
Test status
Simulation time 6464028902 ps
CPU time 8.53 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:45:47 PM PDT 24
Peak memory 211724 kb
Host smart-61368d6e-ed30-45db-bb33-14876eba4b11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476057039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1476057039
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2782975068
Short name T264
Test name
Test status
Simulation time 4261434827 ps
CPU time 11.71 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:51 PM PDT 24
Peak memory 211624 kb
Host smart-1a24f658-4c6a-4e4a-90e6-69d4a323e356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782975068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2782975068
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2381170170
Short name T512
Test name
Test status
Simulation time 3809510833 ps
CPU time 38.43 seconds
Started Mar 31 12:28:29 PM PDT 24
Finished Mar 31 12:29:07 PM PDT 24
Peak memory 213536 kb
Host smart-147e4eca-1c5b-40a6-b1ec-229888737d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381170170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2381170170
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3781723229
Short name T70
Test name
Test status
Simulation time 8603067034 ps
CPU time 24.98 seconds
Started Mar 31 12:45:38 PM PDT 24
Finished Mar 31 12:46:03 PM PDT 24
Peak memory 219940 kb
Host smart-0e62c994-4f6f-46bb-8f72-fcabc16fa32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781723229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3781723229
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2067835942
Short name T656
Test name
Test status
Simulation time 3299875509 ps
CPU time 30.38 seconds
Started Mar 31 12:45:42 PM PDT 24
Finished Mar 31 12:46:13 PM PDT 24
Peak memory 215000 kb
Host smart-a88e1b85-e5d3-46b0-80f8-39ca156934ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067835942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2067835942
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2594009450
Short name T88
Test name
Test status
Simulation time 288153789 ps
CPU time 14.34 seconds
Started Mar 31 12:28:50 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 215396 kb
Host smart-18e65eea-1abb-49eb-a1f7-09eab0ac7251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594009450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2594009450
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1563430312
Short name T27
Test name
Test status
Simulation time 15733288537 ps
CPU time 589.8 seconds
Started Mar 31 12:28:32 PM PDT 24
Finished Mar 31 12:38:21 PM PDT 24
Peak memory 222208 kb
Host smart-4691e542-e254-41f2-9a08-acc5f219fb10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563430312 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1563430312
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.368376034
Short name T385
Test name
Test status
Simulation time 1827409490 ps
CPU time 15.42 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 211656 kb
Host smart-a3ab0bed-d0ac-4ea9-919c-468e7d0827a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368376034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.368376034
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.952743583
Short name T640
Test name
Test status
Simulation time 2465590033 ps
CPU time 14.82 seconds
Started Mar 31 12:45:46 PM PDT 24
Finished Mar 31 12:46:01 PM PDT 24
Peak memory 211816 kb
Host smart-9568dbbe-2c2d-48c8-8436-d0125f6975b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952743583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.952743583
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2914505547
Short name T51
Test name
Test status
Simulation time 10483995747 ps
CPU time 166.01 seconds
Started Mar 31 12:45:39 PM PDT 24
Finished Mar 31 12:48:25 PM PDT 24
Peak memory 213032 kb
Host smart-5aed64e6-d752-4d2e-8b23-1ee9ded58d6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914505547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2914505547
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1425609230
Short name T190
Test name
Test status
Simulation time 1380439023 ps
CPU time 17.61 seconds
Started Mar 31 12:28:45 PM PDT 24
Finished Mar 31 12:29:03 PM PDT 24
Peak memory 212292 kb
Host smart-d26185de-9a56-45dd-9856-d865b20ead15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425609230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1425609230
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3248900379
Short name T334
Test name
Test status
Simulation time 947624131 ps
CPU time 15.62 seconds
Started Mar 31 12:45:47 PM PDT 24
Finished Mar 31 12:46:03 PM PDT 24
Peak memory 212184 kb
Host smart-95b729be-4898-4432-af4c-52221928996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248900379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3248900379
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3423464636
Short name T340
Test name
Test status
Simulation time 13387589305 ps
CPU time 11.49 seconds
Started Mar 31 12:45:41 PM PDT 24
Finished Mar 31 12:45:53 PM PDT 24
Peak memory 211636 kb
Host smart-cb65cbf0-d1e7-4e2c-9729-70860f9b37d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423464636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3423464636
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.615743313
Short name T474
Test name
Test status
Simulation time 4120829082 ps
CPU time 11.47 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 12:28:36 PM PDT 24
Peak memory 211660 kb
Host smart-d4bfaf60-59c4-4aab-91e0-86261646bf2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615743313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.615743313
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1914557877
Short name T223
Test name
Test status
Simulation time 11388523880 ps
CPU time 30.37 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:29:04 PM PDT 24
Peak memory 219860 kb
Host smart-2264937f-6265-4a0e-b5c1-45276afa7f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914557877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1914557877
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2772058632
Short name T629
Test name
Test status
Simulation time 8887120926 ps
CPU time 28.22 seconds
Started Mar 31 12:45:40 PM PDT 24
Finished Mar 31 12:46:09 PM PDT 24
Peak memory 214048 kb
Host smart-8170729a-a8b8-432a-9dd3-7db05bf67409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772058632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2772058632
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.759442767
Short name T455
Test name
Test status
Simulation time 13350008922 ps
CPU time 125.63 seconds
Started Mar 31 12:45:45 PM PDT 24
Finished Mar 31 12:47:50 PM PDT 24
Peak memory 219920 kb
Host smart-07569362-6612-4172-90ba-842463ce055c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759442767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.759442767
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.857734415
Short name T594
Test name
Test status
Simulation time 1592009093 ps
CPU time 21.12 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 219744 kb
Host smart-8ef16e4f-87b8-4769-9c9f-7ab0c6198f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857734415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.857734415
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2691749142
Short name T648
Test name
Test status
Simulation time 333103864 ps
CPU time 4.19 seconds
Started Mar 31 12:45:46 PM PDT 24
Finished Mar 31 12:45:50 PM PDT 24
Peak memory 211768 kb
Host smart-960de5a0-7775-4ac5-b68e-89b7eb96a3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691749142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2691749142
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3756538288
Short name T35
Test name
Test status
Simulation time 1487103273 ps
CPU time 13.18 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:28:47 PM PDT 24
Peak memory 211620 kb
Host smart-cc28ceaf-0e19-4fe9-a2e4-287bd36793cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756538288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3756538288
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1475557896
Short name T447
Test name
Test status
Simulation time 21850503966 ps
CPU time 248.18 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:32:47 PM PDT 24
Peak memory 236732 kb
Host smart-d67895b0-16a5-4ece-92f6-14c986627b8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475557896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1475557896
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.460907676
Short name T22
Test name
Test status
Simulation time 80479212156 ps
CPU time 260.68 seconds
Started Mar 31 12:45:47 PM PDT 24
Finished Mar 31 12:50:08 PM PDT 24
Peak memory 229116 kb
Host smart-cdacf0fb-1980-4c47-9f85-f8975ca07777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460907676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.460907676
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2354311026
Short name T663
Test name
Test status
Simulation time 4121902357 ps
CPU time 33.27 seconds
Started Mar 31 12:45:50 PM PDT 24
Finished Mar 31 12:46:23 PM PDT 24
Peak memory 212304 kb
Host smart-8602bec2-8f3e-4d2a-9d24-b0b592399e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354311026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2354311026
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2396708170
Short name T539
Test name
Test status
Simulation time 3275528127 ps
CPU time 27.68 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 12:29:01 PM PDT 24
Peak memory 212248 kb
Host smart-28b4c55e-72ba-4f66-9641-2e12938422b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396708170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2396708170
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2970424262
Short name T406
Test name
Test status
Simulation time 7732892381 ps
CPU time 16.24 seconds
Started Mar 31 12:45:48 PM PDT 24
Finished Mar 31 12:46:04 PM PDT 24
Peak memory 211784 kb
Host smart-75da0898-a64c-4827-80d2-9aa147913eef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970424262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2970424262
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.856771178
Short name T9
Test name
Test status
Simulation time 2848645877 ps
CPU time 10.05 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:49 PM PDT 24
Peak memory 211648 kb
Host smart-024c4af8-e1ff-4d62-94e1-519013a1259a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856771178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.856771178
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2158199972
Short name T159
Test name
Test status
Simulation time 3403040016 ps
CPU time 34.72 seconds
Started Mar 31 12:45:49 PM PDT 24
Finished Mar 31 12:46:24 PM PDT 24
Peak memory 219796 kb
Host smart-a8a8061b-ee40-4d7d-9c44-fa1af094d85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158199972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2158199972
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4073965652
Short name T432
Test name
Test status
Simulation time 185626808 ps
CPU time 9.9 seconds
Started Mar 31 12:28:39 PM PDT 24
Finished Mar 31 12:28:49 PM PDT 24
Peak memory 213396 kb
Host smart-d442c9b9-b665-497f-9ad3-53d9f7b42018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073965652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4073965652
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1822577246
Short name T140
Test name
Test status
Simulation time 3493257103 ps
CPU time 26.18 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:29:06 PM PDT 24
Peak memory 213764 kb
Host smart-224b1a24-893f-40e3-814a-3b59a25011e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822577246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1822577246
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2995857225
Short name T319
Test name
Test status
Simulation time 6028950527 ps
CPU time 59.75 seconds
Started Mar 31 12:45:50 PM PDT 24
Finished Mar 31 12:46:50 PM PDT 24
Peak memory 219852 kb
Host smart-429e914b-1852-4ded-8e4b-b89fb9a98f9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995857225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2995857225
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1125347219
Short name T297
Test name
Test status
Simulation time 6159249110 ps
CPU time 13.84 seconds
Started Mar 31 12:28:40 PM PDT 24
Finished Mar 31 12:28:54 PM PDT 24
Peak memory 211808 kb
Host smart-863ac661-e4f2-4b67-9dd4-58b0e74de592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125347219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1125347219
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3983560703
Short name T618
Test name
Test status
Simulation time 1106561677 ps
CPU time 10.36 seconds
Started Mar 31 12:45:48 PM PDT 24
Finished Mar 31 12:45:59 PM PDT 24
Peak memory 211704 kb
Host smart-bc491490-0657-4f1d-a4ad-e4f666338665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983560703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3983560703
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3093157170
Short name T485
Test name
Test status
Simulation time 13261667425 ps
CPU time 148.32 seconds
Started Mar 31 12:28:34 PM PDT 24
Finished Mar 31 12:31:03 PM PDT 24
Peak memory 230244 kb
Host smart-11cc5b04-59ba-4555-b9dc-fde2bd39a922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093157170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3093157170
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3528536127
Short name T370
Test name
Test status
Simulation time 23272445749 ps
CPU time 204.27 seconds
Started Mar 31 12:45:48 PM PDT 24
Finished Mar 31 12:49:12 PM PDT 24
Peak memory 215212 kb
Host smart-7a8cec7f-dd1f-4474-867a-3b9d95def22a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528536127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3528536127
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2366658279
Short name T300
Test name
Test status
Simulation time 4268953493 ps
CPU time 22.24 seconds
Started Mar 31 12:45:50 PM PDT 24
Finished Mar 31 12:46:12 PM PDT 24
Peak memory 212292 kb
Host smart-b0d088ac-0865-4d9f-8af4-9706f6a1b6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366658279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2366658279
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2570852447
Short name T614
Test name
Test status
Simulation time 4108618483 ps
CPU time 22.09 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:50 PM PDT 24
Peak memory 212392 kb
Host smart-2a6e4b35-e737-43f1-9661-7aad17e03b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570852447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2570852447
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3383404211
Short name T335
Test name
Test status
Simulation time 351776000 ps
CPU time 5.36 seconds
Started Mar 31 12:28:43 PM PDT 24
Finished Mar 31 12:28:49 PM PDT 24
Peak memory 211552 kb
Host smart-b95a6c65-fc2d-4ae4-97e0-88a7640ac20c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383404211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3383404211
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3440747545
Short name T407
Test name
Test status
Simulation time 1421704938 ps
CPU time 13.5 seconds
Started Mar 31 12:45:45 PM PDT 24
Finished Mar 31 12:45:58 PM PDT 24
Peak memory 211684 kb
Host smart-b48af69e-d05c-446d-8478-3b8ea5019eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440747545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3440747545
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1320262789
Short name T168
Test name
Test status
Simulation time 3003895829 ps
CPU time 32.45 seconds
Started Mar 31 12:45:46 PM PDT 24
Finished Mar 31 12:46:18 PM PDT 24
Peak memory 215200 kb
Host smart-aae5e958-5421-4b33-a347-fdfb7b8bac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320262789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1320262789
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4220178022
Short name T258
Test name
Test status
Simulation time 6629874794 ps
CPU time 39.01 seconds
Started Mar 31 12:28:36 PM PDT 24
Finished Mar 31 12:29:15 PM PDT 24
Peak memory 219836 kb
Host smart-e2d8c6b2-4ad2-46d7-8392-4fb42422a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220178022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4220178022
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1123398087
Short name T636
Test name
Test status
Simulation time 6773331575 ps
CPU time 31.02 seconds
Started Mar 31 12:28:28 PM PDT 24
Finished Mar 31 12:28:59 PM PDT 24
Peak memory 219908 kb
Host smart-69402f0d-28b8-4a63-bbef-c7541d3b385d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123398087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1123398087
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1631702824
Short name T541
Test name
Test status
Simulation time 663493448 ps
CPU time 9.99 seconds
Started Mar 31 12:45:50 PM PDT 24
Finished Mar 31 12:46:00 PM PDT 24
Peak memory 212020 kb
Host smart-bededb43-9518-47f0-9aa2-1baa4a964561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631702824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1631702824
Directory /workspace/9.rom_ctrl_stress_all/latest
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