SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
87.50 | 87.50 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_tlul_cg | 87.50 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_regs_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_rom_invalid_condition | 2 | 1 | 1 | 50.00 | 100 | 1 | 1 | 0 | |
cp_rom_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 2675445 | 1 | T1 | 1 | T2 | 4 | T4 | 64 | ||||
req_and_done | 7 | 1 | T18 | 1 | T50 | 1 | T120 | 1 | ||||
req_before_done | 4 | 1 | T77 | 1 | T84 | 1 | T85 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
check_invalid | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
check_valid | 635684118 | 1 | T1 | 285471 | T2 | 734697 | T3 | 559214 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 2996647 | 1 | T1 | 18 | T2 | 6 | T4 | 1 | ||||
req_and_done | 128 | 1 | T8 | 1 | T15 | 1 | T46 | 1 | ||||
req_before_done | 463 | 1 | T4 | 3 | T6 | 2 | T10 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |