Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	100995	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2077558

1

T1

18

T2

6

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	582074	1			T1	18		T2	6		T4	103
values[0x0]	783381	1			T18	36095		T19	50932		T20	6963
values[0x1]	813098	1			T18	37245		T19	52810		T20	7385

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51048	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2127505

1

T1

18

T2

6

T4

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8394	1			T5	2		T6	8		T8	1
valid_sources[0x01]	7986	1			T8	2		T80	1		T135	1
valid_sources[0x02]	7902	1			T4	4		T6	18		T8	1
valid_sources[0x03]	8369	1			T4	1		T47	4		T16	1
valid_sources[0x04]	8305	1			T4	2		T8	3		T11	16
valid_sources[0x05]	9593	1			T4	1		T7	9		T8	3
valid_sources[0x06]	7944	1			T6	8		T10	1		T17	3
valid_sources[0x07]	8849	1			T4	1		T8	1		T119	3
valid_sources[0x08]	9479	1			T6	8		T10	3		T17	1
valid_sources[0x09]	9235	1			T2	1		T4	2		T17	1
valid_sources[0x0a]	7737	1			T8	3		T10	1		T16	1
valid_sources[0x0b]	8236	1			T8	4		T11	11		T17	1
valid_sources[0x0c]	9651	1			T10	1		T15	39		T18	253
valid_sources[0x0d]	10271	1			T4	1		T8	1		T12	4
valid_sources[0x0e]	9640	1			T10	1		T46	74		T81	6
valid_sources[0x0f]	9318	1			T8	1		T17	1		T119	2
valid_sources[0x10]	7498	1			T6	3		T8	1		T17	3
valid_sources[0x11]	8390	1			T8	3		T17	4		T136	4
valid_sources[0x12]	8569	1			T1	7		T6	1		T7	5
valid_sources[0x13]	9065	1			T8	1		T10	1		T81	2
valid_sources[0x14]	8976	1			T6	2		T11	1		T16	1
valid_sources[0x15]	8386	1			T6	3		T8	1		T10	1
valid_sources[0x16]	9125	1			T2	2		T6	20		T17	1
valid_sources[0x17]	8706	1			T4	1		T8	1		T119	4
valid_sources[0x18]	9371	1			T10	1		T47	35		T135	7
valid_sources[0x19]	10161	1			T8	3		T17	1		T16	1
valid_sources[0x1a]	8199	1			T8	4		T10	2		T11	6
valid_sources[0x1b]	8493	1			T6	2		T8	1		T17	1
valid_sources[0x1c]	8183	1			T6	2		T10	1		T135	1
valid_sources[0x1d]	7269	1			T8	1		T17	1		T18	197
valid_sources[0x1e]	7799	1			T4	3		T8	3		T16	1
valid_sources[0x1f]	8416	1			T17	1		T137	1		T12	4
valid_sources[0x20]	8715	1			T47	20		T16	1		T12	1
valid_sources[0x21]	6924	1			T5	3		T8	1		T17	2
valid_sources[0x22]	8968	1			T137	1		T135	2		T18	324
valid_sources[0x23]	6823	1			T47	17		T17	2		T135	3
valid_sources[0x24]	7771	1			T7	1		T46	30		T47	15
valid_sources[0x25]	8276	1			T4	1		T135	2		T18	458
valid_sources[0x26]	8370	1			T10	1		T11	13		T80	3
valid_sources[0x27]	7364	1			T8	3		T10	1		T47	64
valid_sources[0x28]	7097	1			T4	1		T6	7		T8	1
valid_sources[0x29]	6928	1			T10	1		T135	2		T138	4
valid_sources[0x2a]	8172	1			T12	3		T135	1		T138	2
valid_sources[0x2b]	10953	1			T4	1		T17	1		T119	4
valid_sources[0x2c]	8438	1			T4	1		T8	6		T17	1
valid_sources[0x2d]	8533	1			T8	2		T46	14		T136	5
valid_sources[0x2e]	8390	1			T6	2		T16	1		T119	2
valid_sources[0x2f]	9056	1			T8	3		T11	7		T16	1
valid_sources[0x30]	7299	1			T8	4		T16	1		T135	1
valid_sources[0x31]	8301	1			T4	1		T10	1		T15	16
valid_sources[0x32]	7436	1			T10	2		T80	1		T12	7
valid_sources[0x33]	9451	1			T8	1		T10	1		T135	3
valid_sources[0x34]	8444	1			T8	3		T12	5		T139	4
valid_sources[0x35]	7745	1			T1	6		T8	2		T10	1
valid_sources[0x36]	7568	1			T8	2		T48	1		T16	1
valid_sources[0x37]	8760	1			T135	1		T138	3		T18	497
valid_sources[0x38]	9592	1			T10	1		T81	12		T135	2
valid_sources[0x39]	8445	1			T138	1		T18	375		T140	1
valid_sources[0x3a]	8735	1			T137	2		T135	2		T138	3
valid_sources[0x3b]	9151	1			T8	3		T139	15		T135	4
valid_sources[0x3c]	7850	1			T8	1		T16	1		T135	1
valid_sources[0x3d]	9139	1			T4	2		T7	2		T8	1
valid_sources[0x3e]	8089	1			T4	1		T8	6		T10	1
valid_sources[0x3f]	10003	1			T8	7		T11	1		T48	4
valid_sources[0x40]	11057	1			T5	2		T8	2		T17	1
valid_sources[0x41]	8399	1			T7	1		T12	6		T139	2
valid_sources[0x42]	8015	1			T46	16		T17	1		T16	1
valid_sources[0x43]	7616	1			T4	1		T137	2		T18	349
valid_sources[0x44]	8986	1			T12	1		T135	3		T13	2
valid_sources[0x45]	9498	1			T4	5		T11	5		T16	1
valid_sources[0x46]	9560	1			T16	1		T135	3		T13	1
valid_sources[0x47]	8897	1			T6	1		T10	1		T46	12
valid_sources[0x48]	7980	1			T8	2		T10	1		T12	5
valid_sources[0x49]	7380	1			T17	1		T119	1		T135	2
valid_sources[0x4a]	9057	1			T10	1		T13	8		T18	485
valid_sources[0x4b]	8580	1			T4	2		T8	3		T13	3
valid_sources[0x4c]	7850	1			T8	1		T12	1		T135	3
valid_sources[0x4d]	9701	1			T6	3		T11	13		T46	17
valid_sources[0x4e]	7534	1			T8	6		T135	1		T18	456
valid_sources[0x4f]	8102	1			T119	3		T139	5		T135	2
valid_sources[0x50]	9921	1			T8	1		T48	1		T80	2
valid_sources[0x51]	9483	1			T17	4		T119	3		T136	1
valid_sources[0x52]	8796	1			T8	1		T11	2		T17	1
valid_sources[0x53]	8697	1			T119	4		T18	411		T141	40
valid_sources[0x54]	9031	1			T4	1		T6	8		T10	1
valid_sources[0x55]	8573	1			T4	1		T7	4		T8	1
valid_sources[0x56]	8746	1			T6	12		T10	1		T80	3
valid_sources[0x57]	7342	1			T4	2		T6	4		T10	3
valid_sources[0x58]	7886	1			T4	2		T17	1		T119	6
valid_sources[0x59]	9250	1			T2	1		T10	1		T139	10
valid_sources[0x5a]	7207	1			T8	1		T48	4		T119	1
valid_sources[0x5b]	6938	1			T4	1		T7	4		T11	2
valid_sources[0x5c]	8296	1			T17	2		T135	5		T138	4
valid_sources[0x5d]	9705	1			T10	1		T11	3		T17	5
valid_sources[0x5e]	7523	1			T15	10		T17	1		T135	1
valid_sources[0x5f]	8963	1			T6	3		T8	3		T119	3
valid_sources[0x60]	8294	1			T8	2		T17	1		T135	4
valid_sources[0x61]	8171	1			T11	1		T17	2		T119	1
valid_sources[0x62]	6939	1			T4	2		T6	1		T8	2
valid_sources[0x63]	9061	1			T6	2		T7	1		T83	3
valid_sources[0x64]	7525	1			T4	2		T7	1		T10	1
valid_sources[0x65]	8283	1			T6	1		T17	2		T18	315
valid_sources[0x66]	7792	1			T4	1		T10	1		T48	1
valid_sources[0x67]	9265	1			T8	1		T119	1		T12	1
valid_sources[0x68]	7601	1			T17	2		T119	1		T137	1
valid_sources[0x69]	7102	1			T4	1		T8	1		T17	1
valid_sources[0x6a]	8242	1			T2	2		T8	3		T17	1
valid_sources[0x6b]	9751	1			T12	3		T138	1		T18	330
valid_sources[0x6c]	9163	1			T4	1		T119	3		T138	1
valid_sources[0x6d]	8050	1			T8	1		T10	1		T17	1
valid_sources[0x6e]	8944	1			T4	2		T8	3		T83	2
valid_sources[0x6f]	8375	1			T6	5		T8	1		T10	1
valid_sources[0x70]	8860	1			T8	3		T17	3		T119	1
valid_sources[0x71]	9958	1			T11	3		T17	2		T135	1
valid_sources[0x72]	8741	1			T135	8		T18	379		T19	606
valid_sources[0x73]	8442	1			T8	2		T10	2		T16	1
valid_sources[0x74]	9318	1			T137	2		T139	8		T18	430
valid_sources[0x75]	9229	1			T119	2		T137	1		T12	1
valid_sources[0x76]	7009	1			T17	1		T135	1		T83	1
valid_sources[0x77]	9694	1			T4	2		T7	3		T17	4
valid_sources[0x78]	8556	1			T8	3		T10	1		T17	2
valid_sources[0x79]	7976	1			T4	5		T17	1		T81	4
valid_sources[0x7a]	7345	1			T4	1		T139	10		T18	307
valid_sources[0x7b]	9586	1			T6	5		T8	1		T11	2
valid_sources[0x7c]	8877	1			T10	1		T17	1		T135	4
valid_sources[0x7d]	7514	1			T10	1		T15	26		T47	40
valid_sources[0x7e]	9986	1			T17	3		T119	1		T136	1
valid_sources[0x7f]	7641	1			T10	1		T47	27		T17	1
valid_sources[0x80]	8814	1			T8	2		T10	1		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

523390

1

T1

18

T2

6

T4

10

values[0x0]

all_enables

biggest_size

776524

1

T18

35772

T19

50496

T20

6915

values[0x1]

all_enables

biggest_size

777644

1

T18

35667

T19

50446

T20

7082

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1568318

1

T1

4

T2

20

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	434660	1			T1	14		T2	41		T3	1
values[0x0]	597738	1			T9	4		T36	3		T37	8
values[0x1]	692019	1			T9	10		T38	1		T36	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70844	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1653573

1

T1

6

T2

25

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5512	1			T7	2		T11	2		T16	1
valid_sources[0x01]	6516	1			T1	2		T18	333		T60	1
valid_sources[0x02]	7112	1			T10	1		T16	1		T83	4
valid_sources[0x03]	8040	1			T18	352		T60	1		T19	444
valid_sources[0x04]	6935	1			T13	21		T18	421		T19	616
valid_sources[0x05]	6862	1			T5	1		T18	211		T55	1
valid_sources[0x06]	7110	1			T18	343		T60	1		T61	1
valid_sources[0x07]	7337	1			T18	290		T60	1		T141	1
valid_sources[0x08]	7023	1			T7	2		T10	1		T11	2
valid_sources[0x09]	6595	1			T10	1		T18	284		T60	1
valid_sources[0x0a]	6814	1			T1	1		T10	1		T11	2
valid_sources[0x0b]	7558	1			T10	1		T80	6		T35	1
valid_sources[0x0c]	7653	1			T10	1		T11	1		T18	218
valid_sources[0x0d]	6429	1			T7	2		T11	1		T18	271
valid_sources[0x0e]	6704	1			T11	1		T18	264		T55	4
valid_sources[0x0f]	6908	1			T18	276		T19	388		T40	1
valid_sources[0x10]	6356	1			T1	1		T11	2		T16	1
valid_sources[0x11]	7777	1			T18	255		T140	1		T19	399
valid_sources[0x12]	6378	1			T1	1		T12	9		T18	329
valid_sources[0x13]	6723	1			T81	64		T12	2		T18	376
valid_sources[0x14]	7139	1			T11	2		T16	1		T18	458
valid_sources[0x15]	6938	1			T14	1		T11	2		T18	295
valid_sources[0x16]	6563	1			T10	1		T14	2		T80	2
valid_sources[0x17]	7300	1			T6	1		T10	1		T11	1
valid_sources[0x18]	6300	1			T7	2		T10	1		T18	288
valid_sources[0x19]	6285	1			T10	1		T48	1		T119	3
valid_sources[0x1a]	6439	1			T11	1		T18	282		T19	544
valid_sources[0x1b]	6300	1			T6	3		T11	1		T80	2
valid_sources[0x1c]	6627	1			T10	1		T11	1		T18	431
valid_sources[0x1d]	6721	1			T7	1		T14	2		T18	280
valid_sources[0x1e]	6777	1			T7	2		T119	1		T25	1
valid_sources[0x1f]	6338	1			T16	1		T80	4		T12	1
valid_sources[0x20]	6412	1			T11	2		T48	2		T18	363
valid_sources[0x21]	6959	1			T18	367		T60	3		T32	1
valid_sources[0x22]	7161	1			T37	1		T18	345		T19	299
valid_sources[0x23]	6237	1			T11	1		T18	369		T19	466
valid_sources[0x24]	6461	1			T1	1		T18	233		T140	2
valid_sources[0x25]	6709	1			T6	3		T7	2		T11	1
valid_sources[0x26]	7326	1			T11	3		T18	353		T26	2
valid_sources[0x27]	6710	1			T10	1		T119	1		T25	6
valid_sources[0x28]	6732	1			T10	1		T11	1		T18	269
valid_sources[0x29]	6468	1			T10	1		T18	306		T140	1
valid_sources[0x2a]	5984	1			T5	1		T16	1		T18	407
valid_sources[0x2b]	6579	1			T82	1		T18	275		T60	3
valid_sources[0x2c]	6667	1			T5	2		T6	6		T48	3
valid_sources[0x2d]	5106	1			T5	1		T119	1		T25	2
valid_sources[0x2e]	6899	1			T16	2		T25	1		T18	283
valid_sources[0x2f]	5936	1			T10	2		T12	4		T39	3
valid_sources[0x30]	6282	1			T6	1		T10	1		T12	11
valid_sources[0x31]	7786	1			T11	2		T48	1		T25	1
valid_sources[0x32]	6866	1			T11	5		T12	7		T18	354
valid_sources[0x33]	7140	1			T5	2		T11	1		T48	1
valid_sources[0x34]	5880	1			T10	1		T11	1		T119	5
valid_sources[0x35]	6321	1			T119	1		T18	309		T60	1
valid_sources[0x36]	6789	1			T18	385		T26	1		T141	1
valid_sources[0x37]	7001	1			T10	1		T16	1		T18	260
valid_sources[0x38]	5711	1			T18	211		T56	1		T60	1
valid_sources[0x39]	7270	1			T6	5		T82	1		T12	5
valid_sources[0x3a]	7231	1			T11	1		T13	11		T18	349
valid_sources[0x3b]	7237	1			T5	1		T11	1		T119	1
valid_sources[0x3c]	6338	1			T5	1		T11	2		T12	5
valid_sources[0x3d]	6301	1			T10	1		T11	3		T119	2
valid_sources[0x3e]	6554	1			T1	1		T18	275		T19	374
valid_sources[0x3f]	6894	1			T2	1		T11	1		T119	1
valid_sources[0x40]	6615	1			T1	1		T119	4		T82	1
valid_sources[0x41]	5918	1			T136	10		T18	286		T60	1
valid_sources[0x42]	7438	1			T2	6		T82	1		T18	346
valid_sources[0x43]	6146	1			T10	1		T18	343		T19	182
valid_sources[0x44]	7690	1			T18	364		T60	2		T19	563
valid_sources[0x45]	6650	1			T18	312		T60	1		T32	1
valid_sources[0x46]	6534	1			T18	337		T19	258		T20	46
valid_sources[0x47]	6732	1			T2	1		T48	2		T18	346
valid_sources[0x48]	7849	1			T11	1		T16	2		T18	302
valid_sources[0x49]	7281	1			T10	1		T18	326		T60	2
valid_sources[0x4a]	5393	1			T18	256		T27	1		T19	183
valid_sources[0x4b]	5938	1			T10	1		T18	265		T19	235
valid_sources[0x4c]	6067	1			T80	1		T18	285		T27	1
valid_sources[0x4d]	7610	1			T18	287		T19	257		T20	60
valid_sources[0x4e]	7206	1			T18	293		T19	316		T20	58
valid_sources[0x4f]	7788	1			T6	3		T10	2		T11	1
valid_sources[0x50]	5525	1			T83	5		T18	323		T142	1
valid_sources[0x51]	6323	1			T18	230		T60	2		T140	1
valid_sources[0x52]	5818	1			T10	1		T82	1		T18	240
valid_sources[0x53]	6203	1			T11	2		T22	1		T18	422
valid_sources[0x54]	6584	1			T48	5		T18	258		T55	10
valid_sources[0x55]	7097	1			T10	1		T11	2		T18	450
valid_sources[0x56]	6018	1			T11	1		T18	355		T60	2
valid_sources[0x57]	7787	1			T2	3		T18	269		T19	389
valid_sources[0x58]	6922	1			T80	2		T18	296		T60	2
valid_sources[0x59]	6481	1			T18	403		T140	2		T19	201
valid_sources[0x5a]	6796	1			T11	1		T119	1		T83	9
valid_sources[0x5b]	7794	1			T10	2		T11	3		T18	337
valid_sources[0x5c]	6083	1			T10	1		T11	1		T37	4
valid_sources[0x5d]	7006	1			T18	333		T19	448		T20	43
valid_sources[0x5e]	7296	1			T7	1		T18	270		T60	1
valid_sources[0x5f]	7127	1			T11	1		T80	2		T18	268
valid_sources[0x60]	5654	1			T48	1		T18	254		T60	1
valid_sources[0x61]	6315	1			T10	1		T18	318		T60	2
valid_sources[0x62]	7320	1			T5	1		T12	2		T18	371
valid_sources[0x63]	5931	1			T48	2		T30	1		T82	1
valid_sources[0x64]	6753	1			T11	1		T18	238		T60	1
valid_sources[0x65]	7254	1			T18	302		T60	1		T19	678
valid_sources[0x66]	6810	1			T6	4		T18	254		T60	2
valid_sources[0x67]	7133	1			T6	1		T119	4		T18	272
valid_sources[0x68]	7404	1			T31	22		T18	281		T19	641
valid_sources[0x69]	7617	1			T11	1		T25	1		T18	293
valid_sources[0x6a]	5863	1			T11	1		T18	303		T58	1
valid_sources[0x6b]	7937	1			T10	2		T18	356		T60	1
valid_sources[0x6c]	6076	1			T11	1		T82	2		T25	3
valid_sources[0x6d]	7252	1			T11	1		T16	1		T119	2
valid_sources[0x6e]	7147	1			T16	2		T18	257		T60	1
valid_sources[0x6f]	6498	1			T1	1		T11	2		T37	2
valid_sources[0x70]	7263	1			T119	1		T18	259		T26	1
valid_sources[0x71]	6997	1			T6	2		T18	310		T59	32
valid_sources[0x72]	7278	1			T16	2		T18	270		T19	443
valid_sources[0x73]	6101	1			T18	217		T60	1		T19	310
valid_sources[0x74]	7087	1			T18	304		T19	536		T20	58
valid_sources[0x75]	6473	1			T6	3		T18	293		T60	1
valid_sources[0x76]	6269	1			T33	20		T14	1		T82	1
valid_sources[0x77]	6611	1			T11	1		T82	1		T18	183
valid_sources[0x78]	5588	1			T18	270		T60	1		T140	1
valid_sources[0x79]	6297	1			T10	1		T18	293		T19	385
valid_sources[0x7a]	7234	1			T11	4		T82	2		T18	508
valid_sources[0x7b]	5645	1			T18	302		T60	1		T27	1
valid_sources[0x7c]	7413	1			T7	1		T11	1		T36	2
valid_sources[0x7d]	7678	1			T11	1		T12	20		T18	338
valid_sources[0x7e]	6538	1			T2	1		T7	2		T18	383
valid_sources[0x7f]	6392	1			T37	2		T12	3		T18	284
valid_sources[0x80]	6214	1			T6	1		T11	1		T18	405

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

398885

1

T1

4

T2

20

T3

1

values[0x0]

all_enables

biggest_size

585280

1

T9

2

T36

1

T37

1

values[0x1]

all_enables

biggest_size

584153

1

T9

4

T38

1

T36

1