Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3797974

1

T4

93

T6

271

T7

57

full_word

2422894

1

T1

12

T2

4

T4

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6220578	1			T1	12		T2	4		T4	103
auto[TlIntgErrCmd]	93	1			T62	9		T63	3		T64	4
auto[TlIntgErrData]	93	1			T62	6		T63	4		T64	3
auto[TlIntgErrBoth]	104	1			T62	5		T63	3		T64	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002068

1

T1

12

T2

4

T4

103

auto[1]

5218800

1

T18

236869

T19

341932

T20

43131

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	428709	1			T4	93		T6	271		T7	57
auto[TlIntgErrNone]	partial	auto[1]	3369001	1			T18	152134		T19	221607		T20	26714
auto[TlIntgErrNone]	full_word	auto[0]	573233	1			T1	12		T2	4		T4	10
auto[TlIntgErrNone]	full_word	auto[1]	1849635	1			T18	84735		T19	120325		T20	16417
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T62	6		T63	2		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T62	3		T63	1		T64	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T64	1		T121	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T121	1		T126	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T62	3		T63	2		T122	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T62	1		T63	2		T64	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T62	1		T129	2		T125	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T62	1		T125	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T62	1		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T62	4		T63	2		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T124	1		T131	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T129	1		T128	1		T133	1