Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1414255

1

T1

141

T3

65

T4

282

full_word

885109

1

T1

21

T3

9

T4

31

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2298744	1			T1	162		T3	74		T4	313
auto[TlIntgErrCmd]	214	1			T56	4		T57	5		T58	3
auto[TlIntgErrData]	170	1			T56	5		T57	4		T58	4
auto[TlIntgErrBoth]	236	1			T56	11		T57	11		T58	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

374041

1

T1

162

T3

74

T4

313

auto[1]

1925323

1

T13

174938

T16

218872

T17

115047

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	163612	1			T1	141		T3	65		T4	282
auto[TlIntgErrNone]	partial	auto[1]	1250072	1			T13	111892		T16	142801		T17	75447
auto[TlIntgErrNone]	full_word	auto[0]	210155	1			T1	21		T3	9		T4	31
auto[TlIntgErrNone]	full_word	auto[1]	674905	1			T13	63046		T16	76071		T17	39600
auto[TlIntgErrCmd]	partial	auto[0]	80	1			T56	2		T57	2		T58	2
auto[TlIntgErrCmd]	partial	auto[1]	119	1			T56	2		T57	2		T58	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T121	1		T122	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T57	1		T113	1		T124	2
auto[TlIntgErrData]	partial	auto[0]	79	1			T56	1		T57	2		T58	1
auto[TlIntgErrData]	partial	auto[1]	79	1			T56	4		T57	2		T58	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T58	1		T113	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T125	1		T126	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	90	1			T56	4		T57	4		T58	2
auto[TlIntgErrBoth]	partial	auto[1]	124	1			T56	6		T57	6		T58	1
auto[TlIntgErrBoth]	full_word	auto[0]	13	1			T56	1		T57	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T112	1		T117	1		T118	2