Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.98 100.00 98.28 97.33 100.00 79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.98 100.00 98.28 97.33 100.00 79.31



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.98 100.00 98.28 97.33 100.00 79.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.45 96.96 93.11 97.88 100.00 98.68 98.04


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_alert_sender 100.00 100.00
gen_fsm_scramble_enabled.u_checker_fsm 96.36 100.00 97.22 90.00 100.00 100.00 90.91
gen_rom_scramble_enabled.u_rom 97.06 88.24 100.00 100.00 100.00
regs_tlul_assert_device 100.00 100.00 100.00 100.00
rom_ctrl_regs_csr_assert 100.00 100.00
rom_tlul_assert_device 99.30 100.00 100.00 97.90
u_mux 95.24 100.00 85.71 100.00
u_reg_regs 99.72 99.41 99.21 100.00 100.00 100.00
u_tl_adapter_rom 94.13 91.45 84.93 99.07 95.18 100.00
u_tl_rom_h2d_buf 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rom_ctrl
Line No.TotalCoveredPercent
TOTAL6565100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42211100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN43711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
125 1 1
126 1 1
127 1 1
128 1 1
131 1 1
207 1 1
253 1 1
308 1 1
409 8 8
410 8 8
412 8 8
413 8 8
415 8 8
416 8 8
420 1 1
422 1 1
425 1 1
426 1 1
427 1 1
428 1 1
433 1 1
437 1 1


Cond Coverage for Module : rom_ctrl
TotalCoveredPercent
Conditions585798.28
Logical585798.28
Non-Logical00
Event00

 LINE       207
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       253
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T12,T14
11CoveredT1,T3,T4

 LINE       413
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       413
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       413
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       420
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT29,T30,T31
10Not Covered

 LINE       422
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T12,T14
10CoveredT6,T8,T12

 LINE       433
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT2,T5,T7
10CoveredT1,T2,T3
11CoveredT2,T5,T7

 LINE       437
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT6,T12,T14
010CoveredT6,T8,T12
100CoveredT29,T30,T31

Toggle Coverage for Module : rom_ctrl
TotalCoveredPercent
Totals 61 56 91.80
Total Bits 2882 2805 97.33
Total Bits 0->1 1441 1402 97.29
Total Bits 1->0 1441 1403 97.36

Ports 61 56 91.80
Port Bits 2882 2805 97.33
Port Bits 0->1 1441 1402 97.29
Port Bits 1->0 1441 1403 97.36

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T6 Yes T1,T2,T3 INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
rom_tl_i.d_ready Yes Yes T1,T3,T5 Yes T1,T2,T3 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T1,T7,T9 Yes T1,T9,T13 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
rom_tl_i.a_address[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
rom_tl_i.a_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
rom_tl_i.a_size[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[2:0] Yes Yes T1,T9,T13 Yes T1,T2,T9 INPUT
rom_tl_i.a_valid Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
rom_tl_o.a_ready Yes Yes T1,T3,T6 Yes T1,T2,T3 OUTPUT
rom_tl_o.d_error Yes Yes T13,T16,T17 Yes T13,T16,T17 OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
rom_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T3,*T4 Yes T1,T3,T4 OUTPUT
rom_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
rom_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
rom_tl_o.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] Yes Yes *T13,*T16,*T17 Yes T13,T16,T17 OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T3,T5 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_source[7:0] Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
regs_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
regs_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_o.d_error Yes Yes T13,T16,T17 Yes T13,T16,T17 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T1,T3,T6 Yes T1,T3,T6 OUTPUT
regs_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
regs_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T1,T3,T6 Yes T1,T2,T3 OUTPUT
regs_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_source[7:0] Yes Yes T3,T6,T10 Yes T3,T6,T7 OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T1,*T3,*T6 Yes T1,T3,T6 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T1,T2,T3 Yes T1,T3,T6 OUTPUT
keymgr_data_o.valid Yes Yes T1,T3,T6 Yes T1,T2,T3 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T1,T6,T8 Yes T1,T3,T4 OUTPUT
kmac_data_i.error No Yes T8,T24,T25 No INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T3,T6,T10 Yes T1,T6,T8 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T6,T8,T12 Yes T6,T12,T13 INPUT
kmac_data_i.done Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_i.ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
kmac_data_o.last Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.strb[7:0] No No No OUTPUT
kmac_data_o.data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
kmac_data_o.data[63:39] No No No OUTPUT
kmac_data_o.valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rom_ctrl
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 207 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 207 (rom_tl_i.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Module : rom_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 29 29 100.00 23 79.31
Cover properties 0 0 0
Cover sequences 0 0 0
Total 29 29 100.00 23 79.31




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxOKnown_A 264878140 264709278 0 0
BusRomIndicesMatch_A 264864242 264701387 0 0
FpvSecCmFifoRptrCheck_A 264878140 0 0 0
FpvSecCmFifoWptrCheck_A 264878140 0 0 0
FpvSecCmRegWeOnehotCheck_A 264878140 100 0 0
KeymgrDataODataKnown_A 264878140 29386085 0 0
KeymgrDataODataKnown_AKnownEnable 264878140 264709278 0 0
KeymgrDataOValidKnown_A 264878140 264709278 0 0
KeymgrValidChk_A 264878140 0 0 313
KmacDataODataKnown_A 264878140 235193585 0 0
KmacDataODataKnown_AKnownEnable 264878140 264709278 0 0
KmacDataOValidKnown_A 264878140 264709278 0 0
PwrmgrDataChk_A 264878140 0 0 313
PwrmgrDataOKnown_A 264878140 264709278 0 0
RegsTlOAReadyKnown_A 264878140 264709278 0 0
RegsTlODDataKnown_A 264878140 3958799 0 0
RegsTlODDataKnown_AKnownEnable 264878140 264709278 0 0
RegsTlODValidKnown_A 264878140 264709278 0 0
RomTlOAReadyKnown_A 264878140 264709278 0 0
RomTlODDataKnown_A 264878140 3780997 0 0
RomTlODDataKnown_AKnownEnable 264878140 264709278 0 0
RomTlODValidKnown_A 264878140 264709278 0 0
StabilityChkKmac_A 264878140 235191288 0 0
StabilityChkkeymgr_A 264878140 29384981 0 0
TlAccessChk_A 264878140 235323193 0 0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A 264878140 100 0 0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A 264878140 0 0 0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A 264878140 403 0 0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A 264878140 0 0 0


AlertTxOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

BusRomIndicesMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264864242 264701387 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

FpvSecCmFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 0 0 0

FpvSecCmFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 100 0 0
T29 365850 20 0 0
T30 272936 20 0 0
T31 133750 20 0 0
T32 0 20 0 0
T33 0 20 0 0
T34 918903 0 0 0
T35 164198 0 0 0
T36 165142 0 0 0
T37 139260 0 0 0
T38 279286 0 0 0
T39 16597 0 0 0
T40 133087 0 0 0

KeymgrDataODataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 29386085 0 0
T1 36061 3117 0 0
T2 228788 284 0 0
T3 34971 2064 0 0
T4 303952 818 0 0
T5 196445 139 0 0
T6 540676 14436 0 0
T7 196827 40 0 0
T8 606877 134 0 0
T9 116057 1419 0 0
T10 558388 1587 0 0

KeymgrDataODataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

KeymgrDataOValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

KeymgrValidChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 0 0 313

KmacDataODataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 235193585 0 0
T1 36061 32752 0 0
T2 228788 228342 0 0
T3 34971 32752 0 0
T4 303952 303050 0 0
T5 196445 196197 0 0
T6 540676 538861 0 0
T7 196827 196669 0 0
T8 606877 606338 0 0
T9 116057 114515 0 0
T10 558388 556459 0 0

KmacDataODataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

KmacDataOValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

PwrmgrDataChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 0 0 313

PwrmgrDataOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RegsTlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RegsTlODDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 3958799 0 0
T1 36061 64 0 0
T2 228788 7 0 0
T3 34971 82 0 0
T4 303952 0 0 0
T5 196445 7 0 0
T6 540676 28 0 0
T7 196827 11 0 0
T8 606877 1 0 0
T9 116057 0 0 0
T10 558388 99 0 0
T12 0 23 0 0
T13 0 175609 0 0

RegsTlODDataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RegsTlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RomTlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RomTlODDataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 3780997 0 0
T1 36061 162 0 0
T2 228788 0 0 0
T3 34971 383 0 0
T4 303952 313 0 0
T5 196445 0 0 0
T6 540676 0 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 156 0 0
T10 558388 379 0 0
T11 0 233 0 0
T12 0 3 0 0
T13 0 207099 0 0
T14 0 12 0 0
T15 0 71 0 0

RomTlODDataKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RomTlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

StabilityChkKmac_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 235191288 0 0
T1 36061 32750 0 0
T2 228788 228341 0 0
T3 34971 32750 0 0
T4 303952 303049 0 0
T5 196445 196196 0 0
T6 540676 538858 0 0
T7 196827 196668 0 0
T8 606877 606336 0 0
T9 116057 114514 0 0
T10 558388 556457 0 0

StabilityChkkeymgr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 29384981 0 0
T1 36061 3115 0 0
T2 228788 283 0 0
T3 34971 2062 0 0
T4 303952 817 0 0
T5 196445 138 0 0
T6 540676 14425 0 0
T7 196827 39 0 0
T8 606877 133 0 0
T9 116057 1418 0 0
T10 558388 1585 0 0

TlAccessChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 235323193 0 0
T1 36061 32794 0 0
T2 228788 228433 0 0
T3 34971 32794 0 0
T4 303952 303083 0 0
T5 196445 196218 0 0
T6 540676 539003 0 0
T7 196827 196725 0 0
T8 606877 606614 0 0
T9 116057 114541 0 0
T10 558388 556610 0 0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 100 0 0
T29 365850 20 0 0
T30 272936 20 0 0
T31 133750 20 0 0
T32 0 20 0 0
T33 0 20 0 0
T34 918903 0 0 0
T35 164198 0 0 0
T36 165142 0 0 0
T37 139260 0 0 0
T38 279286 0 0 0
T39 16597 0 0 0
T40 133087 0 0 0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 0 0 0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 403 0 0
T6 540676 5 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 0 0 0
T10 558388 0 0 0
T11 394193 0 0 0
T12 266127 10 0 0
T13 286966 0 0 0
T14 336595 22 0 0
T15 312822 0 0 0
T26 0 5 0 0
T29 0 20 0 0
T30 0 20 0 0
T31 0 20 0 0
T32 0 20 0 0
T41 0 5 0 0
T42 0 5 0 0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%