Module Definition
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Module Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.22 96.92 83.05 88.89 100.00 u_tl_adapter_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 100.00 100.00
u_tlul_data_integ_dec 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_regs.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 100.00 100.00
u_tlul_data_integ_dec 100.00 100.00 100.00

Line Coverage for Module : tlul_cmd_intg_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Module : tlul_cmd_intg_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 916 916 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 916 916 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 313 313 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 313 313 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_regs.u_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
22 1 1
44 unreachable
49 1 1


Assert Coverage for Instance : tb.dut.u_reg_regs.u_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 603 603 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 603 603 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0