Module Definition
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Module Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.06 100.00 56.25 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 100.00 75.00 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.22 96.92 83.05 88.89 100.00 u_tl_adapter_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91



Module Instance : tb.dut.u_tl_adapter_rom.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.53 100.00 86.11 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.22 96.92 83.05 88.89 100.00 u_tl_adapter_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_rom.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.79 100.00 79.17 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.02 100.00 85.11 90.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.22 96.92 83.05 88.89 100.00 u_tl_adapter_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 95.33 100.00 91.30 90.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_tl_adapter_rom.u_reqfifo

SCORELINE
89.06 100.00
tb.dut.u_tl_adapter_rom.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
94.79 100.00
tb.dut.u_tl_adapter_rom.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_tl_adapter_rom.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T9
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
94.79 79.17
tb.dut.u_tl_adapter_rom.u_rspfifo

TotalCoveredPercent
Conditions241979.17
Logical241979.17
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T9
110Not Covered
111CoveredT1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
89.06 56.25
tb.dut.u_tl_adapter_rom.u_sramreqfifo

TotalCoveredPercent
Conditions16956.25
Logical16956.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
92.19 100.00
tb.dut.u_tl_adapter_rom.u_reqfifo

SCOREBRANCH
89.06 100.00
tb.dut.u_tl_adapter_rom.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
94.79 100.00
tb.dut.u_tl_adapter_rom.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 794634420 3870736 0 0
DepthKnown_A 794634420 794127834 0 0
RvalidKnown_A 794634420 794127834 0 0
WreadyKnown_A 794634420 794127834 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 794634420 3870736 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794634420 3870736 0 0
T1 108183 486 0 0
T2 686364 0 0 0
T3 104913 840 0 0
T4 911856 939 0 0
T5 589335 0 0 0
T6 1622028 0 0 0
T7 590481 0 0 0
T8 1820631 0 0 0
T9 348171 468 0 0
T10 1675164 825 0 0
T11 0 537 0 0
T12 0 9 0 0
T13 0 208403 0 0
T14 0 36 0 0
T15 0 213 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794634420 794127834 0 0
T1 108183 107733 0 0
T2 686364 686151 0 0
T3 104913 104574 0 0
T4 911856 911703 0 0
T5 589335 589071 0 0
T6 1622028 1621338 0 0
T7 590481 590295 0 0
T8 1820631 1820244 0 0
T9 348171 347880 0 0
T10 1675164 1674591 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794634420 794127834 0 0
T1 108183 107733 0 0
T2 686364 686151 0 0
T3 104913 104574 0 0
T4 911856 911703 0 0
T5 589335 589071 0 0
T6 1622028 1621338 0 0
T7 590481 590295 0 0
T8 1820631 1820244 0 0
T9 348171 347880 0 0
T10 1675164 1674591 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 794634420 794127834 0 0
T1 108183 107733 0 0
T2 686364 686151 0 0
T3 104913 104574 0 0
T4 911856 911703 0 0
T5 589335 589071 0 0
T6 1622028 1621338 0 0
T7 590481 590295 0 0
T8 1820631 1820244 0 0
T9 348171 347880 0 0
T10 1675164 1674591 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 794634420 3870736 0 0
T1 108183 486 0 0
T2 686364 0 0 0
T3 104913 840 0 0
T4 911856 939 0 0
T5 589335 0 0 0
T6 1622028 0 0 0
T7 590481 0 0 0
T8 1820631 0 0 0
T9 348171 468 0 0
T10 1675164 825 0 0
T11 0 537 0 0
T12 0 9 0 0
T13 0 208403 0 0
T14 0 36 0 0
T15 0 213 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
TotalCoveredPercent
Conditions16956.25
Logical16956.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 264878140 30791 0 0
DepthKnown_A 264878140 264709278 0 0
RvalidKnown_A 264878140 264709278 0 0
WreadyKnown_A 264878140 264709278 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 264878140 30791 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 30791 0 0
T1 36061 162 0 0
T2 228788 0 0 0
T3 34971 74 0 0
T4 303952 313 0 0
T5 196445 0 0 0
T6 540676 0 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 156 0 0
T10 558388 67 0 0
T11 0 71 0 0
T12 0 3 0 0
T13 0 652 0 0
T14 0 12 0 0
T15 0 71 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 30791 0 0
T1 36061 162 0 0
T2 228788 0 0 0
T3 34971 74 0 0
T4 303952 313 0 0
T5 196445 0 0 0
T6 540676 0 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 156 0 0
T10 558388 67 0 0
T11 0 71 0 0
T12 0 3 0 0
T13 0 652 0 0
T14 0 12 0 0
T15 0 71 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T9
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 264878140 3780997 0 0
DepthKnown_A 264878140 264709278 0 0
RvalidKnown_A 264878140 264709278 0 0
WreadyKnown_A 264878140 264709278 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 264878140 3780997 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 3780997 0 0
T1 36061 162 0 0
T2 228788 0 0 0
T3 34971 383 0 0
T4 303952 313 0 0
T5 196445 0 0 0
T6 540676 0 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 156 0 0
T10 558388 379 0 0
T11 0 233 0 0
T12 0 3 0 0
T13 0 207099 0 0
T14 0 12 0 0
T15 0 71 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 3780997 0 0
T1 36061 162 0 0
T2 228788 0 0 0
T3 34971 383 0 0
T4 303952 313 0 0
T5 196445 0 0 0
T6 540676 0 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 156 0 0
T10 558388 379 0 0
T11 0 233 0 0
T12 0 3 0 0
T13 0 207099 0 0
T14 0 12 0 0
T15 0 71 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
TotalCoveredPercent
Conditions241979.17
Logical241979.17
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T9
110Not Covered
111CoveredT1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 264878140 58948 0 0
DepthKnown_A 264878140 264709278 0 0
RvalidKnown_A 264878140 264709278 0 0
WreadyKnown_A 264878140 264709278 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 264878140 58948 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 58948 0 0
T1 36061 162 0 0
T2 228788 0 0 0
T3 34971 383 0 0
T4 303952 313 0 0
T5 196445 0 0 0
T6 540676 0 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 156 0 0
T10 558388 379 0 0
T11 0 233 0 0
T12 0 3 0 0
T13 0 652 0 0
T14 0 12 0 0
T15 0 71 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 264709278 0 0
T1 36061 35911 0 0
T2 228788 228717 0 0
T3 34971 34858 0 0
T4 303952 303901 0 0
T5 196445 196357 0 0
T6 540676 540446 0 0
T7 196827 196765 0 0
T8 606877 606748 0 0
T9 116057 115960 0 0
T10 558388 558197 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 264878140 58948 0 0
T1 36061 162 0 0
T2 228788 0 0 0
T3 34971 383 0 0
T4 303952 313 0 0
T5 196445 0 0 0
T6 540676 0 0 0
T7 196827 0 0 0
T8 606877 0 0 0
T9 116057 156 0 0
T10 558388 379 0 0
T11 0 233 0 0
T12 0 3 0 0
T13 0 652 0 0
T14 0 12 0 0
T15 0 71 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%