Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 96810 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1873891 1 T1 11 T4 6 T5 6



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 531285 1 T1 85 T4 65 T5 6
values[0x0] 707173 1 T17 14434 T21 10718 T22 73693
values[0x1] 732243 1 T17 14493 T21 10998 T22 76311



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 48644 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1922057 1 T1 53 T4 35 T5 6



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 6932 1 T1 1 T10 13 T103 2
valid_sources[0x01] 6884 1 T125 4 T81 2 T53 23
valid_sources[0x02] 7131 1 T8 1 T13 1 T65 3
valid_sources[0x03] 7529 1 T8 3 T13 1 T65 2
valid_sources[0x04] 7201 1 T8 3 T10 2 T16 1
valid_sources[0x05] 6564 1 T1 1 T16 1 T57 3
valid_sources[0x06] 6737 1 T8 2 T13 1 T12 1
valid_sources[0x07] 8098 1 T14 5 T58 12 T126 2
valid_sources[0x08] 8095 1 T1 4 T8 2 T16 1
valid_sources[0x09] 7871 1 T4 8 T8 1 T11 8
valid_sources[0x0a] 7279 1 T1 1 T12 1 T81 1
valid_sources[0x0b] 7774 1 T8 2 T14 1 T103 1
valid_sources[0x0c] 7811 1 T103 1 T16 1 T82 1
valid_sources[0x0d] 7572 1 T8 1 T33 1 T16 4
valid_sources[0x0e] 6721 1 T10 5 T80 1 T99 1
valid_sources[0x0f] 9205 1 T8 1 T103 1 T80 2
valid_sources[0x10] 8058 1 T1 1 T103 3 T17 345
valid_sources[0x11] 6664 1 T1 1 T8 4 T13 1
valid_sources[0x12] 7195 1 T8 4 T10 6 T16 1
valid_sources[0x13] 6858 1 T65 1 T101 4 T126 1
valid_sources[0x14] 9440 1 T10 6 T16 1 T81 2
valid_sources[0x15] 7387 1 T13 1 T65 1 T99 3
valid_sources[0x16] 8507 1 T65 4 T16 1 T81 2
valid_sources[0x17] 7731 1 T8 1 T65 1 T16 3
valid_sources[0x18] 8526 1 T16 1 T127 1 T128 2
valid_sources[0x19] 6564 1 T10 4 T103 2 T16 1
valid_sources[0x1a] 7050 1 T65 1 T126 1 T128 2
valid_sources[0x1b] 7181 1 T13 2 T81 3 T99 2
valid_sources[0x1c] 7492 1 T1 1 T8 1 T13 2
valid_sources[0x1d] 9226 1 T8 3 T17 146 T58 2
valid_sources[0x1e] 6589 1 T8 1 T17 102 T99 1
valid_sources[0x1f] 7936 1 T1 1 T8 2 T80 1
valid_sources[0x20] 8099 1 T1 1 T8 1 T65 1
valid_sources[0x21] 7255 1 T65 1 T80 3 T17 228
valid_sources[0x22] 7380 1 T10 12 T11 2 T17 418
valid_sources[0x23] 7632 1 T8 1 T12 1 T17 158
valid_sources[0x24] 9511 1 T8 1 T30 1 T129 1
valid_sources[0x25] 6710 1 T1 2 T10 5 T103 1
valid_sources[0x26] 7644 1 T10 2 T81 2 T17 137
valid_sources[0x27] 6887 1 T8 1 T125 1 T82 1
valid_sources[0x28] 7658 1 T1 1 T8 2 T11 1
valid_sources[0x29] 9016 1 T1 2 T33 1 T17 981
valid_sources[0x2a] 6786 1 T65 2 T16 1 T82 1
valid_sources[0x2b] 7514 1 T8 1 T65 2 T16 1
valid_sources[0x2c] 7032 1 T12 1 T14 6 T103 1
valid_sources[0x2d] 8321 1 T8 2 T10 3 T11 1
valid_sources[0x2e] 7271 1 T65 1 T103 1 T17 49
valid_sources[0x2f] 7845 1 T16 2 T80 2 T17 1360
valid_sources[0x30] 7243 1 T4 3 T10 1 T16 1
valid_sources[0x31] 6724 1 T1 1 T14 2 T102 6
valid_sources[0x32] 8003 1 T8 1 T65 2 T16 1
valid_sources[0x33] 6598 1 T102 9 T17 146 T58 2
valid_sources[0x34] 7342 1 T1 1 T11 2 T65 1
valid_sources[0x35] 7038 1 T13 1 T102 1 T82 1
valid_sources[0x36] 7261 1 T11 3 T65 2 T53 48
valid_sources[0x37] 6694 1 T99 1 T101 1 T126 1
valid_sources[0x38] 7566 1 T8 1 T17 254 T99 1
valid_sources[0x39] 7200 1 T12 5 T16 4 T58 2
valid_sources[0x3a] 7251 1 T65 1 T17 165 T101 2
valid_sources[0x3b] 7293 1 T1 3 T10 3 T16 1
valid_sources[0x3c] 7602 1 T65 2 T99 1 T127 4
valid_sources[0x3d] 7680 1 T33 2 T103 1 T16 1
valid_sources[0x3e] 7193 1 T1 6 T82 1 T99 1
valid_sources[0x3f] 7744 1 T11 1 T16 2 T17 99
valid_sources[0x40] 8637 1 T1 1 T10 1 T13 1
valid_sources[0x41] 7556 1 T4 4 T8 1 T16 1
valid_sources[0x42] 7160 1 T65 1 T103 1 T58 2
valid_sources[0x43] 7037 1 T1 1 T4 10 T8 2
valid_sources[0x44] 7124 1 T13 1 T11 1 T14 7
valid_sources[0x45] 6452 1 T10 1 T65 1 T103 1
valid_sources[0x46] 8077 1 T8 1 T65 4 T103 1
valid_sources[0x47] 6691 1 T8 1 T13 1 T103 2
valid_sources[0x48] 9282 1 T1 1 T16 3 T17 724
valid_sources[0x49] 9219 1 T14 1 T33 1 T103 1
valid_sources[0x4a] 7737 1 T8 1 T10 2 T65 3
valid_sources[0x4b] 7617 1 T102 2 T65 2 T16 1
valid_sources[0x4c] 7288 1 T8 2 T102 5 T65 2
valid_sources[0x4d] 6909 1 T1 1 T8 2 T13 2
valid_sources[0x4e] 7742 1 T65 2 T80 1 T82 1
valid_sources[0x4f] 6677 1 T65 1 T125 3 T82 1
valid_sources[0x50] 8298 1 T10 1 T80 2 T17 321
valid_sources[0x51] 8079 1 T1 1 T10 2 T12 2
valid_sources[0x52] 7786 1 T8 5 T10 12 T80 1
valid_sources[0x53] 8689 1 T8 1 T10 2 T103 1
valid_sources[0x54] 7375 1 T8 1 T102 2 T16 1
valid_sources[0x55] 7467 1 T4 3 T8 1 T13 1
valid_sources[0x56] 7545 1 T8 1 T16 2 T81 1
valid_sources[0x57] 7510 1 T11 2 T14 1 T65 1
valid_sources[0x58] 6877 1 T103 1 T16 2 T82 1
valid_sources[0x59] 7876 1 T1 4 T8 1 T99 2
valid_sources[0x5a] 8753 1 T65 1 T80 1 T17 361
valid_sources[0x5b] 7859 1 T103 3 T82 1 T17 171
valid_sources[0x5c] 7790 1 T1 2 T10 9 T13 2
valid_sources[0x5d] 6836 1 T8 1 T13 1 T81 1
valid_sources[0x5e] 8340 1 T1 1 T8 1 T13 1
valid_sources[0x5f] 7812 1 T12 2 T65 1 T130 40
valid_sources[0x60] 8519 1 T65 1 T16 1 T99 1
valid_sources[0x61] 8526 1 T10 2 T13 1 T58 3
valid_sources[0x62] 7797 1 T13 1 T17 428 T58 4
valid_sources[0x63] 6837 1 T14 2 T30 1 T131 2
valid_sources[0x64] 7417 1 T10 1 T103 1 T16 1
valid_sources[0x65] 7941 1 T17 172 T99 2 T126 1
valid_sources[0x66] 8232 1 T8 1 T17 57 T99 3
valid_sources[0x67] 7674 1 T8 1 T65 1 T16 3
valid_sources[0x68] 6510 1 T1 1 T4 1 T16 1
valid_sources[0x69] 7966 1 T8 1 T103 1 T82 1
valid_sources[0x6a] 6754 1 T13 2 T65 1 T16 1
valid_sources[0x6b] 6912 1 T13 1 T65 2 T16 1
valid_sources[0x6c] 7600 1 T8 2 T14 5 T65 1
valid_sources[0x6d] 7073 1 T10 1 T65 3 T82 1
valid_sources[0x6e] 8611 1 T13 1 T12 3 T101 1
valid_sources[0x6f] 6874 1 T12 2 T65 2 T16 1
valid_sources[0x70] 10095 1 T16 2 T58 1 T99 2
valid_sources[0x71] 8806 1 T13 1 T11 2 T103 1
valid_sources[0x72] 7138 1 T8 1 T13 1 T65 1
valid_sources[0x73] 7743 1 T13 1 T80 4 T82 2
valid_sources[0x74] 7045 1 T10 9 T65 1 T80 1
valid_sources[0x75] 8732 1 T4 1 T8 2 T11 7
valid_sources[0x76] 7953 1 T10 4 T13 1 T12 3
valid_sources[0x77] 7540 1 T8 1 T11 1 T12 3
valid_sources[0x78] 8329 1 T8 1 T13 1 T11 2
valid_sources[0x79] 7311 1 T17 241 T99 1 T127 1
valid_sources[0x7a] 8586 1 T8 2 T65 5 T33 1
valid_sources[0x7b] 6685 1 T14 7 T103 1 T16 1
valid_sources[0x7c] 9167 1 T13 1 T18 15 T80 1
valid_sources[0x7d] 7885 1 T8 3 T14 1 T103 1
valid_sources[0x7e] 7784 1 T16 1 T17 42 T99 1
valid_sources[0x7f] 7450 1 T1 1 T82 3 T57 1
valid_sources[0x80] 10754 1 T16 2 T17 111 T127 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 472356 1 T1 11 T4 6 T5 6
values[0x0] all_enables biggest_size 701004 1 T17 14291 T21 10622 T22 73046
values[0x1] all_enables biggest_size 700531 1 T17 13867 T21 10541 T22 73033


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 142497 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1431261 1 T1 20 T2 1 T4 14



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 400058 1 T1 32 T2 1 T3 10
values[0x0] 544342 1 T9 4 T20 4 T38 6
values[0x1] 629358 1 T7 2 T9 1 T20 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 65747 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1508011 1 T1 24 T2 1 T3 4



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 6025 1 T11 1 T17 153 T58 1
valid_sources[0x01] 6120 1 T5 1 T13 6 T33 1
valid_sources[0x02] 6058 1 T1 1 T102 1 T17 25
valid_sources[0x03] 6191 1 T17 70 T126 1 T132 1
valid_sources[0x04] 5724 1 T17 108 T126 1 T129 1
valid_sources[0x05] 5699 1 T17 18 T126 1 T133 1
valid_sources[0x06] 6815 1 T38 1 T11 1 T102 1
valid_sources[0x07] 6706 1 T102 1 T17 205 T134 1
valid_sources[0x08] 5518 1 T15 2 T17 5 T135 2
valid_sources[0x09] 5822 1 T12 1 T17 7 T60 1
valid_sources[0x0a] 6588 1 T17 218 T136 13 T132 1
valid_sources[0x0b] 5284 1 T33 1 T17 12 T126 3
valid_sources[0x0c] 6465 1 T1 1 T82 1 T17 267
valid_sources[0x0d] 6758 1 T17 565 T137 1 T135 1
valid_sources[0x0e] 5621 1 T5 1 T17 148 T29 25
valid_sources[0x0f] 6572 1 T17 5 T60 1 T138 1
valid_sources[0x10] 6028 1 T1 1 T17 115 T139 5
valid_sources[0x11] 6082 1 T17 209 T100 1 T140 1
valid_sources[0x12] 6851 1 T1 1 T65 64 T33 1
valid_sources[0x13] 6189 1 T81 1 T17 136 T100 1
valid_sources[0x14] 6406 1 T33 1 T17 5 T141 2
valid_sources[0x15] 5463 1 T17 279 T127 12 T142 1
valid_sources[0x16] 6072 1 T15 2 T11 2 T17 19
valid_sources[0x17] 6040 1 T4 2 T82 1 T17 107
valid_sources[0x18] 6535 1 T15 1 T33 1 T17 93
valid_sources[0x19] 6340 1 T11 1 T17 411 T57 2
valid_sources[0x1a] 6468 1 T5 1 T15 1 T34 2
valid_sources[0x1b] 6322 1 T82 2 T17 23 T60 1
valid_sources[0x1c] 6222 1 T69 16 T17 189 T143 1
valid_sources[0x1d] 5636 1 T34 1 T17 14 T100 2
valid_sources[0x1e] 6171 1 T17 24 T126 1 T137 1
valid_sources[0x1f] 5505 1 T82 1 T17 69 T141 4
valid_sources[0x20] 5545 1 T1 1 T17 13 T144 7
valid_sources[0x21] 6513 1 T17 7 T58 1 T126 1
valid_sources[0x22] 5326 1 T17 29 T126 1 T145 4
valid_sources[0x23] 5671 1 T17 47 T126 1 T137 1
valid_sources[0x24] 6332 1 T102 2 T34 1 T17 18
valid_sources[0x25] 5455 1 T70 18 T34 2 T17 21
valid_sources[0x26] 5695 1 T82 1 T17 16 T126 2
valid_sources[0x27] 6888 1 T5 1 T17 370 T126 2
valid_sources[0x28] 5949 1 T11 1 T17 113 T134 1
valid_sources[0x29] 7111 1 T33 1 T130 1 T17 98
valid_sources[0x2a] 5824 1 T11 1 T17 124 T134 1
valid_sources[0x2b] 6037 1 T7 2 T11 2 T17 159
valid_sources[0x2c] 5702 1 T17 92 T127 4 T146 4
valid_sources[0x2d] 6538 1 T15 1 T33 1 T17 12
valid_sources[0x2e] 5691 1 T5 1 T102 2 T82 1
valid_sources[0x2f] 6297 1 T1 1 T20 2 T102 1
valid_sources[0x30] 5041 1 T17 60 T147 1 T132 1
valid_sources[0x31] 6053 1 T1 2 T102 1 T17 178
valid_sources[0x32] 6540 1 T33 2 T82 1 T17 145
valid_sources[0x33] 5950 1 T1 1 T17 3 T126 1
valid_sources[0x34] 6273 1 T1 1 T17 11 T100 1
valid_sources[0x35] 6253 1 T130 1 T17 289 T28 1
valid_sources[0x36] 5551 1 T17 11 T58 1 T148 1
valid_sources[0x37] 5334 1 T1 1 T130 5 T17 24
valid_sources[0x38] 6334 1 T13 3 T17 203 T149 1
valid_sources[0x39] 6395 1 T82 1 T17 195 T58 1
valid_sources[0x3a] 6171 1 T5 1 T130 2 T17 199
valid_sources[0x3b] 5863 1 T5 1 T17 167 T132 1
valid_sources[0x3c] 6156 1 T17 14 T126 1 T27 1
valid_sources[0x3d] 7119 1 T17 189 T147 2 T141 2
valid_sources[0x3e] 6278 1 T82 3 T17 190 T143 1
valid_sources[0x3f] 5857 1 T17 26 T100 2 T35 1
valid_sources[0x40] 5750 1 T34 3 T17 26 T58 1
valid_sources[0x41] 5680 1 T5 1 T11 2 T17 21
valid_sources[0x42] 5380 1 T33 1 T82 1 T17 90
valid_sources[0x43] 6260 1 T1 1 T15 1 T102 1
valid_sources[0x44] 6017 1 T1 1 T5 1 T17 29
valid_sources[0x45] 7016 1 T81 1 T17 13 T129 1
valid_sources[0x46] 6231 1 T5 1 T102 1 T17 20
valid_sources[0x47] 6110 1 T17 125 T126 1 T129 1
valid_sources[0x48] 6259 1 T13 17 T17 137 T58 1
valid_sources[0x49] 5867 1 T11 1 T31 1 T17 5
valid_sources[0x4a] 6222 1 T34 3 T17 14 T100 1
valid_sources[0x4b] 6941 1 T5 2 T15 1 T17 535
valid_sources[0x4c] 5597 1 T130 2 T17 5 T135 2
valid_sources[0x4d] 6127 1 T82 2 T17 2 T36 1
valid_sources[0x4e] 5771 1 T17 281 T57 1 T100 2
valid_sources[0x4f] 5747 1 T102 1 T33 1 T17 22
valid_sources[0x50] 6769 1 T33 1 T17 324 T150 1
valid_sources[0x51] 6169 1 T5 1 T12 2 T82 1
valid_sources[0x52] 5575 1 T17 148 T126 1 T123 28
valid_sources[0x53] 5661 1 T5 1 T11 1 T12 3
valid_sources[0x54] 6106 1 T17 140 T28 1 T143 3
valid_sources[0x55] 6482 1 T17 157 T127 3 T133 2
valid_sources[0x56] 6584 1 T17 384 T53 32 T151 3
valid_sources[0x57] 6940 1 T17 123 T126 1 T152 1
valid_sources[0x58] 6696 1 T33 2 T34 1 T17 187
valid_sources[0x59] 6138 1 T5 1 T17 14 T126 1
valid_sources[0x5a] 5821 1 T12 2 T17 3 T128 96
valid_sources[0x5b] 6480 1 T4 4 T17 119 T58 1
valid_sources[0x5c] 5993 1 T11 2 T102 1 T82 2
valid_sources[0x5d] 5990 1 T17 12 T153 2 T137 2
valid_sources[0x5e] 6547 1 T11 1 T17 143 T58 1
valid_sources[0x5f] 7145 1 T1 1 T17 167 T126 1
valid_sources[0x60] 6312 1 T11 1 T102 1 T34 1
valid_sources[0x61] 5810 1 T17 178 T127 2 T129 1
valid_sources[0x62] 6466 1 T12 1 T68 11 T17 77
valid_sources[0x63] 7153 1 T3 1 T17 10 T54 1
valid_sources[0x64] 6288 1 T17 6 T28 1 T126 1
valid_sources[0x65] 5811 1 T17 236 T129 1 T142 1
valid_sources[0x66] 6607 1 T102 1 T17 248 T137 1
valid_sources[0x67] 5670 1 T17 16 T58 1 T46 1
valid_sources[0x68] 5389 1 T130 2 T17 158 T58 1
valid_sources[0x69] 5957 1 T1 1 T13 6 T17 15
valid_sources[0x6a] 6015 1 T20 2 T82 1 T17 190
valid_sources[0x6b] 6502 1 T17 341 T28 7 T122 2
valid_sources[0x6c] 5917 1 T17 340 T154 1 T155 1
valid_sources[0x6d] 5591 1 T17 234 T147 1 T141 2
valid_sources[0x6e] 6745 1 T9 3 T17 545 T126 2
valid_sources[0x6f] 5776 1 T3 1 T17 324 T58 2
valid_sources[0x70] 5918 1 T19 4 T11 1 T12 1
valid_sources[0x71] 6913 1 T17 134 T135 2 T139 10
valid_sources[0x72] 6592 1 T1 2 T12 1 T17 211
valid_sources[0x73] 6449 1 T17 101 T60 1 T126 1
valid_sources[0x74] 5599 1 T17 102 T35 1 T156 1
valid_sources[0x75] 6514 1 T17 36 T126 1 T141 2
valid_sources[0x76] 5624 1 T102 1 T34 1 T17 339
valid_sources[0x77] 6435 1 T12 2 T17 415 T126 1
valid_sources[0x78] 5490 1 T3 1 T17 250 T126 1
valid_sources[0x79] 5853 1 T17 208 T126 2 T149 1
valid_sources[0x7a] 6168 1 T17 228 T100 2 T126 3
valid_sources[0x7b] 5852 1 T33 1 T17 226 T157 1
valid_sources[0x7c] 6082 1 T15 1 T34 1 T17 6
valid_sources[0x7d] 5562 1 T15 1 T33 1 T82 1
valid_sources[0x7e] 6547 1 T82 5 T17 279 T137 1
valid_sources[0x7f] 6148 1 T17 20 T158 1 T159 3
valid_sources[0x80] 5988 1 T15 1 T17 146 T58 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 365202 1 T1 20 T2 1 T4 14
values[0x0] all_enables biggest_size 532979 1 T9 1 T20 1 T19 1
values[0x1] all_enables biggest_size 533080 1 T20 3 T68 1 T17 10539

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