Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3405200

1

T1

74

T4

59

T6

55

full_word

2182065

1

T1

11

T4

6

T5

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5586945	1			T1	85		T4	65		T5	4
auto[TlIntgErrCmd]	104	1			T62	3		T63	1		T64	5
auto[TlIntgErrData]	104	1			T62	3		T63	7		T64	1
auto[TlIntgErrBoth]	112	1			T62	4		T63	2		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

904168

1

T1

85

T4

65

T5

4

auto[1]

4683097

1

T17

94865

T21

73564

T22

488880

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	387483	1			T1	74		T4	59		T6	55
auto[TlIntgErrNone]	partial	auto[1]	3017414	1			T17	61340		T21	48165		T22	315656
auto[TlIntgErrNone]	full_word	auto[0]	516554	1			T1	11		T4	6		T5	4
auto[TlIntgErrNone]	full_word	auto[1]	1665494	1			T17	33525		T21	25399		T22	173224
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T62	1		T111	2		T112	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T62	2		T63	1		T64	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T64	1		T118	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T119	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T63	2		T64	1		T111	2
auto[TlIntgErrData]	partial	auto[1]	58	1			T62	1		T63	5		T111	9
auto[TlIntgErrData]	full_word	auto[0]	4	1			T62	2		T117	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T111	1		T110	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T62	1		T111	2		T115	4
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T62	3		T63	2		T64	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T112	1		T108	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T111	1		T115	1		T121	1