Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.96 92.97 97.88 100.00 98.36 97.89 99.07


Total test records in report: 769
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T550 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2786013517 Apr 16 12:21:57 PM PDT 24 Apr 16 12:22:17 PM PDT 24 346477791 ps
T551 /workspace/coverage/default/17.rom_ctrl_smoke.3691759171 Apr 16 12:22:53 PM PDT 24 Apr 16 12:24:08 PM PDT 24 7795094795 ps
T106 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.569734748 Apr 16 02:03:19 PM PDT 24 Apr 16 02:38:55 PM PDT 24 139631720404 ps
T552 /workspace/coverage/default/1.rom_ctrl_stress_all.2765556039 Apr 16 12:22:39 PM PDT 24 Apr 16 12:24:51 PM PDT 24 47329011354 ps
T553 /workspace/coverage/default/3.rom_ctrl_smoke.1786111588 Apr 16 12:21:31 PM PDT 24 Apr 16 12:22:27 PM PDT 24 23061460179 ps
T554 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2244858847 Apr 16 02:03:30 PM PDT 24 Apr 16 02:11:43 PM PDT 24 41025999423 ps
T555 /workspace/coverage/default/44.rom_ctrl_smoke.2528903048 Apr 16 02:03:23 PM PDT 24 Apr 16 02:04:12 PM PDT 24 3787197576 ps
T556 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3385196732 Apr 16 02:03:11 PM PDT 24 Apr 16 02:26:39 PM PDT 24 30639655894 ps
T557 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.559560401 Apr 16 02:03:06 PM PDT 24 Apr 16 02:03:28 PM PDT 24 20275327196 ps
T558 /workspace/coverage/default/11.rom_ctrl_smoke.1371307214 Apr 16 02:02:48 PM PDT 24 Apr 16 02:03:36 PM PDT 24 9658227097 ps
T559 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1302578593 Apr 16 02:03:20 PM PDT 24 Apr 16 02:08:48 PM PDT 24 110473416281 ps
T560 /workspace/coverage/default/21.rom_ctrl_smoke.2261905307 Apr 16 12:21:48 PM PDT 24 Apr 16 12:22:15 PM PDT 24 691172901 ps
T561 /workspace/coverage/default/42.rom_ctrl_alert_test.3697134392 Apr 16 02:03:30 PM PDT 24 Apr 16 02:03:41 PM PDT 24 172549217 ps
T562 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.620845703 Apr 16 02:02:42 PM PDT 24 Apr 16 02:10:01 PM PDT 24 73169203384 ps
T563 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.692214684 Apr 16 12:21:58 PM PDT 24 Apr 16 12:22:38 PM PDT 24 15503211140 ps
T564 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2409138630 Apr 16 02:03:01 PM PDT 24 Apr 16 02:04:03 PM PDT 24 13813953214 ps
T565 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2790217442 Apr 16 12:19:47 PM PDT 24 Apr 16 12:34:05 PM PDT 24 67354828605 ps
T566 /workspace/coverage/default/2.rom_ctrl_smoke.1770490445 Apr 16 02:02:36 PM PDT 24 Apr 16 02:02:58 PM PDT 24 359905512 ps
T567 /workspace/coverage/default/40.rom_ctrl_stress_all.960023538 Apr 16 12:21:59 PM PDT 24 Apr 16 12:22:44 PM PDT 24 22170538220 ps
T568 /workspace/coverage/default/46.rom_ctrl_alert_test.3791837371 Apr 16 02:03:20 PM PDT 24 Apr 16 02:03:54 PM PDT 24 17563391107 ps
T569 /workspace/coverage/default/30.rom_ctrl_smoke.522276290 Apr 16 12:21:51 PM PDT 24 Apr 16 12:22:52 PM PDT 24 5468453098 ps
T570 /workspace/coverage/default/8.rom_ctrl_alert_test.1551619556 Apr 16 02:02:48 PM PDT 24 Apr 16 02:03:22 PM PDT 24 3962074591 ps
T571 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4267411614 Apr 16 02:03:10 PM PDT 24 Apr 16 02:06:00 PM PDT 24 9936605620 ps
T572 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4062216500 Apr 16 12:21:58 PM PDT 24 Apr 16 12:22:18 PM PDT 24 1319612656 ps
T573 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4153797886 Apr 16 12:20:09 PM PDT 24 Apr 16 12:21:16 PM PDT 24 15705797538 ps
T574 /workspace/coverage/default/7.rom_ctrl_stress_all.3934636114 Apr 16 02:02:57 PM PDT 24 Apr 16 02:04:28 PM PDT 24 10005037457 ps
T575 /workspace/coverage/default/30.rom_ctrl_smoke.2042612459 Apr 16 02:03:14 PM PDT 24 Apr 16 02:04:36 PM PDT 24 49076703705 ps
T576 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.246323436 Apr 16 12:21:48 PM PDT 24 Apr 16 12:25:16 PM PDT 24 14381714867 ps
T577 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1620573680 Apr 16 12:21:44 PM PDT 24 Apr 16 12:22:19 PM PDT 24 15383412142 ps
T578 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1151196047 Apr 16 02:03:16 PM PDT 24 Apr 16 02:18:35 PM PDT 24 354843583427 ps
T105 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3692668126 Apr 16 12:22:12 PM PDT 24 Apr 16 12:55:48 PM PDT 24 56326512690 ps
T579 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1349839989 Apr 16 12:21:49 PM PDT 24 Apr 16 12:22:37 PM PDT 24 14551712100 ps
T580 /workspace/coverage/default/40.rom_ctrl_smoke.2344917988 Apr 16 02:03:12 PM PDT 24 Apr 16 02:03:33 PM PDT 24 662008479 ps
T581 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1909877906 Apr 16 12:22:12 PM PDT 24 Apr 16 12:25:01 PM PDT 24 7963998014 ps
T582 /workspace/coverage/default/2.rom_ctrl_alert_test.1736886233 Apr 16 12:21:03 PM PDT 24 Apr 16 12:21:27 PM PDT 24 9507907145 ps
T583 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.404194535 Apr 16 02:03:04 PM PDT 24 Apr 16 02:03:20 PM PDT 24 3013689937 ps
T584 /workspace/coverage/default/46.rom_ctrl_stress_all.2037091255 Apr 16 02:03:34 PM PDT 24 Apr 16 02:03:54 PM PDT 24 3622711448 ps
T585 /workspace/coverage/default/33.rom_ctrl_smoke.2945923842 Apr 16 02:03:15 PM PDT 24 Apr 16 02:04:23 PM PDT 24 6489418849 ps
T586 /workspace/coverage/default/16.rom_ctrl_smoke.2228920318 Apr 16 02:02:52 PM PDT 24 Apr 16 02:03:13 PM PDT 24 356026138 ps
T587 /workspace/coverage/default/19.rom_ctrl_smoke.3647194500 Apr 16 12:21:49 PM PDT 24 Apr 16 12:22:15 PM PDT 24 1056526751 ps
T588 /workspace/coverage/default/3.rom_ctrl_alert_test.3195285242 Apr 16 02:02:54 PM PDT 24 Apr 16 02:03:26 PM PDT 24 17094525447 ps
T589 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3056213799 Apr 16 02:03:27 PM PDT 24 Apr 16 02:11:52 PM PDT 24 175145245649 ps
T590 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2761076531 Apr 16 12:21:52 PM PDT 24 Apr 16 12:22:57 PM PDT 24 7353798377 ps
T591 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.144534751 Apr 16 12:22:06 PM PDT 24 Apr 16 12:22:34 PM PDT 24 10192779986 ps
T592 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3196929930 Apr 16 12:22:19 PM PDT 24 Apr 16 01:01:20 PM PDT 24 233861968542 ps
T593 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.807832797 Apr 16 12:22:42 PM PDT 24 Apr 16 12:23:48 PM PDT 24 6848915717 ps
T594 /workspace/coverage/default/36.rom_ctrl_smoke.3339386211 Apr 16 12:21:49 PM PDT 24 Apr 16 12:23:14 PM PDT 24 17383502496 ps
T595 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1634565634 Apr 16 12:21:56 PM PDT 24 Apr 16 12:22:16 PM PDT 24 11288713527 ps
T596 /workspace/coverage/default/20.rom_ctrl_alert_test.3923344264 Apr 16 02:03:01 PM PDT 24 Apr 16 02:03:27 PM PDT 24 11247074771 ps
T597 /workspace/coverage/default/12.rom_ctrl_smoke.3265964453 Apr 16 02:02:49 PM PDT 24 Apr 16 02:03:41 PM PDT 24 3662720717 ps
T598 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.401620290 Apr 16 12:22:25 PM PDT 24 Apr 16 12:29:07 PM PDT 24 220989229631 ps
T599 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1928904691 Apr 16 02:03:09 PM PDT 24 Apr 16 02:03:30 PM PDT 24 342522652 ps
T600 /workspace/coverage/default/23.rom_ctrl_alert_test.3887700530 Apr 16 02:03:05 PM PDT 24 Apr 16 02:03:14 PM PDT 24 486958754 ps
T601 /workspace/coverage/default/28.rom_ctrl_smoke.426058895 Apr 16 02:03:10 PM PDT 24 Apr 16 02:03:32 PM PDT 24 1429019859 ps
T602 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3257319679 Apr 16 12:20:34 PM PDT 24 Apr 16 12:21:06 PM PDT 24 18030279874 ps
T603 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.359505643 Apr 16 12:22:16 PM PDT 24 Apr 16 12:27:54 PM PDT 24 20108457194 ps
T604 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3209533451 Apr 16 12:22:25 PM PDT 24 Apr 16 12:29:04 PM PDT 24 429209352202 ps
T45 /workspace/coverage/default/2.rom_ctrl_sec_cm.4051906685 Apr 16 12:19:04 PM PDT 24 Apr 16 12:22:55 PM PDT 24 1073838881 ps
T605 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3508363074 Apr 16 02:03:08 PM PDT 24 Apr 16 02:12:25 PM PDT 24 79617808270 ps
T606 /workspace/coverage/default/24.rom_ctrl_stress_all.1578776648 Apr 16 02:03:02 PM PDT 24 Apr 16 02:04:31 PM PDT 24 72168424168 ps
T607 /workspace/coverage/default/15.rom_ctrl_smoke.111267146 Apr 16 12:21:38 PM PDT 24 Apr 16 12:22:02 PM PDT 24 3899759240 ps
T608 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2720229554 Apr 16 12:23:25 PM PDT 24 Apr 16 12:34:02 PM PDT 24 48953550500 ps
T24 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.796466447 Apr 16 12:21:46 PM PDT 24 Apr 16 12:49:12 PM PDT 24 37793994233 ps
T609 /workspace/coverage/default/42.rom_ctrl_stress_all.3316150464 Apr 16 02:03:16 PM PDT 24 Apr 16 02:03:54 PM PDT 24 2269724881 ps
T610 /workspace/coverage/default/46.rom_ctrl_smoke.264629788 Apr 16 12:22:06 PM PDT 24 Apr 16 12:23:01 PM PDT 24 12035551019 ps
T611 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1885411438 Apr 16 02:03:18 PM PDT 24 Apr 16 02:04:17 PM PDT 24 37346246127 ps
T612 /workspace/coverage/default/27.rom_ctrl_alert_test.922514699 Apr 16 12:21:51 PM PDT 24 Apr 16 12:22:12 PM PDT 24 1946107843 ps
T613 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.481541326 Apr 16 12:22:10 PM PDT 24 Apr 16 12:27:39 PM PDT 24 142246585158 ps
T614 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3121447441 Apr 16 12:23:00 PM PDT 24 Apr 16 12:43:41 PM PDT 24 125376828351 ps
T615 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.259130339 Apr 16 02:02:57 PM PDT 24 Apr 16 02:03:33 PM PDT 24 19064616232 ps
T616 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.162336640 Apr 16 12:22:08 PM PDT 24 Apr 16 12:22:20 PM PDT 24 1083937902 ps
T617 /workspace/coverage/default/4.rom_ctrl_smoke.1539058586 Apr 16 02:02:43 PM PDT 24 Apr 16 02:03:21 PM PDT 24 1992272017 ps
T618 /workspace/coverage/default/14.rom_ctrl_stress_all.1977383269 Apr 16 12:21:44 PM PDT 24 Apr 16 12:24:07 PM PDT 24 56118191413 ps
T619 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1760024749 Apr 16 02:02:49 PM PDT 24 Apr 16 02:03:25 PM PDT 24 8530788334 ps
T620 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3719882783 Apr 16 02:03:22 PM PDT 24 Apr 16 02:03:58 PM PDT 24 25697192547 ps
T621 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.834232494 Apr 16 12:21:49 PM PDT 24 Apr 16 12:56:11 PM PDT 24 133729275803 ps
T622 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2685758375 Apr 16 02:03:17 PM PDT 24 Apr 16 02:04:05 PM PDT 24 4219181547 ps
T623 /workspace/coverage/default/28.rom_ctrl_alert_test.360248489 Apr 16 02:03:12 PM PDT 24 Apr 16 02:03:40 PM PDT 24 12619958355 ps
T624 /workspace/coverage/default/33.rom_ctrl_stress_all.4291882246 Apr 16 12:21:53 PM PDT 24 Apr 16 12:22:13 PM PDT 24 382417220 ps
T625 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1328761331 Apr 16 02:03:17 PM PDT 24 Apr 16 02:07:44 PM PDT 24 15421358336 ps
T626 /workspace/coverage/default/40.rom_ctrl_smoke.858856592 Apr 16 12:22:06 PM PDT 24 Apr 16 12:22:47 PM PDT 24 13832601823 ps
T107 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3087407925 Apr 16 12:22:32 PM PDT 24 Apr 16 12:46:09 PM PDT 24 40025684156 ps
T627 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.291591619 Apr 16 12:22:53 PM PDT 24 Apr 16 12:24:02 PM PDT 24 18344817111 ps
T628 /workspace/coverage/default/41.rom_ctrl_alert_test.3024347847 Apr 16 02:03:08 PM PDT 24 Apr 16 02:03:43 PM PDT 24 8870984659 ps
T629 /workspace/coverage/default/11.rom_ctrl_alert_test.3783006233 Apr 16 02:02:52 PM PDT 24 Apr 16 02:03:21 PM PDT 24 6737626938 ps
T630 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3597909998 Apr 16 12:22:35 PM PDT 24 Apr 16 12:23:07 PM PDT 24 3121461243 ps
T631 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3683345337 Apr 16 02:02:58 PM PDT 24 Apr 16 02:11:49 PM PDT 24 203142100967 ps
T632 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4014670477 Apr 16 02:03:09 PM PDT 24 Apr 16 02:03:43 PM PDT 24 24750325693 ps
T633 /workspace/coverage/default/48.rom_ctrl_alert_test.2582823316 Apr 16 02:03:25 PM PDT 24 Apr 16 02:03:54 PM PDT 24 9342774182 ps
T634 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1876095567 Apr 16 02:03:22 PM PDT 24 Apr 16 02:04:23 PM PDT 24 6547816941 ps
T635 /workspace/coverage/default/41.rom_ctrl_alert_test.2022145000 Apr 16 12:22:00 PM PDT 24 Apr 16 12:22:13 PM PDT 24 1709055704 ps
T636 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2575453460 Apr 16 02:02:47 PM PDT 24 Apr 16 04:02:39 PM PDT 24 20297430753 ps
T637 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1976119381 Apr 16 02:03:07 PM PDT 24 Apr 16 02:03:48 PM PDT 24 12966261668 ps
T638 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.572627721 Apr 16 02:03:15 PM PDT 24 Apr 16 02:03:35 PM PDT 24 346026506 ps
T639 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3114244581 Apr 16 02:02:52 PM PDT 24 Apr 16 02:03:12 PM PDT 24 3207747708 ps
T640 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3337252539 Apr 16 02:03:12 PM PDT 24 Apr 16 02:03:38 PM PDT 24 8920431898 ps
T641 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1128436904 Apr 16 02:02:56 PM PDT 24 Apr 16 02:09:42 PM PDT 24 18205714477 ps
T642 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3012098976 Apr 16 12:22:47 PM PDT 24 Apr 16 12:23:11 PM PDT 24 6187805630 ps
T643 /workspace/coverage/default/40.rom_ctrl_alert_test.1233179777 Apr 16 02:03:22 PM PDT 24 Apr 16 02:03:52 PM PDT 24 3607408797 ps
T644 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2823967605 Apr 16 12:22:13 PM PDT 24 Apr 16 12:22:48 PM PDT 24 9751870638 ps
T645 /workspace/coverage/default/37.rom_ctrl_stress_all.2818478889 Apr 16 02:03:10 PM PDT 24 Apr 16 02:03:52 PM PDT 24 19046227132 ps
T646 /workspace/coverage/default/40.rom_ctrl_stress_all.49520476 Apr 16 02:03:21 PM PDT 24 Apr 16 02:04:35 PM PDT 24 23729003373 ps
T647 /workspace/coverage/default/6.rom_ctrl_alert_test.1202329302 Apr 16 12:22:42 PM PDT 24 Apr 16 12:23:03 PM PDT 24 1104047319 ps
T648 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.779938102 Apr 16 12:22:30 PM PDT 24 Apr 16 12:23:06 PM PDT 24 4388074326 ps
T649 /workspace/coverage/default/12.rom_ctrl_alert_test.3866148989 Apr 16 12:21:20 PM PDT 24 Apr 16 12:21:30 PM PDT 24 332107900 ps
T650 /workspace/coverage/default/26.rom_ctrl_stress_all.1016619889 Apr 16 12:21:55 PM PDT 24 Apr 16 12:22:31 PM PDT 24 1165534263 ps
T651 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2962745480 Apr 16 12:23:09 PM PDT 24 Apr 16 12:27:14 PM PDT 24 16032546952 ps
T652 /workspace/coverage/default/33.rom_ctrl_alert_test.3686131345 Apr 16 02:03:08 PM PDT 24 Apr 16 02:03:33 PM PDT 24 5129115408 ps
T653 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1077722953 Apr 16 02:02:42 PM PDT 24 Apr 16 02:15:21 PM PDT 24 351483976894 ps
T654 /workspace/coverage/default/31.rom_ctrl_stress_all.3725514187 Apr 16 12:21:51 PM PDT 24 Apr 16 12:23:09 PM PDT 24 13581301342 ps
T655 /workspace/coverage/default/18.rom_ctrl_stress_all.494341565 Apr 16 02:02:50 PM PDT 24 Apr 16 02:03:22 PM PDT 24 1606214156 ps
T656 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2558290526 Apr 16 12:22:25 PM PDT 24 Apr 16 12:36:00 PM PDT 24 83704015368 ps
T657 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1789340498 Apr 16 02:02:57 PM PDT 24 Apr 16 02:03:08 PM PDT 24 181838488 ps
T658 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3563768604 Apr 16 02:03:30 PM PDT 24 Apr 16 02:03:51 PM PDT 24 5499285031 ps
T659 /workspace/coverage/default/21.rom_ctrl_alert_test.3588836165 Apr 16 02:02:55 PM PDT 24 Apr 16 02:03:28 PM PDT 24 19620575563 ps
T660 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.800106088 Apr 16 12:22:07 PM PDT 24 Apr 16 12:22:22 PM PDT 24 3578016140 ps
T661 /workspace/coverage/default/10.rom_ctrl_smoke.1003527905 Apr 16 12:22:42 PM PDT 24 Apr 16 12:23:24 PM PDT 24 10959476323 ps
T662 /workspace/coverage/default/38.rom_ctrl_alert_test.3540458750 Apr 16 02:03:23 PM PDT 24 Apr 16 02:03:55 PM PDT 24 7710345263 ps
T663 /workspace/coverage/default/34.rom_ctrl_alert_test.2464468052 Apr 16 12:21:56 PM PDT 24 Apr 16 12:22:19 PM PDT 24 8490684090 ps
T664 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.77356567 Apr 16 12:21:30 PM PDT 24 Apr 16 12:22:12 PM PDT 24 3419536438 ps
T665 /workspace/coverage/default/46.rom_ctrl_smoke.2481138188 Apr 16 02:03:22 PM PDT 24 Apr 16 02:04:44 PM PDT 24 16548608785 ps
T666 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.641238811 Apr 16 12:22:30 PM PDT 24 Apr 16 12:24:32 PM PDT 24 2571411738 ps
T667 /workspace/coverage/default/22.rom_ctrl_stress_all.1031361659 Apr 16 12:21:47 PM PDT 24 Apr 16 12:25:16 PM PDT 24 89103857162 ps
T668 /workspace/coverage/default/40.rom_ctrl_alert_test.3822386416 Apr 16 12:22:04 PM PDT 24 Apr 16 12:22:14 PM PDT 24 338826123 ps
T669 /workspace/coverage/default/10.rom_ctrl_stress_all.2756179735 Apr 16 12:22:42 PM PDT 24 Apr 16 12:25:38 PM PDT 24 58981093487 ps
T66 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2214009994 Apr 16 02:19:30 PM PDT 24 Apr 16 02:19:58 PM PDT 24 6159969747 ps
T62 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3433394577 Apr 16 02:19:45 PM PDT 24 Apr 16 02:21:18 PM PDT 24 7420847235 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3567758187 Apr 16 02:19:34 PM PDT 24 Apr 16 02:19:57 PM PDT 24 3251860358 ps
T71 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.540030468 Apr 16 02:19:34 PM PDT 24 Apr 16 02:20:45 PM PDT 24 9422954316 ps
T670 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2357912057 Apr 16 02:19:30 PM PDT 24 Apr 16 02:19:55 PM PDT 24 3175596395 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1662081877 Apr 16 02:19:24 PM PDT 24 Apr 16 02:19:37 PM PDT 24 170764076 ps
T73 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.51841143 Apr 16 02:19:31 PM PDT 24 Apr 16 02:20:30 PM PDT 24 1048251264 ps
T671 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1135030337 Apr 16 02:19:28 PM PDT 24 Apr 16 02:19:42 PM PDT 24 674375770 ps
T74 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1321072509 Apr 16 02:19:38 PM PDT 24 Apr 16 02:20:06 PM PDT 24 38106481900 ps
T672 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.914627958 Apr 16 02:19:48 PM PDT 24 Apr 16 02:20:06 PM PDT 24 1342859378 ps
T673 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.674039511 Apr 16 02:19:29 PM PDT 24 Apr 16 02:19:39 PM PDT 24 404797098 ps
T674 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.831505559 Apr 16 02:19:36 PM PDT 24 Apr 16 02:20:08 PM PDT 24 6491411231 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.91058803 Apr 16 02:19:43 PM PDT 24 Apr 16 02:20:13 PM PDT 24 3753110577 ps
T94 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1718904497 Apr 16 02:19:40 PM PDT 24 Apr 16 02:20:11 PM PDT 24 4011967145 ps
T75 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1797947802 Apr 16 02:19:40 PM PDT 24 Apr 16 02:20:38 PM PDT 24 1074419140 ps
T675 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1268088810 Apr 16 02:19:25 PM PDT 24 Apr 16 02:19:47 PM PDT 24 7325656922 ps
T63 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3115733258 Apr 16 02:19:24 PM PDT 24 Apr 16 02:21:00 PM PDT 24 4682592488 ps
T76 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2699424842 Apr 16 02:19:47 PM PDT 24 Apr 16 02:20:43 PM PDT 24 1034668481 ps
T676 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4128911430 Apr 16 02:19:19 PM PDT 24 Apr 16 02:19:39 PM PDT 24 5941655531 ps
T677 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.995942048 Apr 16 02:19:54 PM PDT 24 Apr 16 02:20:22 PM PDT 24 3120412831 ps
T98 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1045169754 Apr 16 02:19:43 PM PDT 24 Apr 16 02:21:18 PM PDT 24 8996258073 ps
T77 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1354353975 Apr 16 02:19:48 PM PDT 24 Apr 16 02:19:57 PM PDT 24 174506914 ps
T678 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.652051607 Apr 16 02:19:28 PM PDT 24 Apr 16 02:19:47 PM PDT 24 3092603409 ps
T95 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2141833823 Apr 16 02:19:48 PM PDT 24 Apr 16 02:20:17 PM PDT 24 6085485694 ps
T679 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.611938578 Apr 16 02:19:46 PM PDT 24 Apr 16 02:20:17 PM PDT 24 15945014243 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.330856844 Apr 16 02:19:24 PM PDT 24 Apr 16 02:19:58 PM PDT 24 4035449165 ps
T680 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3678454939 Apr 16 02:19:34 PM PDT 24 Apr 16 02:19:51 PM PDT 24 17969628808 ps
T79 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.929191872 Apr 16 02:19:39 PM PDT 24 Apr 16 02:19:49 PM PDT 24 331614284 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2492030398 Apr 16 02:19:29 PM PDT 24 Apr 16 02:19:57 PM PDT 24 17333633310 ps
T681 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.222072639 Apr 16 02:19:26 PM PDT 24 Apr 16 02:19:54 PM PDT 24 2346110935 ps
T64 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3888566912 Apr 16 02:19:29 PM PDT 24 Apr 16 02:21:08 PM PDT 24 2799382947 ps
T682 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4129463874 Apr 16 02:19:29 PM PDT 24 Apr 16 02:22:31 PM PDT 24 134398416564 ps
T683 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1698551670 Apr 16 02:19:19 PM PDT 24 Apr 16 02:19:39 PM PDT 24 2174696159 ps
T684 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2871137911 Apr 16 02:19:31 PM PDT 24 Apr 16 02:20:00 PM PDT 24 11092474202 ps
T97 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2971468323 Apr 16 02:19:46 PM PDT 24 Apr 16 02:20:15 PM PDT 24 3102164734 ps
T685 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3306506471 Apr 16 02:19:34 PM PDT 24 Apr 16 02:20:07 PM PDT 24 57317527312 ps
T686 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2740848773 Apr 16 02:19:46 PM PDT 24 Apr 16 02:20:11 PM PDT 24 17571030259 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2675727622 Apr 16 02:19:21 PM PDT 24 Apr 16 02:19:52 PM PDT 24 3713016058 ps
T687 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1420563182 Apr 16 02:19:48 PM PDT 24 Apr 16 02:20:24 PM PDT 24 7660297576 ps
T688 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2402938747 Apr 16 02:19:43 PM PDT 24 Apr 16 02:22:19 PM PDT 24 16891803090 ps
T84 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2144775054 Apr 16 02:19:34 PM PDT 24 Apr 16 02:21:01 PM PDT 24 4709782320 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1808460126 Apr 16 02:19:21 PM PDT 24 Apr 16 02:22:02 PM PDT 24 1459710360 ps
T115 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3145651262 Apr 16 02:19:44 PM PDT 24 Apr 16 02:21:08 PM PDT 24 298613623 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4157751830 Apr 16 02:19:21 PM PDT 24 Apr 16 02:22:06 PM PDT 24 2274078589 ps
T689 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3980992407 Apr 16 02:19:39 PM PDT 24 Apr 16 02:20:04 PM PDT 24 10350213669 ps
T118 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2949085925 Apr 16 02:19:57 PM PDT 24 Apr 16 02:22:53 PM PDT 24 19290077416 ps
T690 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3828218594 Apr 16 02:19:49 PM PDT 24 Apr 16 02:20:19 PM PDT 24 3595677083 ps
T691 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.393035168 Apr 16 02:19:45 PM PDT 24 Apr 16 02:19:59 PM PDT 24 768163019 ps
T692 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.366290293 Apr 16 02:19:15 PM PDT 24 Apr 16 02:19:26 PM PDT 24 169042164 ps
T693 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3763464957 Apr 16 02:19:17 PM PDT 24 Apr 16 02:19:48 PM PDT 24 3736584614 ps
T694 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.822141368 Apr 16 02:19:39 PM PDT 24 Apr 16 02:20:16 PM PDT 24 4389861402 ps
T695 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1652807756 Apr 16 02:19:19 PM PDT 24 Apr 16 02:19:29 PM PDT 24 175973915 ps
T696 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1846750345 Apr 16 02:19:46 PM PDT 24 Apr 16 02:22:34 PM PDT 24 75020050756 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1061255153 Apr 16 02:19:21 PM PDT 24 Apr 16 02:21:32 PM PDT 24 73251806552 ps
T697 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.487990459 Apr 16 02:19:35 PM PDT 24 Apr 16 02:20:14 PM PDT 24 4292839951 ps
T108 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3773429975 Apr 16 02:19:49 PM PDT 24 Apr 16 02:21:32 PM PDT 24 15600961712 ps
T698 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1667822914 Apr 16 02:19:45 PM PDT 24 Apr 16 02:19:57 PM PDT 24 422664470 ps
T699 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2783696511 Apr 16 02:19:21 PM PDT 24 Apr 16 02:19:31 PM PDT 24 171162744 ps
T700 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2711922457 Apr 16 02:19:50 PM PDT 24 Apr 16 02:20:09 PM PDT 24 951048208 ps
T701 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1280455010 Apr 16 02:19:24 PM PDT 24 Apr 16 02:19:38 PM PDT 24 640828966 ps
T702 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.621480209 Apr 16 02:19:36 PM PDT 24 Apr 16 02:20:06 PM PDT 24 6554587319 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.710953885 Apr 16 02:19:58 PM PDT 24 Apr 16 02:22:47 PM PDT 24 2982762558 ps
T703 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2581157675 Apr 16 02:19:49 PM PDT 24 Apr 16 02:23:10 PM PDT 24 34734581459 ps
T704 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1796573970 Apr 16 02:19:39 PM PDT 24 Apr 16 02:20:01 PM PDT 24 8285352414 ps
T705 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.908255920 Apr 16 02:19:23 PM PDT 24 Apr 16 02:19:41 PM PDT 24 2731022851 ps
T706 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.877247569 Apr 16 02:19:18 PM PDT 24 Apr 16 02:19:48 PM PDT 24 13623456350 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2913230962 Apr 16 02:19:21 PM PDT 24 Apr 16 02:19:38 PM PDT 24 708737011 ps
T707 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.390357719 Apr 16 02:19:49 PM PDT 24 Apr 16 02:20:18 PM PDT 24 19322341609 ps
T708 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1459110904 Apr 16 02:19:28 PM PDT 24 Apr 16 02:19:59 PM PDT 24 38436902715 ps
T709 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3027091450 Apr 16 02:19:32 PM PDT 24 Apr 16 02:20:05 PM PDT 24 76978857869 ps
T710 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.637443623 Apr 16 02:19:35 PM PDT 24 Apr 16 02:20:01 PM PDT 24 9873615623 ps
T711 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.473837789 Apr 16 02:19:25 PM PDT 24 Apr 16 02:19:59 PM PDT 24 16475543690 ps
T712 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1131644101 Apr 16 02:19:20 PM PDT 24 Apr 16 02:21:28 PM PDT 24 75637927352 ps
T713 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1538563950 Apr 16 02:19:38 PM PDT 24 Apr 16 02:19:53 PM PDT 24 775782377 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1596598725 Apr 16 02:19:25 PM PDT 24 Apr 16 02:21:24 PM PDT 24 37583426844 ps
T714 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3583435343 Apr 16 02:19:20 PM PDT 24 Apr 16 02:19:34 PM PDT 24 351187032 ps
T715 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1762485840 Apr 16 02:19:38 PM PDT 24 Apr 16 02:20:08 PM PDT 24 5334243132 ps
T716 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3091737856 Apr 16 02:19:45 PM PDT 24 Apr 16 02:20:00 PM PDT 24 718700111 ps
T717 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1882051062 Apr 16 02:19:51 PM PDT 24 Apr 16 02:20:19 PM PDT 24 3052516826 ps
T718 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3438612192 Apr 16 02:19:29 PM PDT 24 Apr 16 02:19:48 PM PDT 24 5905389459 ps
T719 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.777520385 Apr 16 02:19:48 PM PDT 24 Apr 16 02:19:59 PM PDT 24 369604854 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.226280330 Apr 16 02:19:17 PM PDT 24 Apr 16 02:19:47 PM PDT 24 4377356590 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.871129343 Apr 16 02:19:31 PM PDT 24 Apr 16 02:22:13 PM PDT 24 900517405 ps
T720 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1328631295 Apr 16 02:19:38 PM PDT 24 Apr 16 02:20:17 PM PDT 24 2757552799 ps
T89 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1839952285 Apr 16 02:19:48 PM PDT 24 Apr 16 02:20:27 PM PDT 24 711786382 ps
T721 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1977464223 Apr 16 02:19:24 PM PDT 24 Apr 16 02:19:34 PM PDT 24 345879945 ps
T722 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.900196109 Apr 16 02:19:58 PM PDT 24 Apr 16 02:20:32 PM PDT 24 3490575888 ps
T723 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3297227326 Apr 16 02:19:29 PM PDT 24 Apr 16 02:19:53 PM PDT 24 4424913294 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3545917563 Apr 16 02:19:35 PM PDT 24 Apr 16 02:22:24 PM PDT 24 10829810776 ps
T724 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3118933012 Apr 16 02:19:45 PM PDT 24 Apr 16 02:20:02 PM PDT 24 5035239811 ps
T90 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3984734281 Apr 16 02:19:35 PM PDT 24 Apr 16 02:21:41 PM PDT 24 15428037293 ps
T725 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4218060463 Apr 16 02:19:28 PM PDT 24 Apr 16 02:19:45 PM PDT 24 2676888588 ps
T726 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.505041736 Apr 16 02:19:27 PM PDT 24 Apr 16 02:19:49 PM PDT 24 1862132134 ps
T727 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4248011672 Apr 16 02:19:24 PM PDT 24 Apr 16 02:19:38 PM PDT 24 352841136 ps
T728 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4001648954 Apr 16 02:19:20 PM PDT 24 Apr 16 02:19:40 PM PDT 24 1699212836 ps
T729 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3686266784 Apr 16 02:19:44 PM PDT 24 Apr 16 02:19:56 PM PDT 24 2176019525 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1030844553 Apr 16 02:19:15 PM PDT 24 Apr 16 02:20:54 PM PDT 24 10378002123 ps
T730 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4113407148 Apr 16 02:19:20 PM PDT 24 Apr 16 02:19:46 PM PDT 24 1880578653 ps
T731 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.529058378 Apr 16 02:19:21 PM PDT 24 Apr 16 02:19:39 PM PDT 24 765359442 ps
T732 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3902738380 Apr 16 02:19:45 PM PDT 24 Apr 16 02:20:19 PM PDT 24 4098976342 ps
T733 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2203513823 Apr 16 02:19:45 PM PDT 24 Apr 16 02:20:03 PM PDT 24 426327312 ps
T114 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3786596321 Apr 16 02:19:39 PM PDT 24 Apr 16 02:21:23 PM PDT 24 4004504331 ps
T734 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.554130864 Apr 16 02:19:19 PM PDT 24 Apr 16 02:19:33 PM PDT 24 1372286548 ps
T735 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3268124953 Apr 16 02:19:24 PM PDT 24 Apr 16 02:19:49 PM PDT 24 9860785426 ps
T736 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1925397874 Apr 16 02:19:40 PM PDT 24 Apr 16 02:19:55 PM PDT 24 625424854 ps
T737 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.236554003 Apr 16 02:19:28 PM PDT 24 Apr 16 02:19:56 PM PDT 24 2949505538 ps
T738 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.229155552 Apr 16 02:19:23 PM PDT 24 Apr 16 02:19:32 PM PDT 24 272417635 ps
T739 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.566533966 Apr 16 02:19:39 PM PDT 24 Apr 16 02:20:11 PM PDT 24 27407954556 ps
T740 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2464246275 Apr 16 02:19:25 PM PDT 24 Apr 16 02:19:36 PM PDT 24 332275525 ps
T741 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3549682966 Apr 16 02:19:48 PM PDT 24 Apr 16 02:20:28 PM PDT 24 691944361 ps
T742 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3769110025 Apr 16 02:19:51 PM PDT 24 Apr 16 02:20:17 PM PDT 24 5693963727 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.966757410 Apr 16 02:19:28 PM PDT 24 Apr 16 02:19:45 PM PDT 24 1969401178 ps
T743 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.349112263 Apr 16 02:19:17 PM PDT 24 Apr 16 02:21:49 PM PDT 24 63673937604 ps
T744 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.963452541 Apr 16 02:19:20 PM PDT 24 Apr 16 02:19:39 PM PDT 24 8200456182 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3896386130 Apr 16 02:19:26 PM PDT 24 Apr 16 02:19:36 PM PDT 24 167331013 ps
T121 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1590847881 Apr 16 02:19:40 PM PDT 24 Apr 16 02:22:18 PM PDT 24 635510592 ps
T745 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4179798287 Apr 16 02:19:49 PM PDT 24 Apr 16 02:22:24 PM PDT 24 1537241510 ps
T746 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3010615614 Apr 16 02:19:29 PM PDT 24 Apr 16 02:22:25 PM PDT 24 16956125698 ps
T747 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3227815644 Apr 16 02:19:19 PM PDT 24 Apr 16 02:19:49 PM PDT 24 5131841825 ps
T117 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1984255151 Apr 16 02:19:36 PM PDT 24 Apr 16 02:22:21 PM PDT 24 8445574812 ps
T748 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.826068858 Apr 16 02:19:15 PM PDT 24 Apr 16 02:19:25 PM PDT 24 167342587 ps
T749 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1371680367 Apr 16 02:19:37 PM PDT 24 Apr 16 02:20:01 PM PDT 24 10087010508 ps
T750 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2870671828 Apr 16 02:19:30 PM PDT 24 Apr 16 02:20:30 PM PDT 24 12417969367 ps
T751 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3219995978 Apr 16 02:19:31 PM PDT 24 Apr 16 02:22:21 PM PDT 24 74695064844 ps
T119 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3484869284 Apr 16 02:19:42 PM PDT 24 Apr 16 02:22:29 PM PDT 24 4012320802 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%