Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	96.96	92.97	97.88	100.00	98.36	97.89	99.07

Total test records in report: 769

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html

T752	/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1168826529			Apr 16 02:19:49 PM PDT 24	Apr 16 02:20:21 PM PDT 24	15249652634 ps
T753	/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3015897852			Apr 16 02:19:30 PM PDT 24	Apr 16 02:20:03 PM PDT 24	2945179138 ps
T754	/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1137877137			Apr 16 02:19:49 PM PDT 24	Apr 16 02:20:01 PM PDT 24	170960847 ps
T755	/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2060342107			Apr 16 02:19:48 PM PDT 24	Apr 16 02:20:01 PM PDT 24	693651998 ps
T756	/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2028470803			Apr 16 02:19:26 PM PDT 24	Apr 16 02:19:59 PM PDT 24	15733494090 ps
T757	/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3763060688			Apr 16 02:19:40 PM PDT 24	Apr 16 02:20:13 PM PDT 24	3210977238 ps
T758	/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3659221865			Apr 16 02:19:33 PM PDT 24	Apr 16 02:20:02 PM PDT 24	3498974508 ps
T759	/workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2212039737			Apr 16 02:19:19 PM PDT 24	Apr 16 02:19:46 PM PDT 24	2190773128 ps
T760	/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2310341599			Apr 16 02:19:24 PM PDT 24	Apr 16 02:20:00 PM PDT 24	6624482761 ps
T761	/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3424934838			Apr 16 02:19:28 PM PDT 24	Apr 16 02:21:10 PM PDT 24	13279752761 ps
T762	/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2801979310			Apr 16 02:19:46 PM PDT 24	Apr 16 02:20:06 PM PDT 24	4320732060 ps
T763	/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3485731164			Apr 16 02:19:28 PM PDT 24	Apr 16 02:19:46 PM PDT 24	1727642364 ps
T764	/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2959305485			Apr 16 02:19:16 PM PDT 24	Apr 16 02:19:30 PM PDT 24	167568884 ps
T765	/workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.239952446			Apr 16 02:19:34 PM PDT 24	Apr 16 02:20:03 PM PDT 24	3549742800 ps
T766	/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3216785100			Apr 16 02:19:30 PM PDT 24	Apr 16 02:20:04 PM PDT 24	4119115347 ps
T767	/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1406406232			Apr 16 02:19:27 PM PDT 24	Apr 16 02:19:54 PM PDT 24	2973671160 ps
T768	/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.995410849			Apr 16 02:19:51 PM PDT 24	Apr 16 02:20:15 PM PDT 24	2604992296 ps
T120	/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3886255039			Apr 16 02:19:41 PM PDT 24	Apr 16 02:22:25 PM PDT 24	31082250010 ps
T769	/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3695505121			Apr 16 02:19:25 PM PDT 24	Apr 16 02:19:49 PM PDT 24	4696161846 ps

Test location	/workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1739057992
Short name	T5
Test name
Test status
Simulation time	70949982114 ps
CPU time	725.69 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:34:00 PM PDT 24
Peak memory	240196 kb
Host	smart-0ace669e-5bdf-4347-be4f-1d46986fa8a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739057992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_ corrupt_sig_fatal_chk.1739057992
Directory	/workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.62820384
Short name	T17
Test name
Test status
Simulation time	17001225714 ps
CPU time	618.49 seconds
Started	Apr 16 12:21:41 PM PDT 24
Finished	Apr 16 12:32:02 PM PDT 24
Peak memory	230336 kb
Host	smart-2444e599-ee9c-4442-ad04-7c950c362ead
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62820384 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.62820384
Directory	/workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.rom_ctrl_smoke.3090972034
Short name	T11
Test name
Test status
Simulation time	2469416071 ps
CPU time	34.08 seconds
Started	Apr 16 02:02:59 PM PDT 24
Finished	Apr 16 02:03:34 PM PDT 24
Peak memory	218160 kb
Host	smart-341631c8-50d8-48b1-b02b-d493ed3f7472
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090972034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3090972034
Directory	/workspace/20.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1123157045
Short name	T29
Test name
Test status
Simulation time	89642141704 ps
CPU time	616.81 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:13:34 PM PDT 24
Peak memory	228796 kb
Host	smart-3bb2430a-0b16-4ef3-bc44-47df8d04997b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123157045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_ corrupt_sig_fatal_chk.1123157045
Directory	/workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/36.rom_ctrl_max_throughput_chk.679088663
Short name	T99
Test name
Test status
Simulation time	827740190 ps
CPU time	10.81 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	212712 kb
Host	smart-2c6a3097-f90a-416d-ab58-b9e0794c4a0c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=679088663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.679088663
Directory	/workspace/36.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/1.rom_ctrl_sec_cm.4242557861
Short name	T3
Test name
Test status
Simulation time	12360119033 ps
CPU time	127.02 seconds
Started	Apr 16 12:20:04 PM PDT 24
Finished	Apr 16 12:22:11 PM PDT 24
Peak memory	238880 kb
Host	smart-5d66a613-35bc-4c64-b599-4907fc78bd68
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242557861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4242557861
Directory	/workspace/1.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.871129343
Short name	T109
Test name
Test status
Simulation time	900517405 ps
CPU time	160.63 seconds
Started	Apr 16 02:19:31 PM PDT 24
Finished	Apr 16 02:22:13 PM PDT 24
Peak memory	213996 kb
Host	smart-0cb8f418-78db-496b-bb2c-7adc7a94b75f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871129343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int g_err.871129343
Directory	/workspace/6.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/37.rom_ctrl_max_throughput_chk.809325526
Short name	T177
Test name
Test status
Simulation time	624178225 ps
CPU time	10.52 seconds
Started	Apr 16 12:22:54 PM PDT 24
Finished	Apr 16 12:23:09 PM PDT 24
Peak memory	211556 kb
Host	smart-de40d91c-61f0-4925-bcee-22963dbf0c85
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=809325526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.809325526
Directory	/workspace/37.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/20.rom_ctrl_smoke.3376732498
Short name	T14
Test name
Test status
Simulation time	3901138831 ps
CPU time	51.93 seconds
Started	Apr 16 12:22:58 PM PDT 24
Finished	Apr 16 12:23:54 PM PDT 24
Peak memory	214656 kb
Host	smart-0534162d-412e-4fde-9029-1497005496ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376732498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3376732498
Directory	/workspace/20.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.rom_ctrl_smoke.259995467
Short name	T82
Test name
Test status
Simulation time	15362038356 ps
CPU time	79.97 seconds
Started	Apr 16 02:02:29 PM PDT 24
Finished	Apr 16 02:03:49 PM PDT 24
Peak memory	216648 kb
Host	smart-5751519f-5050-4712-a4c8-ba85b901c586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259995467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.259995467
Directory	/workspace/1.rom_ctrl_smoke/latest

Test location	/workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2699424842
Short name	T76
Test name
Test status
Simulation time	1034668481 ps
CPU time	55.27 seconds
Started	Apr 16 02:19:47 PM PDT 24
Finished	Apr 16 02:20:43 PM PDT 24
Peak memory	215376 kb
Host	smart-7baad327-16da-4fd6-9f50-8424f0dd8c57
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699424842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p assthru_mem_tl_intg_err.2699424842
Directory	/workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.569734748
Short name	T106
Test name
Test status
Simulation time	139631720404 ps
CPU time	2134.69 seconds
Started	Apr 16 02:03:19 PM PDT 24
Finished	Apr 16 02:38:55 PM PDT 24
Peak memory	244520 kb
Host	smart-24695d2c-431b-4e8b-bb5b-e9d6a9ef7d23
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569734748 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.569734748
Directory	/workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.rom_ctrl_stress_all.1498886915
Short name	T13
Test name
Test status
Simulation time	63296943828 ps
CPU time	84.05 seconds
Started	Apr 16 12:22:33 PM PDT 24
Finished	Apr 16 12:24:01 PM PDT 24
Peak memory	216988 kb
Host	smart-bf09c3d4-f7ef-4d42-b211-06a2f5ed792c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498886915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.rom_ctrl_stress_all.1498886915
Directory	/workspace/41.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.rom_ctrl_alert_test.1424393176
Short name	T38
Test name
Test status
Simulation time	261436684 ps
CPU time	9.74 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:06 PM PDT 24
Peak memory	210828 kb
Host	smart-e5fea92e-31d6-4fc9-bd77-6154d80acf76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424393176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1424393176
Directory	/workspace/18.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1334739115
Short name	T165
Test name
Test status
Simulation time	15080217906 ps
CPU time	44.11 seconds
Started	Apr 16 12:22:17 PM PDT 24
Finished	Apr 16 12:23:02 PM PDT 24
Peak memory	215116 kb
Host	smart-538e839c-204e-4cae-822d-6ba0e942d316
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334739115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1334739115
Directory	/workspace/43.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1003616548
Short name	T231
Test name
Test status
Simulation time	3784496777 ps
CPU time	26.84 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	214852 kb
Host	smart-ba4b4e5e-8d23-4476-8418-bda73b6260ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003616548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1003616548
Directory	/workspace/1.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4157751830
Short name	T112
Test name
Test status
Simulation time	2274078589 ps
CPU time	163.58 seconds
Started	Apr 16 02:19:21 PM PDT 24
Finished	Apr 16 02:22:06 PM PDT 24
Peak memory	215048 kb
Host	smart-f5999bb9-ad85-4e44-bbd5-75858f56514d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157751830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in tg_err.4157751830
Directory	/workspace/1.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3886255039
Short name	T120
Test name
Test status
Simulation time	31082250010 ps
CPU time	162.67 seconds
Started	Apr 16 02:19:41 PM PDT 24
Finished	Apr 16 02:22:25 PM PDT 24
Peak memory	214252 kb
Host	smart-54abbc99-171f-43c8-bca2-2de20a235abd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886255039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i ntg_err.3886255039
Directory	/workspace/10.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3888566912
Short name	T64
Test name
Test status
Simulation time	2799382947 ps
CPU time	96.95 seconds
Started	Apr 16 02:19:29 PM PDT 24
Finished	Apr 16 02:21:08 PM PDT 24
Peak memory	213764 kb
Host	smart-cfa25dc9-2944-4c9c-990d-c847566ce1da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888566912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in tg_err.3888566912
Directory	/workspace/7.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.928455063
Short name	T23
Test name
Test status
Simulation time	87510215103 ps
CPU time	1626.16 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:29:57 PM PDT 24
Peak memory	237792 kb
Host	smart-d6d4f7c3-d873-41fb-a774-d5ad9a3bf3fe
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928455063 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.928455063
Directory	/workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.702656315
Short name	T123
Test name
Test status
Simulation time	5462703961 ps
CPU time	256.07 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:07:33 PM PDT 24
Peak memory	236916 kb
Host	smart-1094c9ed-a50b-4164-ac6f-9ae05c603294
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702656315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c orrupt_sig_fatal_chk.702656315
Directory	/workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1718904497
Short name	T94
Test name
Test status
Simulation time	4011967145 ps
CPU time	29.69 seconds
Started	Apr 16 02:19:40 PM PDT 24
Finished	Apr 16 02:20:11 PM PDT 24
Peak memory	212528 kb
Host	smart-3719e33d-9bfd-4663-92c7-d1d3539ff719
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718904497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ ctrl_same_csr_outstanding.1718904497
Directory	/workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/default/15.rom_ctrl_stress_all.2746803277
Short name	T65
Test name
Test status
Simulation time	6922077446 ps
CPU time	66.78 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:04:19 PM PDT 24
Peak memory	218828 kb
Host	smart-165cd521-d2ea-488e-bf23-6132309ebac7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746803277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.rom_ctrl_stress_all.2746803277
Directory	/workspace/15.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3484869284
Short name	T119
Test name
Test status
Simulation time	4012320802 ps
CPU time	164.76 seconds
Started	Apr 16 02:19:42 PM PDT 24
Finished	Apr 16 02:22:29 PM PDT 24
Peak memory	213972 kb
Host	smart-b2fd9ad5-6e41-49df-93c7-d52c8043f983
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484869284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i ntg_err.3484869284
Directory	/workspace/13.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1808460126
Short name	T111
Test name
Test status
Simulation time	1459710360 ps
CPU time	159.86 seconds
Started	Apr 16 02:19:21 PM PDT 24
Finished	Apr 16 02:22:02 PM PDT 24
Peak memory	213960 kb
Host	smart-5cd000a7-c3a1-46b1-b13b-b1b72df57470
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808460126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in tg_err.1808460126
Directory	/workspace/2.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/14.rom_ctrl_smoke.3052138332
Short name	T202
Test name
Test status
Simulation time	31710230554 ps
CPU time	72.37 seconds
Started	Apr 16 12:22:59 PM PDT 24
Finished	Apr 16 12:24:15 PM PDT 24
Peak memory	215908 kb
Host	smart-ad4c9485-c53d-48b1-bfa9-498a38a295db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052138332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3052138332
Directory	/workspace/14.rom_ctrl_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1652807756
Short name	T695
Test name
Test status
Simulation time	175973915 ps
CPU time	8.5 seconds
Started	Apr 16 02:19:19 PM PDT 24
Finished	Apr 16 02:19:29 PM PDT 24
Peak memory	211332 kb
Host	smart-1abc5de9-0c30-436f-8d8d-0805c5b069b5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652807756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia sing.1652807756
Directory	/workspace/0.rom_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.877247569
Short name	T706
Test name
Test status
Simulation time	13623456350 ps
CPU time	28.98 seconds
Started	Apr 16 02:19:18 PM PDT 24
Finished	Apr 16 02:19:48 PM PDT 24
Peak memory	212048 kb
Host	smart-115e100b-8726-4f9b-9469-e052577ab731
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877247569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b ash.877247569
Directory	/workspace/0.rom_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.226280330
Short name	T91
Test name
Test status
Simulation time	4377356590 ps
CPU time	28.7 seconds
Started	Apr 16 02:19:17 PM PDT 24
Finished	Apr 16 02:19:47 PM PDT 24
Peak memory	212416 kb
Host	smart-a286db9c-8ef7-46fd-92e6-7e53879f8723
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226280330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re set.226280330
Directory	/workspace/0.rom_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4128911430
Short name	T676
Test name
Test status
Simulation time	5941655531 ps
CPU time	18.68 seconds
Started	Apr 16 02:19:19 PM PDT 24
Finished	Apr 16 02:19:39 PM PDT 24
Peak memory	217620 kb
Host	smart-ceabf65b-5bff-431a-9263-3546c082c3f9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128911430 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4128911430
Directory	/workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.826068858
Short name	T748
Test name
Test status
Simulation time	167342587 ps
CPU time	8.2 seconds
Started	Apr 16 02:19:15 PM PDT 24
Finished	Apr 16 02:19:25 PM PDT 24
Peak memory	211288 kb
Host	smart-bc63afc5-9f4f-449b-9066-38a3926b3f21
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826068858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.826068858
Directory	/workspace/0.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.366290293
Short name	T692
Test name
Test status
Simulation time	169042164 ps
CPU time	8.07 seconds
Started	Apr 16 02:19:15 PM PDT 24
Finished	Apr 16 02:19:26 PM PDT 24
Peak memory	211180 kb
Host	smart-8ac32f17-4186-408b-9091-fb49de6d4ef3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366290293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl _mem_partial_access.366290293
Directory	/workspace/0.rom_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3763464957
Short name	T693
Test name
Test status
Simulation time	3736584614 ps
CPU time	28.52 seconds
Started	Apr 16 02:19:17 PM PDT 24
Finished	Apr 16 02:19:48 PM PDT 24
Peak memory	211236 kb
Host	smart-e72ccbf7-91f9-4783-984b-4580dab91d2a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763464957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk .3763464957
Directory	/workspace/0.rom_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.349112263
Short name	T743
Test name
Test status
Simulation time	63673937604 ps
CPU time	150.8 seconds
Started	Apr 16 02:19:17 PM PDT 24
Finished	Apr 16 02:21:49 PM PDT 24
Peak memory	215504 kb
Host	smart-2b2482e6-f0e0-43f0-8771-e346df2cc32d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349112263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas sthru_mem_tl_intg_err.349112263
Directory	/workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2212039737
Short name	T759
Test name
Test status
Simulation time	2190773128 ps
CPU time	25.34 seconds
Started	Apr 16 02:19:19 PM PDT 24
Finished	Apr 16 02:19:46 PM PDT 24
Peak memory	212356 kb
Host	smart-36ca4785-e4d5-4b69-91fd-9b7374207d3c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212039737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c trl_same_csr_outstanding.2212039737
Directory	/workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2959305485
Short name	T764
Test name
Test status
Simulation time	167568884 ps
CPU time	11.75 seconds
Started	Apr 16 02:19:16 PM PDT 24
Finished	Apr 16 02:19:30 PM PDT 24
Peak memory	217412 kb
Host	smart-93c382c6-8868-4f1e-b616-2c103de1dbd4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959305485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2959305485
Directory	/workspace/0.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1030844553
Short name	T116
Test name
Test status
Simulation time	10378002123 ps
CPU time	96.68 seconds
Started	Apr 16 02:19:15 PM PDT 24
Finished	Apr 16 02:20:54 PM PDT 24
Peak memory	213912 kb
Host	smart-3a441dbf-31fd-49c7-ac40-b773b91f4e65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030844553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in tg_err.1030844553
Directory	/workspace/0.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2675727622
Short name	T83
Test name
Test status
Simulation time	3713016058 ps
CPU time	30.36 seconds
Started	Apr 16 02:19:21 PM PDT 24
Finished	Apr 16 02:19:52 PM PDT 24
Peak memory	211724 kb
Host	smart-6df3acf3-19e6-40f8-b159-33340b841bc6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675727622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia sing.2675727622
Directory	/workspace/1.rom_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2783696511
Short name	T699
Test name
Test status
Simulation time	171162744 ps
CPU time	8.66 seconds
Started	Apr 16 02:19:21 PM PDT 24
Finished	Apr 16 02:19:31 PM PDT 24
Peak memory	211252 kb
Host	smart-d2b129c7-7244-4a06-ad5f-a025f66f2091
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783696511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ bash.2783696511
Directory	/workspace/1.rom_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2913230962
Short name	T86
Test name
Test status
Simulation time	708737011 ps
CPU time	15.6 seconds
Started	Apr 16 02:19:21 PM PDT 24
Finished	Apr 16 02:19:38 PM PDT 24
Peak memory	212112 kb
Host	smart-e405701c-d8a0-4dcb-ac21-60b5ae349805
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913230962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r eset.2913230962
Directory	/workspace/1.rom_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1698551670
Short name	T683
Test name
Test status
Simulation time	2174696159 ps
CPU time	18.35 seconds
Started	Apr 16 02:19:19 PM PDT 24
Finished	Apr 16 02:19:39 PM PDT 24
Peak memory	217136 kb
Host	smart-d0ac2bd5-f696-4dae-b12d-407d2ba412cf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698551670 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1698551670
Directory	/workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4001648954
Short name	T728
Test name
Test status
Simulation time	1699212836 ps
CPU time	19.2 seconds
Started	Apr 16 02:19:20 PM PDT 24
Finished	Apr 16 02:19:40 PM PDT 24
Peak memory	211800 kb
Host	smart-69795b4e-a8af-4065-94c6-a1f9637cf5b6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001648954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4001648954
Directory	/workspace/1.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3227815644
Short name	T747
Test name
Test status
Simulation time	5131841825 ps
CPU time	28.57 seconds
Started	Apr 16 02:19:19 PM PDT 24
Finished	Apr 16 02:19:49 PM PDT 24
Peak memory	211228 kb
Host	smart-6f0fad82-1fe0-4838-b354-a686bd7852c3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227815644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr l_mem_partial_access.3227815644
Directory	/workspace/1.rom_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.963452541
Short name	T744
Test name
Test status
Simulation time	8200456182 ps
CPU time	18.11 seconds
Started	Apr 16 02:19:20 PM PDT 24
Finished	Apr 16 02:19:39 PM PDT 24
Peak memory	211300 kb
Host	smart-fa828ae1-1fc6-49bd-9f66-5603f224ed30
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963452541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk. 963452541
Directory	/workspace/1.rom_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1061255153
Short name	T85
Test name
Test status
Simulation time	73251806552 ps
CPU time	130.72 seconds
Started	Apr 16 02:19:21 PM PDT 24
Finished	Apr 16 02:21:32 PM PDT 24
Peak memory	214436 kb
Host	smart-c163fe50-23d2-42b3-ab55-9b671eab175d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061255153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa ssthru_mem_tl_intg_err.1061255153
Directory	/workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3583435343
Short name	T714
Test name
Test status
Simulation time	351187032 ps
CPU time	12.36 seconds
Started	Apr 16 02:19:20 PM PDT 24
Finished	Apr 16 02:19:34 PM PDT 24
Peak memory	211340 kb
Host	smart-56d18d4c-4866-4f60-b899-e5ce9f2a221e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583435343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c trl_same_csr_outstanding.3583435343
Directory	/workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4113407148
Short name	T730
Test name
Test status
Simulation time	1880578653 ps
CPU time	25.19 seconds
Started	Apr 16 02:19:20 PM PDT 24
Finished	Apr 16 02:19:46 PM PDT 24
Peak memory	218596 kb
Host	smart-0af96122-9490-4e5d-9de7-073e374a3dbb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113407148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4113407148
Directory	/workspace/1.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1925397874
Short name	T736
Test name
Test status
Simulation time	625424854 ps
CPU time	13.42 seconds
Started	Apr 16 02:19:40 PM PDT 24
Finished	Apr 16 02:19:55 PM PDT 24
Peak memory	217688 kb
Host	smart-f68d1370-55c3-4856-ad71-c944c730641b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925397874 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1925397874
Directory	/workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1321072509
Short name	T74
Test name
Test status
Simulation time	38106481900 ps
CPU time	26.7 seconds
Started	Apr 16 02:19:38 PM PDT 24
Finished	Apr 16 02:20:06 PM PDT 24
Peak memory	212420 kb
Host	smart-82d24b65-66e0-4f82-855c-f3c93706456a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321072509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1321072509
Directory	/workspace/10.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2144775054
Short name	T84
Test name
Test status
Simulation time	4709782320 ps
CPU time	85.61 seconds
Started	Apr 16 02:19:34 PM PDT 24
Finished	Apr 16 02:21:01 PM PDT 24
Peak memory	215784 kb
Host	smart-6be5282c-38ee-4694-bbfe-5215262a2068
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144775054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p assthru_mem_tl_intg_err.2144775054
Directory	/workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.566533966
Short name	T739
Test name
Test status
Simulation time	27407954556 ps
CPU time	29.74 seconds
Started	Apr 16 02:19:39 PM PDT 24
Finished	Apr 16 02:20:11 PM PDT 24
Peak memory	212888 kb
Host	smart-fabd2491-723b-450d-b1b3-6f6c51bd26ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566533966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c trl_same_csr_outstanding.566533966
Directory	/workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.621480209
Short name	T702
Test name
Test status
Simulation time	6554587319 ps
CPU time	28.42 seconds
Started	Apr 16 02:19:36 PM PDT 24
Finished	Apr 16 02:20:06 PM PDT 24
Peak memory	218416 kb
Host	smart-26e0f233-dc55-4df3-b9c4-3811563fd4f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621480209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.621480209
Directory	/workspace/10.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3980992407
Short name	T689
Test name
Test status
Simulation time	10350213669 ps
CPU time	23.03 seconds
Started	Apr 16 02:19:39 PM PDT 24
Finished	Apr 16 02:20:04 PM PDT 24
Peak memory	217712 kb
Host	smart-5e3004cf-ff36-4f3c-8207-e0d6beea6a7d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980992407 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3980992407
Directory	/workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.929191872
Short name	T79
Test name
Test status
Simulation time	331614284 ps
CPU time	8.23 seconds
Started	Apr 16 02:19:39 PM PDT 24
Finished	Apr 16 02:19:49 PM PDT 24
Peak memory	211316 kb
Host	smart-4843bb51-d82b-49b8-a6d2-326311491b53
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929191872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.929191872
Directory	/workspace/11.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1797947802
Short name	T75
Test name
Test status
Simulation time	1074419140 ps
CPU time	56.17 seconds
Started	Apr 16 02:19:40 PM PDT 24
Finished	Apr 16 02:20:38 PM PDT 24
Peak memory	214516 kb
Host	smart-7be2bb4a-d59e-429d-8c6f-bf9cb8863398
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797947802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p assthru_mem_tl_intg_err.1797947802
Directory	/workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1762485840
Short name	T715
Test name
Test status
Simulation time	5334243132 ps
CPU time	27.79 seconds
Started	Apr 16 02:19:38 PM PDT 24
Finished	Apr 16 02:20:08 PM PDT 24
Peak memory	212828 kb
Host	smart-29763a99-0f08-453f-9049-801b38ddb6f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762485840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ ctrl_same_csr_outstanding.1762485840
Directory	/workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3763060688
Short name	T757
Test name
Test status
Simulation time	3210977238 ps
CPU time	31.07 seconds
Started	Apr 16 02:19:40 PM PDT 24
Finished	Apr 16 02:20:13 PM PDT 24
Peak memory	217668 kb
Host	smart-cc6bf762-32ec-40ce-b159-ce125777f2ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763060688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3763060688
Directory	/workspace/11.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1590847881
Short name	T121
Test name
Test status
Simulation time	635510592 ps
CPU time	156.55 seconds
Started	Apr 16 02:19:40 PM PDT 24
Finished	Apr 16 02:22:18 PM PDT 24
Peak memory	213988 kb
Host	smart-4f01d40b-6aee-418b-a19b-d384d634a217
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590847881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i ntg_err.1590847881
Directory	/workspace/11.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.822141368
Short name	T694
Test name
Test status
Simulation time	4389861402 ps
CPU time	34.86 seconds
Started	Apr 16 02:19:39 PM PDT 24
Finished	Apr 16 02:20:16 PM PDT 24
Peak memory	215444 kb
Host	smart-e860be5c-5765-4b47-8787-8b04a12fe03e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822141368 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.822141368
Directory	/workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1538563950
Short name	T713
Test name
Test status
Simulation time	775782377 ps
CPU time	13.13 seconds
Started	Apr 16 02:19:38 PM PDT 24
Finished	Apr 16 02:19:53 PM PDT 24
Peak memory	211316 kb
Host	smart-aedfcd44-ac5e-43be-a7ca-0677bab7213c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538563950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1538563950
Directory	/workspace/12.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1328631295
Short name	T720
Test name
Test status
Simulation time	2757552799 ps
CPU time	37.48 seconds
Started	Apr 16 02:19:38 PM PDT 24
Finished	Apr 16 02:20:17 PM PDT 24
Peak memory	214492 kb
Host	smart-b109b25e-ebb6-469c-b0d0-4cfb11b94a56
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328631295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p assthru_mem_tl_intg_err.1328631295
Directory	/workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1796573970
Short name	T704
Test name
Test status
Simulation time	8285352414 ps
CPU time	20.07 seconds
Started	Apr 16 02:19:39 PM PDT 24
Finished	Apr 16 02:20:01 PM PDT 24
Peak memory	218976 kb
Host	smart-c461967a-ade9-420d-91ec-880cfed5c594
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796573970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1796573970
Directory	/workspace/12.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3786596321
Short name	T114
Test name
Test status
Simulation time	4004504331 ps
CPU time	102.68 seconds
Started	Apr 16 02:19:39 PM PDT 24
Finished	Apr 16 02:21:23 PM PDT 24
Peak memory	213708 kb
Host	smart-0586f3fd-44c4-4f3d-a0be-0d5893471f43
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786596321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i ntg_err.3786596321
Directory	/workspace/12.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2740848773
Short name	T686
Test name
Test status
Simulation time	17571030259 ps
CPU time	23.91 seconds
Started	Apr 16 02:19:46 PM PDT 24
Finished	Apr 16 02:20:11 PM PDT 24
Peak memory	215308 kb
Host	smart-5dabe4fd-31ca-4164-8684-1ddbc08dcf29
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740848773 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2740848773
Directory	/workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3902738380
Short name	T732
Test name
Test status
Simulation time	4098976342 ps
CPU time	32.24 seconds
Started	Apr 16 02:19:45 PM PDT 24
Finished	Apr 16 02:20:19 PM PDT 24
Peak memory	211940 kb
Host	smart-2635bfa3-bc64-4f2b-9e7e-befd0fd89e76
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902738380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3902738380
Directory	/workspace/13.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1846750345
Short name	T696
Test name
Test status
Simulation time	75020050756 ps
CPU time	166.91 seconds
Started	Apr 16 02:19:46 PM PDT 24
Finished	Apr 16 02:22:34 PM PDT 24
Peak memory	214704 kb
Host	smart-64200d1e-7c5a-42bc-af4b-892ff431ad71
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846750345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p assthru_mem_tl_intg_err.1846750345
Directory	/workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.91058803
Short name	T93
Test name
Test status
Simulation time	3753110577 ps
CPU time	29 seconds
Started	Apr 16 02:19:43 PM PDT 24
Finished	Apr 16 02:20:13 PM PDT 24
Peak memory	211988 kb
Host	smart-8cd62449-19cc-4cc8-8dc6-8c7e216c102b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91058803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ct rl_same_csr_outstanding.91058803
Directory	/workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3091737856
Short name	T716
Test name
Test status
Simulation time	718700111 ps
CPU time	12.85 seconds
Started	Apr 16 02:19:45 PM PDT 24
Finished	Apr 16 02:20:00 PM PDT 24
Peak memory	217552 kb
Host	smart-efed90ac-4bcc-48d7-9864-335d0dab0f18
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091737856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3091737856
Directory	/workspace/13.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3686266784
Short name	T729
Test name
Test status
Simulation time	2176019525 ps
CPU time	11.85 seconds
Started	Apr 16 02:19:44 PM PDT 24
Finished	Apr 16 02:19:56 PM PDT 24
Peak memory	217176 kb
Host	smart-8f31aec3-e76b-49ad-9527-9362d12e8188
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686266784 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3686266784
Directory	/workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.393035168
Short name	T691
Test name
Test status
Simulation time	768163019 ps
CPU time	13.26 seconds
Started	Apr 16 02:19:45 PM PDT 24
Finished	Apr 16 02:19:59 PM PDT 24
Peak memory	211332 kb
Host	smart-176e65d9-95a5-445b-bab0-1cd131d32261
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393035168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.393035168
Directory	/workspace/14.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2402938747
Short name	T688
Test name
Test status
Simulation time	16891803090 ps
CPU time	154.94 seconds
Started	Apr 16 02:19:43 PM PDT 24
Finished	Apr 16 02:22:19 PM PDT 24
Peak memory	215744 kb
Host	smart-83c7d853-cdb4-46fb-aa15-54c34f8a0c4b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402938747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p assthru_mem_tl_intg_err.2402938747
Directory	/workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2971468323
Short name	T97
Test name
Test status
Simulation time	3102164734 ps
CPU time	27.82 seconds
Started	Apr 16 02:19:46 PM PDT 24
Finished	Apr 16 02:20:15 PM PDT 24
Peak memory	212548 kb
Host	smart-7fe23b12-7a66-49e2-99cd-c8002166d25a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971468323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ ctrl_same_csr_outstanding.2971468323
Directory	/workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.611938578
Short name	T679
Test name
Test status
Simulation time	15945014243 ps
CPU time	30.13 seconds
Started	Apr 16 02:19:46 PM PDT 24
Finished	Apr 16 02:20:17 PM PDT 24
Peak memory	217668 kb
Host	smart-09f07312-99ae-4d27-895f-cef4f42e8639
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611938578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.611938578
Directory	/workspace/14.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3145651262
Short name	T115
Test name
Test status
Simulation time	298613623 ps
CPU time	82.98 seconds
Started	Apr 16 02:19:44 PM PDT 24
Finished	Apr 16 02:21:08 PM PDT 24
Peak memory	213328 kb
Host	smart-923ea2fc-99bf-4155-8156-2fd09f2680fa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145651262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i ntg_err.3145651262
Directory	/workspace/14.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3118933012
Short name	T724
Test name
Test status
Simulation time	5035239811 ps
CPU time	17.02 seconds
Started	Apr 16 02:19:45 PM PDT 24
Finished	Apr 16 02:20:02 PM PDT 24
Peak memory	217660 kb
Host	smart-8dccb7c3-f10c-40d1-9cb4-04230bf939c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118933012 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3118933012
Directory	/workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1667822914
Short name	T698
Test name
Test status
Simulation time	422664470 ps
CPU time	11.16 seconds
Started	Apr 16 02:19:45 PM PDT 24
Finished	Apr 16 02:19:57 PM PDT 24
Peak memory	211332 kb
Host	smart-3cb5b07a-0013-49d3-9554-4f59a3c189ba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667822914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1667822914
Directory	/workspace/15.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1045169754
Short name	T98
Test name
Test status
Simulation time	8996258073 ps
CPU time	93.54 seconds
Started	Apr 16 02:19:43 PM PDT 24
Finished	Apr 16 02:21:18 PM PDT 24
Peak memory	213756 kb
Host	smart-5efa2ab5-4f31-45f2-b0c4-587bf4774473
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045169754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p assthru_mem_tl_intg_err.1045169754
Directory	/workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2801979310
Short name	T762
Test name
Test status
Simulation time	4320732060 ps
CPU time	19.38 seconds
Started	Apr 16 02:19:46 PM PDT 24
Finished	Apr 16 02:20:06 PM PDT 24
Peak memory	212804 kb
Host	smart-fd2cad42-523f-4a39-abcd-897c04afb0b7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801979310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ ctrl_same_csr_outstanding.2801979310
Directory	/workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2203513823
Short name	T733
Test name
Test status
Simulation time	426327312 ps
CPU time	16.14 seconds
Started	Apr 16 02:19:45 PM PDT 24
Finished	Apr 16 02:20:03 PM PDT 24
Peak memory	217496 kb
Host	smart-44d65158-f3d5-423c-8e2f-ab037031b507
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203513823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2203513823
Directory	/workspace/15.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3433394577
Short name	T62
Test name
Test status
Simulation time	7420847235 ps
CPU time	91.4 seconds
Started	Apr 16 02:19:45 PM PDT 24
Finished	Apr 16 02:21:18 PM PDT 24
Peak memory	214008 kb
Host	smart-a2f02a42-dd72-4f3d-b12e-71c8fe0b9954
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433394577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i ntg_err.3433394577
Directory	/workspace/15.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1168826529
Short name	T752
Test name
Test status
Simulation time	15249652634 ps
CPU time	31.06 seconds
Started	Apr 16 02:19:49 PM PDT 24
Finished	Apr 16 02:20:21 PM PDT 24
Peak memory	218032 kb
Host	smart-2a1ca514-8fe8-469c-841a-27cbe9be45b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168826529 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1168826529
Directory	/workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3828218594
Short name	T690
Test name
Test status
Simulation time	3595677083 ps
CPU time	29.44 seconds
Started	Apr 16 02:19:49 PM PDT 24
Finished	Apr 16 02:20:19 PM PDT 24
Peak memory	211832 kb
Host	smart-9ce2062d-2eca-4b4e-bf4b-a915e4727235
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828218594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3828218594
Directory	/workspace/16.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3549682966
Short name	T741
Test name
Test status
Simulation time	691944361 ps
CPU time	38.64 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:20:28 PM PDT 24
Peak memory	213392 kb
Host	smart-7a675996-7b5f-4307-b30a-a9637d124eea
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549682966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p assthru_mem_tl_intg_err.3549682966
Directory	/workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2141833823
Short name	T95
Test name
Test status
Simulation time	6085485694 ps
CPU time	27.53 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:20:17 PM PDT 24
Peak memory	212684 kb
Host	smart-405fbe02-f766-49e5-988d-8a8c8e0c8794
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141833823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ ctrl_same_csr_outstanding.2141833823
Directory	/workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.914627958
Short name	T672
Test name
Test status
Simulation time	1342859378 ps
CPU time	16.79 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:20:06 PM PDT 24
Peak memory	218452 kb
Host	smart-744021a3-fff2-45b0-b5da-a81d664144ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914627958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.914627958
Directory	/workspace/16.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4179798287
Short name	T745
Test name
Test status
Simulation time	1537241510 ps
CPU time	154.56 seconds
Started	Apr 16 02:19:49 PM PDT 24
Finished	Apr 16 02:22:24 PM PDT 24
Peak memory	213792 kb
Host	smart-fad1408a-5fd9-427d-93d9-95ee731cbecf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179798287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i ntg_err.4179798287
Directory	/workspace/16.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.995942048
Short name	T677
Test name
Test status
Simulation time	3120412831 ps
CPU time	26.76 seconds
Started	Apr 16 02:19:54 PM PDT 24
Finished	Apr 16 02:20:22 PM PDT 24
Peak memory	217972 kb
Host	smart-97aa208d-e46f-448d-9dbb-49a09e5b99fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995942048 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.995942048
Directory	/workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.995410849
Short name	T768
Test name
Test status
Simulation time	2604992296 ps
CPU time	23.15 seconds
Started	Apr 16 02:19:51 PM PDT 24
Finished	Apr 16 02:20:15 PM PDT 24
Peak memory	211932 kb
Host	smart-8d05fc88-2592-45a4-9283-24f76e7519ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995410849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.995410849
Directory	/workspace/17.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1839952285
Short name	T89
Test name
Test status
Simulation time	711786382 ps
CPU time	38.22 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:20:27 PM PDT 24
Peak memory	211404 kb
Host	smart-0d66a85d-377d-49fe-ad34-a85b6473816a
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839952285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p assthru_mem_tl_intg_err.1839952285
Directory	/workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2711922457
Short name	T700
Test name
Test status
Simulation time	951048208 ps
CPU time	18.05 seconds
Started	Apr 16 02:19:50 PM PDT 24
Finished	Apr 16 02:20:09 PM PDT 24
Peak memory	212544 kb
Host	smart-a4d131ea-ec0e-40ec-b33f-f10f05ce821f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711922457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ ctrl_same_csr_outstanding.2711922457
Directory	/workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1137877137
Short name	T754
Test name
Test status
Simulation time	170960847 ps
CPU time	11.78 seconds
Started	Apr 16 02:19:49 PM PDT 24
Finished	Apr 16 02:20:01 PM PDT 24
Peak memory	217344 kb
Host	smart-392d5e0a-5f38-4204-9872-4e3c62efe657
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137877137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1137877137
Directory	/workspace/17.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.710953885
Short name	T113
Test name
Test status
Simulation time	2982762558 ps
CPU time	168.1 seconds
Started	Apr 16 02:19:58 PM PDT 24
Finished	Apr 16 02:22:47 PM PDT 24
Peak memory	214928 kb
Host	smart-bb13a41d-1f3c-4b90-baff-48085bf628f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710953885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in tg_err.710953885
Directory	/workspace/17.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1882051062
Short name	T717
Test name
Test status
Simulation time	3052516826 ps
CPU time	27.47 seconds
Started	Apr 16 02:19:51 PM PDT 24
Finished	Apr 16 02:20:19 PM PDT 24
Peak memory	218180 kb
Host	smart-5f52812d-8de7-4f5c-ba1a-862dc508e023
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882051062 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1882051062
Directory	/workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1354353975
Short name	T77
Test name
Test status
Simulation time	174506914 ps
CPU time	8.27 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:19:57 PM PDT 24
Peak memory	211332 kb
Host	smart-b5f5a677-f07a-4ad4-b1d8-c9846a5e12d4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354353975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1354353975
Directory	/workspace/18.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2581157675
Short name	T703
Test name
Test status
Simulation time	34734581459 ps
CPU time	199.56 seconds
Started	Apr 16 02:19:49 PM PDT 24
Finished	Apr 16 02:23:10 PM PDT 24
Peak memory	215508 kb
Host	smart-e9fadee9-d61c-49de-92ed-9b2df1e03215
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581157675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p assthru_mem_tl_intg_err.2581157675
Directory	/workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.390357719
Short name	T707
Test name
Test status
Simulation time	19322341609 ps
CPU time	28.03 seconds
Started	Apr 16 02:19:49 PM PDT 24
Finished	Apr 16 02:20:18 PM PDT 24
Peak memory	212312 kb
Host	smart-aea47289-dd64-4807-9021-85b1b5da4641
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390357719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c trl_same_csr_outstanding.390357719
Directory	/workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1420563182
Short name	T687
Test name
Test status
Simulation time	7660297576 ps
CPU time	35.18 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:20:24 PM PDT 24
Peak memory	217792 kb
Host	smart-8ebd1032-4b18-46d3-9805-8d2d702aae02
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420563182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1420563182
Directory	/workspace/18.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2949085925
Short name	T118
Test name
Test status
Simulation time	19290077416 ps
CPU time	174.9 seconds
Started	Apr 16 02:19:57 PM PDT 24
Finished	Apr 16 02:22:53 PM PDT 24
Peak memory	214480 kb
Host	smart-e055158e-0216-4d29-992f-9945cc2390e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949085925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i ntg_err.2949085925
Directory	/workspace/18.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.777520385
Short name	T719
Test name
Test status
Simulation time	369604854 ps
CPU time	9.16 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:19:59 PM PDT 24
Peak memory	216568 kb
Host	smart-407b1a2c-90a2-4ce5-81b1-17afd5d6834f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777520385 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.777520385
Directory	/workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3769110025
Short name	T742
Test name
Test status
Simulation time	5693963727 ps
CPU time	25.62 seconds
Started	Apr 16 02:19:51 PM PDT 24
Finished	Apr 16 02:20:17 PM PDT 24
Peak memory	212292 kb
Host	smart-30d7c46d-f1e5-4ddd-bd9f-b44cb7c28798
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769110025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3769110025
Directory	/workspace/19.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2060342107
Short name	T755
Test name
Test status
Simulation time	693651998 ps
CPU time	11.99 seconds
Started	Apr 16 02:19:48 PM PDT 24
Finished	Apr 16 02:20:01 PM PDT 24
Peak memory	212352 kb
Host	smart-9e56ea3b-6a23-4dff-96e2-b9e154cff9d0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060342107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ ctrl_same_csr_outstanding.2060342107
Directory	/workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.900196109
Short name	T722
Test name
Test status
Simulation time	3490575888 ps
CPU time	32.59 seconds
Started	Apr 16 02:19:58 PM PDT 24
Finished	Apr 16 02:20:32 PM PDT 24
Peak memory	217564 kb
Host	smart-82d6280c-0c88-4378-a2be-df75f16ff154
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900196109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.900196109
Directory	/workspace/19.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3773429975
Short name	T108
Test name
Test status
Simulation time	15600961712 ps
CPU time	101.57 seconds
Started	Apr 16 02:19:49 PM PDT 24
Finished	Apr 16 02:21:32 PM PDT 24
Peak memory	213644 kb
Host	smart-ce4141d0-eb76-463e-a786-09319b131b4d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773429975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i ntg_err.3773429975
Directory	/workspace/19.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1459110904
Short name	T708
Test name
Test status
Simulation time	38436902715 ps
CPU time	30.36 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:19:59 PM PDT 24
Peak memory	212124 kb
Host	smart-c4ab8a8d-aae9-4046-ab33-40caf32d2aee
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459110904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia sing.1459110904
Directory	/workspace/2.rom_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1977464223
Short name	T721
Test name
Test status
Simulation time	345879945 ps
CPU time	8.49 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:19:34 PM PDT 24
Peak memory	211296 kb
Host	smart-90f89c03-e8ef-4ecf-b793-8fe082cf62dc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977464223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ bash.1977464223
Directory	/workspace/2.rom_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2310341599
Short name	T760
Test name
Test status
Simulation time	6624482761 ps
CPU time	34.73 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:20:00 PM PDT 24
Peak memory	212376 kb
Host	smart-ec8562d7-a6c9-474a-93e4-fc5dee327332
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310341599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r eset.2310341599
Directory	/workspace/2.rom_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1268088810
Short name	T675
Test name
Test status
Simulation time	7325656922 ps
CPU time	20.8 seconds
Started	Apr 16 02:19:25 PM PDT 24
Finished	Apr 16 02:19:47 PM PDT 24
Peak memory	218580 kb
Host	smart-a7618db5-1bed-481e-8336-e6193c383fcd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268088810 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1268088810
Directory	/workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3695505121
Short name	T769
Test name
Test status
Simulation time	4696161846 ps
CPU time	22.12 seconds
Started	Apr 16 02:19:25 PM PDT 24
Finished	Apr 16 02:19:49 PM PDT 24
Peak memory	212144 kb
Host	smart-048c9648-ae3b-499b-972d-4362f8c08ef8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695505121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3695505121
Directory	/workspace/2.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2464246275
Short name	T740
Test name
Test status
Simulation time	332275525 ps
CPU time	8.59 seconds
Started	Apr 16 02:19:25 PM PDT 24
Finished	Apr 16 02:19:36 PM PDT 24
Peak memory	211084 kb
Host	smart-4a6080dc-6252-420a-bd31-2cf2f9c319fa
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464246275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr l_mem_partial_access.2464246275
Directory	/workspace/2.rom_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.554130864
Short name	T734
Test name
Test status
Simulation time	1372286548 ps
CPU time	12.56 seconds
Started	Apr 16 02:19:19 PM PDT 24
Finished	Apr 16 02:19:33 PM PDT 24
Peak memory	211228 kb
Host	smart-5e38f812-81ef-49cd-84b5-bf6eae5f322b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554130864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk. 554130864
Directory	/workspace/2.rom_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1131644101
Short name	T712
Test name
Test status
Simulation time	75637927352 ps
CPU time	127.28 seconds
Started	Apr 16 02:19:20 PM PDT 24
Finished	Apr 16 02:21:28 PM PDT 24
Peak memory	219572 kb
Host	smart-27cff1e7-60d6-4d2d-a1f0-d14454a92a15
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131644101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa ssthru_mem_tl_intg_err.1131644101
Directory	/workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1280455010
Short name	T701
Test name
Test status
Simulation time	640828966 ps
CPU time	12.32 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:19:38 PM PDT 24
Peak memory	212524 kb
Host	smart-0a3a8556-5bf8-45cc-8873-1bbe3918b7f4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280455010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c trl_same_csr_outstanding.1280455010
Directory	/workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.529058378
Short name	T731
Test name
Test status
Simulation time	765359442 ps
CPU time	16.31 seconds
Started	Apr 16 02:19:21 PM PDT 24
Finished	Apr 16 02:19:39 PM PDT 24
Peak memory	217172 kb
Host	smart-228d3995-6d22-47bb-8678-8cccbe03435b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529058378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.529058378
Directory	/workspace/2.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.473837789
Short name	T711
Test name
Test status
Simulation time	16475543690 ps
CPU time	32.33 seconds
Started	Apr 16 02:19:25 PM PDT 24
Finished	Apr 16 02:19:59 PM PDT 24
Peak memory	211788 kb
Host	smart-d66f26ca-8f42-4eca-b058-a1cde307de98
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473837789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias ing.473837789
Directory	/workspace/3.rom_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.505041736
Short name	T726
Test name
Test status
Simulation time	1862132134 ps
CPU time	20.23 seconds
Started	Apr 16 02:19:27 PM PDT 24
Finished	Apr 16 02:19:49 PM PDT 24
Peak memory	211680 kb
Host	smart-c3138ca0-be57-4cc3-b27a-fcb80cccc49d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505041736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b ash.505041736
Directory	/workspace/3.rom_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1662081877
Short name	T72
Test name
Test status
Simulation time	170764076 ps
CPU time	11.94 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:19:37 PM PDT 24
Peak memory	211828 kb
Host	smart-11389254-ce3b-468b-b346-ad9862ded1ac
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662081877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r eset.1662081877
Directory	/workspace/3.rom_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3268124953
Short name	T735
Test name
Test status
Simulation time	9860785426 ps
CPU time	23.9 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:19:49 PM PDT 24
Peak memory	219280 kb
Host	smart-3e16dc63-9caf-4eae-a232-eb210145bd3c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268124953 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3268124953
Directory	/workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.966757410
Short name	T92
Test name
Test status
Simulation time	1969401178 ps
CPU time	14.49 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:19:45 PM PDT 24
Peak memory	211312 kb
Host	smart-7171f822-b37a-4c4b-85aa-e4b29bf4c1ed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966757410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.966757410
Directory	/workspace/3.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.674039511
Short name	T673
Test name
Test status
Simulation time	404797098 ps
CPU time	8.08 seconds
Started	Apr 16 02:19:29 PM PDT 24
Finished	Apr 16 02:19:39 PM PDT 24
Peak memory	211012 kb
Host	smart-e3cd73b4-85c6-4287-ac00-d586e748c2c9
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674039511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl _mem_partial_access.674039511
Directory	/workspace/3.rom_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.229155552
Short name	T738
Test name
Test status
Simulation time	272417635 ps
CPU time	8.41 seconds
Started	Apr 16 02:19:23 PM PDT 24
Finished	Apr 16 02:19:32 PM PDT 24
Peak memory	211236 kb
Host	smart-00312091-c861-4c1b-a9f7-03011e1a367d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229155552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk. 229155552
Directory	/workspace/3.rom_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1596598725
Short name	T87
Test name
Test status
Simulation time	37583426844 ps
CPU time	117.19 seconds
Started	Apr 16 02:19:25 PM PDT 24
Finished	Apr 16 02:21:24 PM PDT 24
Peak memory	215696 kb
Host	smart-2069551a-9dad-40a8-9c26-ce5392f83c94
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596598725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa ssthru_mem_tl_intg_err.1596598725
Directory	/workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.330856844
Short name	T78
Test name
Test status
Simulation time	4035449165 ps
CPU time	32.13 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:19:58 PM PDT 24
Peak memory	211852 kb
Host	smart-68bc70cc-7618-4a1c-8835-4ad893237462
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330856844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct rl_same_csr_outstanding.330856844
Directory	/workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4248011672
Short name	T727
Test name
Test status
Simulation time	352841136 ps
CPU time	12.74 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:19:38 PM PDT 24
Peak memory	217536 kb
Host	smart-44dee5a5-b913-4244-82d7-43882dd4c79b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248011672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4248011672
Directory	/workspace/3.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3010615614
Short name	T746
Test name
Test status
Simulation time	16956125698 ps
CPU time	174.46 seconds
Started	Apr 16 02:19:29 PM PDT 24
Finished	Apr 16 02:22:25 PM PDT 24
Peak memory	214284 kb
Host	smart-ca64631c-19ef-4502-9026-7baf627ba01a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010615614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in tg_err.3010615614
Directory	/workspace/3.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3896386130
Short name	T88
Test name
Test status
Simulation time	167331013 ps
CPU time	8.24 seconds
Started	Apr 16 02:19:26 PM PDT 24
Finished	Apr 16 02:19:36 PM PDT 24
Peak memory	211312 kb
Host	smart-ea2c9e1b-7f2a-413c-ac4f-5b00518427c1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896386130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia sing.3896386130
Directory	/workspace/4.rom_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2028470803
Short name	T756
Test name
Test status
Simulation time	15733494090 ps
CPU time	31.54 seconds
Started	Apr 16 02:19:26 PM PDT 24
Finished	Apr 16 02:19:59 PM PDT 24
Peak memory	212212 kb
Host	smart-0b95f2a2-9a3f-421b-9e1d-9fb7c6942e39
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028470803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ bash.2028470803
Directory	/workspace/4.rom_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.222072639
Short name	T681
Test name
Test status
Simulation time	2346110935 ps
CPU time	26.6 seconds
Started	Apr 16 02:19:26 PM PDT 24
Finished	Apr 16 02:19:54 PM PDT 24
Peak memory	212128 kb
Host	smart-6150097b-8ef2-474b-a001-d356041d401d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222072639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re set.222072639
Directory	/workspace/4.rom_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3297227326
Short name	T723
Test name
Test status
Simulation time	4424913294 ps
CPU time	22.72 seconds
Started	Apr 16 02:19:29 PM PDT 24
Finished	Apr 16 02:19:53 PM PDT 24
Peak memory	218532 kb
Host	smart-3869dde0-ccf8-4e2f-b6dc-74c310912127
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297227326 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3297227326
Directory	/workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3485731164
Short name	T763
Test name
Test status
Simulation time	1727642364 ps
CPU time	16.78 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:19:46 PM PDT 24
Peak memory	211956 kb
Host	smart-f50fddb0-1380-4480-ab8e-80a9067ea3f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485731164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3485731164
Directory	/workspace/4.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.652051607
Short name	T678
Test name
Test status
Simulation time	3092603409 ps
CPU time	17.23 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:19:47 PM PDT 24
Peak memory	211248 kb
Host	smart-0307d1c6-5c43-4d32-916e-44393a53a009
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652051607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl _mem_partial_access.652051607
Directory	/workspace/4.rom_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1135030337
Short name	T671
Test name
Test status
Simulation time	674375770 ps
CPU time	13.05 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:19:42 PM PDT 24
Peak memory	211256 kb
Host	smart-5a1efce5-aea5-4274-8031-a14b6cdf7a4c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135030337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk .1135030337
Directory	/workspace/4.rom_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4129463874
Short name	T682
Test name
Test status
Simulation time	134398416564 ps
CPU time	179.59 seconds
Started	Apr 16 02:19:29 PM PDT 24
Finished	Apr 16 02:22:31 PM PDT 24
Peak memory	215356 kb
Host	smart-6d7c4c94-d873-4113-b87d-445ef23e0d61
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129463874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa ssthru_mem_tl_intg_err.4129463874
Directory	/workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2492030398
Short name	T96
Test name
Test status
Simulation time	17333633310 ps
CPU time	26.02 seconds
Started	Apr 16 02:19:29 PM PDT 24
Finished	Apr 16 02:19:57 PM PDT 24
Peak memory	212712 kb
Host	smart-2e6b5a14-301a-4470-84ba-fca261183e59
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492030398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c trl_same_csr_outstanding.2492030398
Directory	/workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.908255920
Short name	T705
Test name
Test status
Simulation time	2731022851 ps
CPU time	17.89 seconds
Started	Apr 16 02:19:23 PM PDT 24
Finished	Apr 16 02:19:41 PM PDT 24
Peak memory	217508 kb
Host	smart-06887fe5-a619-42c1-acc9-cb0419055956
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908255920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.908255920
Directory	/workspace/4.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3115733258
Short name	T63
Test name
Test status
Simulation time	4682592488 ps
CPU time	94.73 seconds
Started	Apr 16 02:19:24 PM PDT 24
Finished	Apr 16 02:21:00 PM PDT 24
Peak memory	214032 kb
Host	smart-9902b034-f36b-4169-bced-42ec3e651ef4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115733258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in tg_err.3115733258
Directory	/workspace/4.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4218060463
Short name	T725
Test name
Test status
Simulation time	2676888588 ps
CPU time	14.85 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:19:45 PM PDT 24
Peak memory	217372 kb
Host	smart-62472d61-597c-4abd-bd69-fe26ca97de92
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218060463 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4218060463
Directory	/workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.236554003
Short name	T737
Test name
Test status
Simulation time	2949505538 ps
CPU time	26.47 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:19:56 PM PDT 24
Peak memory	211640 kb
Host	smart-d9769820-26bd-4387-b439-29ca3a790a39
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236554003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.236554003
Directory	/workspace/5.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.51841143
Short name	T73
Test name
Test status
Simulation time	1048251264 ps
CPU time	57.86 seconds
Started	Apr 16 02:19:31 PM PDT 24
Finished	Apr 16 02:20:30 PM PDT 24
Peak memory	214480 kb
Host	smart-518d9daf-b318-4aa4-8421-d4ec72bd3e4f
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51841143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pass thru_mem_tl_intg_err.51841143
Directory	/workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.239952446
Short name	T765
Test name
Test status
Simulation time	3549742800 ps
CPU time	28.41 seconds
Started	Apr 16 02:19:34 PM PDT 24
Finished	Apr 16 02:20:03 PM PDT 24
Peak memory	212240 kb
Host	smart-d3dda3d6-7aa9-41a8-879a-55bef6362711
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239952446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct rl_same_csr_outstanding.239952446
Directory	/workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3015897852
Short name	T753
Test name
Test status
Simulation time	2945179138 ps
CPU time	30.41 seconds
Started	Apr 16 02:19:30 PM PDT 24
Finished	Apr 16 02:20:03 PM PDT 24
Peak memory	218408 kb
Host	smart-9983725d-530b-4a23-91d8-faa81e9227a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015897852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3015897852
Directory	/workspace/5.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3424934838
Short name	T761
Test name
Test status
Simulation time	13279752761 ps
CPU time	100.02 seconds
Started	Apr 16 02:19:28 PM PDT 24
Finished	Apr 16 02:21:10 PM PDT 24
Peak memory	214680 kb
Host	smart-f2b9cf7d-e230-47a9-8f69-1d1bf38db338
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424934838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in tg_err.3424934838
Directory	/workspace/5.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2214009994
Short name	T66
Test name
Test status
Simulation time	6159969747 ps
CPU time	26.75 seconds
Started	Apr 16 02:19:30 PM PDT 24
Finished	Apr 16 02:19:58 PM PDT 24
Peak memory	216108 kb
Host	smart-3b1ce529-78b2-4523-aa3e-f579cee1cc39
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214009994 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2214009994
Directory	/workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3216785100
Short name	T766
Test name
Test status
Simulation time	4119115347 ps
CPU time	32.17 seconds
Started	Apr 16 02:19:30 PM PDT 24
Finished	Apr 16 02:20:04 PM PDT 24
Peak memory	211896 kb
Host	smart-953411e2-e4b8-4e86-a73d-29b2f80256cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216785100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3216785100
Directory	/workspace/6.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3219995978
Short name	T751
Test name
Test status
Simulation time	74695064844 ps
CPU time	168.75 seconds
Started	Apr 16 02:19:31 PM PDT 24
Finished	Apr 16 02:22:21 PM PDT 24
Peak memory	215504 kb
Host	smart-931e17ad-5768-487d-b567-3ed8e095391d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219995978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa ssthru_mem_tl_intg_err.3219995978
Directory	/workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1406406232
Short name	T767
Test name
Test status
Simulation time	2973671160 ps
CPU time	25.87 seconds
Started	Apr 16 02:19:27 PM PDT 24
Finished	Apr 16 02:19:54 PM PDT 24
Peak memory	212208 kb
Host	smart-65ad8a63-3776-41f2-b19f-5bcc6002fdd3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406406232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c trl_same_csr_outstanding.1406406232
Directory	/workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2357912057
Short name	T670
Test name
Test status
Simulation time	3175596395 ps
CPU time	22.68 seconds
Started	Apr 16 02:19:30 PM PDT 24
Finished	Apr 16 02:19:55 PM PDT 24
Peak memory	218736 kb
Host	smart-8aeb3f13-cd77-491d-a7cb-f1f1377b0ea6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357912057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2357912057
Directory	/workspace/6.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3438612192
Short name	T718
Test name
Test status
Simulation time	5905389459 ps
CPU time	18.03 seconds
Started	Apr 16 02:19:29 PM PDT 24
Finished	Apr 16 02:19:48 PM PDT 24
Peak memory	214052 kb
Host	smart-4875af46-a605-4d0c-bb62-bc6ce0396af5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438612192 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3438612192
Directory	/workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3306506471
Short name	T685
Test name
Test status
Simulation time	57317527312 ps
CPU time	32.04 seconds
Started	Apr 16 02:19:34 PM PDT 24
Finished	Apr 16 02:20:07 PM PDT 24
Peak memory	212100 kb
Host	smart-7b905dc5-43a3-49e0-89dd-0792c4caf50f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306506471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3306506471
Directory	/workspace/7.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2870671828
Short name	T750
Test name
Test status
Simulation time	12417969367 ps
CPU time	57.72 seconds
Started	Apr 16 02:19:30 PM PDT 24
Finished	Apr 16 02:20:30 PM PDT 24
Peak memory	211792 kb
Host	smart-ba179b35-f3ca-4e3c-a68a-2c841461bc86
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870671828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa ssthru_mem_tl_intg_err.2870671828
Directory	/workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3567758187
Short name	T67
Test name
Test status
Simulation time	3251860358 ps
CPU time	21.38 seconds
Started	Apr 16 02:19:34 PM PDT 24
Finished	Apr 16 02:19:57 PM PDT 24
Peak memory	212540 kb
Host	smart-d8511403-ca0b-4192-b5b0-b69b473fb854
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567758187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c trl_same_csr_outstanding.3567758187
Directory	/workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2871137911
Short name	T684
Test name
Test status
Simulation time	11092474202 ps
CPU time	27.98 seconds
Started	Apr 16 02:19:31 PM PDT 24
Finished	Apr 16 02:20:00 PM PDT 24
Peak memory	217484 kb
Host	smart-ce365d02-3eff-4790-a7ac-7b72b3b492a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871137911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2871137911
Directory	/workspace/7.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3678454939
Short name	T680
Test name
Test status
Simulation time	17969628808 ps
CPU time	15.97 seconds
Started	Apr 16 02:19:34 PM PDT 24
Finished	Apr 16 02:19:51 PM PDT 24
Peak memory	216020 kb
Host	smart-1ce8b6e5-ab74-4964-b00d-2b6167288c5d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678454939 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3678454939
Directory	/workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3659221865
Short name	T758
Test name
Test status
Simulation time	3498974508 ps
CPU time	27.93 seconds
Started	Apr 16 02:19:33 PM PDT 24
Finished	Apr 16 02:20:02 PM PDT 24
Peak memory	211368 kb
Host	smart-f19c84e7-f501-4463-99f2-ff766e925770
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659221865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3659221865
Directory	/workspace/8.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3984734281
Short name	T90
Test name
Test status
Simulation time	15428037293 ps
CPU time	124.95 seconds
Started	Apr 16 02:19:35 PM PDT 24
Finished	Apr 16 02:21:41 PM PDT 24
Peak memory	214444 kb
Host	smart-01948812-e923-4f63-8377-7f21e9e23bf4
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984734281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa ssthru_mem_tl_intg_err.3984734281
Directory	/workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3027091450
Short name	T709
Test name
Test status
Simulation time	76978857869 ps
CPU time	31.22 seconds
Started	Apr 16 02:19:32 PM PDT 24
Finished	Apr 16 02:20:05 PM PDT 24
Peak memory	212532 kb
Host	smart-6cea63fb-cdf6-484f-9b34-d85073412fca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027091450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c trl_same_csr_outstanding.3027091450
Directory	/workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.487990459
Short name	T697
Test name
Test status
Simulation time	4292839951 ps
CPU time	37.27 seconds
Started	Apr 16 02:19:35 PM PDT 24
Finished	Apr 16 02:20:14 PM PDT 24
Peak memory	218784 kb
Host	smart-8ca75edd-0b0c-4b43-a594-20d3d10eb9c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487990459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.487990459
Directory	/workspace/8.rom_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3545917563
Short name	T110
Test name
Test status
Simulation time	10829810776 ps
CPU time	166.66 seconds
Started	Apr 16 02:19:35 PM PDT 24
Finished	Apr 16 02:22:24 PM PDT 24
Peak memory	214284 kb
Host	smart-f340803f-e19a-47c4-a91b-8a14f4e36894
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545917563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in tg_err.3545917563
Directory	/workspace/8.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.831505559
Short name	T674
Test name
Test status
Simulation time	6491411231 ps
CPU time	30.66 seconds
Started	Apr 16 02:19:36 PM PDT 24
Finished	Apr 16 02:20:08 PM PDT 24
Peak memory	216548 kb
Host	smart-fa723a7a-aac8-467a-86fd-2dac97003079
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831505559 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.831505559
Directory	/workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1371680367
Short name	T749
Test name
Test status
Simulation time	10087010508 ps
CPU time	22.77 seconds
Started	Apr 16 02:19:37 PM PDT 24
Finished	Apr 16 02:20:01 PM PDT 24
Peak memory	212204 kb
Host	smart-d45ed56e-59db-448a-a2b5-a66a5494c25c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371680367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1371680367
Directory	/workspace/9.rom_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.540030468
Short name	T71
Test name
Test status
Simulation time	9422954316 ps
CPU time	69.11 seconds
Started	Apr 16 02:19:34 PM PDT 24
Finished	Apr 16 02:20:45 PM PDT 24
Peak memory	214568 kb
Host	smart-88078b71-0200-4c2b-a7c7-c80e5bcd288a
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540030468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas sthru_mem_tl_intg_err.540030468
Directory	/workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.637443623
Short name	T710
Test name
Test status
Simulation time	9873615623 ps
CPU time	24.35 seconds
Started	Apr 16 02:19:35 PM PDT 24
Finished	Apr 16 02:20:01 PM PDT 24
Peak memory	212400 kb
Host	smart-0f65044d-262c-4b08-a073-bb0a7368ef81
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637443623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct rl_same_csr_outstanding.637443623
Directory	/workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1984255151
Short name	T117
Test name
Test status
Simulation time	8445574812 ps
CPU time	163.56 seconds
Started	Apr 16 02:19:36 PM PDT 24
Finished	Apr 16 02:22:21 PM PDT 24
Peak memory	214404 kb
Host	smart-bfdc1aaf-5abc-4d7b-ae70-5e778c84130f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984255151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in tg_err.1984255151
Directory	/workspace/9.rom_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rom_ctrl_alert_test.2903237392
Short name	T7
Test name
Test status
Simulation time	1936125389 ps
CPU time	20.35 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:03:28 PM PDT 24
Peak memory	211300 kb
Host	smart-5d88b4a8-335c-4249-a89f-b844d47fbe78
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903237392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2903237392
Directory	/workspace/0.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.rom_ctrl_alert_test.3679371526
Short name	T186
Test name
Test status
Simulation time	2297185559 ps
CPU time	15.69 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:23:03 PM PDT 24
Peak memory	211052 kb
Host	smart-f25de554-3ec6-439b-9734-fa5743c117fe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679371526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3679371526
Directory	/workspace/0.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4002334350
Short name	T265
Test name
Test status
Simulation time	62712402392 ps
CPU time	375.96 seconds
Started	Apr 16 02:02:36 PM PDT 24
Finished	Apr 16 02:08:53 PM PDT 24
Peak memory	237964 kb
Host	smart-c63d981d-2015-44e8-8e29-0419f2c8f33a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002334350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c orrupt_sig_fatal_chk.4002334350
Directory	/workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.619450858
Short name	T204
Test name
Test status
Simulation time	324843023570 ps
CPU time	270.64 seconds
Started	Apr 16 12:21:14 PM PDT 24
Finished	Apr 16 12:25:46 PM PDT 24
Peak memory	227748 kb
Host	smart-bafbbbce-1b3a-4412-b16c-9f73732232a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619450858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co rrupt_sig_fatal_chk.619450858
Directory	/workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2250787981
Short name	T150
Test name
Test status
Simulation time	16729705423 ps
CPU time	66.32 seconds
Started	Apr 16 02:02:35 PM PDT 24
Finished	Apr 16 02:03:42 PM PDT 24
Peak memory	215232 kb
Host	smart-6deb7200-f308-4269-bfdb-2c28a0191285
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2250787981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2250787981
Directory	/workspace/0.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/0.rom_ctrl_kmac_err_chk.777564282
Short name	T357
Test name
Test status
Simulation time	5087608523 ps
CPU time	50.23 seconds
Started	Apr 16 12:21:04 PM PDT 24
Finished	Apr 16 12:21:57 PM PDT 24
Peak memory	214044 kb
Host	smart-719542ef-54ac-4ef9-88fa-8e3654502a58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777564282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.777564282
Directory	/workspace/0.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1760024749
Short name	T619
Test name
Test status
Simulation time	8530788334 ps
CPU time	34.83 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:03:25 PM PDT 24
Peak memory	212940 kb
Host	smart-0af80365-2525-4e2e-96e2-f3595edf03f6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1760024749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1760024749
Directory	/workspace/0.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2977181614
Short name	T319
Test name
Test status
Simulation time	2487252491 ps
CPU time	17.54 seconds
Started	Apr 16 12:21:12 PM PDT 24
Finished	Apr 16 12:21:31 PM PDT 24
Peak memory	212164 kb
Host	smart-3011e5c4-127e-4fff-94bc-7101fa3b5ab8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2977181614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2977181614
Directory	/workspace/0.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/0.rom_ctrl_sec_cm.2467246655
Short name	T37
Test name
Test status
Simulation time	2171522249 ps
CPU time	232.77 seconds
Started	Apr 16 12:21:05 PM PDT 24
Finished	Apr 16 12:25:00 PM PDT 24
Peak memory	237816 kb
Host	smart-2d9786a5-f09a-4f42-9323-4dc882947730
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467246655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2467246655
Directory	/workspace/0.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.rom_ctrl_sec_cm.285886589
Short name	T40
Test name
Test status
Simulation time	3597057666 ps
CPU time	122.13 seconds
Started	Apr 16 02:02:36 PM PDT 24
Finished	Apr 16 02:04:39 PM PDT 24
Peak memory	236956 kb
Host	smart-31093e82-c3a7-4a6b-afa8-b68d299d794c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285886589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.285886589
Directory	/workspace/0.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.rom_ctrl_smoke.2248900039
Short name	T148
Test name
Test status
Simulation time	2182641287 ps
CPU time	34.41 seconds
Started	Apr 16 12:21:37 PM PDT 24
Finished	Apr 16 12:22:13 PM PDT 24
Peak memory	216740 kb
Host	smart-deef8dc6-952c-4e6a-a0e2-cfaef963475b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248900039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2248900039
Directory	/workspace/0.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.rom_ctrl_smoke.2385444071
Short name	T80
Test name
Test status
Simulation time	14817541027 ps
CPU time	73.69 seconds
Started	Apr 16 02:02:43 PM PDT 24
Finished	Apr 16 02:03:59 PM PDT 24
Peak memory	217560 kb
Host	smart-6955d8b4-ad0c-4af6-a8e3-07f76a61f145
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385444071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2385444071
Directory	/workspace/0.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.rom_ctrl_stress_all.1180720972
Short name	T465
Test name
Test status
Simulation time	3309228999 ps
CPU time	32.15 seconds
Started	Apr 16 12:22:47 PM PDT 24
Finished	Apr 16 12:23:24 PM PDT 24
Peak memory	210840 kb
Host	smart-7d0318fa-d154-43bb-8a96-21de6ee51699
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180720972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.rom_ctrl_stress_all.1180720972
Directory	/workspace/0.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.rom_ctrl_stress_all.671055473
Short name	T242
Test name
Test status
Simulation time	5008331014 ps
CPU time	20.29 seconds
Started	Apr 16 02:02:42 PM PDT 24
Finished	Apr 16 02:03:04 PM PDT 24
Peak memory	216332 kb
Host	smart-9c1cec54-49c2-4f88-8b44-9a78887d09de
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671055473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_ctrl_stress_all.671055473
Directory	/workspace/0.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.rom_ctrl_alert_test.1636812155
Short name	T355
Test name
Test status
Simulation time	2568518464 ps
CPU time	23.94 seconds
Started	Apr 16 12:17:54 PM PDT 24
Finished	Apr 16 12:18:18 PM PDT 24
Peak memory	211952 kb
Host	smart-63818288-ffc8-4572-86f3-bfb486acfd09
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636812155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1636812155
Directory	/workspace/1.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.rom_ctrl_alert_test.3869189957
Short name	T61
Test name
Test status
Simulation time	167466401 ps
CPU time	8.39 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:02:59 PM PDT 24
Peak memory	211380 kb
Host	smart-b2411c6d-0711-4b56-b0dd-d9b413f51b8c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869189957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3869189957
Directory	/workspace/1.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2563618779
Short name	T225
Test name
Test status
Simulation time	248637295994 ps
CPU time	827.34 seconds
Started	Apr 16 12:22:39 PM PDT 24
Finished	Apr 16 12:36:33 PM PDT 24
Peak memory	228688 kb
Host	smart-f8caac1a-e437-4e16-b763-d5c8f627fc9e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563618779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c orrupt_sig_fatal_chk.2563618779
Directory	/workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3155797236
Short name	T28
Test name
Test status
Simulation time	98815636868 ps
CPU time	493.1 seconds
Started	Apr 16 02:02:39 PM PDT 24
Finished	Apr 16 02:10:53 PM PDT 24
Peak memory	219436 kb
Host	smart-d137e8e1-3406-4ad0-883a-af886712874b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155797236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c orrupt_sig_fatal_chk.3155797236
Directory	/workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/1.rom_ctrl_kmac_err_chk.470466054
Short name	T457
Test name
Test status
Simulation time	45318966023 ps
CPU time	58.85 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:23:05 PM PDT 24
Peak memory	215040 kb
Host	smart-7c609118-4e71-401c-af22-1b366b9470a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470466054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.470466054
Directory	/workspace/1.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1099697586
Short name	T238
Test name
Test status
Simulation time	1804651997 ps
CPU time	21.08 seconds
Started	Apr 16 02:02:31 PM PDT 24
Finished	Apr 16 02:02:53 PM PDT 24
Peak memory	211304 kb
Host	smart-a13298cf-3f91-43c8-9862-f337f56a223d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1099697586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1099697586
Directory	/workspace/1.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/1.rom_ctrl_max_throughput_chk.522053256
Short name	T464
Test name
Test status
Simulation time	1769179745 ps
CPU time	20.86 seconds
Started	Apr 16 12:18:39 PM PDT 24
Finished	Apr 16 12:19:01 PM PDT 24
Peak memory	211196 kb
Host	smart-56e5c21a-d52c-4ee4-9b21-72de3b31d5fe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=522053256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.522053256
Directory	/workspace/1.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/1.rom_ctrl_sec_cm.863880829
Short name	T44
Test name
Test status
Simulation time	3627968951 ps
CPU time	116.02 seconds
Started	Apr 16 02:02:36 PM PDT 24
Finished	Apr 16 02:04:34 PM PDT 24
Peak memory	237648 kb
Host	smart-daba946c-1d37-40c9-82d3-99494bb76a2a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863880829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.863880829
Directory	/workspace/1.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.rom_ctrl_smoke.2577061921
Short name	T217
Test name
Test status
Simulation time	8973258222 ps
CPU time	78.99 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 12:24:05 PM PDT 24
Peak memory	215692 kb
Host	smart-2190178d-2835-47f2-a689-78594716d667
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577061921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2577061921
Directory	/workspace/1.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.rom_ctrl_stress_all.2169903536
Short name	T473
Test name
Test status
Simulation time	70544113861 ps
CPU time	173.91 seconds
Started	Apr 16 02:02:43 PM PDT 24
Finished	Apr 16 02:05:39 PM PDT 24
Peak memory	227584 kb
Host	smart-f5cd2bd3-ea01-423b-99ae-811bd1493641
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169903536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.rom_ctrl_stress_all.2169903536
Directory	/workspace/1.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.rom_ctrl_stress_all.2765556039
Short name	T552
Test name
Test status
Simulation time	47329011354 ps
CPU time	125.84 seconds
Started	Apr 16 12:22:39 PM PDT 24
Finished	Apr 16 12:24:51 PM PDT 24
Peak memory	218440 kb
Host	smart-15eb3bac-d989-46f5-a287-af8b14745a07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765556039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.rom_ctrl_stress_all.2765556039
Directory	/workspace/1.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.rom_ctrl_alert_test.2262710951
Short name	T136
Test name
Test status
Simulation time	422007619 ps
CPU time	11.47 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	211404 kb
Host	smart-0c4e959e-0285-4229-8a74-d3878b4bd0f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262710951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2262710951
Directory	/workspace/10.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.rom_ctrl_alert_test.2384121411
Short name	T440
Test name
Test status
Simulation time	751136551 ps
CPU time	8.56 seconds
Started	Apr 16 12:20:53 PM PDT 24
Finished	Apr 16 12:21:03 PM PDT 24
Peak memory	211284 kb
Host	smart-963f31a4-1790-4d8d-b591-9920f2a1ca44
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384121411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2384121411
Directory	/workspace/10.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3079259378
Short name	T239
Test name
Test status
Simulation time	827917829487 ps
CPU time	891 seconds
Started	Apr 16 02:02:51 PM PDT 24
Finished	Apr 16 02:17:43 PM PDT 24
Peak memory	238408 kb
Host	smart-a764ce73-ad6a-4b37-992c-872251cdf69f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079259378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_ corrupt_sig_fatal_chk.3079259378
Directory	/workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3426120997
Short name	T299
Test name
Test status
Simulation time	14815189454 ps
CPU time	265.49 seconds
Started	Apr 16 12:20:55 PM PDT 24
Finished	Apr 16 12:25:21 PM PDT 24
Peak memory	237936 kb
Host	smart-2ff6e81f-92f9-491c-80ff-84c77c5e0a7e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426120997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_ corrupt_sig_fatal_chk.3426120997
Directory	/workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1976119381
Short name	T637
Test name
Test status
Simulation time	12966261668 ps
CPU time	40.01 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:03:48 PM PDT 24
Peak memory	215172 kb
Host	smart-cddc8a3f-f982-41e7-9a77-1edf8ddbb9d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976119381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1976119381
Directory	/workspace/10.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2571435117
Short name	T522
Test name
Test status
Simulation time	28177784927 ps
CPU time	61.58 seconds
Started	Apr 16 12:20:59 PM PDT 24
Finished	Apr 16 12:22:02 PM PDT 24
Peak memory	216692 kb
Host	smart-7eea68f4-8013-4146-bd80-85222c78ee4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571435117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2571435117
Directory	/workspace/10.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3719882783
Short name	T620
Test name
Test status
Simulation time	25697192547 ps
CPU time	35.23 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:03:58 PM PDT 24
Peak memory	211400 kb
Host	smart-3fa7266d-cf7f-443a-888e-f92e4aef1ca8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3719882783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3719882783
Directory	/workspace/10.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/10.rom_ctrl_max_throughput_chk.504956000
Short name	T283
Test name
Test status
Simulation time	25612156776 ps
CPU time	34.87 seconds
Started	Apr 16 12:21:14 PM PDT 24
Finished	Apr 16 12:21:51 PM PDT 24
Peak memory	213060 kb
Host	smart-eb75aa89-4a33-4047-a3ba-f1ad89b18917
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=504956000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.504956000
Directory	/workspace/10.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/10.rom_ctrl_smoke.1003527905
Short name	T661
Test name
Test status
Simulation time	10959476323 ps
CPU time	35.95 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:23:24 PM PDT 24
Peak memory	216848 kb
Host	smart-6907ab21-b0bb-4117-8b64-41a265be666a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003527905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1003527905
Directory	/workspace/10.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.rom_ctrl_smoke.3306813294
Short name	T463
Test name
Test status
Simulation time	33559264532 ps
CPU time	72.73 seconds
Started	Apr 16 02:02:53 PM PDT 24
Finished	Apr 16 02:04:07 PM PDT 24
Peak memory	218356 kb
Host	smart-cb942b90-8d7c-480c-9258-c371b2c521c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306813294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3306813294
Directory	/workspace/10.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.rom_ctrl_stress_all.2756179735
Short name	T669
Test name
Test status
Simulation time	58981093487 ps
CPU time	170.74 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:25:38 PM PDT 24
Peak memory	219560 kb
Host	smart-5fca9a3c-6dfd-45d8-b700-4495c58d470c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756179735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.rom_ctrl_stress_all.2756179735
Directory	/workspace/10.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.rom_ctrl_stress_all.3199924565
Short name	T102
Test name
Test status
Simulation time	8083952684 ps
CPU time	74.96 seconds
Started	Apr 16 02:02:54 PM PDT 24
Finished	Apr 16 02:04:10 PM PDT 24
Peak memory	218064 kb
Host	smart-370569d1-baf5-47f8-b257-bc5265b13904
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199924565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.rom_ctrl_stress_all.3199924565
Directory	/workspace/10.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.rom_ctrl_alert_test.3783006233
Short name	T629
Test name
Test status
Simulation time	6737626938 ps
CPU time	28.8 seconds
Started	Apr 16 02:02:52 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	212456 kb
Host	smart-5c1535ff-208e-4730-94a5-94da17a97c86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783006233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3783006233
Directory	/workspace/11.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.rom_ctrl_alert_test.3978457864
Short name	T320
Test name
Test status
Simulation time	172893378 ps
CPU time	8.06 seconds
Started	Apr 16 12:22:24 PM PDT 24
Finished	Apr 16 12:22:34 PM PDT 24
Peak memory	211024 kb
Host	smart-c76db9d2-ba10-4a72-beb9-9fe79a337e80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978457864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3978457864
Directory	/workspace/11.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1270707874
Short name	T439
Test name
Test status
Simulation time	145425199982 ps
CPU time	642.44 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:33:29 PM PDT 24
Peak memory	215844 kb
Host	smart-c9d88fb9-11e4-41df-ae5d-85bb3d96ff73
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270707874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_ corrupt_sig_fatal_chk.1270707874
Directory	/workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.716877851
Short name	T544
Test name
Test status
Simulation time	94508026831 ps
CPU time	427.18 seconds
Started	Apr 16 02:02:40 PM PDT 24
Finished	Apr 16 02:09:49 PM PDT 24
Peak memory	237180 kb
Host	smart-5090bee0-9745-4435-a704-233c207705c6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716877851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c orrupt_sig_fatal_chk.716877851
Directory	/workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3041597432
Short name	T408
Test name
Test status
Simulation time	3429714012 ps
CPU time	39.42 seconds
Started	Apr 16 02:02:55 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	215128 kb
Host	smart-606dd690-925a-4886-89bf-816e71d052ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041597432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3041597432
Directory	/workspace/11.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/11.rom_ctrl_kmac_err_chk.333857015
Short name	T403
Test name
Test status
Simulation time	8360116973 ps
CPU time	67 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:23:55 PM PDT 24
Peak memory	213816 kb
Host	smart-23ba96d5-721f-43a5-b711-4c56b1b51bbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333857015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.333857015
Directory	/workspace/11.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3853348045
Short name	T376
Test name
Test status
Simulation time	37573662061 ps
CPU time	25.75 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:23:13 PM PDT 24
Peak memory	212472 kb
Host	smart-5ebc33bc-2afb-422d-a394-9d95bf427984
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3853348045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3853348045
Directory	/workspace/11.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/11.rom_ctrl_max_throughput_chk.664375168
Short name	T346
Test name
Test status
Simulation time	7895579029 ps
CPU time	26.74 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:03:39 PM PDT 24
Peak memory	211788 kb
Host	smart-b7ebff5d-999a-426c-a229-dacb4e558263
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=664375168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.664375168
Directory	/workspace/11.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/11.rom_ctrl_smoke.1371307214
Short name	T558
Test name
Test status
Simulation time	9658227097 ps
CPU time	47.54 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:36 PM PDT 24
Peak memory	217608 kb
Host	smart-44592f79-b380-4f68-a140-b13216f1f352
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371307214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1371307214
Directory	/workspace/11.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.rom_ctrl_smoke.3899142767
Short name	T252
Test name
Test status
Simulation time	19851291194 ps
CPU time	60.54 seconds
Started	Apr 16 12:21:05 PM PDT 24
Finished	Apr 16 12:22:07 PM PDT 24
Peak memory	214768 kb
Host	smart-bc09f9ba-eefc-4e86-856e-e172e4c389b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899142767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3899142767
Directory	/workspace/11.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.rom_ctrl_stress_all.2288452720
Short name	T482
Test name
Test status
Simulation time	28841061331 ps
CPU time	137.4 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:05:29 PM PDT 24
Peak memory	221136 kb
Host	smart-6f5c9715-55c5-4712-97da-eeb8adf48f08
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288452720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.rom_ctrl_stress_all.2288452720
Directory	/workspace/11.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.rom_ctrl_stress_all.2774165350
Short name	T391
Test name
Test status
Simulation time	1573184469 ps
CPU time	21.18 seconds
Started	Apr 16 12:20:59 PM PDT 24
Finished	Apr 16 12:21:22 PM PDT 24
Peak memory	218508 kb
Host	smart-c960a243-9eb3-4c51-9591-25d741e05d77
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774165350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.rom_ctrl_stress_all.2774165350
Directory	/workspace/11.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.rom_ctrl_alert_test.3495512778
Short name	T185
Test name
Test status
Simulation time	11618575857 ps
CPU time	26.61 seconds
Started	Apr 16 02:02:40 PM PDT 24
Finished	Apr 16 02:03:07 PM PDT 24
Peak memory	212400 kb
Host	smart-510db9bc-8a5a-45c3-9d61-cb69c883d6d3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495512778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3495512778
Directory	/workspace/12.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.rom_ctrl_alert_test.3866148989
Short name	T649
Test name
Test status
Simulation time	332107900 ps
CPU time	8.93 seconds
Started	Apr 16 12:21:20 PM PDT 24
Finished	Apr 16 12:21:30 PM PDT 24
Peak memory	211300 kb
Host	smart-31562d3d-719f-492d-9e60-8b975ad8f7d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866148989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3866148989
Directory	/workspace/12.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.359505643
Short name	T603
Test name
Test status
Simulation time	20108457194 ps
CPU time	336.72 seconds
Started	Apr 16 12:22:16 PM PDT 24
Finished	Apr 16 12:27:54 PM PDT 24
Peak memory	224668 kb
Host	smart-874bbd7f-1100-43f0-9ae5-d72670f907ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359505643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c orrupt_sig_fatal_chk.359505643
Directory	/workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.541795804
Short name	T145
Test name
Test status
Simulation time	849804697234 ps
CPU time	885.94 seconds
Started	Apr 16 02:02:46 PM PDT 24
Finished	Apr 16 02:17:33 PM PDT 24
Peak memory	235424 kb
Host	smart-0d8a255c-3891-47dc-8398-2ba06e0b65cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541795804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c orrupt_sig_fatal_chk.541795804
Directory	/workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1538083910
Short name	T529
Test name
Test status
Simulation time	13606402839 ps
CPU time	61.56 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:04:10 PM PDT 24
Peak memory	214044 kb
Host	smart-5719774f-6e6a-4de5-9476-7689f42019c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538083910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1538083910
Directory	/workspace/12.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2358113636
Short name	T55
Test name
Test status
Simulation time	5364080764 ps
CPU time	49.66 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:23:36 PM PDT 24
Peak memory	213288 kb
Host	smart-e554fdbc-5215-4862-9acb-23942c7d649c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2358113636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2358113636
Directory	/workspace/12.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1725961614
Short name	T257
Test name
Test status
Simulation time	919291207 ps
CPU time	15.88 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:05 PM PDT 24
Peak memory	211424 kb
Host	smart-b52c0e15-f639-4bad-900a-4e43ea7831b5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1725961614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1725961614
Directory	/workspace/12.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2331196495
Short name	T101
Test name
Test status
Simulation time	1552407014 ps
CPU time	12.68 seconds
Started	Apr 16 12:22:28 PM PDT 24
Finished	Apr 16 12:22:42 PM PDT 24
Peak memory	211176 kb
Host	smart-8ffbb424-60ed-4d22-afad-c2c56b1806d5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2331196495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2331196495
Directory	/workspace/12.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/12.rom_ctrl_smoke.216871569
Short name	T226
Test name
Test status
Simulation time	356006680 ps
CPU time	20.73 seconds
Started	Apr 16 12:21:07 PM PDT 24
Finished	Apr 16 12:21:30 PM PDT 24
Peak memory	216776 kb
Host	smart-efeccbac-706b-4c60-932a-fb567834e3d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216871569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.216871569
Directory	/workspace/12.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.rom_ctrl_smoke.3265964453
Short name	T597
Test name
Test status
Simulation time	3662720717 ps
CPU time	50.35 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:03:41 PM PDT 24
Peak memory	215120 kb
Host	smart-562e88f8-5fc9-4bb7-abff-d5b3f37b5fd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3265964453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3265964453
Directory	/workspace/12.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.rom_ctrl_stress_all.1028652926
Short name	T141
Test name
Test status
Simulation time	182380354426 ps
CPU time	198.5 seconds
Started	Apr 16 02:02:53 PM PDT 24
Finished	Apr 16 02:06:12 PM PDT 24
Peak memory	219464 kb
Host	smart-668b524d-d503-4ac3-ac24-1e78968ad382
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028652926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.rom_ctrl_stress_all.1028652926
Directory	/workspace/12.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.rom_ctrl_stress_all.1060798888
Short name	T291
Test name
Test status
Simulation time	769585378 ps
CPU time	17.26 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:23:05 PM PDT 24
Peak memory	209488 kb
Host	smart-f10703df-206a-4bf5-a988-e4f49891b12f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060798888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.rom_ctrl_stress_all.1060798888
Directory	/workspace/12.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1712312835
Short name	T22
Test name
Test status
Simulation time	352767205217 ps
CPU time	3306.53 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 01:17:53 PM PDT 24
Peak memory	242996 kb
Host	smart-08a0df91-2e8b-416f-89e9-0bd46e69ae3c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712312835 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1712312835
Directory	/workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.rom_ctrl_alert_test.1614032040
Short name	T406
Test name
Test status
Simulation time	1231705334 ps
CPU time	15.84 seconds
Started	Apr 16 12:21:42 PM PDT 24
Finished	Apr 16 12:22:00 PM PDT 24
Peak memory	211772 kb
Host	smart-1c0fd841-1b46-46fd-82d6-36cc7b3a9e96
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614032040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1614032040
Directory	/workspace/13.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.rom_ctrl_alert_test.3633791002
Short name	T276
Test name
Test status
Simulation time	3317960188 ps
CPU time	28.71 seconds
Started	Apr 16 02:02:51 PM PDT 24
Finished	Apr 16 02:03:20 PM PDT 24
Peak memory	212136 kb
Host	smart-ccc91a1a-fe5c-4528-a38c-d3fc12b4fc64
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633791002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3633791002
Directory	/workspace/13.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2970974324
Short name	T488
Test name
Test status
Simulation time	12349660700 ps
CPU time	256.65 seconds
Started	Apr 16 02:02:50 PM PDT 24
Finished	Apr 16 02:07:08 PM PDT 24
Peak memory	217040 kb
Host	smart-e70cf4c8-dd93-416b-856b-5980fa464a03
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970974324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_ corrupt_sig_fatal_chk.2970974324
Directory	/workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.479927556
Short name	T369
Test name
Test status
Simulation time	39607079425 ps
CPU time	435.24 seconds
Started	Apr 16 12:21:20 PM PDT 24
Finished	Apr 16 12:28:36 PM PDT 24
Peak memory	241044 kb
Host	smart-0b423839-1d70-4e36-ba61-ba71ad520b9c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479927556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c orrupt_sig_fatal_chk.479927556
Directory	/workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3656100151
Short name	T189
Test name
Test status
Simulation time	5160426629 ps
CPU time	46.52 seconds
Started	Apr 16 02:03:06 PM PDT 24
Finished	Apr 16 02:03:54 PM PDT 24
Peak memory	215092 kb
Host	smart-b3e3fb6b-7472-450e-a689-e448ac8c2d69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656100151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3656100151
Directory	/workspace/13.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/13.rom_ctrl_kmac_err_chk.926530044
Short name	T537
Test name
Test status
Simulation time	16340816935 ps
CPU time	42.49 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 12:23:28 PM PDT 24
Peak memory	213600 kb
Host	smart-d4a0c6fb-236f-4001-b35e-b45dc9d8d71b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926530044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.926530044
Directory	/workspace/13.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/13.rom_ctrl_max_throughput_chk.182001749
Short name	T509
Test name
Test status
Simulation time	7220751179 ps
CPU time	20.27 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 12:23:06 PM PDT 24
Peak memory	209592 kb
Host	smart-8cb24cda-7f71-47f1-8e20-9f04418a955a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=182001749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.182001749
Directory	/workspace/13.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/13.rom_ctrl_max_throughput_chk.559560401
Short name	T557
Test name
Test status
Simulation time	20275327196 ps
CPU time	22 seconds
Started	Apr 16 02:03:06 PM PDT 24
Finished	Apr 16 02:03:28 PM PDT 24
Peak memory	212940 kb
Host	smart-6e422676-0807-474c-b1f7-57c091277cd8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=559560401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.559560401
Directory	/workspace/13.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/13.rom_ctrl_smoke.1454731463
Short name	T182
Test name
Test status
Simulation time	51756517951 ps
CPU time	70.68 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:23:57 PM PDT 24
Peak memory	217880 kb
Host	smart-4af22f94-8f14-452b-a405-72e14f0b92a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454731463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1454731463
Directory	/workspace/13.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.rom_ctrl_smoke.1687992176
Short name	T193
Test name
Test status
Simulation time	26647514117 ps
CPU time	67.43 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:04:24 PM PDT 24
Peak memory	216748 kb
Host	smart-9c2e7815-e715-4675-8d83-b2dddd6d5962
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1687992176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1687992176
Directory	/workspace/13.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.rom_ctrl_stress_all.3815368073
Short name	T506
Test name
Test status
Simulation time	10694998729 ps
CPU time	67.23 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:04:16 PM PDT 24
Peak memory	219428 kb
Host	smart-965718b3-393f-4a61-ab18-6580753a68d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815368073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.rom_ctrl_stress_all.3815368073
Directory	/workspace/13.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.rom_ctrl_stress_all.438299013
Short name	T478
Test name
Test status
Simulation time	3049337773 ps
CPU time	56.64 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 12:23:43 PM PDT 24
Peak memory	219036 kb
Host	smart-77563883-675e-4a2b-885a-5c5c648cc484
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438299013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.rom_ctrl_stress_all.438299013
Directory	/workspace/13.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.rom_ctrl_alert_test.3304992284
Short name	T279
Test name
Test status
Simulation time	917051512 ps
CPU time	7.83 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:22:55 PM PDT 24
Peak memory	210900 kb
Host	smart-84d468d2-8cf0-4b5d-b417-e39ca8949de3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304992284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3304992284
Directory	/workspace/14.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.rom_ctrl_alert_test.3735820680
Short name	T497
Test name
Test status
Simulation time	2196835747 ps
CPU time	23.04 seconds
Started	Apr 16 02:02:58 PM PDT 24
Finished	Apr 16 02:03:22 PM PDT 24
Peak memory	211488 kb
Host	smart-279c41bf-5cfb-494e-b276-713945219884
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735820680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3735820680
Directory	/workspace/14.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3779729147
Short name	T337
Test name
Test status
Simulation time	33838176373 ps
CPU time	253.45 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:26:02 PM PDT 24
Peak memory	225712 kb
Host	smart-32996988-3532-4135-8595-36ab988e5f06
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779729147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_ corrupt_sig_fatal_chk.3779729147
Directory	/workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.537929458
Short name	T311
Test name
Test status
Simulation time	125429488259 ps
CPU time	623.05 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:13:28 PM PDT 24
Peak memory	217872 kb
Host	smart-a8e5b0e1-6767-4f48-aa38-a541e2a98b00
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537929458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c orrupt_sig_fatal_chk.537929458
Directory	/workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2122408313
Short name	T162
Test name
Test status
Simulation time	2983118956 ps
CPU time	35.51 seconds
Started	Apr 16 02:02:51 PM PDT 24
Finished	Apr 16 02:03:28 PM PDT 24
Peak memory	213992 kb
Host	smart-32702094-5b78-4003-9adb-dfe446809093
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122408313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2122408313
Directory	/workspace/14.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/14.rom_ctrl_kmac_err_chk.77356567
Short name	T664
Test name
Test status
Simulation time	3419536438 ps
CPU time	40.16 seconds
Started	Apr 16 12:21:30 PM PDT 24
Finished	Apr 16 12:22:12 PM PDT 24
Peak memory	214888 kb
Host	smart-9dd5361a-be73-4689-a6db-c6e0ece19707
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77356567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.77356567
Directory	/workspace/14.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/14.rom_ctrl_max_throughput_chk.259130339
Short name	T615
Test name
Test status
Simulation time	19064616232 ps
CPU time	35.02 seconds
Started	Apr 16 02:02:57 PM PDT 24
Finished	Apr 16 02:03:33 PM PDT 24
Peak memory	211788 kb
Host	smart-b42185bb-48cd-4a3e-9a97-d860b8c3e0dd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=259130339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.259130339
Directory	/workspace/14.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3128669801
Short name	T335
Test name
Test status
Simulation time	3892845776 ps
CPU time	31.27 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:22:19 PM PDT 24
Peak memory	211532 kb
Host	smart-9a3f3a6e-7f01-4f7c-a83e-f596f44c032d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3128669801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3128669801
Directory	/workspace/14.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/14.rom_ctrl_smoke.154003051
Short name	T130
Test name
Test status
Simulation time	539350591 ps
CPU time	19.92 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:14 PM PDT 24
Peak memory	217452 kb
Host	smart-a3bd88f8-e16b-455e-b5b1-9312fc21317e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154003051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.154003051
Directory	/workspace/14.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.rom_ctrl_stress_all.1361192269
Short name	T81
Test name
Test status
Simulation time	33167232671 ps
CPU time	48.47 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:03:38 PM PDT 24
Peak memory	219420 kb
Host	smart-7d2b5590-ddf6-4f55-91f0-4572491ada7d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361192269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.rom_ctrl_stress_all.1361192269
Directory	/workspace/14.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.rom_ctrl_stress_all.1977383269
Short name	T618
Test name
Test status
Simulation time	56118191413 ps
CPU time	140.11 seconds
Started	Apr 16 12:21:44 PM PDT 24
Finished	Apr 16 12:24:07 PM PDT 24
Peak memory	219740 kb
Host	smart-ca059600-d630-4ce2-887a-3f40a0ff9c3c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977383269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.rom_ctrl_stress_all.1977383269
Directory	/workspace/14.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3121447441
Short name	T614
Test name
Test status
Simulation time	125376828351 ps
CPU time	1237.88 seconds
Started	Apr 16 12:23:00 PM PDT 24
Finished	Apr 16 12:43:41 PM PDT 24
Peak memory	244408 kb
Host	smart-e94a6304-5b4c-4d0e-b33b-8876a69ae959
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121447441 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3121447441
Directory	/workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.rom_ctrl_alert_test.1292268888
Short name	T60
Test name
Test status
Simulation time	37131868053 ps
CPU time	28.69 seconds
Started	Apr 16 12:21:38 PM PDT 24
Finished	Apr 16 12:22:08 PM PDT 24
Peak memory	211728 kb
Host	smart-f31eb2e4-b9b6-4483-8fbd-6c1107409574
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292268888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1292268888
Directory	/workspace/15.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.rom_ctrl_alert_test.806093514
Short name	T143
Test name
Test status
Simulation time	7489136962 ps
CPU time	19.64 seconds
Started	Apr 16 02:02:54 PM PDT 24
Finished	Apr 16 02:03:14 PM PDT 24
Peak memory	211552 kb
Host	smart-d942fead-2582-4488-b51a-0d4b6c81b05a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806093514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.806093514
Directory	/workspace/15.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2128428650
Short name	T241
Test name
Test status
Simulation time	28334253914 ps
CPU time	262.19 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:27:09 PM PDT 24
Peak memory	217448 kb
Host	smart-3e059f08-b8b8-419c-93f5-5b8aedda25ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128428650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_ corrupt_sig_fatal_chk.2128428650
Directory	/workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2248629394
Short name	T476
Test name
Test status
Simulation time	163558593108 ps
CPU time	514.41 seconds
Started	Apr 16 02:02:55 PM PDT 24
Finished	Apr 16 02:11:30 PM PDT 24
Peak memory	239940 kb
Host	smart-0d47e699-3195-4ed0-beb8-6ee5b4b42508
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248629394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_ corrupt_sig_fatal_chk.2248629394
Directory	/workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3245698873
Short name	T158
Test name
Test status
Simulation time	58278062021 ps
CPU time	64.1 seconds
Started	Apr 16 02:02:50 PM PDT 24
Finished	Apr 16 02:03:55 PM PDT 24
Peak memory	215984 kb
Host	smart-adf7056a-304f-4961-982f-56449006b6d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245698873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3245698873
Directory	/workspace/15.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3915976272
Short name	T173
Test name
Test status
Simulation time	112065136201 ps
CPU time	62.31 seconds
Started	Apr 16 12:21:47 PM PDT 24
Finished	Apr 16 12:22:53 PM PDT 24
Peak memory	215036 kb
Host	smart-bedf24a9-6f19-4f27-9bca-b90d286f9457
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915976272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3915976272
Directory	/workspace/15.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/15.rom_ctrl_max_throughput_chk.114418352
Short name	T184
Test name
Test status
Simulation time	427442367 ps
CPU time	12.97 seconds
Started	Apr 16 02:03:02 PM PDT 24
Finished	Apr 16 02:03:16 PM PDT 24
Peak memory	211364 kb
Host	smart-817f6fe8-8459-435f-b22d-fa3f80f974d1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=114418352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.114418352
Directory	/workspace/15.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3204187582
Short name	T378
Test name
Test status
Simulation time	6183527342 ps
CPU time	18.87 seconds
Started	Apr 16 12:21:41 PM PDT 24
Finished	Apr 16 12:22:02 PM PDT 24
Peak memory	212796 kb
Host	smart-12dd9669-f930-45e5-8116-d0f65767d108
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3204187582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3204187582
Directory	/workspace/15.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/15.rom_ctrl_smoke.111267146
Short name	T607
Test name
Test status
Simulation time	3899759240 ps
CPU time	23.42 seconds
Started	Apr 16 12:21:38 PM PDT 24
Finished	Apr 16 12:22:02 PM PDT 24
Peak memory	217128 kb
Host	smart-3aecd5ce-2a9d-490c-8799-de6e5a3f459d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111267146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.111267146
Directory	/workspace/15.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.rom_ctrl_smoke.2092699591
Short name	T419
Test name
Test status
Simulation time	32817574488 ps
CPU time	68.47 seconds
Started	Apr 16 02:03:13 PM PDT 24
Finished	Apr 16 02:04:23 PM PDT 24
Peak memory	217236 kb
Host	smart-42c04c41-1c99-46e4-9a55-13a0ee40d30e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092699591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2092699591
Directory	/workspace/15.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.rom_ctrl_stress_all.406627311
Short name	T323
Test name
Test status
Simulation time	777136834 ps
CPU time	14.76 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:22:03 PM PDT 24
Peak memory	213516 kb
Host	smart-a9cb4747-6c90-4daa-a449-4ea1390271a6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406627311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.rom_ctrl_stress_all.406627311
Directory	/workspace/15.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.rom_ctrl_alert_test.2488841285
Short name	T151
Test name
Test status
Simulation time	170724135 ps
CPU time	8.09 seconds
Started	Apr 16 12:21:39 PM PDT 24
Finished	Apr 16 12:21:48 PM PDT 24
Peak memory	210888 kb
Host	smart-48fb581f-06a7-4a19-b0b2-211b0e3184a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488841285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2488841285
Directory	/workspace/16.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.rom_ctrl_alert_test.3718653592
Short name	T149
Test name
Test status
Simulation time	612105659 ps
CPU time	8.24 seconds
Started	Apr 16 02:02:53 PM PDT 24
Finished	Apr 16 02:03:02 PM PDT 24
Peak memory	211428 kb
Host	smart-7ac072a6-4325-4606-bcbe-044047f80263
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718653592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3718653592
Directory	/workspace/16.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1077722953
Short name	T653
Test name
Test status
Simulation time	351483976894 ps
CPU time	756.96 seconds
Started	Apr 16 02:02:42 PM PDT 24
Finished	Apr 16 02:15:21 PM PDT 24
Peak memory	234984 kb
Host	smart-88381d18-219c-445a-9966-9d6838f759c6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077722953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_ corrupt_sig_fatal_chk.1077722953
Directory	/workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.885468658
Short name	T302
Test name
Test status
Simulation time	21435961741 ps
CPU time	274.34 seconds
Started	Apr 16 12:22:53 PM PDT 24
Finished	Apr 16 12:27:32 PM PDT 24
Peak memory	239628 kb
Host	smart-8dd84e7e-7e2b-4415-a486-c8dcb35b2716
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885468658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c orrupt_sig_fatal_chk.885468658
Directory	/workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/16.rom_ctrl_kmac_err_chk.291591619
Short name	T627
Test name
Test status
Simulation time	18344817111 ps
CPU time	63.51 seconds
Started	Apr 16 12:22:53 PM PDT 24
Finished	Apr 16 12:24:02 PM PDT 24
Peak memory	213444 kb
Host	smart-0ac66c04-a713-4715-b033-991f00b5d232
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291591619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.291591619
Directory	/workspace/16.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3801563646
Short name	T268
Test name
Test status
Simulation time	12493884432 ps
CPU time	58.89 seconds
Started	Apr 16 02:03:06 PM PDT 24
Finished	Apr 16 02:04:06 PM PDT 24
Peak memory	215156 kb
Host	smart-a3314b2f-3a3a-4028-9307-6f61f3c6cc73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801563646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3801563646
Directory	/workspace/16.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1021231274
Short name	T452
Test name
Test status
Simulation time	1579327284 ps
CPU time	9.89 seconds
Started	Apr 16 12:22:54 PM PDT 24
Finished	Apr 16 12:23:08 PM PDT 24
Peak memory	212032 kb
Host	smart-43d4732b-a208-4d5b-ab05-d213675880b2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1021231274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1021231274
Directory	/workspace/16.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2933216702
Short name	T209
Test name
Test status
Simulation time	6618223419 ps
CPU time	20.82 seconds
Started	Apr 16 02:03:20 PM PDT 24
Finished	Apr 16 02:03:42 PM PDT 24
Peak memory	211696 kb
Host	smart-974b85ea-abcf-4327-b5ea-672d88e856d1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2933216702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2933216702
Directory	/workspace/16.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/16.rom_ctrl_smoke.2228920318
Short name	T586
Test name
Test status
Simulation time	356026138 ps
CPU time	20.17 seconds
Started	Apr 16 02:02:52 PM PDT 24
Finished	Apr 16 02:03:13 PM PDT 24
Peak memory	216264 kb
Host	smart-4730161b-3223-4abd-84af-11726825d539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228920318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2228920318
Directory	/workspace/16.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.rom_ctrl_stress_all.1386739943
Short name	T129
Test name
Test status
Simulation time	216706379 ps
CPU time	15.05 seconds
Started	Apr 16 02:03:14 PM PDT 24
Finished	Apr 16 02:03:30 PM PDT 24
Peak memory	213432 kb
Host	smart-3e33218a-dc72-4ac2-9509-6ec1a7afa952
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386739943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_stress_all.1386739943
Directory	/workspace/16.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.rom_ctrl_stress_all.2151699958
Short name	T531
Test name
Test status
Simulation time	10874280136 ps
CPU time	66.04 seconds
Started	Apr 16 12:22:53 PM PDT 24
Finished	Apr 16 12:24:04 PM PDT 24
Peak memory	217316 kb
Host	smart-a260e991-00f1-44c1-acbd-1e415e3653e3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151699958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_stress_all.2151699958
Directory	/workspace/16.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.rom_ctrl_alert_test.1051732822
Short name	T292
Test name
Test status
Simulation time	687783007 ps
CPU time	8.28 seconds
Started	Apr 16 02:02:46 PM PDT 24
Finished	Apr 16 02:02:55 PM PDT 24
Peak memory	211348 kb
Host	smart-b04e1a6c-cfd2-4036-a926-332eb72b4a4a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051732822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1051732822
Directory	/workspace/17.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.rom_ctrl_alert_test.2062216004
Short name	T395
Test name
Test status
Simulation time	10496326270 ps
CPU time	24.31 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:21 PM PDT 24
Peak memory	212252 kb
Host	smart-92048eb2-cf95-4807-b1c3-c21fe711f1ec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062216004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2062216004
Directory	/workspace/17.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.380930482
Short name	T414
Test name
Test status
Simulation time	5704494892 ps
CPU time	186.8 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:24:54 PM PDT 24
Peak memory	239936 kb
Host	smart-10ba18c7-34a1-48b3-8eab-0843cbce3083
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380930482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c orrupt_sig_fatal_chk.380930482
Directory	/workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2409138630
Short name	T564
Test name
Test status
Simulation time	13813953214 ps
CPU time	60.23 seconds
Started	Apr 16 02:03:01 PM PDT 24
Finished	Apr 16 02:04:03 PM PDT 24
Peak memory	215032 kb
Host	smart-44997bb9-3e31-49ca-8a17-b469bd9dd2dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409138630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2409138630
Directory	/workspace/17.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3934478285
Short name	T329
Test name
Test status
Simulation time	5937701394 ps
CPU time	54.3 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:54 PM PDT 24
Peak memory	215180 kb
Host	smart-9a4bc4a4-b5d8-4ba5-8198-998afc338f3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934478285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3934478285
Directory	/workspace/17.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3337252539
Short name	T640
Test name
Test status
Simulation time	8920431898 ps
CPU time	25.08 seconds
Started	Apr 16 02:03:12 PM PDT 24
Finished	Apr 16 02:03:38 PM PDT 24
Peak memory	211804 kb
Host	smart-fe0943e8-9b11-4edb-b133-6ee695c824e6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3337252539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3337252539
Directory	/workspace/17.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3690248698
Short name	T446
Test name
Test status
Simulation time	13839790607 ps
CPU time	30.74 seconds
Started	Apr 16 12:21:42 PM PDT 24
Finished	Apr 16 12:22:15 PM PDT 24
Peak memory	212876 kb
Host	smart-0dc983c6-0b06-4746-9487-6e6bdaad517f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3690248698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3690248698
Directory	/workspace/17.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/17.rom_ctrl_smoke.187387172
Short name	T53
Test name
Test status
Simulation time	4167483894 ps
CPU time	45.08 seconds
Started	Apr 16 02:03:03 PM PDT 24
Finished	Apr 16 02:03:49 PM PDT 24
Peak memory	217316 kb
Host	smart-f085e8e2-4756-4d5b-b68c-65c83da1b227
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187387172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.187387172
Directory	/workspace/17.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.rom_ctrl_smoke.3691759171
Short name	T551
Test name
Test status
Simulation time	7795094795 ps
CPU time	69.62 seconds
Started	Apr 16 12:22:53 PM PDT 24
Finished	Apr 16 12:24:08 PM PDT 24
Peak memory	216712 kb
Host	smart-5b0a1756-15e4-4fe6-a8e8-b959212728f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691759171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3691759171
Directory	/workspace/17.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.rom_ctrl_stress_all.2458667708
Short name	T159
Test name
Test status
Simulation time	5113107247 ps
CPU time	51.27 seconds
Started	Apr 16 12:21:31 PM PDT 24
Finished	Apr 16 12:22:23 PM PDT 24
Peak memory	218532 kb
Host	smart-2e64cec7-c8fb-47e5-8cfc-11f553e32fd1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458667708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.rom_ctrl_stress_all.2458667708
Directory	/workspace/17.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.rom_ctrl_stress_all.719944416
Short name	T521
Test name
Test status
Simulation time	22205612133 ps
CPU time	131.92 seconds
Started	Apr 16 02:02:51 PM PDT 24
Finished	Apr 16 02:05:04 PM PDT 24
Peak memory	222584 kb
Host	smart-8f01d486-80ce-490e-8904-370ab9870c52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719944416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.rom_ctrl_stress_all.719944416
Directory	/workspace/17.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3196929930
Short name	T592
Test name
Test status
Simulation time	233861968542 ps
CPU time	2340.1 seconds
Started	Apr 16 12:22:19 PM PDT 24
Finished	Apr 16 01:01:20 PM PDT 24
Peak memory	240260 kb
Host	smart-78db4650-4ce5-4bd3-8ad9-0ad528049fe3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196929930 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3196929930
Directory	/workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.rom_ctrl_alert_test.2334096548
Short name	T168
Test name
Test status
Simulation time	3464106546 ps
CPU time	29.59 seconds
Started	Apr 16 02:03:29 PM PDT 24
Finished	Apr 16 02:04:01 PM PDT 24
Peak memory	211516 kb
Host	smart-4ad54b15-60cd-488a-8fe2-bf62f33dd38e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334096548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2334096548
Directory	/workspace/18.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1614068482
Short name	T411
Test name
Test status
Simulation time	14674049308 ps
CPU time	388.15 seconds
Started	Apr 16 02:02:57 PM PDT 24
Finished	Apr 16 02:09:26 PM PDT 24
Peak memory	234096 kb
Host	smart-96f57514-7574-487b-be5c-b06d968bf451
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614068482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_ corrupt_sig_fatal_chk.1614068482
Directory	/workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.926188662
Short name	T199
Test name
Test status
Simulation time	15496568092 ps
CPU time	265.07 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:26:16 PM PDT 24
Peak memory	230804 kb
Host	smart-678a6fa1-bb38-446d-a0a8-c2d68561ba4e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926188662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c orrupt_sig_fatal_chk.926188662
Directory	/workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2383437619
Short name	T344
Test name
Test status
Simulation time	18366218047 ps
CPU time	46.07 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:22:36 PM PDT 24
Peak memory	215060 kb
Host	smart-eabe4aab-fb2c-419c-bcc8-9355ff1ba88c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383437619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2383437619
Directory	/workspace/18.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3681155679
Short name	T309
Test name
Test status
Simulation time	82080817477 ps
CPU time	68.18 seconds
Started	Apr 16 02:02:44 PM PDT 24
Finished	Apr 16 02:03:54 PM PDT 24
Peak memory	215048 kb
Host	smart-308b2989-eaf2-435b-84bb-eaf8c83e89cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681155679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3681155679
Directory	/workspace/18.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/18.rom_ctrl_max_throughput_chk.242416572
Short name	T8
Test name
Test status
Simulation time	10762447277 ps
CPU time	25.93 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:23 PM PDT 24
Peak memory	211404 kb
Host	smart-295608c6-e2e9-4270-909f-e631b3362a94
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=242416572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.242416572
Directory	/workspace/18.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/18.rom_ctrl_max_throughput_chk.509710141
Short name	T449
Test name
Test status
Simulation time	6318517344 ps
CPU time	29.42 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:18 PM PDT 24
Peak memory	211940 kb
Host	smart-f594fb6a-2c2c-4996-bc74-eadffdf8511d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=509710141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.509710141
Directory	/workspace/18.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/18.rom_ctrl_smoke.1695499131
Short name	T191
Test name
Test status
Simulation time	4603587541 ps
CPU time	47.85 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:22:42 PM PDT 24
Peak memory	216252 kb
Host	smart-936698fb-4b3b-45f1-8697-90d432776061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695499131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1695499131
Directory	/workspace/18.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.rom_ctrl_smoke.4072999419
Short name	T430
Test name
Test status
Simulation time	17842577510 ps
CPU time	68.61 seconds
Started	Apr 16 02:02:43 PM PDT 24
Finished	Apr 16 02:03:53 PM PDT 24
Peak memory	217036 kb
Host	smart-0cc3bf7f-cfc7-4c6b-bfa3-8e98aef42947
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072999419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4072999419
Directory	/workspace/18.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.rom_ctrl_stress_all.1112670994
Short name	T546
Test name
Test status
Simulation time	37681879922 ps
CPU time	115.7 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:23:46 PM PDT 24
Peak memory	221216 kb
Host	smart-2e4d3e3b-bbb5-4f98-9046-b6f92047227c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112670994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.rom_ctrl_stress_all.1112670994
Directory	/workspace/18.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.rom_ctrl_stress_all.494341565
Short name	T655
Test name
Test status
Simulation time	1606214156 ps
CPU time	31.26 seconds
Started	Apr 16 02:02:50 PM PDT 24
Finished	Apr 16 02:03:22 PM PDT 24
Peak memory	216312 kb
Host	smart-0d3f789d-b84f-499c-8b97-9b45af5f6e79
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494341565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.rom_ctrl_stress_all.494341565
Directory	/workspace/18.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3087407925
Short name	T107
Test name
Test status
Simulation time	40025684156 ps
CPU time	1414.47 seconds
Started	Apr 16 12:22:32 PM PDT 24
Finished	Apr 16 12:46:09 PM PDT 24
Peak memory	235868 kb
Host	smart-cb84a4cf-3390-447b-b3bc-1087627ea631
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087407925 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3087407925
Directory	/workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.rom_ctrl_alert_test.2269371859
Short name	T495
Test name
Test status
Simulation time	6591303716 ps
CPU time	32.48 seconds
Started	Apr 16 12:21:44 PM PDT 24
Finished	Apr 16 12:22:19 PM PDT 24
Peak memory	212352 kb
Host	smart-78070867-e0e4-46ea-a8c1-e496c014f53c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269371859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2269371859
Directory	/workspace/19.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.rom_ctrl_alert_test.3218199867
Short name	T134
Test name
Test status
Simulation time	17472819372 ps
CPU time	33.24 seconds
Started	Apr 16 02:02:56 PM PDT 24
Finished	Apr 16 02:03:30 PM PDT 24
Peak memory	211528 kb
Host	smart-7d0d4e12-0c50-4f43-a6b7-d1d2fdb092b0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218199867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3218199867
Directory	/workspace/19.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2852190787
Short name	T237
Test name
Test status
Simulation time	2974262115 ps
CPU time	238.75 seconds
Started	Apr 16 02:02:43 PM PDT 24
Finished	Apr 16 02:06:44 PM PDT 24
Peak memory	237896 kb
Host	smart-44b60141-7b7a-4dfc-9806-0dec416e6778
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852190787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_ corrupt_sig_fatal_chk.2852190787
Directory	/workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.641238811
Short name	T666
Test name
Test status
Simulation time	2571411738 ps
CPU time	119.6 seconds
Started	Apr 16 12:22:30 PM PDT 24
Finished	Apr 16 12:24:32 PM PDT 24
Peak memory	215572 kb
Host	smart-f14def10-3b56-474c-b564-7406f2265eed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641238811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c orrupt_sig_fatal_chk.641238811
Directory	/workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1898041190
Short name	T454
Test name
Test status
Simulation time	2961500889 ps
CPU time	37.46 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:22:25 PM PDT 24
Peak memory	215620 kb
Host	smart-ae30426d-8924-4453-9801-c09c10de18e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898041190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1898041190
Directory	/workspace/19.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2613518292
Short name	T460
Test name
Test status
Simulation time	30985686223 ps
CPU time	53.88 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:03:59 PM PDT 24
Peak memory	215180 kb
Host	smart-545fdca6-5a9b-44b4-973b-b903c2e2e855
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2613518292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2613518292
Directory	/workspace/19.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1789340498
Short name	T657
Test name
Test status
Simulation time	181838488 ps
CPU time	10.3 seconds
Started	Apr 16 02:02:57 PM PDT 24
Finished	Apr 16 02:03:08 PM PDT 24
Peak memory	211580 kb
Host	smart-635664ca-8001-4360-9c8b-60c0d8fee6b5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1789340498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1789340498
Directory	/workspace/19.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4074968663
Short name	T511
Test name
Test status
Simulation time	3664245155 ps
CPU time	16.04 seconds
Started	Apr 16 12:22:59 PM PDT 24
Finished	Apr 16 12:23:18 PM PDT 24
Peak memory	211296 kb
Host	smart-809aa09b-41ec-410c-8e2a-8fb75ec27314
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4074968663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4074968663
Directory	/workspace/19.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/19.rom_ctrl_smoke.3601552709
Short name	T224
Test name
Test status
Simulation time	2661138597 ps
CPU time	41.16 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:03:49 PM PDT 24
Peak memory	217036 kb
Host	smart-51ae4dec-9edd-41ac-8029-992e10c0fd45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601552709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3601552709
Directory	/workspace/19.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.rom_ctrl_smoke.3647194500
Short name	T587
Test name
Test status
Simulation time	1056526751 ps
CPU time	22.67 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:22:15 PM PDT 24
Peak memory	216376 kb
Host	smart-228dad9e-670a-4fc7-8aa9-63002d6e3e14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647194500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3647194500
Directory	/workspace/19.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.rom_ctrl_stress_all.3676585843
Short name	T474
Test name
Test status
Simulation time	4964735926 ps
CPU time	35.9 seconds
Started	Apr 16 02:02:55 PM PDT 24
Finished	Apr 16 02:03:36 PM PDT 24
Peak memory	219176 kb
Host	smart-6a61ca2c-36ef-45f6-868d-7d95fb3153f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676585843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.rom_ctrl_stress_all.3676585843
Directory	/workspace/19.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.rom_ctrl_stress_all.411594445
Short name	T471
Test name
Test status
Simulation time	42114660041 ps
CPU time	205.09 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:25:24 PM PDT 24
Peak memory	221408 kb
Host	smart-81114f4b-8afd-4321-97b0-c10827676d97
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411594445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.rom_ctrl_stress_all.411594445
Directory	/workspace/19.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.rom_ctrl_alert_test.1736886233
Short name	T582
Test name
Test status
Simulation time	9507907145 ps
CPU time	23.02 seconds
Started	Apr 16 12:21:03 PM PDT 24
Finished	Apr 16 12:21:27 PM PDT 24
Peak memory	210588 kb
Host	smart-4056a225-dd7e-4fa7-8902-bf67a23e9e60
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736886233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1736886233
Directory	/workspace/2.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.rom_ctrl_alert_test.2040032485
Short name	T472
Test name
Test status
Simulation time	41929660790 ps
CPU time	32.19 seconds
Started	Apr 16 02:03:12 PM PDT 24
Finished	Apr 16 02:03:45 PM PDT 24
Peak memory	212292 kb
Host	smart-38172e32-ab57-4ac2-8a48-150f89b9b56b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040032485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2040032485
Directory	/workspace/2.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2537205793
Short name	T366
Test name
Test status
Simulation time	5508075169 ps
CPU time	372.65 seconds
Started	Apr 16 12:20:57 PM PDT 24
Finished	Apr 16 12:27:11 PM PDT 24
Peak memory	227884 kb
Host	smart-50b9c0e6-f97b-466e-8dda-06dd748955bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537205793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c orrupt_sig_fatal_chk.2537205793
Directory	/workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.760506598
Short name	T235
Test name
Test status
Simulation time	184283816746 ps
CPU time	275.81 seconds
Started	Apr 16 02:02:43 PM PDT 24
Finished	Apr 16 02:07:21 PM PDT 24
Peak memory	238024 kb
Host	smart-2fa97587-3ff0-42fd-bfff-7d005977642e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760506598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co rrupt_sig_fatal_chk.760506598
Directory	/workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3621732740
Short name	T32
Test name
Test status
Simulation time	17069344511 ps
CPU time	45.14 seconds
Started	Apr 16 12:21:11 PM PDT 24
Finished	Apr 16 12:21:57 PM PDT 24
Peak memory	213588 kb
Host	smart-bbdcbc3b-20e9-47a4-84ff-9a1af68f81ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621732740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3621732740
Directory	/workspace/2.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3682936124
Short name	T267
Test name
Test status
Simulation time	7248972379 ps
CPU time	31.7 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:20 PM PDT 24
Peak memory	214832 kb
Host	smart-5f8f1dcd-b934-4771-aa73-7f5482bed121
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682936124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3682936124
Directory	/workspace/2.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1298443481
Short name	T194
Test name
Test status
Simulation time	2822925700 ps
CPU time	26.4 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:22:14 PM PDT 24
Peak memory	210936 kb
Host	smart-8eea0677-7a84-4505-b323-3d1e65a432f8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1298443481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1298443481
Directory	/workspace/2.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1858203833
Short name	T374
Test name
Test status
Simulation time	4289000643 ps
CPU time	23.71 seconds
Started	Apr 16 02:02:41 PM PDT 24
Finished	Apr 16 02:03:07 PM PDT 24
Peak memory	211384 kb
Host	smart-3afebd89-e093-4cef-8e74-b2e0e5b6884e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1858203833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1858203833
Directory	/workspace/2.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/2.rom_ctrl_sec_cm.1175263817
Short name	T41
Test name
Test status
Simulation time	2043962790 ps
CPU time	129.72 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:05:14 PM PDT 24
Peak memory	236724 kb
Host	smart-d3d825eb-eb0f-411d-afc4-930e2e029c6c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175263817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1175263817
Directory	/workspace/2.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.rom_ctrl_sec_cm.4051906685
Short name	T45
Test name
Test status
Simulation time	1073838881 ps
CPU time	230.13 seconds
Started	Apr 16 12:19:04 PM PDT 24
Finished	Apr 16 12:22:55 PM PDT 24
Peak memory	238072 kb
Host	smart-6c171e03-5b64-46f8-84cc-49ca24384fa6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051906685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4051906685
Directory	/workspace/2.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.rom_ctrl_smoke.1770490445
Short name	T566
Test name
Test status
Simulation time	359905512 ps
CPU time	20.41 seconds
Started	Apr 16 02:02:36 PM PDT 24
Finished	Apr 16 02:02:58 PM PDT 24
Peak memory	215640 kb
Host	smart-68d292b6-1c96-4cda-87ab-37f1cfde93e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770490445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1770490445
Directory	/workspace/2.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.rom_ctrl_smoke.3797667642
Short name	T287
Test name
Test status
Simulation time	17475998269 ps
CPU time	68.86 seconds
Started	Apr 16 12:22:41 PM PDT 24
Finished	Apr 16 12:23:56 PM PDT 24
Peak memory	217612 kb
Host	smart-e2ed5913-67ff-4321-867d-4d52d611fcb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797667642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3797667642
Directory	/workspace/2.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.rom_ctrl_stress_all.1614599227
Short name	T296
Test name
Test status
Simulation time	27812566170 ps
CPU time	77.84 seconds
Started	Apr 16 02:02:47 PM PDT 24
Finished	Apr 16 02:04:06 PM PDT 24
Peak memory	219420 kb
Host	smart-46780067-a964-48fc-9138-6bc9697769af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614599227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.rom_ctrl_stress_all.1614599227
Directory	/workspace/2.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.rom_ctrl_stress_all.2312677418
Short name	T137
Test name
Test status
Simulation time	8739607893 ps
CPU time	86.47 seconds
Started	Apr 16 12:20:59 PM PDT 24
Finished	Apr 16 12:22:27 PM PDT 24
Peak memory	219276 kb
Host	smart-eee1d3e5-6312-4584-ace3-b3b8432ddd4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312677418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.rom_ctrl_stress_all.2312677418
Directory	/workspace/2.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2575453460
Short name	T636
Test name
Test status
Simulation time	20297430753 ps
CPU time	7190.68 seconds
Started	Apr 16 02:02:47 PM PDT 24
Finished	Apr 16 04:02:39 PM PDT 24
Peak memory	234992 kb
Host	smart-15f16eee-7014-4221-9f79-ef7b600b3359
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575453460 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2575453460
Directory	/workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.rom_ctrl_alert_test.2239872147
Short name	T318
Test name
Test status
Simulation time	331837135 ps
CPU time	8.13 seconds
Started	Apr 16 12:21:57 PM PDT 24
Finished	Apr 16 12:22:07 PM PDT 24
Peak memory	211224 kb
Host	smart-b26aab85-e0c0-49f0-8b51-24e80d291165
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239872147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2239872147
Directory	/workspace/20.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.rom_ctrl_alert_test.3923344264
Short name	T596
Test name
Test status
Simulation time	11247074771 ps
CPU time	24.66 seconds
Started	Apr 16 02:03:01 PM PDT 24
Finished	Apr 16 02:03:27 PM PDT 24
Peak memory	211460 kb
Host	smart-2bebacf0-0c84-4e72-a4d5-369831974702
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923344264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3923344264
Directory	/workspace/20.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1128436904
Short name	T641
Test name
Test status
Simulation time	18205714477 ps
CPU time	405.54 seconds
Started	Apr 16 02:02:56 PM PDT 24
Finished	Apr 16 02:09:42 PM PDT 24
Peak memory	230512 kb
Host	smart-f40575ee-d120-42c7-8e7a-1555b287c1b5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128436904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_ corrupt_sig_fatal_chk.1128436904
Directory	/workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1184732027
Short name	T124
Test name
Test status
Simulation time	17044510258 ps
CPU time	245.97 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:25:58 PM PDT 24
Peak memory	224524 kb
Host	smart-08a6efe6-4138-447c-8bbd-ef0ecba37e58
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184732027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_ corrupt_sig_fatal_chk.1184732027
Directory	/workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3709551402
Short name	T379
Test name
Test status
Simulation time	12175797331 ps
CPU time	48.85 seconds
Started	Apr 16 02:02:56 PM PDT 24
Finished	Apr 16 02:03:46 PM PDT 24
Peak memory	215248 kb
Host	smart-473ac81d-18a3-4ced-9d56-150e8a433cf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3709551402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3709551402
Directory	/workspace/20.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3767675192
Short name	T221
Test name
Test status
Simulation time	4982665684 ps
CPU time	43.13 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:22:37 PM PDT 24
Peak memory	215120 kb
Host	smart-bd54ae72-01d0-4be4-93ee-c72efb1b3519
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767675192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3767675192
Directory	/workspace/20.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1706015477
Short name	T215
Test name
Test status
Simulation time	6433097158 ps
CPU time	30.07 seconds
Started	Apr 16 12:22:58 PM PDT 24
Finished	Apr 16 12:23:32 PM PDT 24
Peak memory	211076 kb
Host	smart-4eb63e55-14a7-429c-bd5a-eac58005a767
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1706015477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1706015477
Directory	/workspace/20.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2844384487
Short name	T451
Test name
Test status
Simulation time	441908016 ps
CPU time	13.16 seconds
Started	Apr 16 02:03:02 PM PDT 24
Finished	Apr 16 02:03:16 PM PDT 24
Peak memory	211284 kb
Host	smart-210a0942-2a48-453d-869b-1b9853218bb0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2844384487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2844384487
Directory	/workspace/20.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/20.rom_ctrl_stress_all.1790268043
Short name	T417
Test name
Test status
Simulation time	44619463393 ps
CPU time	85.94 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:23:24 PM PDT 24
Peak memory	218776 kb
Host	smart-1031cac2-a592-4c53-8e2a-4f64491e99d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790268043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_stress_all.1790268043
Directory	/workspace/20.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.rom_ctrl_stress_all.4033216572
Short name	T339
Test name
Test status
Simulation time	20266008271 ps
CPU time	102.69 seconds
Started	Apr 16 02:02:53 PM PDT 24
Finished	Apr 16 02:04:36 PM PDT 24
Peak memory	221228 kb
Host	smart-669422c6-92c6-4369-b5d3-8dfabcf6efdc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033216572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_stress_all.4033216572
Directory	/workspace/20.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.rom_ctrl_alert_test.3588836165
Short name	T659
Test name
Test status
Simulation time	19620575563 ps
CPU time	31.63 seconds
Started	Apr 16 02:02:55 PM PDT 24
Finished	Apr 16 02:03:28 PM PDT 24
Peak memory	212372 kb
Host	smart-3a84f506-124a-4c36-8906-4281ee869279
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588836165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3588836165
Directory	/workspace/21.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.rom_ctrl_alert_test.3968298314
Short name	T142
Test name
Test status
Simulation time	6656821767 ps
CPU time	27.73 seconds
Started	Apr 16 12:21:43 PM PDT 24
Finished	Apr 16 12:22:14 PM PDT 24
Peak memory	212352 kb
Host	smart-a10a66d2-7023-461f-9e87-7c5eab3795db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968298314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3968298314
Directory	/workspace/21.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2660391593
Short name	T489
Test name
Test status
Simulation time	17931832893 ps
CPU time	239.09 seconds
Started	Apr 16 02:02:58 PM PDT 24
Finished	Apr 16 02:06:58 PM PDT 24
Peak memory	240932 kb
Host	smart-9c49fc97-21c8-400e-bcc7-327d5a0f4cf5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660391593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ corrupt_sig_fatal_chk.2660391593
Directory	/workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2798826801
Short name	T479
Test name
Test status
Simulation time	5520356696 ps
CPU time	198.35 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:25:16 PM PDT 24
Peak memory	237788 kb
Host	smart-b6a91beb-660f-4943-85ce-b4f3565ff151
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798826801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ corrupt_sig_fatal_chk.2798826801
Directory	/workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1209461003
Short name	T260
Test name
Test status
Simulation time	10590804327 ps
CPU time	50.25 seconds
Started	Apr 16 02:03:15 PM PDT 24
Finished	Apr 16 02:04:06 PM PDT 24
Peak memory	215936 kb
Host	smart-55eb18b6-1cfd-484d-8cf7-1cf942c1207c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209461003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1209461003
Directory	/workspace/21.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/21.rom_ctrl_kmac_err_chk.916027510
Short name	T310
Test name
Test status
Simulation time	2695802954 ps
CPU time	34.93 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:22:33 PM PDT 24
Peak memory	214812 kb
Host	smart-4e52fd1e-48c2-46a8-9a31-3e781a39afa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916027510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.916027510
Directory	/workspace/21.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2268814018
Short name	T338
Test name
Test status
Simulation time	3207909628 ps
CPU time	28.68 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:03:19 PM PDT 24
Peak memory	211612 kb
Host	smart-ebbdd1aa-bf28-4e6b-b88f-21340d2ae113
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2268814018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2268814018
Directory	/workspace/21.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3926412220
Short name	T370
Test name
Test status
Simulation time	24816292015 ps
CPU time	23.59 seconds
Started	Apr 16 12:21:47 PM PDT 24
Finished	Apr 16 12:22:13 PM PDT 24
Peak memory	211760 kb
Host	smart-88bd56ab-bb28-41c1-a01d-c57df940bbe0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3926412220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3926412220
Directory	/workspace/21.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/21.rom_ctrl_smoke.2261905307
Short name	T560
Test name
Test status
Simulation time	691172901 ps
CPU time	24.27 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:22:15 PM PDT 24
Peak memory	217136 kb
Host	smart-7fd84557-d105-4ff4-8f42-6ec05f31b5d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261905307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2261905307
Directory	/workspace/21.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.rom_ctrl_smoke.602530022
Short name	T342
Test name
Test status
Simulation time	40454700212 ps
CPU time	55.34 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:04:08 PM PDT 24
Peak memory	216972 kb
Host	smart-15a91211-f328-494b-87b2-1881316fe199
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=602530022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.602530022
Directory	/workspace/21.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.rom_ctrl_stress_all.2359112806
Short name	T256
Test name
Test status
Simulation time	9330708676 ps
CPU time	92.31 seconds
Started	Apr 16 02:03:03 PM PDT 24
Finished	Apr 16 02:04:36 PM PDT 24
Peak memory	220656 kb
Host	smart-a6aa38ee-105b-4b5b-a8e3-dfae58a911e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359112806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.rom_ctrl_stress_all.2359112806
Directory	/workspace/21.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.rom_ctrl_stress_all.387931378
Short name	T216
Test name
Test status
Simulation time	543793589 ps
CPU time	33.24 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:22:24 PM PDT 24
Peak memory	219236 kb
Host	smart-adffc0f6-5b81-4031-8b6b-3961401a9279
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387931378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.rom_ctrl_stress_all.387931378
Directory	/workspace/21.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.rom_ctrl_alert_test.3122361501
Short name	T140
Test name
Test status
Simulation time	174498344 ps
CPU time	8.21 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:05 PM PDT 24
Peak memory	211224 kb
Host	smart-ef8b6449-e204-44ac-aee3-95ca9c70299d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122361501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3122361501
Directory	/workspace/22.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.rom_ctrl_alert_test.4243781367
Short name	T444
Test name
Test status
Simulation time	7694096730 ps
CPU time	30.8 seconds
Started	Apr 16 02:03:03 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	211520 kb
Host	smart-cf84bb83-7c60-4733-afce-f7214844b40e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243781367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4243781367
Directory	/workspace/22.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.246323436
Short name	T576
Test name
Test status
Simulation time	14381714867 ps
CPU time	205.19 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:25:16 PM PDT 24
Peak memory	225452 kb
Host	smart-6dad42c3-be88-4270-9d96-d45666bb81fa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246323436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c orrupt_sig_fatal_chk.246323436
Directory	/workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3409102145
Short name	T345
Test name
Test status
Simulation time	147607539180 ps
CPU time	517.26 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:11:46 PM PDT 24
Peak memory	219080 kb
Host	smart-3d94e2f0-d5bf-4376-9208-1490d289df7f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409102145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_ corrupt_sig_fatal_chk.3409102145
Directory	/workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2786013517
Short name	T550
Test name
Test status
Simulation time	346477791 ps
CPU time	18.26 seconds
Started	Apr 16 12:21:57 PM PDT 24
Finished	Apr 16 12:22:17 PM PDT 24
Peak memory	214664 kb
Host	smart-986d3c67-5562-42dd-a3db-f987ce874410
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786013517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2786013517
Directory	/workspace/22.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3770707506
Short name	T208
Test name
Test status
Simulation time	8785009342 ps
CPU time	69.97 seconds
Started	Apr 16 02:02:58 PM PDT 24
Finished	Apr 16 02:04:09 PM PDT 24
Peak memory	215188 kb
Host	smart-29c5cd6b-fd28-443e-a544-a9e143d38175
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770707506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3770707506
Directory	/workspace/22.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1370756062
Short name	T188
Test name
Test status
Simulation time	2385094812 ps
CPU time	21.4 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:21 PM PDT 24
Peak memory	211412 kb
Host	smart-fe5210ea-a6dc-4230-a526-ec2bfb448ecb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1370756062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1370756062
Directory	/workspace/22.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/22.rom_ctrl_max_throughput_chk.893011335
Short name	T475
Test name
Test status
Simulation time	4126100106 ps
CPU time	23.98 seconds
Started	Apr 16 02:03:01 PM PDT 24
Finished	Apr 16 02:03:26 PM PDT 24
Peak memory	212456 kb
Host	smart-f488c436-7188-42eb-a938-4098a99dbdf8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=893011335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.893011335
Directory	/workspace/22.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/22.rom_ctrl_smoke.1917454712
Short name	T190
Test name
Test status
Simulation time	454888794 ps
CPU time	20.46 seconds
Started	Apr 16 02:03:00 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	217372 kb
Host	smart-9204dad2-2bbc-4ffb-adb1-54f4555cdd45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917454712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1917454712
Directory	/workspace/22.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.rom_ctrl_smoke.2911205092
Short name	T198
Test name
Test status
Simulation time	1980332117 ps
CPU time	33.91 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:34 PM PDT 24
Peak memory	215496 kb
Host	smart-78db6f5d-8ece-487a-b0b3-6c2af231ea22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911205092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2911205092
Directory	/workspace/22.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.rom_ctrl_stress_all.1031361659
Short name	T667
Test name
Test status
Simulation time	89103857162 ps
CPU time	207.14 seconds
Started	Apr 16 12:21:47 PM PDT 24
Finished	Apr 16 12:25:16 PM PDT 24
Peak memory	219648 kb
Host	smart-faac1026-bac7-4159-87c5-389dafaffba0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031361659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.rom_ctrl_stress_all.1031361659
Directory	/workspace/22.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.rom_ctrl_stress_all.1921532169
Short name	T334
Test name
Test status
Simulation time	3052259489 ps
CPU time	45.91 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:03:51 PM PDT 24
Peak memory	219460 kb
Host	smart-b537a71c-bca4-4a1e-807c-09e0391ebd8c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921532169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.rom_ctrl_stress_all.1921532169
Directory	/workspace/22.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.834232494
Short name	T621
Test name
Test status
Simulation time	133729275803 ps
CPU time	2059.51 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:56:11 PM PDT 24
Peak memory	235804 kb
Host	smart-44fd74ea-8d17-41fa-97c2-52fd6dccbd8d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834232494 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.834232494
Directory	/workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.rom_ctrl_alert_test.2173800789
Short name	T515
Test name
Test status
Simulation time	590606340 ps
CPU time	8.31 seconds
Started	Apr 16 12:22:21 PM PDT 24
Finished	Apr 16 12:22:30 PM PDT 24
Peak memory	211304 kb
Host	smart-fa0c52dd-cab6-475f-824b-866f94f747a1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173800789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2173800789
Directory	/workspace/23.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.rom_ctrl_alert_test.3887700530
Short name	T600
Test name
Test status
Simulation time	486958754 ps
CPU time	8.29 seconds
Started	Apr 16 02:03:05 PM PDT 24
Finished	Apr 16 02:03:14 PM PDT 24
Peak memory	211392 kb
Host	smart-c6932675-4299-438a-97d2-540ef106892e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887700530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3887700530
Directory	/workspace/23.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1133600572
Short name	T434
Test name
Test status
Simulation time	4161701426 ps
CPU time	318.94 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:08:30 PM PDT 24
Peak memory	240188 kb
Host	smart-195b992a-c278-448b-b0cc-7727b0350fa3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133600572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_ corrupt_sig_fatal_chk.1133600572
Directory	/workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1024745264
Short name	T494
Test name
Test status
Simulation time	1375569890 ps
CPU time	19.65 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:03:32 PM PDT 24
Peak memory	214728 kb
Host	smart-6bc3b420-d629-4757-bacf-0a61a99e265a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024745264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1024745264
Directory	/workspace/23.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3638959400
Short name	T26
Test name
Test status
Simulation time	8445718881 ps
CPU time	65.49 seconds
Started	Apr 16 12:22:35 PM PDT 24
Finished	Apr 16 12:23:45 PM PDT 24
Peak memory	214560 kb
Host	smart-077a2e9e-bc6e-42ef-9e5c-f3f46322ffa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638959400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3638959400
Directory	/workspace/23.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/23.rom_ctrl_max_throughput_chk.144534751
Short name	T591
Test name
Test status
Simulation time	10192779986 ps
CPU time	25.82 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:22:34 PM PDT 24
Peak memory	211656 kb
Host	smart-44c39e73-d875-4c4d-bf43-ab86dd8769c7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=144534751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.144534751
Directory	/workspace/23.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3037584045
Short name	T510
Test name
Test status
Simulation time	5360801070 ps
CPU time	16.28 seconds
Started	Apr 16 02:03:00 PM PDT 24
Finished	Apr 16 02:03:17 PM PDT 24
Peak memory	212936 kb
Host	smart-199d2bfb-8c3e-4211-891c-93ff6ede961b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3037584045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3037584045
Directory	/workspace/23.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/23.rom_ctrl_smoke.2335127404
Short name	T139
Test name
Test status
Simulation time	1376248186 ps
CPU time	20 seconds
Started	Apr 16 02:03:01 PM PDT 24
Finished	Apr 16 02:03:22 PM PDT 24
Peak memory	217552 kb
Host	smart-cf3ff1e6-3da0-4d52-a7d1-29d64008495a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335127404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2335127404
Directory	/workspace/23.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.rom_ctrl_smoke.3632021165
Short name	T437
Test name
Test status
Simulation time	717803328 ps
CPU time	18.82 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:22:09 PM PDT 24
Peak memory	216296 kb
Host	smart-16b64d1b-904d-4f63-bc75-b2a0bc2a0415
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632021165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3632021165
Directory	/workspace/23.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.rom_ctrl_stress_all.314009432
Short name	T491
Test name
Test status
Simulation time	14635598317 ps
CPU time	33.84 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:22:35 PM PDT 24
Peak memory	212788 kb
Host	smart-041ed64f-0890-4705-befd-fbea3e899e29
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314009432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.rom_ctrl_stress_all.314009432
Directory	/workspace/23.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.rom_ctrl_stress_all.660325943
Short name	T304
Test name
Test status
Simulation time	21318359390 ps
CPU time	62.91 seconds
Started	Apr 16 02:03:12 PM PDT 24
Finished	Apr 16 02:04:16 PM PDT 24
Peak memory	216212 kb
Host	smart-d0be87ce-f49e-4829-8cf4-63d49fe6deb8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660325943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.rom_ctrl_stress_all.660325943
Directory	/workspace/23.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.rom_ctrl_alert_test.1414483621
Short name	T373
Test name
Test status
Simulation time	14217151126 ps
CPU time	29 seconds
Started	Apr 16 12:21:52 PM PDT 24
Finished	Apr 16 12:22:24 PM PDT 24
Peak memory	212224 kb
Host	smart-986a0717-b77e-4d9a-a6f4-5549f16f1768
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414483621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1414483621
Directory	/workspace/24.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.rom_ctrl_alert_test.698422932
Short name	T176
Test name
Test status
Simulation time	594249412 ps
CPU time	12.57 seconds
Started	Apr 16 02:03:00 PM PDT 24
Finished	Apr 16 02:03:14 PM PDT 24
Peak memory	211420 kb
Host	smart-a23fbd4d-4fcb-4367-a790-7e7c4df994a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698422932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.698422932
Directory	/workspace/24.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2757531022
Short name	T303
Test name
Test status
Simulation time	286175912350 ps
CPU time	948.66 seconds
Started	Apr 16 02:03:00 PM PDT 24
Finished	Apr 16 02:18:50 PM PDT 24
Peak memory	239808 kb
Host	smart-3691c464-82b4-4c6c-9402-eae229388f16
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757531022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_ corrupt_sig_fatal_chk.2757531022
Directory	/workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3504111221
Short name	T502
Test name
Test status
Simulation time	404610342593 ps
CPU time	564.63 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:31:15 PM PDT 24
Peak memory	229792 kb
Host	smart-eb45421d-a64e-45b0-8d8c-3fafb06a8e3f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504111221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_ corrupt_sig_fatal_chk.3504111221
Directory	/workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2947711887
Short name	T154
Test name
Test status
Simulation time	8209329194 ps
CPU time	64.6 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:22:53 PM PDT 24
Peak memory	215048 kb
Host	smart-acaf3407-f7d6-4239-9ef0-358b6320a103
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947711887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2947711887
Directory	/workspace/24.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/24.rom_ctrl_kmac_err_chk.40135609
Short name	T364
Test name
Test status
Simulation time	26397016490 ps
CPU time	57.17 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:04:09 PM PDT 24
Peak memory	214052 kb
Host	smart-9adfa74f-b1c3-4942-be7b-0c55011f42f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40135609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.40135609
Directory	/workspace/24.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1353320965
Short name	T170
Test name
Test status
Simulation time	11695719044 ps
CPU time	27.58 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:27 PM PDT 24
Peak memory	211720 kb
Host	smart-aaf1643b-c0ec-482d-99e5-be86b3e95c7e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1353320965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1353320965
Directory	/workspace/24.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/24.rom_ctrl_max_throughput_chk.371384118
Short name	T480
Test name
Test status
Simulation time	14666420691 ps
CPU time	31.07 seconds
Started	Apr 16 02:03:00 PM PDT 24
Finished	Apr 16 02:03:32 PM PDT 24
Peak memory	211888 kb
Host	smart-582d1730-98ce-4659-93ef-68ce07674d12
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=371384118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.371384118
Directory	/workspace/24.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/24.rom_ctrl_smoke.2952697325
Short name	T6
Test name
Test status
Simulation time	4909199253 ps
CPU time	29.15 seconds
Started	Apr 16 02:02:56 PM PDT 24
Finished	Apr 16 02:03:26 PM PDT 24
Peak memory	215040 kb
Host	smart-5cbadf36-2f39-4838-9ada-3350208aad34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952697325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2952697325
Directory	/workspace/24.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.rom_ctrl_smoke.3783683679
Short name	T206
Test name
Test status
Simulation time	349143708 ps
CPU time	19.63 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:22:13 PM PDT 24
Peak memory	216588 kb
Host	smart-af0f2de0-60ea-42b3-9036-1a4dd941de56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783683679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3783683679
Directory	/workspace/24.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.rom_ctrl_stress_all.1578776648
Short name	T606
Test name
Test status
Simulation time	72168424168 ps
CPU time	88.94 seconds
Started	Apr 16 02:03:02 PM PDT 24
Finished	Apr 16 02:04:31 PM PDT 24
Peak memory	219296 kb
Host	smart-cf16571a-4662-41e8-a958-18ddb331c2b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578776648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_stress_all.1578776648
Directory	/workspace/24.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.rom_ctrl_stress_all.3518147992
Short name	T481
Test name
Test status
Simulation time	42971143461 ps
CPU time	36.57 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:22:29 PM PDT 24
Peak memory	217968 kb
Host	smart-62b030c4-471b-4ba7-a2c5-07a0a6e91e5d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518147992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_stress_all.3518147992
Directory	/workspace/24.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.rom_ctrl_alert_test.1735799767
Short name	T492
Test name
Test status
Simulation time	972272554 ps
CPU time	8.33 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:21:59 PM PDT 24
Peak memory	211312 kb
Host	smart-eefd273a-095a-4af9-8382-4a9d546c9ba3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735799767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1735799767
Directory	/workspace/25.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.rom_ctrl_alert_test.2697284501
Short name	T218
Test name
Test status
Simulation time	8569389018 ps
CPU time	19.89 seconds
Started	Apr 16 02:03:21 PM PDT 24
Finished	Apr 16 02:03:42 PM PDT 24
Peak memory	211472 kb
Host	smart-bf068e85-b0b9-4188-bd39-50abe1b73087
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697284501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2697284501
Directory	/workspace/25.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2197798799
Short name	T210
Test name
Test status
Simulation time	44052080148 ps
CPU time	446.79 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:10:32 PM PDT 24
Peak memory	215696 kb
Host	smart-f6609d0b-652a-4ee6-bb27-e15b10496d7c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197798799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_ corrupt_sig_fatal_chk.2197798799
Directory	/workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.817328172
Short name	T251
Test name
Test status
Simulation time	46090375227 ps
CPU time	213.56 seconds
Started	Apr 16 12:22:35 PM PDT 24
Finished	Apr 16 12:26:13 PM PDT 24
Peak memory	237924 kb
Host	smart-b75213a3-0999-4edf-8928-32c8745a9d52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817328172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c orrupt_sig_fatal_chk.817328172
Directory	/workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1380627605
Short name	T25
Test name
Test status
Simulation time	335978894 ps
CPU time	18.48 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:22:11 PM PDT 24
Peak memory	214988 kb
Host	smart-8a354a25-9f23-4b26-b8f6-4e0804810a36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380627605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1380627605
Directory	/workspace/25.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3686495287
Short name	T214
Test name
Test status
Simulation time	661451786 ps
CPU time	19.59 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:03:25 PM PDT 24
Peak memory	214656 kb
Host	smart-be2a955b-53d5-4527-a079-fb516dfb9fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686495287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3686495287
Directory	/workspace/25.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1215223643
Short name	T171
Test name
Test status
Simulation time	9299613098 ps
CPU time	22.79 seconds
Started	Apr 16 12:21:57 PM PDT 24
Finished	Apr 16 12:22:22 PM PDT 24
Peak memory	211524 kb
Host	smart-7d273fce-bbed-4c53-8d3d-a6f575193930
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1215223643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1215223643
Directory	/workspace/25.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3351030339
Short name	T349
Test name
Test status
Simulation time	3305773743 ps
CPU time	17.73 seconds
Started	Apr 16 02:03:01 PM PDT 24
Finished	Apr 16 02:03:19 PM PDT 24
Peak memory	211676 kb
Host	smart-1e80fd8f-785e-42b2-a922-61820d5f1b82
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3351030339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3351030339
Directory	/workspace/25.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/25.rom_ctrl_smoke.2219333881
Short name	T125
Test name
Test status
Simulation time	9041225847 ps
CPU time	27.71 seconds
Started	Apr 16 02:02:58 PM PDT 24
Finished	Apr 16 02:03:27 PM PDT 24
Peak memory	217732 kb
Host	smart-221a7443-0017-4141-8326-c186ce6d63b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219333881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2219333881
Directory	/workspace/25.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.rom_ctrl_smoke.4093868389
Short name	T443
Test name
Test status
Simulation time	12482363643 ps
CPU time	55.12 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:22:47 PM PDT 24
Peak memory	218016 kb
Host	smart-8d0deb26-2cc6-4d1b-a037-67a85f2c854c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093868389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4093868389
Directory	/workspace/25.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.rom_ctrl_stress_all.2592398843
Short name	T407
Test name
Test status
Simulation time	30089717234 ps
CPU time	144.76 seconds
Started	Apr 16 02:03:01 PM PDT 24
Finished	Apr 16 02:05:26 PM PDT 24
Peak memory	219468 kb
Host	smart-209ecb51-06a2-4f17-9432-1a91ba235576
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592398843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.rom_ctrl_stress_all.2592398843
Directory	/workspace/25.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.rom_ctrl_stress_all.921148021
Short name	T222
Test name
Test status
Simulation time	7441905339 ps
CPU time	60.83 seconds
Started	Apr 16 12:22:28 PM PDT 24
Finished	Apr 16 12:23:30 PM PDT 24
Peak memory	221096 kb
Host	smart-7a816db8-e826-4e94-994c-ce4d0d756725
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921148021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.rom_ctrl_stress_all.921148021
Directory	/workspace/25.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.rom_ctrl_alert_test.2076472538
Short name	T397
Test name
Test status
Simulation time	174203845 ps
CPU time	8.71 seconds
Started	Apr 16 12:21:48 PM PDT 24
Finished	Apr 16 12:21:59 PM PDT 24
Peak memory	211300 kb
Host	smart-c3b57d92-580d-4b4f-8702-7d56459be664
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076472538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2076472538
Directory	/workspace/26.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.rom_ctrl_alert_test.3570455600
Short name	T381
Test name
Test status
Simulation time	167584471 ps
CPU time	8.39 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	211380 kb
Host	smart-a7c40d30-1b86-4bfb-9a0b-48dbeea90db3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570455600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3570455600
Directory	/workspace/26.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3683345337
Short name	T631
Test name
Test status
Simulation time	203142100967 ps
CPU time	530.02 seconds
Started	Apr 16 02:02:58 PM PDT 24
Finished	Apr 16 02:11:49 PM PDT 24
Peak memory	239972 kb
Host	smart-5fec32a2-c587-4514-89a5-c87e7880b0bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683345337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_ corrupt_sig_fatal_chk.3683345337
Directory	/workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.694681730
Short name	T232
Test name
Test status
Simulation time	78929137831 ps
CPU time	842.39 seconds
Started	Apr 16 12:23:11 PM PDT 24
Finished	Apr 16 12:37:15 PM PDT 24
Peak memory	239656 kb
Host	smart-308e4734-c993-4189-a1fc-efead57b42d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694681730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c orrupt_sig_fatal_chk.694681730
Directory	/workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1970495279
Short name	T263
Test name
Test status
Simulation time	675936549 ps
CPU time	19.34 seconds
Started	Apr 16 02:03:24 PM PDT 24
Finished	Apr 16 02:03:44 PM PDT 24
Peak memory	214816 kb
Host	smart-20c786f4-c62b-4313-802b-a92f92395799
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970495279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1970495279
Directory	/workspace/26.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/26.rom_ctrl_kmac_err_chk.619347334
Short name	T255
Test name
Test status
Simulation time	30133271090 ps
CPU time	62.57 seconds
Started	Apr 16 12:21:50 PM PDT 24
Finished	Apr 16 12:22:56 PM PDT 24
Peak memory	215104 kb
Host	smart-94b24075-af70-402a-920c-39644f75af05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=619347334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.619347334
Directory	/workspace/26.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3597909998
Short name	T630
Test name
Test status
Simulation time	3121461243 ps
CPU time	27.1 seconds
Started	Apr 16 12:22:35 PM PDT 24
Finished	Apr 16 12:23:07 PM PDT 24
Peak memory	212536 kb
Host	smart-a66af243-afb8-453e-8ccf-86feb342ead1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3597909998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3597909998
Directory	/workspace/26.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/26.rom_ctrl_max_throughput_chk.670118866
Short name	T520
Test name
Test status
Simulation time	4608761881 ps
CPU time	17.21 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:03:29 PM PDT 24
Peak memory	212952 kb
Host	smart-35bd9441-a642-4ede-8d75-1492b674cb76
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=670118866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.670118866
Directory	/workspace/26.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/26.rom_ctrl_smoke.3956750814
Short name	T387
Test name
Test status
Simulation time	352672957 ps
CPU time	19.8 seconds
Started	Apr 16 02:03:06 PM PDT 24
Finished	Apr 16 02:03:27 PM PDT 24
Peak memory	215816 kb
Host	smart-6b484ebb-569d-451b-b585-5b57e0f469fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956750814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3956750814
Directory	/workspace/26.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.rom_ctrl_smoke.933312383
Short name	T277
Test name
Test status
Simulation time	2083375025 ps
CPU time	27.29 seconds
Started	Apr 16 12:21:47 PM PDT 24
Finished	Apr 16 12:22:17 PM PDT 24
Peak memory	216356 kb
Host	smart-84d5a5fd-25c6-441a-a3d5-fe8ef9b2e6ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933312383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.933312383
Directory	/workspace/26.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.rom_ctrl_stress_all.1016619889
Short name	T650
Test name
Test status
Simulation time	1165534263 ps
CPU time	34.57 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:31 PM PDT 24
Peak memory	219164 kb
Host	smart-e9ee557a-ca7d-43a9-9295-a4693e1ec476
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016619889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_stress_all.1016619889
Directory	/workspace/26.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.rom_ctrl_stress_all.1315078182
Short name	T12
Test name
Test status
Simulation time	1319453377 ps
CPU time	23.24 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:03:33 PM PDT 24
Peak memory	218012 kb
Host	smart-a5c3fe44-7d17-49bb-a296-b4fa12720a63
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315078182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_stress_all.1315078182
Directory	/workspace/26.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.rom_ctrl_alert_test.3165519702
Short name	T274
Test name
Test status
Simulation time	5228652507 ps
CPU time	17.44 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:03:22 PM PDT 24
Peak memory	211520 kb
Host	smart-600b60a9-b518-43d9-a4e8-bbd54dc8b62f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165519702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3165519702
Directory	/workspace/27.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.rom_ctrl_alert_test.922514699
Short name	T612
Test name
Test status
Simulation time	1946107843 ps
CPU time	18.56 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:22:12 PM PDT 24
Peak memory	211876 kb
Host	smart-8de1e0f9-5802-453a-91ec-b7421e5d0717
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922514699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.922514699
Directory	/workspace/27.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3741602491
Short name	T35
Test name
Test status
Simulation time	5224131564 ps
CPU time	167.29 seconds
Started	Apr 16 12:21:43 PM PDT 24
Finished	Apr 16 12:24:33 PM PDT 24
Peak memory	223808 kb
Host	smart-39c796ed-a6bb-4f28-a123-2c8752fe2928
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741602491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_ corrupt_sig_fatal_chk.3741602491
Directory	/workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.562315060
Short name	T297
Test name
Test status
Simulation time	30279857081 ps
CPU time	334.07 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:08:57 PM PDT 24
Peak memory	239992 kb
Host	smart-965efbf2-dbda-4490-a7df-1c11d120c73c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562315060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c orrupt_sig_fatal_chk.562315060
Directory	/workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3875305429
Short name	T160
Test name
Test status
Simulation time	30837429727 ps
CPU time	50.31 seconds
Started	Apr 16 12:22:00 PM PDT 24
Finished	Apr 16 12:22:52 PM PDT 24
Peak memory	215028 kb
Host	smart-51b09233-e9ae-4981-9f96-1f02233d767c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875305429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3875305429
Directory	/workspace/27.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4027489165
Short name	T466
Test name
Test status
Simulation time	12399383278 ps
CPU time	56.42 seconds
Started	Apr 16 02:03:23 PM PDT 24
Finished	Apr 16 02:04:21 PM PDT 24
Peak memory	215084 kb
Host	smart-b5e3d0f7-a2e7-4d9c-95b5-eab0d1ea996d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027489165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4027489165
Directory	/workspace/27.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1563763795
Short name	T547
Test name
Test status
Simulation time	27846409479 ps
CPU time	27.23 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:37 PM PDT 24
Peak memory	211808 kb
Host	smart-731468d2-e20a-4587-9abf-745d7422b80b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1563763795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1563763795
Directory	/workspace/27.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/27.rom_ctrl_max_throughput_chk.800106088
Short name	T660
Test name
Test status
Simulation time	3578016140 ps
CPU time	14.16 seconds
Started	Apr 16 12:22:07 PM PDT 24
Finished	Apr 16 12:22:22 PM PDT 24
Peak memory	211636 kb
Host	smart-b3f6a150-852c-435f-af71-7b9d19e7c876
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=800106088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.800106088
Directory	/workspace/27.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/27.rom_ctrl_smoke.3555340989
Short name	T156
Test name
Test status
Simulation time	6048957193 ps
CPU time	57.74 seconds
Started	Apr 16 12:21:47 PM PDT 24
Finished	Apr 16 12:22:47 PM PDT 24
Peak memory	217156 kb
Host	smart-c2d494fb-61b6-487e-94ad-9c576ea137b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555340989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3555340989
Directory	/workspace/27.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.rom_ctrl_smoke.498239827
Short name	T498
Test name
Test status
Simulation time	24977573189 ps
CPU time	55.37 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:04:08 PM PDT 24
Peak memory	217232 kb
Host	smart-d323a4e0-5355-456f-b6ca-be55d2a1a7b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498239827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.498239827
Directory	/workspace/27.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.rom_ctrl_stress_all.2178450807
Short name	T517
Test name
Test status
Simulation time	369882210 ps
CPU time	25.08 seconds
Started	Apr 16 02:03:18 PM PDT 24
Finished	Apr 16 02:03:44 PM PDT 24
Peak memory	217604 kb
Host	smart-05f25bed-d01c-4c64-8e9e-68cd272e11a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178450807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.rom_ctrl_stress_all.2178450807
Directory	/workspace/27.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.rom_ctrl_stress_all.2806393261
Short name	T358
Test name
Test status
Simulation time	4231329480 ps
CPU time	100.54 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:23:38 PM PDT 24
Peak memory	219712 kb
Host	smart-1b4f4bb7-1ac0-4876-999b-44e257966f99
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806393261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.rom_ctrl_stress_all.2806393261
Directory	/workspace/27.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.rom_ctrl_alert_test.224935199
Short name	T361
Test name
Test status
Simulation time	1905624021 ps
CPU time	18.69 seconds
Started	Apr 16 12:21:54 PM PDT 24
Finished	Apr 16 12:22:15 PM PDT 24
Peak memory	211820 kb
Host	smart-d8b26b19-1106-4eaf-b107-d918e19a7c30
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224935199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.224935199
Directory	/workspace/28.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.rom_ctrl_alert_test.360248489
Short name	T623
Test name
Test status
Simulation time	12619958355 ps
CPU time	26.73 seconds
Started	Apr 16 02:03:12 PM PDT 24
Finished	Apr 16 02:03:40 PM PDT 24
Peak memory	212344 kb
Host	smart-6e04a927-e4a6-4392-ac68-3d209239afad
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360248489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.360248489
Directory	/workspace/28.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1302578593
Short name	T559
Test name
Test status
Simulation time	110473416281 ps
CPU time	326.34 seconds
Started	Apr 16 02:03:20 PM PDT 24
Finished	Apr 16 02:08:48 PM PDT 24
Peak memory	237092 kb
Host	smart-fd8b905e-97d2-40a6-b7ae-3c87b62f2bca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302578593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_ corrupt_sig_fatal_chk.1302578593
Directory	/workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3560869781
Short name	T34
Test name
Test status
Simulation time	308954850905 ps
CPU time	797.81 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:35:25 PM PDT 24
Peak memory	237748 kb
Host	smart-f93201a1-fb03-4f28-a25a-7c77e5eb6a6d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560869781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_ corrupt_sig_fatal_chk.3560869781
Directory	/workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3752901498
Short name	T324
Test name
Test status
Simulation time	4542581484 ps
CPU time	44.74 seconds
Started	Apr 16 02:03:06 PM PDT 24
Finished	Apr 16 02:03:52 PM PDT 24
Peak memory	215112 kb
Host	smart-c5063cdb-3286-488f-b784-c85615169a18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752901498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3752901498
Directory	/workspace/28.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/28.rom_ctrl_kmac_err_chk.692214684
Short name	T563
Test name
Test status
Simulation time	15503211140 ps
CPU time	37.64 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:38 PM PDT 24
Peak memory	214872 kb
Host	smart-c478605c-bda7-46f5-b63d-cb35e3c45a28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692214684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.692214684
Directory	/workspace/28.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2920168853
Short name	T340
Test name
Test status
Simulation time	4255024241 ps
CPU time	32.92 seconds
Started	Apr 16 12:23:10 PM PDT 24
Finished	Apr 16 12:23:44 PM PDT 24
Peak memory	210776 kb
Host	smart-6e11a5a3-5ff8-4aef-a137-97fbeec7352b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2920168853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2920168853
Directory	/workspace/28.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/28.rom_ctrl_max_throughput_chk.404194535
Short name	T583
Test name
Test status
Simulation time	3013689937 ps
CPU time	14.94 seconds
Started	Apr 16 02:03:04 PM PDT 24
Finished	Apr 16 02:03:20 PM PDT 24
Peak memory	211540 kb
Host	smart-fcc0102e-cdce-48a3-b87c-9b321df2c345
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=404194535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.404194535
Directory	/workspace/28.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/28.rom_ctrl_smoke.1749124223
Short name	T380
Test name
Test status
Simulation time	2748663589 ps
CPU time	36.21 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:33 PM PDT 24
Peak memory	215052 kb
Host	smart-36d5ea6e-9e7d-4f66-a600-c9cb70d2074c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749124223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1749124223
Directory	/workspace/28.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.rom_ctrl_smoke.426058895
Short name	T601
Test name
Test status
Simulation time	1429019859 ps
CPU time	20.05 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:03:32 PM PDT 24
Peak memory	216892 kb
Host	smart-8a07add6-aa6f-40c7-835a-f14d6195efd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426058895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.426058895
Directory	/workspace/28.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.rom_ctrl_stress_all.2117317481
Short name	T362
Test name
Test status
Simulation time	13792034988 ps
CPU time	126.63 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:05:16 PM PDT 24
Peak memory	220956 kb
Host	smart-9442d0d7-d22c-47a3-8514-90212784015c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117317481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.rom_ctrl_stress_all.2117317481
Directory	/workspace/28.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.rom_ctrl_stress_all.3126986572
Short name	T261
Test name
Test status
Simulation time	562360770 ps
CPU time	28.53 seconds
Started	Apr 16 12:21:57 PM PDT 24
Finished	Apr 16 12:22:28 PM PDT 24
Peak memory	219168 kb
Host	smart-509d1bef-9079-4b7e-93ae-fbc517df399f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126986572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.rom_ctrl_stress_all.3126986572
Directory	/workspace/28.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.rom_ctrl_alert_test.2987474880
Short name	T247
Test name
Test status
Simulation time	10928766281 ps
CPU time	18.77 seconds
Started	Apr 16 02:03:14 PM PDT 24
Finished	Apr 16 02:03:34 PM PDT 24
Peak memory	212464 kb
Host	smart-fcb96e2c-4975-4f8f-9f8b-f4cb5c3df79f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987474880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2987474880
Directory	/workspace/29.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.rom_ctrl_alert_test.3934949208
Short name	T404
Test name
Test status
Simulation time	10207065492 ps
CPU time	23.59 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:23 PM PDT 24
Peak memory	211308 kb
Host	smart-3707b040-578d-47ee-9842-86a2a4f3f10f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934949208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3934949208
Directory	/workspace/29.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2046531574
Short name	T317
Test name
Test status
Simulation time	140372805402 ps
CPU time	385.16 seconds
Started	Apr 16 12:21:53 PM PDT 24
Finished	Apr 16 12:28:21 PM PDT 24
Peak memory	225616 kb
Host	smart-51ec2bce-6c90-4824-b659-474096616bcc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046531574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_ corrupt_sig_fatal_chk.2046531574
Directory	/workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2254515503
Short name	T15
Test name
Test status
Simulation time	68583809685 ps
CPU time	447.24 seconds
Started	Apr 16 02:03:17 PM PDT 24
Finished	Apr 16 02:10:45 PM PDT 24
Peak memory	216896 kb
Host	smart-61938fae-5ff9-432a-be8e-c57bd64a59e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254515503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_ corrupt_sig_fatal_chk.2254515503
Directory	/workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/29.rom_ctrl_kmac_err_chk.252560210
Short name	T164
Test name
Test status
Simulation time	2744982740 ps
CPU time	28.76 seconds
Started	Apr 16 12:21:50 PM PDT 24
Finished	Apr 16 12:22:22 PM PDT 24
Peak memory	213120 kb
Host	smart-101a9eef-e9d4-48c3-bd99-ee6378cd3330
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252560210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.252560210
Directory	/workspace/29.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/29.rom_ctrl_kmac_err_chk.639828066
Short name	T388
Test name
Test status
Simulation time	28362136282 ps
CPU time	63.05 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:04:12 PM PDT 24
Peak memory	215132 kb
Host	smart-24d54b75-23f3-43ce-850b-b94eb4c3088a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=639828066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.639828066
Directory	/workspace/29.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1549602943
Short name	T285
Test name
Test status
Simulation time	6290256850 ps
CPU time	19.9 seconds
Started	Apr 16 02:03:03 PM PDT 24
Finished	Apr 16 02:03:23 PM PDT 24
Peak memory	212964 kb
Host	smart-c26332ea-e94c-4bdc-8d64-58f654a72099
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1549602943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1549602943
Directory	/workspace/29.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/29.rom_ctrl_max_throughput_chk.975447293
Short name	T272
Test name
Test status
Simulation time	2368664856 ps
CPU time	23.74 seconds
Started	Apr 16 12:21:53 PM PDT 24
Finished	Apr 16 12:22:19 PM PDT 24
Peak memory	212204 kb
Host	smart-a962182c-154d-42d4-bbde-b65e62ac63e3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=975447293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.975447293
Directory	/workspace/29.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/29.rom_ctrl_smoke.1061363972
Short name	T536
Test name
Test status
Simulation time	4877327819 ps
CPU time	48.8 seconds
Started	Apr 16 12:23:10 PM PDT 24
Finished	Apr 16 12:24:00 PM PDT 24
Peak memory	215824 kb
Host	smart-ef8bb64d-c63f-480d-9cb6-18a9a1ec4687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061363972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1061363972
Directory	/workspace/29.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.rom_ctrl_smoke.3234351847
Short name	T30
Test name
Test status
Simulation time	6010022771 ps
CPU time	61.8 seconds
Started	Apr 16 02:03:29 PM PDT 24
Finished	Apr 16 02:04:34 PM PDT 24
Peak memory	217792 kb
Host	smart-63fff4f4-bcb6-4b15-83ea-86d5bed717c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234351847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3234351847
Directory	/workspace/29.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.rom_ctrl_stress_all.1162185575
Short name	T58
Test name
Test status
Simulation time	811521933 ps
CPU time	11 seconds
Started	Apr 16 12:22:08 PM PDT 24
Finished	Apr 16 12:22:20 PM PDT 24
Peak memory	213672 kb
Host	smart-6d824266-38cf-4eeb-8fa6-43bb8eb0c6e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162185575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_stress_all.1162185575
Directory	/workspace/29.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.rom_ctrl_stress_all.1206330144
Short name	T353
Test name
Test status
Simulation time	1093979596 ps
CPU time	24.3 seconds
Started	Apr 16 02:03:14 PM PDT 24
Finished	Apr 16 02:03:39 PM PDT 24
Peak memory	212488 kb
Host	smart-4c1af99f-35e1-4ae7-8838-658c16e617ec
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206330144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_stress_all.1206330144
Directory	/workspace/29.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.rom_ctrl_alert_test.2015268737
Short name	T295
Test name
Test status
Simulation time	39799019162 ps
CPU time	28.73 seconds
Started	Apr 16 12:17:48 PM PDT 24
Finished	Apr 16 12:18:17 PM PDT 24
Peak memory	212192 kb
Host	smart-2f827605-8879-4b38-b86c-68a5e062a28c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015268737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2015268737
Directory	/workspace/3.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.rom_ctrl_alert_test.3195285242
Short name	T588
Test name
Test status
Simulation time	17094525447 ps
CPU time	31.18 seconds
Started	Apr 16 02:02:54 PM PDT 24
Finished	Apr 16 02:03:26 PM PDT 24
Peak memory	212440 kb
Host	smart-ebd4c533-53b7-4d1e-a7ff-3b9c9e83bdbe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195285242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3195285242
Directory	/workspace/3.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2790217442
Short name	T565
Test name
Test status
Simulation time	67354828605 ps
CPU time	856.96 seconds
Started	Apr 16 12:19:47 PM PDT 24
Finished	Apr 16 12:34:05 PM PDT 24
Peak memory	237348 kb
Host	smart-a90a8b22-92c9-492c-b251-53192af027ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790217442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c orrupt_sig_fatal_chk.2790217442
Directory	/workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.321624414
Short name	T278
Test name
Test status
Simulation time	148920697158 ps
CPU time	378.54 seconds
Started	Apr 16 02:02:46 PM PDT 24
Finished	Apr 16 02:09:06 PM PDT 24
Peak memory	237632 kb
Host	smart-1cf5b98a-d17e-4c23-beae-5eb1bb8f94ff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321624414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co rrupt_sig_fatal_chk.321624414
Directory	/workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2987984508
Short name	T262
Test name
Test status
Simulation time	1180698685 ps
CPU time	18.64 seconds
Started	Apr 16 02:02:44 PM PDT 24
Finished	Apr 16 02:03:05 PM PDT 24
Peak memory	214756 kb
Host	smart-510b1658-ade6-47f5-922e-75de57e0cf21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987984508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2987984508
Directory	/workspace/3.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4153797886
Short name	T573
Test name
Test status
Simulation time	15705797538 ps
CPU time	65.33 seconds
Started	Apr 16 12:20:09 PM PDT 24
Finished	Apr 16 12:21:16 PM PDT 24
Peak memory	214996 kb
Host	smart-0d4bb2f6-8051-4fc2-a9e7-2aa049510ca9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153797886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4153797886
Directory	/workspace/3.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2241897083
Short name	T10
Test name
Test status
Simulation time	182341885 ps
CPU time	10.76 seconds
Started	Apr 16 12:18:37 PM PDT 24
Finished	Apr 16 12:18:49 PM PDT 24
Peak memory	212272 kb
Host	smart-98b2d70f-47ea-40ce-9aea-6b04dda8bff8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2241897083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2241897083
Directory	/workspace/3.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/3.rom_ctrl_max_throughput_chk.59835026
Short name	T384
Test name
Test status
Simulation time	9128670734 ps
CPU time	20.94 seconds
Started	Apr 16 02:02:58 PM PDT 24
Finished	Apr 16 02:03:20 PM PDT 24
Peak memory	213032 kb
Host	smart-04bf946e-959c-4805-8149-c81557042584
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=59835026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.59835026
Directory	/workspace/3.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/3.rom_ctrl_sec_cm.4032229772
Short name	T43
Test name
Test status
Simulation time	4645518067 ps
CPU time	127.03 seconds
Started	Apr 16 12:19:38 PM PDT 24
Finished	Apr 16 12:21:46 PM PDT 24
Peak memory	236748 kb
Host	smart-8451d362-92f8-4576-8fe4-a687ded7e6c2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032229772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4032229772
Directory	/workspace/3.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.rom_ctrl_sec_cm.477307954
Short name	T39
Test name
Test status
Simulation time	6666667335 ps
CPU time	240.23 seconds
Started	Apr 16 02:03:02 PM PDT 24
Finished	Apr 16 02:07:03 PM PDT 24
Peak memory	236920 kb
Host	smart-38d9a651-cef8-43d9-90b4-647dee0bc475
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477307954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.477307954
Directory	/workspace/3.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.rom_ctrl_smoke.1786111588
Short name	T553
Test name
Test status
Simulation time	23061460179 ps
CPU time	54.85 seconds
Started	Apr 16 12:21:31 PM PDT 24
Finished	Apr 16 12:22:27 PM PDT 24
Peak memory	217580 kb
Host	smart-69ad228a-b92a-4bfe-96fe-bf529b8e6199
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786111588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1786111588
Directory	/workspace/3.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.rom_ctrl_smoke.3109995340
Short name	T212
Test name
Test status
Simulation time	17958693062 ps
CPU time	43.19 seconds
Started	Apr 16 02:02:34 PM PDT 24
Finished	Apr 16 02:03:19 PM PDT 24
Peak memory	217944 kb
Host	smart-fa121554-ff8e-49ed-ac68-0ed39ffa5742
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109995340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3109995340
Directory	/workspace/3.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.rom_ctrl_stress_all.207958013
Short name	T459
Test name
Test status
Simulation time	13023991502 ps
CPU time	66.42 seconds
Started	Apr 16 12:21:05 PM PDT 24
Finished	Apr 16 12:22:14 PM PDT 24
Peak memory	218532 kb
Host	smart-bc8e7889-36d7-4494-b9dd-8d1586ae1386
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207958013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.rom_ctrl_stress_all.207958013
Directory	/workspace/3.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.rom_ctrl_stress_all.96296483
Short name	T293
Test name
Test status
Simulation time	31926725767 ps
CPU time	97.45 seconds
Started	Apr 16 02:02:35 PM PDT 24
Finished	Apr 16 02:04:14 PM PDT 24
Peak memory	222884 kb
Host	smart-0496f605-60ec-4184-864e-e114e67bdba7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96296483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.rom_ctrl_stress_all.96296483
Directory	/workspace/3.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3385196732
Short name	T556
Test name
Test status
Simulation time	30639655894 ps
CPU time	1406.44 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:26:39 PM PDT 24
Peak memory	220556 kb
Host	smart-13ee5232-4f6a-47e2-8639-b594fab2df31
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385196732 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3385196732
Directory	/workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.796466447
Short name	T24
Test name
Test status
Simulation time	37793994233 ps
CPU time	1643.21 seconds
Started	Apr 16 12:21:46 PM PDT 24
Finished	Apr 16 12:49:12 PM PDT 24
Peak memory	227320 kb
Host	smart-8f276aa8-4945-40c5-adae-18104d5af930
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796466447 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.796466447
Directory	/workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.rom_ctrl_alert_test.2578422592
Short name	T220
Test name
Test status
Simulation time	339000592 ps
CPU time	8.29 seconds
Started	Apr 16 02:03:14 PM PDT 24
Finished	Apr 16 02:03:23 PM PDT 24
Peak memory	211336 kb
Host	smart-27ea694d-f216-4dc5-8273-9117a18eef2e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578422592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2578422592
Directory	/workspace/30.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.rom_ctrl_alert_test.343075417
Short name	T327
Test name
Test status
Simulation time	18114449675 ps
CPU time	32.03 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:22:33 PM PDT 24
Peak memory	211492 kb
Host	smart-0c9beda9-4b17-4ba8-a528-c19a66575118
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343075417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.343075417
Directory	/workspace/30.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1773294532
Short name	T456
Test name
Test status
Simulation time	182871921937 ps
CPU time	925.86 seconds
Started	Apr 16 02:03:00 PM PDT 24
Finished	Apr 16 02:18:26 PM PDT 24
Peak memory	237996 kb
Host	smart-b2af2c86-5c7d-4f4d-8c93-e10a94e4e0c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773294532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_ corrupt_sig_fatal_chk.1773294532
Directory	/workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2656495776
Short name	T386
Test name
Test status
Simulation time	4990233704 ps
CPU time	35.82 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:03:48 PM PDT 24
Peak memory	215176 kb
Host	smart-e9999ddb-8393-4d88-aa6c-9dce3c2f530c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656495776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2656495776
Directory	/workspace/30.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2761076531
Short name	T590
Test name
Test status
Simulation time	7353798377 ps
CPU time	62.6 seconds
Started	Apr 16 12:21:52 PM PDT 24
Finished	Apr 16 12:22:57 PM PDT 24
Peak memory	215036 kb
Host	smart-4bdcaf2e-290c-4b1c-9afc-bb40ce8905d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761076531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2761076531
Directory	/workspace/30.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2584543101
Short name	T415
Test name
Test status
Simulation time	8603682573 ps
CPU time	36.52 seconds
Started	Apr 16 02:03:14 PM PDT 24
Finished	Apr 16 02:03:52 PM PDT 24
Peak memory	211764 kb
Host	smart-5e03842d-3522-4ba9-b745-982484cda1c8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2584543101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2584543101
Directory	/workspace/30.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/30.rom_ctrl_max_throughput_chk.427983183
Short name	T540
Test name
Test status
Simulation time	18899263685 ps
CPU time	19.11 seconds
Started	Apr 16 12:23:09 PM PDT 24
Finished	Apr 16 12:23:30 PM PDT 24
Peak memory	210496 kb
Host	smart-3cbbf1cd-4e7e-4da7-9109-fd96d56b1921
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=427983183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.427983183
Directory	/workspace/30.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/30.rom_ctrl_smoke.2042612459
Short name	T575
Test name
Test status
Simulation time	49076703705 ps
CPU time	80.4 seconds
Started	Apr 16 02:03:14 PM PDT 24
Finished	Apr 16 02:04:36 PM PDT 24
Peak memory	215848 kb
Host	smart-aec6441a-3586-40de-bc7a-e182ac019541
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042612459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2042612459
Directory	/workspace/30.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.rom_ctrl_smoke.522276290
Short name	T569
Test name
Test status
Simulation time	5468453098 ps
CPU time	57.58 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:22:52 PM PDT 24
Peak memory	217856 kb
Host	smart-93bc8fdb-e841-4435-8f93-632ba72a7087
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522276290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.522276290
Directory	/workspace/30.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.rom_ctrl_stress_all.2299022633
Short name	T228
Test name
Test status
Simulation time	22505162764 ps
CPU time	97.33 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:23:38 PM PDT 24
Peak memory	218496 kb
Host	smart-9e947d2e-3d67-41b5-bd24-d4193e5e24b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299022633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.rom_ctrl_stress_all.2299022633
Directory	/workspace/30.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.rom_ctrl_stress_all.3801910434
Short name	T192
Test name
Test status
Simulation time	17862590505 ps
CPU time	143.27 seconds
Started	Apr 16 02:03:28 PM PDT 24
Finished	Apr 16 02:05:54 PM PDT 24
Peak memory	219928 kb
Host	smart-8c60e42b-574a-45d3-aa2d-f3ef572b4416
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801910434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.rom_ctrl_stress_all.3801910434
Directory	/workspace/30.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.rom_ctrl_alert_test.3878255193
Short name	T56
Test name
Test status
Simulation time	413615750 ps
CPU time	11.44 seconds
Started	Apr 16 02:03:27 PM PDT 24
Finished	Apr 16 02:03:40 PM PDT 24
Peak memory	211332 kb
Host	smart-2bce5f3d-4060-4d91-a166-d01b3d20a075
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878255193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3878255193
Directory	/workspace/31.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.rom_ctrl_alert_test.4268263196
Short name	T248
Test name
Test status
Simulation time	2320259353 ps
CPU time	21.11 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:21 PM PDT 24
Peak memory	211916 kb
Host	smart-8a795279-3bb9-412a-bb6a-8820a43638d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268263196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4268263196
Directory	/workspace/31.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3499796063
Short name	T46
Test name
Test status
Simulation time	30212711548 ps
CPU time	383.34 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:28:31 PM PDT 24
Peak memory	237732 kb
Host	smart-9a9b2f47-0c17-40e8-a064-fd8131ccd39e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499796063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_ corrupt_sig_fatal_chk.3499796063
Directory	/workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3508363074
Short name	T605
Test name
Test status
Simulation time	79617808270 ps
CPU time	556.4 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:12:25 PM PDT 24
Peak memory	227840 kb
Host	smart-1ae5518e-08fe-4ac6-b1fc-09b12bcee5e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508363074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_ corrupt_sig_fatal_chk.3508363074
Directory	/workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/31.rom_ctrl_kmac_err_chk.672870204
Short name	T368
Test name
Test status
Simulation time	10231086574 ps
CPU time	49.68 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:04:02 PM PDT 24
Peak memory	215304 kb
Host	smart-f452a963-23ec-4263-bdea-c71d6ffa017b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672870204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.672870204
Directory	/workspace/31.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/31.rom_ctrl_kmac_err_chk.750085853
Short name	T211
Test name
Test status
Simulation time	4614906974 ps
CPU time	47.25 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:48 PM PDT 24
Peak memory	215080 kb
Host	smart-3b40efd5-b1d2-4769-8013-a2d70c7ccd09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750085853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.750085853
Directory	/workspace/31.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3107627334
Short name	T401
Test name
Test status
Simulation time	5550740253 ps
CPU time	21.4 seconds
Started	Apr 16 02:03:21 PM PDT 24
Finished	Apr 16 02:03:43 PM PDT 24
Peak memory	213016 kb
Host	smart-e7ab618b-6a2c-4ca2-a086-1120f4182e8f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3107627334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3107627334
Directory	/workspace/31.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/31.rom_ctrl_max_throughput_chk.721685330
Short name	T542
Test name
Test status
Simulation time	10920647988 ps
CPU time	25.54 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:26 PM PDT 24
Peak memory	211684 kb
Host	smart-86f4e818-ea42-4219-91f1-834c67cf2170
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=721685330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.721685330
Directory	/workspace/31.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/31.rom_ctrl_smoke.2653686826
Short name	T280
Test name
Test status
Simulation time	11183982814 ps
CPU time	61.49 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:04:12 PM PDT 24
Peak memory	217068 kb
Host	smart-bb611a0c-3ad7-419d-ac27-8467e2bfecfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653686826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2653686826
Directory	/workspace/31.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.rom_ctrl_smoke.2914046714
Short name	T166
Test name
Test status
Simulation time	4207744350 ps
CPU time	43 seconds
Started	Apr 16 12:23:11 PM PDT 24
Finished	Apr 16 12:23:55 PM PDT 24
Peak memory	216728 kb
Host	smart-95feaedc-f07e-4e37-9750-f2ad3704f43c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914046714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2914046714
Directory	/workspace/31.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.rom_ctrl_stress_all.1578001882
Short name	T100
Test name
Test status
Simulation time	14216398441 ps
CPU time	31.15 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:03:39 PM PDT 24
Peak memory	214324 kb
Host	smart-3cafcd97-4fe3-4597-9271-b72311ab7213
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578001882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.rom_ctrl_stress_all.1578001882
Directory	/workspace/31.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.rom_ctrl_stress_all.3725514187
Short name	T654
Test name
Test status
Simulation time	13581301342 ps
CPU time	75.4 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:23:09 PM PDT 24
Peak memory	222072 kb
Host	smart-afc0d578-e45a-43e5-909e-376f895737cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725514187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.rom_ctrl_stress_all.3725514187
Directory	/workspace/31.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.rom_ctrl_alert_test.164606550
Short name	T9
Test name
Test status
Simulation time	11508901078 ps
CPU time	26.52 seconds
Started	Apr 16 02:03:29 PM PDT 24
Finished	Apr 16 02:03:58 PM PDT 24
Peak memory	211500 kb
Host	smart-2276bd81-f5c7-43b8-b0dd-ac69c8d7fdb9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164606550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.164606550
Directory	/workspace/32.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.rom_ctrl_alert_test.516071112
Short name	T20
Test name
Test status
Simulation time	6738314012 ps
CPU time	15.66 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:13 PM PDT 24
Peak memory	211292 kb
Host	smart-59222c74-a00a-4287-8321-ea12288d1bff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516071112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.516071112
Directory	/workspace/32.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3729349355
Short name	T530
Test name
Test status
Simulation time	163914454855 ps
CPU time	557.39 seconds
Started	Apr 16 02:03:13 PM PDT 24
Finished	Apr 16 02:12:31 PM PDT 24
Peak memory	234940 kb
Host	smart-6d286d04-702d-42ba-a233-32944ad51e9d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729349355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_ corrupt_sig_fatal_chk.3729349355
Directory	/workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4155321558
Short name	T526
Test name
Test status
Simulation time	15269291426 ps
CPU time	402.33 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:28:40 PM PDT 24
Peak memory	240792 kb
Host	smart-8b184036-db2e-4559-85cd-6f760e7046b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155321558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_ corrupt_sig_fatal_chk.4155321558
Directory	/workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3295798769
Short name	T227
Test name
Test status
Simulation time	8207387308 ps
CPU time	64.24 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:23:03 PM PDT 24
Peak memory	216500 kb
Host	smart-fd62f457-5d63-48dd-8d8d-af5049c0f189
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295798769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3295798769
Directory	/workspace/32.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4013445210
Short name	T163
Test name
Test status
Simulation time	3173706495 ps
CPU time	37.96 seconds
Started	Apr 16 02:03:02 PM PDT 24
Finished	Apr 16 02:03:41 PM PDT 24
Peak memory	215080 kb
Host	smart-9953de32-fc3a-4608-8ad8-877c90827e4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013445210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4013445210
Directory	/workspace/32.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3092798811
Short name	T341
Test name
Test status
Simulation time	666603759 ps
CPU time	14.28 seconds
Started	Apr 16 12:23:10 PM PDT 24
Finished	Apr 16 12:23:26 PM PDT 24
Peak memory	210652 kb
Host	smart-ac952187-a11e-4044-960c-b3a96c8cc363
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3092798811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3092798811
Directory	/workspace/32.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3554890079
Short name	T496
Test name
Test status
Simulation time	2094759598 ps
CPU time	14.24 seconds
Started	Apr 16 02:03:31 PM PDT 24
Finished	Apr 16 02:03:48 PM PDT 24
Peak memory	212360 kb
Host	smart-4318d0b8-7ab2-45bc-bc04-441484bd3e1b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3554890079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3554890079
Directory	/workspace/32.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/32.rom_ctrl_smoke.3993143866
Short name	T249
Test name
Test status
Simulation time	18410242061 ps
CPU time	52.92 seconds
Started	Apr 16 12:21:57 PM PDT 24
Finished	Apr 16 12:22:52 PM PDT 24
Peak memory	217604 kb
Host	smart-71ea6b5b-3dcf-4888-bb5f-c1e136dadbbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993143866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3993143866
Directory	/workspace/32.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.rom_ctrl_smoke.923890519
Short name	T533
Test name
Test status
Simulation time	6123924098 ps
CPU time	29.15 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:03:41 PM PDT 24
Peak memory	218692 kb
Host	smart-29164716-bf3d-43f2-9500-f7f9bc395bf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923890519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.923890519
Directory	/workspace/32.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.rom_ctrl_stress_all.1574302316
Short name	T348
Test name
Test status
Simulation time	83977456919 ps
CPU time	196.31 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:25:13 PM PDT 24
Peak memory	220896 kb
Host	smart-abc4c31b-ed43-4b92-91ca-7db04f7580d5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574302316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.rom_ctrl_stress_all.1574302316
Directory	/workspace/32.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.rom_ctrl_stress_all.3198107845
Short name	T144
Test name
Test status
Simulation time	21826469304 ps
CPU time	106.28 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:04:56 PM PDT 24
Peak memory	219812 kb
Host	smart-99a11848-f73b-4283-9bef-6f1b328278c6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198107845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.rom_ctrl_stress_all.3198107845
Directory	/workspace/32.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.rom_ctrl_alert_test.3395762979
Short name	T441
Test name
Test status
Simulation time	174478756 ps
CPU time	7.91 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:22:09 PM PDT 24
Peak memory	211228 kb
Host	smart-342a078a-0caa-4cc0-abb0-54eaf0b22645
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395762979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3395762979
Directory	/workspace/33.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.rom_ctrl_alert_test.3686131345
Short name	T652
Test name
Test status
Simulation time	5129115408 ps
CPU time	23.5 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:33 PM PDT 24
Peak memory	212296 kb
Host	smart-d964d531-1ef6-4ffb-8305-93de540fa87b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686131345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3686131345
Directory	/workspace/33.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1151196047
Short name	T578
Test name
Test status
Simulation time	354843583427 ps
CPU time	918.48 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:18:35 PM PDT 24
Peak memory	216812 kb
Host	smart-da9da5b7-6d8c-4b85-beea-8b0918d0c4aa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151196047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_ corrupt_sig_fatal_chk.1151196047
Directory	/workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2962745480
Short name	T651
Test name
Test status
Simulation time	16032546952 ps
CPU time	243.64 seconds
Started	Apr 16 12:23:09 PM PDT 24
Finished	Apr 16 12:27:14 PM PDT 24
Peak memory	223616 kb
Host	smart-94b3a43f-e3fb-49ed-ad17-8d90637e63b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962745480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_ corrupt_sig_fatal_chk.2962745480
Directory	/workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1290372936
Short name	T347
Test name
Test status
Simulation time	35028056965 ps
CPU time	50.49 seconds
Started	Apr 16 12:23:09 PM PDT 24
Finished	Apr 16 12:24:01 PM PDT 24
Peak memory	212752 kb
Host	smart-82c019b1-53fa-41b2-8860-6e2582f918d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290372936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1290372936
Directory	/workspace/33.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/33.rom_ctrl_kmac_err_chk.572627721
Short name	T638
Test name
Test status
Simulation time	346026506 ps
CPU time	19.24 seconds
Started	Apr 16 02:03:15 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	214760 kb
Host	smart-cbf3eb11-c73e-47e8-8b84-501690a817f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572627721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.572627721
Directory	/workspace/33.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1275126309
Short name	T413
Test name
Test status
Simulation time	3476109447 ps
CPU time	30.17 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:22:25 PM PDT 24
Peak memory	211272 kb
Host	smart-fc358579-fa71-46e6-92e5-d85012a4f08f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1275126309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1275126309
Directory	/workspace/33.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2573852451
Short name	T499
Test name
Test status
Simulation time	5324967282 ps
CPU time	25.64 seconds
Started	Apr 16 02:03:21 PM PDT 24
Finished	Apr 16 02:03:47 PM PDT 24
Peak memory	211400 kb
Host	smart-32ea3adb-4262-4c36-bb43-15bc34d50c09
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2573852451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2573852451
Directory	/workspace/33.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/33.rom_ctrl_smoke.1330514877
Short name	T250
Test name
Test status
Simulation time	24632554823 ps
CPU time	47.56 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:22:48 PM PDT 24
Peak memory	218360 kb
Host	smart-602bdd0e-fbc6-4eed-8f18-0444937c087f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330514877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1330514877
Directory	/workspace/33.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.rom_ctrl_smoke.2945923842
Short name	T585
Test name
Test status
Simulation time	6489418849 ps
CPU time	66.19 seconds
Started	Apr 16 02:03:15 PM PDT 24
Finished	Apr 16 02:04:23 PM PDT 24
Peak memory	215852 kb
Host	smart-dd80c45c-36a0-492b-a937-7939f3e10cc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945923842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2945923842
Directory	/workspace/33.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.rom_ctrl_stress_all.2838590148
Short name	T207
Test name
Test status
Simulation time	8784046393 ps
CPU time	29.54 seconds
Started	Apr 16 02:03:26 PM PDT 24
Finished	Apr 16 02:03:56 PM PDT 24
Peak memory	214236 kb
Host	smart-943729ae-95f3-4829-ba4a-120653f825ff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838590148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.rom_ctrl_stress_all.2838590148
Directory	/workspace/33.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.rom_ctrl_stress_all.4291882246
Short name	T624
Test name
Test status
Simulation time	382417220 ps
CPU time	17.48 seconds
Started	Apr 16 12:21:53 PM PDT 24
Finished	Apr 16 12:22:13 PM PDT 24
Peak memory	212344 kb
Host	smart-883cba92-aebe-48e0-bee2-ead3e0d8f6ff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291882246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.rom_ctrl_stress_all.4291882246
Directory	/workspace/33.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.rom_ctrl_alert_test.2178458467
Short name	T68
Test name
Test status
Simulation time	15770860231 ps
CPU time	31.4 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:03:48 PM PDT 24
Peak memory	212312 kb
Host	smart-a0048990-9326-4ceb-98b7-fb44c27558ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178458467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2178458467
Directory	/workspace/34.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.rom_ctrl_alert_test.2464468052
Short name	T663
Test name
Test status
Simulation time	8490684090 ps
CPU time	20.9 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:22:19 PM PDT 24
Peak memory	211356 kb
Host	smart-5fb3ae8f-b4a6-42bc-ae2e-4ca9b8b2027e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464468052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2464468052
Directory	/workspace/34.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2667911478
Short name	T428
Test name
Test status
Simulation time	41187259662 ps
CPU time	237.09 seconds
Started	Apr 16 12:21:50 PM PDT 24
Finished	Apr 16 12:25:50 PM PDT 24
Peak memory	240440 kb
Host	smart-0edc61b2-8fec-43c1-8ea2-2cf08cf25e20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667911478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_ corrupt_sig_fatal_chk.2667911478
Directory	/workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4267411614
Short name	T571
Test name
Test status
Simulation time	9936605620 ps
CPU time	168.57 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:06:00 PM PDT 24
Peak memory	237964 kb
Host	smart-6b188895-dbda-4adc-b879-f2174218f6cc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267411614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_ corrupt_sig_fatal_chk.4267411614
Directory	/workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1105769883
Short name	T421
Test name
Test status
Simulation time	8287226385 ps
CPU time	67.02 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:04:18 PM PDT 24
Peak memory	215164 kb
Host	smart-5ff43321-4f4b-46e9-b909-5f454a006875
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1105769883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1105769883
Directory	/workspace/34.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4062216500
Short name	T572
Test name
Test status
Simulation time	1319612656 ps
CPU time	18.3 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:18 PM PDT 24
Peak memory	214532 kb
Host	smart-a3ae097e-cd7d-42c6-b924-8bd680fef0af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062216500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4062216500
Directory	/workspace/34.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1634565634
Short name	T595
Test name
Test status
Simulation time	11288713527 ps
CPU time	17.92 seconds
Started	Apr 16 12:21:56 PM PDT 24
Finished	Apr 16 12:22:16 PM PDT 24
Peak memory	212820 kb
Host	smart-4061fcfa-ff19-4139-8df9-e3bb71e08665
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1634565634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1634565634
Directory	/workspace/34.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3563768604
Short name	T658
Test name
Test status
Simulation time	5499285031 ps
CPU time	18.52 seconds
Started	Apr 16 02:03:30 PM PDT 24
Finished	Apr 16 02:03:51 PM PDT 24
Peak memory	212960 kb
Host	smart-d6e75190-7966-4046-b5a9-0290d77729dd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3563768604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3563768604
Directory	/workspace/34.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/34.rom_ctrl_smoke.1440641648
Short name	T203
Test name
Test status
Simulation time	11976598856 ps
CPU time	52.1 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:23:00 PM PDT 24
Peak memory	217244 kb
Host	smart-3ab99f0a-524f-42ad-bb3d-b4c3149da392
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440641648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1440641648
Directory	/workspace/34.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.rom_ctrl_smoke.944272690
Short name	T306
Test name
Test status
Simulation time	1827811627 ps
CPU time	32.62 seconds
Started	Apr 16 02:03:18 PM PDT 24
Finished	Apr 16 02:03:52 PM PDT 24
Peak memory	216536 kb
Host	smart-1a09c848-533e-4f0d-ae68-339163e7cc5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944272690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.944272690
Directory	/workspace/34.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.rom_ctrl_stress_all.2542323824
Short name	T382
Test name
Test status
Simulation time	4074837436 ps
CPU time	52.87 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:04:04 PM PDT 24
Peak memory	219348 kb
Host	smart-ca808bab-c9cc-4baa-afca-5b8783a8e9eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542323824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.rom_ctrl_stress_all.2542323824
Directory	/workspace/34.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.rom_ctrl_stress_all.4259844458
Short name	T519
Test name
Test status
Simulation time	14616265413 ps
CPU time	84.73 seconds
Started	Apr 16 12:23:09 PM PDT 24
Finished	Apr 16 12:24:35 PM PDT 24
Peak memory	213860 kb
Host	smart-0d749b92-2c1d-46a2-99da-eedb1ddc4117
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259844458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.rom_ctrl_stress_all.4259844458
Directory	/workspace/34.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.rom_ctrl_alert_test.2135292938
Short name	T461
Test name
Test status
Simulation time	8201370005 ps
CPU time	31.34 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:22:37 PM PDT 24
Peak memory	212272 kb
Host	smart-ff510a36-c348-46e3-82d3-0302cb534fda
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135292938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2135292938
Directory	/workspace/35.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.rom_ctrl_alert_test.3632132360
Short name	T326
Test name
Test status
Simulation time	16320471852 ps
CPU time	32.64 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:42 PM PDT 24
Peak memory	212296 kb
Host	smart-8edfcdb4-65b6-48fa-a6cd-71c1815b02b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632132360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3632132360
Directory	/workspace/35.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2244858847
Short name	T554
Test name
Test status
Simulation time	41025999423 ps
CPU time	490.26 seconds
Started	Apr 16 02:03:30 PM PDT 24
Finished	Apr 16 02:11:43 PM PDT 24
Peak memory	241028 kb
Host	smart-5e101171-2161-4094-87c4-20c8b3b8ba49
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244858847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_ corrupt_sig_fatal_chk.2244858847
Directory	/workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2947481534
Short name	T234
Test name
Test status
Simulation time	301992879956 ps
CPU time	636.26 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:32:37 PM PDT 24
Peak memory	217752 kb
Host	smart-014545e5-78d1-440f-b26f-64778f059b59
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947481534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_ corrupt_sig_fatal_chk.2947481534
Directory	/workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1195148437
Short name	T436
Test name
Test status
Simulation time	2223535421 ps
CPU time	32.86 seconds
Started	Apr 16 02:03:24 PM PDT 24
Finished	Apr 16 02:03:58 PM PDT 24
Peak memory	216996 kb
Host	smart-0a866c14-0441-4a79-bca3-66153d707503
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195148437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1195148437
Directory	/workspace/35.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1827002715
Short name	T312
Test name
Test status
Simulation time	29963698549 ps
CPU time	50.47 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:22:58 PM PDT 24
Peak memory	212544 kb
Host	smart-9d1a547d-b8ce-4210-9a92-10d13fbc8fa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827002715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1827002715
Directory	/workspace/35.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1671203391
Short name	T197
Test name
Test status
Simulation time	1967661626 ps
CPU time	22.94 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	211304 kb
Host	smart-5500c66a-8d45-43a4-a647-6deb787816d1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1671203391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1671203391
Directory	/workspace/35.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3085454331
Short name	T131
Test name
Test status
Simulation time	1147456204 ps
CPU time	9.81 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:22:11 PM PDT 24
Peak memory	212348 kb
Host	smart-b54991ad-e630-4755-8ebb-301d39475534
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3085454331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3085454331
Directory	/workspace/35.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/35.rom_ctrl_smoke.1205505112
Short name	T513
Test name
Test status
Simulation time	21593927425 ps
CPU time	57.19 seconds
Started	Apr 16 12:22:05 PM PDT 24
Finished	Apr 16 12:23:04 PM PDT 24
Peak memory	217376 kb
Host	smart-9881feea-430c-4a4d-a737-1e46fc19e0b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205505112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1205505112
Directory	/workspace/35.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.rom_ctrl_smoke.1979825251
Short name	T253
Test name
Test status
Simulation time	34696105761 ps
CPU time	80.13 seconds
Started	Apr 16 02:03:23 PM PDT 24
Finished	Apr 16 02:04:44 PM PDT 24
Peak memory	217136 kb
Host	smart-22ff06ef-b972-4ab1-8554-8f0f92e0ca8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979825251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1979825251
Directory	/workspace/35.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.rom_ctrl_stress_all.3560737710
Short name	T4
Test name
Test status
Simulation time	22553880493 ps
CPU time	60.86 seconds
Started	Apr 16 12:22:35 PM PDT 24
Finished	Apr 16 12:23:40 PM PDT 24
Peak memory	218964 kb
Host	smart-ced17de5-f622-4d69-945d-27b01a15d61b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560737710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.rom_ctrl_stress_all.3560737710
Directory	/workspace/35.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.rom_ctrl_stress_all.3874075548
Short name	T321
Test name
Test status
Simulation time	3667247158 ps
CPU time	35.68 seconds
Started	Apr 16 02:03:26 PM PDT 24
Finished	Apr 16 02:04:03 PM PDT 24
Peak memory	217580 kb
Host	smart-e2d768a2-024a-4b9e-861a-2ecf1ac12de8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874075548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.rom_ctrl_stress_all.3874075548
Directory	/workspace/35.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2326243522
Short name	T51
Test name
Test status
Simulation time	168461353518 ps
CPU time	3315.61 seconds
Started	Apr 16 12:22:28 PM PDT 24
Finished	Apr 16 01:17:46 PM PDT 24
Peak memory	235740 kb
Host	smart-2a1e0d7e-5185-4805-97ed-81173fb30f99
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326243522 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2326243522
Directory	/workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.rom_ctrl_alert_test.3126635453
Short name	T343
Test name
Test status
Simulation time	940807501 ps
CPU time	14.21 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:24 PM PDT 24
Peak memory	211380 kb
Host	smart-6c1fbd3b-fe7e-466f-bdfa-1d8c1d586dfa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126635453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3126635453
Directory	/workspace/36.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.rom_ctrl_alert_test.3524235302
Short name	T528
Test name
Test status
Simulation time	6524283789 ps
CPU time	18.39 seconds
Started	Apr 16 12:22:45 PM PDT 24
Finished	Apr 16 12:23:09 PM PDT 24
Peak memory	211460 kb
Host	smart-716fd306-306b-45b5-9f19-5360daf14a4d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524235302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3524235302
Directory	/workspace/36.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2148700528
Short name	T490
Test name
Test status
Simulation time	30564905905 ps
CPU time	424.38 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:29:05 PM PDT 24
Peak memory	240444 kb
Host	smart-93ae6a53-68ad-49b7-bd9d-f928b9460b4d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148700528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_ corrupt_sig_fatal_chk.2148700528
Directory	/workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.367016772
Short name	T33
Test name
Test status
Simulation time	360838849085 ps
CPU time	822.5 seconds
Started	Apr 16 02:03:25 PM PDT 24
Finished	Apr 16 02:17:09 PM PDT 24
Peak memory	237972 kb
Host	smart-dfc233d6-6846-4791-94c7-c379a4b347ae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367016772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c orrupt_sig_fatal_chk.367016772
Directory	/workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/36.rom_ctrl_kmac_err_chk.224201321
Short name	T2
Test name
Test status
Simulation time	20458017899 ps
CPU time	47 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:22:52 PM PDT 24
Peak memory	216184 kb
Host	smart-1a72ee1f-af3c-4d4d-bd06-e09894dfe4cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224201321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.224201321
Directory	/workspace/36.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4013060757
Short name	T485
Test name
Test status
Simulation time	4449233168 ps
CPU time	44.74 seconds
Started	Apr 16 02:03:06 PM PDT 24
Finished	Apr 16 02:03:52 PM PDT 24
Peak memory	214444 kb
Host	smart-d7c2a880-f985-40c2-b481-b930fc30f788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013060757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4013060757
Directory	/workspace/36.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/36.rom_ctrl_max_throughput_chk.449511580
Short name	T399
Test name
Test status
Simulation time	182798560 ps
CPU time	9.87 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:22:58 PM PDT 24
Peak memory	212200 kb
Host	smart-f660eab9-a77b-4f8c-a510-000ac39c45c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=449511580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.449511580
Directory	/workspace/36.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/36.rom_ctrl_smoke.1210099115
Short name	T539
Test name
Test status
Simulation time	705096548 ps
CPU time	20.79 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:03:29 PM PDT 24
Peak memory	214952 kb
Host	smart-8af654e2-99f9-4531-970b-4f8cb1f0a4fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210099115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1210099115
Directory	/workspace/36.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.rom_ctrl_smoke.3339386211
Short name	T594
Test name
Test status
Simulation time	17383502496 ps
CPU time	81.65 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:23:14 PM PDT 24
Peak memory	216780 kb
Host	smart-66ec09e9-0be3-47fd-b02e-be9e865f131e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339386211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3339386211
Directory	/workspace/36.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.rom_ctrl_stress_all.3044255632
Short name	T128
Test name
Test status
Simulation time	9589850047 ps
CPU time	114.47 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:05:17 PM PDT 24
Peak memory	218568 kb
Host	smart-aa5f5148-2d47-4979-8be7-c620e239f8f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044255632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.rom_ctrl_stress_all.3044255632
Directory	/workspace/36.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.rom_ctrl_stress_all.3344922292
Short name	T314
Test name
Test status
Simulation time	3008080268 ps
CPU time	36.11 seconds
Started	Apr 16 12:21:51 PM PDT 24
Finished	Apr 16 12:22:31 PM PDT 24
Peak memory	213656 kb
Host	smart-77ca63ea-ede7-4c82-bbed-b5a5dcc60c7a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344922292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 36.rom_ctrl_stress_all.3344922292
Directory	/workspace/36.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.rom_ctrl_alert_test.1708910430
Short name	T54
Test name
Test status
Simulation time	3827837069 ps
CPU time	29.65 seconds
Started	Apr 16 12:21:58 PM PDT 24
Finished	Apr 16 12:22:30 PM PDT 24
Peak memory	212048 kb
Host	smart-5a7acfad-234d-43b8-9fba-445c20f90a8e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708910430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1708910430
Directory	/workspace/37.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.rom_ctrl_alert_test.612805978
Short name	T19
Test name
Test status
Simulation time	11060056447 ps
CPU time	28.53 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:03:39 PM PDT 24
Peak memory	212424 kb
Host	smart-64c5fa7f-6dfd-4a89-83d1-3184d0877968
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612805978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.612805978
Directory	/workspace/37.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1328761331
Short name	T625
Test name
Test status
Simulation time	15421358336 ps
CPU time	265.23 seconds
Started	Apr 16 02:03:17 PM PDT 24
Finished	Apr 16 02:07:44 PM PDT 24
Peak memory	229604 kb
Host	smart-0da544e4-3d8e-4567-ac85-22fe361acbf2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328761331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_ corrupt_sig_fatal_chk.1328761331
Directory	/workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.267760504
Short name	T315
Test name
Test status
Simulation time	83470225424 ps
CPU time	866.25 seconds
Started	Apr 16 12:23:16 PM PDT 24
Finished	Apr 16 12:37:44 PM PDT 24
Peak memory	225228 kb
Host	smart-8bad52d8-16cf-494a-bce2-336321cd0a1c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267760504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c orrupt_sig_fatal_chk.267760504
Directory	/workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1611745706
Short name	T468
Test name
Test status
Simulation time	675668374 ps
CPU time	19.46 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:29 PM PDT 24
Peak memory	214708 kb
Host	smart-696c6199-ff4f-41be-bb40-671223584ca6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611745706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1611745706
Directory	/workspace/37.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3180063495
Short name	T270
Test name
Test status
Simulation time	3944654190 ps
CPU time	25.45 seconds
Started	Apr 16 12:22:02 PM PDT 24
Finished	Apr 16 12:22:28 PM PDT 24
Peak memory	214716 kb
Host	smart-d050bd57-1aef-4ca4-9f4d-f9f3c6b4a0f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180063495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3180063495
Directory	/workspace/37.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3551634636
Short name	T103
Test name
Test status
Simulation time	2810869017 ps
CPU time	26.73 seconds
Started	Apr 16 02:03:35 PM PDT 24
Finished	Apr 16 02:04:03 PM PDT 24
Peak memory	211384 kb
Host	smart-b8a7871e-4666-427a-923e-0014f7a69fae
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3551634636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3551634636
Directory	/workspace/37.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/37.rom_ctrl_smoke.4075233123
Short name	T57
Test name
Test status
Simulation time	19177375858 ps
CPU time	53.73 seconds
Started	Apr 16 02:03:25 PM PDT 24
Finished	Apr 16 02:04:20 PM PDT 24
Peak memory	217236 kb
Host	smart-e06ad104-a77d-43b5-a019-7ebe39bace7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075233123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4075233123
Directory	/workspace/37.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.rom_ctrl_stress_all.1875598863
Short name	T525
Test name
Test status
Simulation time	1712523548 ps
CPU time	74.45 seconds
Started	Apr 16 12:22:05 PM PDT 24
Finished	Apr 16 12:23:21 PM PDT 24
Peak memory	220732 kb
Host	smart-4a2e0865-a907-42ff-8757-090727cbbbf9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875598863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.rom_ctrl_stress_all.1875598863
Directory	/workspace/37.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.rom_ctrl_stress_all.2818478889
Short name	T645
Test name
Test status
Simulation time	19046227132 ps
CPU time	39.75 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:03:52 PM PDT 24
Peak memory	213260 kb
Host	smart-ba4c4480-5505-4877-9bd3-e77c21dd4a99
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818478889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.rom_ctrl_stress_all.2818478889
Directory	/workspace/37.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.rom_ctrl_alert_test.3540458750
Short name	T662
Test name
Test status
Simulation time	7710345263 ps
CPU time	31.29 seconds
Started	Apr 16 02:03:23 PM PDT 24
Finished	Apr 16 02:03:55 PM PDT 24
Peak memory	212408 kb
Host	smart-28ade2db-ae77-4b34-bd48-69ced12eeffd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540458750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3540458750
Directory	/workspace/38.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.rom_ctrl_alert_test.608101847
Short name	T432
Test name
Test status
Simulation time	494038050 ps
CPU time	12.14 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:22:04 PM PDT 24
Peak memory	210576 kb
Host	smart-fbb90681-5846-4f58-92ee-c8b3ef45b06e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608101847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.608101847
Directory	/workspace/38.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1430600769
Short name	T545
Test name
Test status
Simulation time	9856698488 ps
CPU time	425.23 seconds
Started	Apr 16 02:03:15 PM PDT 24
Finished	Apr 16 02:10:22 PM PDT 24
Peak memory	239644 kb
Host	smart-903ca09b-091b-4db9-adf2-66cdf6671962
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430600769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_ corrupt_sig_fatal_chk.1430600769
Directory	/workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.881212720
Short name	T396
Test name
Test status
Simulation time	36382761878 ps
CPU time	338.31 seconds
Started	Apr 16 12:22:33 PM PDT 24
Finished	Apr 16 12:28:15 PM PDT 24
Peak memory	240260 kb
Host	smart-f64cad00-7878-46ed-acc6-398ed2f76190
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881212720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c orrupt_sig_fatal_chk.881212720
Directory	/workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2488483385
Short name	T507
Test name
Test status
Simulation time	4685614645 ps
CPU time	48.2 seconds
Started	Apr 16 02:03:26 PM PDT 24
Finished	Apr 16 02:04:15 PM PDT 24
Peak memory	215112 kb
Host	smart-a36ca58d-435d-4fb7-9634-503e7f90ab66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488483385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2488483385
Directory	/workspace/38.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3465727439
Short name	T258
Test name
Test status
Simulation time	1163876152 ps
CPU time	26.59 seconds
Started	Apr 16 12:22:34 PM PDT 24
Finished	Apr 16 12:23:05 PM PDT 24
Peak memory	214604 kb
Host	smart-1e6e4c51-6ef9-46c0-b62e-020a0a0fecf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465727439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3465727439
Directory	/workspace/38.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1776396400
Short name	T169
Test name
Test status
Simulation time	186716719 ps
CPU time	10.56 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	212272 kb
Host	smart-d2dc79e3-2f9c-45bf-bef1-a7e762f0798f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1776396400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1776396400
Directory	/workspace/38.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3547147337
Short name	T534
Test name
Test status
Simulation time	1431755215 ps
CPU time	10.11 seconds
Started	Apr 16 12:22:21 PM PDT 24
Finished	Apr 16 12:22:33 PM PDT 24
Peak memory	211484 kb
Host	smart-230074e2-51d3-4102-ad51-a194dd7d6c63
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3547147337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3547147337
Directory	/workspace/38.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/38.rom_ctrl_smoke.1439080416
Short name	T196
Test name
Test status
Simulation time	737193522 ps
CPU time	19.75 seconds
Started	Apr 16 12:22:29 PM PDT 24
Finished	Apr 16 12:22:51 PM PDT 24
Peak memory	216692 kb
Host	smart-3b6c2812-f7ef-480c-a7be-4e579795fd67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439080416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1439080416
Directory	/workspace/38.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.rom_ctrl_smoke.4121246860
Short name	T153
Test name
Test status
Simulation time	16445174052 ps
CPU time	49.37 seconds
Started	Apr 16 02:03:13 PM PDT 24
Finished	Apr 16 02:04:03 PM PDT 24
Peak memory	216628 kb
Host	smart-33a21a34-d2cd-403b-8209-bcf181f48376
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121246860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4121246860
Directory	/workspace/38.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.rom_ctrl_stress_all.390774058
Short name	T161
Test name
Test status
Simulation time	10420615744 ps
CPU time	24.76 seconds
Started	Apr 16 02:03:38 PM PDT 24
Finished	Apr 16 02:04:04 PM PDT 24
Peak memory	212712 kb
Host	smart-c87129e8-d6f9-4609-aa36-d7c770c4ddc6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390774058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.rom_ctrl_stress_all.390774058
Directory	/workspace/38.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.rom_ctrl_alert_test.1920711538
Short name	T70
Test name
Test status
Simulation time	3424302054 ps
CPU time	28.91 seconds
Started	Apr 16 12:22:45 PM PDT 24
Finished	Apr 16 12:23:20 PM PDT 24
Peak memory	211460 kb
Host	smart-a803f6c5-ccd1-4ef2-80fd-487cec470550
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920711538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1920711538
Directory	/workspace/39.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.rom_ctrl_alert_test.3943130881
Short name	T69
Test name
Test status
Simulation time	1852122188 ps
CPU time	12.74 seconds
Started	Apr 16 02:03:07 PM PDT 24
Finished	Apr 16 02:03:20 PM PDT 24
Peak memory	211404 kb
Host	smart-c5b94d8f-95d5-4022-b587-b1d6ee65295a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943130881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3943130881
Directory	/workspace/39.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2966930131
Short name	T236
Test name
Test status
Simulation time	10825704245 ps
CPU time	327.67 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:08:45 PM PDT 24
Peak memory	229188 kb
Host	smart-665d0d3a-ddeb-48e5-8064-65272785cc1f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966930131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_ corrupt_sig_fatal_chk.2966930131
Directory	/workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.45136016
Short name	T372
Test name
Test status
Simulation time	18568325051 ps
CPU time	377.93 seconds
Started	Apr 16 12:22:01 PM PDT 24
Finished	Apr 16 12:28:20 PM PDT 24
Peak memory	240840 kb
Host	smart-2ad1dada-8f89-4b32-bd5e-66b2efc90804
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45136016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_co rrupt_sig_fatal_chk.45136016
Directory	/workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2743687043
Short name	T288
Test name
Test status
Simulation time	1884196874 ps
CPU time	31.2 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:03:42 PM PDT 24
Peak memory	214784 kb
Host	smart-cf831485-324b-4ed1-9eb1-a890bb8237d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743687043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2743687043
Directory	/workspace/39.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/39.rom_ctrl_max_throughput_chk.78690635
Short name	T308
Test name
Test status
Simulation time	2068637193 ps
CPU time	13.8 seconds
Started	Apr 16 02:03:17 PM PDT 24
Finished	Apr 16 02:03:32 PM PDT 24
Peak memory	212604 kb
Host	smart-40511b33-1446-4b84-8f9f-b500aaca695a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=78690635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.78690635
Directory	/workspace/39.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/39.rom_ctrl_max_throughput_chk.956511606
Short name	T453
Test name
Test status
Simulation time	607587317 ps
CPU time	14.57 seconds
Started	Apr 16 12:23:16 PM PDT 24
Finished	Apr 16 12:23:32 PM PDT 24
Peak memory	211384 kb
Host	smart-54582dd7-ae99-41a5-9de2-a4411b5aecca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=956511606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.956511606
Directory	/workspace/39.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/39.rom_ctrl_smoke.3696541526
Short name	T455
Test name
Test status
Simulation time	10789775295 ps
CPU time	50.86 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:04:14 PM PDT 24
Peak memory	217212 kb
Host	smart-6656bb6e-f6ec-4a19-a511-05f5e231f06d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696541526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3696541526
Directory	/workspace/39.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.rom_ctrl_smoke.4260678672
Short name	T418
Test name
Test status
Simulation time	9918328196 ps
CPU time	57.19 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:23:05 PM PDT 24
Peak memory	218168 kb
Host	smart-ae3587d1-92fd-42fa-834b-72504cb34ab0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4260678672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4260678672
Directory	/workspace/39.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.rom_ctrl_stress_all.1031423257
Short name	T503
Test name
Test status
Simulation time	2915998307 ps
CPU time	74.01 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:04:24 PM PDT 24
Peak memory	218864 kb
Host	smart-c5499779-6b2e-4651-891a-37e1c7db4189
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031423257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_stress_all.1031423257
Directory	/workspace/39.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.rom_ctrl_stress_all.1743156348
Short name	T307
Test name
Test status
Simulation time	7905720295 ps
CPU time	30.24 seconds
Started	Apr 16 12:22:03 PM PDT 24
Finished	Apr 16 12:22:35 PM PDT 24
Peak memory	213956 kb
Host	smart-b9f68dac-326c-4263-99ed-55a9d7a1e5e1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743156348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_stress_all.1743156348
Directory	/workspace/39.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.rom_ctrl_alert_test.2221878864
Short name	T375
Test name
Test status
Simulation time	17183104121 ps
CPU time	33.04 seconds
Started	Apr 16 12:18:06 PM PDT 24
Finished	Apr 16 12:18:39 PM PDT 24
Peak memory	211620 kb
Host	smart-12a50247-2d4f-46d3-9e69-26ba6c09d718
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221878864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2221878864
Directory	/workspace/4.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.rom_ctrl_alert_test.4045209736
Short name	T484
Test name
Test status
Simulation time	6411384361 ps
CPU time	27.23 seconds
Started	Apr 16 02:02:40 PM PDT 24
Finished	Apr 16 02:03:09 PM PDT 24
Peak memory	211516 kb
Host	smart-a3dd7ab3-bdc3-41f4-8b46-a110b70565ed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045209736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4045209736
Directory	/workspace/4.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1927465513
Short name	T501
Test name
Test status
Simulation time	50610924700 ps
CPU time	363.62 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:28:09 PM PDT 24
Peak memory	237836 kb
Host	smart-372091e3-5fe5-4a69-af68-06676e0349f7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927465513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c orrupt_sig_fatal_chk.1927465513
Directory	/workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4073433958
Short name	T447
Test name
Test status
Simulation time	39839885478 ps
CPU time	288.05 seconds
Started	Apr 16 02:02:44 PM PDT 24
Finished	Apr 16 02:07:34 PM PDT 24
Peak memory	239476 kb
Host	smart-847a4947-9875-4506-a9da-1baad3124113
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073433958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c orrupt_sig_fatal_chk.4073433958
Directory	/workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2897365401
Short name	T300
Test name
Test status
Simulation time	24604898545 ps
CPU time	55.39 seconds
Started	Apr 16 02:02:53 PM PDT 24
Finished	Apr 16 02:03:49 PM PDT 24
Peak memory	215140 kb
Host	smart-65e9da10-1ca9-4822-a618-d56b51b74d91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897365401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2897365401
Directory	/workspace/4.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/4.rom_ctrl_kmac_err_chk.807832797
Short name	T593
Test name
Test status
Simulation time	6848915717 ps
CPU time	59.68 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:23:48 PM PDT 24
Peak memory	214728 kb
Host	smart-648685f0-d20c-4fc9-ad32-f28b5d87c6fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807832797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.807832797
Directory	/workspace/4.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3283189397
Short name	T402
Test name
Test status
Simulation time	646239841 ps
CPU time	9.98 seconds
Started	Apr 16 12:21:50 PM PDT 24
Finished	Apr 16 12:22:03 PM PDT 24
Peak memory	212064 kb
Host	smart-00359e6f-602c-4fa5-976b-d0b06744fcaa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3283189397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3283189397
Directory	/workspace/4.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3738708755
Short name	T175
Test name
Test status
Simulation time	8456685815 ps
CPU time	25.23 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	212000 kb
Host	smart-9ae48cd6-fc1f-436d-861b-92fbe86f9af0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3738708755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3738708755
Directory	/workspace/4.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/4.rom_ctrl_sec_cm.1895544199
Short name	T42
Test name
Test status
Simulation time	3959692514 ps
CPU time	242.03 seconds
Started	Apr 16 12:19:37 PM PDT 24
Finished	Apr 16 12:23:40 PM PDT 24
Peak memory	239044 kb
Host	smart-ef996ad6-d639-4f62-888c-6abf3581c66c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895544199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1895544199
Directory	/workspace/4.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.rom_ctrl_sec_cm.28981108
Short name	T36
Test name
Test status
Simulation time	3656211467 ps
CPU time	138.06 seconds
Started	Apr 16 02:02:53 PM PDT 24
Finished	Apr 16 02:05:12 PM PDT 24
Peak memory	239492 kb
Host	smart-bfc7e7e9-dfd9-4166-81be-ea28d81550ed
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.28981108
Directory	/workspace/4.rom_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.rom_ctrl_smoke.1539058586
Short name	T617
Test name
Test status
Simulation time	1992272017 ps
CPU time	36.41 seconds
Started	Apr 16 02:02:43 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	217752 kb
Host	smart-028e553b-fdd7-472f-88d9-5f9720b1c482
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539058586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1539058586
Directory	/workspace/4.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.rom_ctrl_smoke.544995581
Short name	T469
Test name
Test status
Simulation time	34808339650 ps
CPU time	69.45 seconds
Started	Apr 16 12:19:50 PM PDT 24
Finished	Apr 16 12:21:00 PM PDT 24
Peak memory	218432 kb
Host	smart-d8917183-ffb6-41db-81ac-269b0758e423
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=544995581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.544995581
Directory	/workspace/4.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.rom_ctrl_stress_all.3035855045
Short name	T289
Test name
Test status
Simulation time	8918155453 ps
CPU time	46.45 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:03:37 PM PDT 24
Peak memory	214316 kb
Host	smart-9b0780a5-8630-427e-8dd8-b4488cde8106
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035855045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.rom_ctrl_stress_all.3035855045
Directory	/workspace/4.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.rom_ctrl_stress_all.3043049778
Short name	T325
Test name
Test status
Simulation time	16567370741 ps
CPU time	91.66 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:23:37 PM PDT 24
Peak memory	221132 kb
Host	smart-a6a621ad-0d55-4de9-ab3b-a175e32a5b22
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043049778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.rom_ctrl_stress_all.3043049778
Directory	/workspace/4.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.rom_ctrl_alert_test.1233179777
Short name	T643
Test name
Test status
Simulation time	3607408797 ps
CPU time	29.1 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:03:52 PM PDT 24
Peak memory	212056 kb
Host	smart-f75a38e0-2e4e-487f-9258-84ce2d8d948c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233179777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1233179777
Directory	/workspace/40.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.rom_ctrl_alert_test.3822386416
Short name	T668
Test name
Test status
Simulation time	338826123 ps
CPU time	7.94 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:22:14 PM PDT 24
Peak memory	211204 kb
Host	smart-a5b80445-e294-4e24-a8eb-4ca6146c6649
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822386416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3822386416
Directory	/workspace/40.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2093876830
Short name	T483
Test name
Test status
Simulation time	31738497126 ps
CPU time	350.61 seconds
Started	Apr 16 02:03:11 PM PDT 24
Finished	Apr 16 02:09:03 PM PDT 24
Peak memory	237240 kb
Host	smart-ab0f0926-6e2f-4ac3-a9fe-c8a9081f3360
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093876830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_ corrupt_sig_fatal_chk.2093876830
Directory	/workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3209533451
Short name	T604
Test name
Test status
Simulation time	429209352202 ps
CPU time	397.05 seconds
Started	Apr 16 12:22:25 PM PDT 24
Finished	Apr 16 12:29:04 PM PDT 24
Peak memory	217648 kb
Host	smart-9f3e6388-4c25-455a-8b0b-d421dd2fd102
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209533451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_ corrupt_sig_fatal_chk.3209533451
Directory	/workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1885411438
Short name	T611
Test name
Test status
Simulation time	37346246127 ps
CPU time	58 seconds
Started	Apr 16 02:03:18 PM PDT 24
Finished	Apr 16 02:04:17 PM PDT 24
Peak memory	215024 kb
Host	smart-b9f5c7a5-719f-4dab-97eb-0312c33c0186
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885411438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1885411438
Directory	/workspace/40.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3613643784
Short name	T331
Test name
Test status
Simulation time	6756115328 ps
CPU time	56.95 seconds
Started	Apr 16 12:21:55 PM PDT 24
Finished	Apr 16 12:22:54 PM PDT 24
Peak memory	215416 kb
Host	smart-bc144457-a585-4e72-99f0-0227d402f725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613643784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3613643784
Directory	/workspace/40.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1891376930
Short name	T183
Test name
Test status
Simulation time	1172912738 ps
CPU time	10.39 seconds
Started	Apr 16 12:22:44 PM PDT 24
Finished	Apr 16 12:23:00 PM PDT 24
Peak memory	212648 kb
Host	smart-7627b767-9bb9-45cc-b41b-1844fd6093a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1891376930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1891376930
Directory	/workspace/40.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2458469924
Short name	T245
Test name
Test status
Simulation time	16824758816 ps
CPU time	32.17 seconds
Started	Apr 16 02:03:23 PM PDT 24
Finished	Apr 16 02:03:57 PM PDT 24
Peak memory	211860 kb
Host	smart-51453a12-3675-49ba-b97d-3449d7e5bd24
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2458469924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2458469924
Directory	/workspace/40.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/40.rom_ctrl_smoke.2344917988
Short name	T580
Test name
Test status
Simulation time	662008479 ps
CPU time	19.97 seconds
Started	Apr 16 02:03:12 PM PDT 24
Finished	Apr 16 02:03:33 PM PDT 24
Peak memory	217080 kb
Host	smart-c2d9570b-8af2-4308-9a4f-f83b1c934961
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344917988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2344917988
Directory	/workspace/40.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.rom_ctrl_smoke.858856592
Short name	T626
Test name
Test status
Simulation time	13832601823 ps
CPU time	39.2 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:22:47 PM PDT 24
Peak memory	217996 kb
Host	smart-2a426720-f468-4860-bc9a-c4b1fdfbeac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858856592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.858856592
Directory	/workspace/40.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.rom_ctrl_stress_all.49520476
Short name	T646
Test name
Test status
Simulation time	23729003373 ps
CPU time	72.8 seconds
Started	Apr 16 02:03:21 PM PDT 24
Finished	Apr 16 02:04:35 PM PDT 24
Peak memory	220732 kb
Host	smart-f4e0c302-ca32-43a9-9b6f-6a7ecf288604
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49520476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 40.rom_ctrl_stress_all.49520476
Directory	/workspace/40.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.rom_ctrl_stress_all.960023538
Short name	T567
Test name
Test status
Simulation time	22170538220 ps
CPU time	43.14 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:22:44 PM PDT 24
Peak memory	219420 kb
Host	smart-ab06d10b-c357-412b-b26c-55f72d3a7c51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960023538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.rom_ctrl_stress_all.960023538
Directory	/workspace/40.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.rom_ctrl_alert_test.2022145000
Short name	T635
Test name
Test status
Simulation time	1709055704 ps
CPU time	11.25 seconds
Started	Apr 16 12:22:00 PM PDT 24
Finished	Apr 16 12:22:13 PM PDT 24
Peak memory	211300 kb
Host	smart-8b0273e1-7f1d-4524-bf32-14004f12a01f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022145000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2022145000
Directory	/workspace/41.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.rom_ctrl_alert_test.3024347847
Short name	T628
Test name
Test status
Simulation time	8870984659 ps
CPU time	33.67 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:43 PM PDT 24
Peak memory	212412 kb
Host	smart-5cf64731-92ce-4553-b612-3c20c4eedfd7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024347847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3024347847
Directory	/workspace/41.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2772513330
Short name	T155
Test name
Test status
Simulation time	570635285936 ps
CPU time	646.64 seconds
Started	Apr 16 02:03:27 PM PDT 24
Finished	Apr 16 02:14:16 PM PDT 24
Peak memory	239016 kb
Host	smart-e67a3c38-439f-4603-aba2-c7c8cf96c10e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772513330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_ corrupt_sig_fatal_chk.2772513330
Directory	/workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.952001719
Short name	T336
Test name
Test status
Simulation time	210019142199 ps
CPU time	342.91 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:27:44 PM PDT 24
Peak memory	236720 kb
Host	smart-e67cdfc6-1776-48b7-bbde-b9f6a2a8298e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952001719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c orrupt_sig_fatal_chk.952001719
Directory	/workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/41.rom_ctrl_kmac_err_chk.242253453
Short name	T512
Test name
Test status
Simulation time	68797427568 ps
CPU time	62.13 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:23:08 PM PDT 24
Peak memory	213008 kb
Host	smart-7f9eef70-bd40-4c61-880d-dd97d7a2354c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242253453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.242253453
Directory	/workspace/41.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3981897979
Short name	T59
Test name
Test status
Simulation time	13278200646 ps
CPU time	38.16 seconds
Started	Apr 16 02:03:20 PM PDT 24
Finished	Apr 16 02:03:59 PM PDT 24
Peak memory	215124 kb
Host	smart-024c58ab-b1e3-44ad-ae55-6fd377d6ce5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981897979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3981897979
Directory	/workspace/41.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/41.rom_ctrl_max_throughput_chk.162336640
Short name	T616
Test name
Test status
Simulation time	1083937902 ps
CPU time	10.54 seconds
Started	Apr 16 12:22:08 PM PDT 24
Finished	Apr 16 12:22:20 PM PDT 24
Peak memory	212768 kb
Host	smart-088a08ac-3bb0-49bc-8fc1-e8142a1dfb94
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=162336640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.162336640
Directory	/workspace/41.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4191062240
Short name	T16
Test name
Test status
Simulation time	36159236980 ps
CPU time	31.28 seconds
Started	Apr 16 02:03:26 PM PDT 24
Finished	Apr 16 02:03:58 PM PDT 24
Peak memory	211880 kb
Host	smart-81c59532-4f06-48f4-b21b-9dbba97fbbcd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4191062240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4191062240
Directory	/workspace/41.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/41.rom_ctrl_smoke.1127263424
Short name	T477
Test name
Test status
Simulation time	5861233814 ps
CPU time	54.26 seconds
Started	Apr 16 12:22:10 PM PDT 24
Finished	Apr 16 12:23:06 PM PDT 24
Peak memory	213920 kb
Host	smart-1bbb5027-3563-4396-93ae-fd82f31c229e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1127263424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1127263424
Directory	/workspace/41.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.rom_ctrl_smoke.3503968010
Short name	T240
Test name
Test status
Simulation time	5130215166 ps
CPU time	47.28 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:56 PM PDT 24
Peak memory	215908 kb
Host	smart-6ff2058b-e54f-4b7e-9834-2e22e5b2816e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503968010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3503968010
Directory	/workspace/41.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.rom_ctrl_stress_all.3066755853
Short name	T424
Test name
Test status
Simulation time	17107136521 ps
CPU time	181.08 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:06:18 PM PDT 24
Peak memory	221476 kb
Host	smart-f7114804-d074-467e-a4ae-e203161b525f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066755853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.rom_ctrl_stress_all.3066755853
Directory	/workspace/41.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.rom_ctrl_alert_test.1717996457
Short name	T157
Test name
Test status
Simulation time	2689910394 ps
CPU time	23.92 seconds
Started	Apr 16 12:21:57 PM PDT 24
Finished	Apr 16 12:22:23 PM PDT 24
Peak memory	211972 kb
Host	smart-67c86623-2bfc-41a1-9a90-204ed708833a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717996457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1717996457
Directory	/workspace/42.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.rom_ctrl_alert_test.3697134392
Short name	T561
Test name
Test status
Simulation time	172549217 ps
CPU time	8.21 seconds
Started	Apr 16 02:03:30 PM PDT 24
Finished	Apr 16 02:03:41 PM PDT 24
Peak memory	211396 kb
Host	smart-5c621c86-b387-45ce-bc54-082f5454ceb5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697134392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3697134392
Directory	/workspace/42.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1847178343
Short name	T330
Test name
Test status
Simulation time	165124879654 ps
CPU time	649.44 seconds
Started	Apr 16 12:22:11 PM PDT 24
Finished	Apr 16 12:33:02 PM PDT 24
Peak memory	225600 kb
Host	smart-9fff7ea8-b056-4086-8eca-9d06fe27cbe4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847178343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_ corrupt_sig_fatal_chk.1847178343
Directory	/workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2685758375
Short name	T622
Test name
Test status
Simulation time	4219181547 ps
CPU time	46.73 seconds
Started	Apr 16 02:03:17 PM PDT 24
Finished	Apr 16 02:04:05 PM PDT 24
Peak memory	214832 kb
Host	smart-3c89044c-6bfd-48ea-ab1e-04163abb8332
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685758375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2685758375
Directory	/workspace/42.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/42.rom_ctrl_kmac_err_chk.632904785
Short name	T313
Test name
Test status
Simulation time	8445645696 ps
CPU time	69.04 seconds
Started	Apr 16 12:21:59 PM PDT 24
Finished	Apr 16 12:23:10 PM PDT 24
Peak memory	214868 kb
Host	smart-6a018ad7-130d-416e-8feb-470230d7ed4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632904785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.632904785
Directory	/workspace/42.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1540211763
Short name	T181
Test name
Test status
Simulation time	348807543 ps
CPU time	9.71 seconds
Started	Apr 16 02:03:18 PM PDT 24
Finished	Apr 16 02:03:29 PM PDT 24
Peak memory	212608 kb
Host	smart-8ea4f9d8-03eb-4478-beb7-b43cda1e686a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1540211763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1540211763
Directory	/workspace/42.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3478567620
Short name	T301
Test name
Test status
Simulation time	1032779512 ps
CPU time	16.1 seconds
Started	Apr 16 12:22:10 PM PDT 24
Finished	Apr 16 12:22:28 PM PDT 24
Peak memory	211156 kb
Host	smart-1df69a07-6416-40d0-a973-6b341ab82198
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3478567620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3478567620
Directory	/workspace/42.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/42.rom_ctrl_smoke.2264801816
Short name	T356
Test name
Test status
Simulation time	21039297271 ps
CPU time	59.17 seconds
Started	Apr 16 02:03:17 PM PDT 24
Finished	Apr 16 02:04:17 PM PDT 24
Peak memory	215832 kb
Host	smart-c001a1ec-44d7-4bb0-b824-d13d0e5f7657
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264801816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2264801816
Directory	/workspace/42.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.rom_ctrl_smoke.820777734
Short name	T445
Test name
Test status
Simulation time	1275198547 ps
CPU time	19.83 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:22:25 PM PDT 24
Peak memory	217236 kb
Host	smart-cb60731a-0a3f-4aa2-9129-5b952b434c3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820777734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.820777734
Directory	/workspace/42.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.rom_ctrl_stress_all.1373188513
Short name	T332
Test name
Test status
Simulation time	3024914934 ps
CPU time	19.08 seconds
Started	Apr 16 12:22:32 PM PDT 24
Finished	Apr 16 12:22:54 PM PDT 24
Peak memory	213936 kb
Host	smart-350ed9ce-5f22-48bd-adaf-f4e4b0f0c2da
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373188513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_stress_all.1373188513
Directory	/workspace/42.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.rom_ctrl_stress_all.3316150464
Short name	T609
Test name
Test status
Simulation time	2269724881 ps
CPU time	37.08 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:03:54 PM PDT 24
Peak memory	219460 kb
Host	smart-5759a022-7e6f-45c4-8380-60b5b8ed029e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316150464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_stress_all.3316150464
Directory	/workspace/42.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.rom_ctrl_alert_test.3771056855
Short name	T508
Test name
Test status
Simulation time	8694804467 ps
CPU time	17.3 seconds
Started	Apr 16 12:22:31 PM PDT 24
Finished	Apr 16 12:22:50 PM PDT 24
Peak memory	212224 kb
Host	smart-fb3a4fe5-396f-4f52-8018-60e3240e662b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771056855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3771056855
Directory	/workspace/43.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.rom_ctrl_alert_test.4233763637
Short name	T524
Test name
Test status
Simulation time	3528145882 ps
CPU time	29.62 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:03:40 PM PDT 24
Peak memory	212116 kb
Host	smart-d6927738-7fe7-43cb-aada-c8e603048078
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233763637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4233763637
Directory	/workspace/43.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1799561738
Short name	T122
Test name
Test status
Simulation time	36290064073 ps
CPU time	306.93 seconds
Started	Apr 16 02:03:19 PM PDT 24
Finished	Apr 16 02:08:26 PM PDT 24
Peak memory	237904 kb
Host	smart-166ca467-1532-4f4a-81b0-7e77381f0d53
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799561738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ corrupt_sig_fatal_chk.1799561738
Directory	/workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2558290526
Short name	T656
Test name
Test status
Simulation time	83704015368 ps
CPU time	813.84 seconds
Started	Apr 16 12:22:25 PM PDT 24
Finished	Apr 16 12:36:00 PM PDT 24
Peak memory	237572 kb
Host	smart-8aad8ea8-7580-4543-b539-7af4508787f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558290526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ corrupt_sig_fatal_chk.2558290526
Directory	/workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1876095567
Short name	T634
Test name
Test status
Simulation time	6547816941 ps
CPU time	60.68 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:04:23 PM PDT 24
Peak memory	215388 kb
Host	smart-def36c69-b4e7-48ba-9c3c-b175078a0694
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876095567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1876095567
Directory	/workspace/43.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2050447429
Short name	T431
Test name
Test status
Simulation time	4165493397 ps
CPU time	33.46 seconds
Started	Apr 16 12:22:10 PM PDT 24
Finished	Apr 16 12:22:45 PM PDT 24
Peak memory	211360 kb
Host	smart-d21387e7-4537-4f73-94a7-ceb5f2c241a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2050447429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2050447429
Directory	/workspace/43.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3670116409
Short name	T316
Test name
Test status
Simulation time	3451141301 ps
CPU time	29.62 seconds
Started	Apr 16 02:03:25 PM PDT 24
Finished	Apr 16 02:03:56 PM PDT 24
Peak memory	211456 kb
Host	smart-7a6b7a07-8121-465f-b657-6193fd7c3e8b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3670116409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3670116409
Directory	/workspace/43.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/43.rom_ctrl_smoke.1711541068
Short name	T500
Test name
Test status
Simulation time	2744743518 ps
CPU time	38.95 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:22:44 PM PDT 24
Peak memory	217236 kb
Host	smart-37d70145-6682-4a49-bfad-28ca78c6eb8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711541068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1711541068
Directory	/workspace/43.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.rom_ctrl_smoke.590567204
Short name	T223
Test name
Test status
Simulation time	60150872159 ps
CPU time	64.25 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:04:28 PM PDT 24
Peak memory	217388 kb
Host	smart-45369434-0c6b-4dc3-92eb-9352216bb857
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=590567204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.590567204
Directory	/workspace/43.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.rom_ctrl_stress_all.2552846000
Short name	T219
Test name
Test status
Simulation time	3377072594 ps
CPU time	36.31 seconds
Started	Apr 16 02:03:20 PM PDT 24
Finished	Apr 16 02:03:57 PM PDT 24
Peak memory	212592 kb
Host	smart-0279a7f5-889e-4e3b-9c29-e319a0be97f8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552846000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.rom_ctrl_stress_all.2552846000
Directory	/workspace/43.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.rom_ctrl_stress_all.3697553846
Short name	T405
Test name
Test status
Simulation time	48319165447 ps
CPU time	207.91 seconds
Started	Apr 16 12:22:59 PM PDT 24
Finished	Apr 16 12:26:30 PM PDT 24
Peak memory	222268 kb
Host	smart-50f54d70-93b3-4b90-84b1-b62ae315063d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697553846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.rom_ctrl_stress_all.3697553846
Directory	/workspace/43.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2331140965
Short name	T48
Test name
Test status
Simulation time	265358658650 ps
CPU time	1357.89 seconds
Started	Apr 16 02:03:10 PM PDT 24
Finished	Apr 16 02:25:49 PM PDT 24
Peak memory	244104 kb
Host	smart-0bc8bad8-c38d-4e4f-8018-367abb317550
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331140965 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2331140965
Directory	/workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.rom_ctrl_alert_test.1870438673
Short name	T172
Test name
Test status
Simulation time	4880277909 ps
CPU time	19.68 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:03:43 PM PDT 24
Peak memory	211448 kb
Host	smart-0cc1f772-5661-482f-bdfd-dc8df8baf23a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870438673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1870438673
Directory	/workspace/44.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.rom_ctrl_alert_test.99454670
Short name	T305
Test name
Test status
Simulation time	1646929748 ps
CPU time	7.79 seconds
Started	Apr 16 12:22:57 PM PDT 24
Finished	Apr 16 12:23:08 PM PDT 24
Peak memory	211364 kb
Host	smart-a7b36883-8e3c-40c5-8c7f-10faaca2de18
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99454670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.99454670
Directory	/workspace/44.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1697590499
Short name	T350
Test name
Test status
Simulation time	3583129029 ps
CPU time	118.72 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:24:06 PM PDT 24
Peak memory	228520 kb
Host	smart-ae1cd5a8-acad-4dd4-89c1-e79357b5bcbc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697590499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_ corrupt_sig_fatal_chk.1697590499
Directory	/workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2957712083
Short name	T328
Test name
Test status
Simulation time	231620377348 ps
CPU time	624.15 seconds
Started	Apr 16 02:03:29 PM PDT 24
Finished	Apr 16 02:13:56 PM PDT 24
Peak memory	240964 kb
Host	smart-94240b38-7818-4259-9c9c-19c4fb815a59
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957712083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_ corrupt_sig_fatal_chk.2957712083
Directory	/workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1177824558
Short name	T390
Test name
Test status
Simulation time	15793086159 ps
CPU time	63.67 seconds
Started	Apr 16 12:22:29 PM PDT 24
Finished	Apr 16 12:23:34 PM PDT 24
Peak memory	215028 kb
Host	smart-3b25db38-7417-433e-9caa-1d5f9f01372f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177824558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1177824558
Directory	/workspace/44.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2363652057
Short name	T427
Test name
Test status
Simulation time	34284093823 ps
CPU time	67.32 seconds
Started	Apr 16 02:03:34 PM PDT 24
Finished	Apr 16 02:04:43 PM PDT 24
Peak memory	215188 kb
Host	smart-459850da-051a-431e-b042-93c1da31f72e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363652057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2363652057
Directory	/workspace/44.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2799985759
Short name	T195
Test name
Test status
Simulation time	5530610804 ps
CPU time	15.61 seconds
Started	Apr 16 12:22:12 PM PDT 24
Finished	Apr 16 12:22:29 PM PDT 24
Peak memory	211808 kb
Host	smart-3c66d8e1-c8ab-41c3-b797-1343a1f8158f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2799985759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2799985759
Directory	/workspace/44.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/44.rom_ctrl_max_throughput_chk.848300353
Short name	T229
Test name
Test status
Simulation time	2916888898 ps
CPU time	27.55 seconds
Started	Apr 16 02:03:27 PM PDT 24
Finished	Apr 16 02:03:56 PM PDT 24
Peak memory	212480 kb
Host	smart-bf351b0d-4949-4b6b-bdcb-aa66ff97e6e6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=848300353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.848300353
Directory	/workspace/44.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/44.rom_ctrl_smoke.1148828853
Short name	T516
Test name
Test status
Simulation time	1495019437 ps
CPU time	20.38 seconds
Started	Apr 16 12:22:25 PM PDT 24
Finished	Apr 16 12:22:47 PM PDT 24
Peak memory	216200 kb
Host	smart-c5b27cce-6b2c-42d5-8180-3b86ede862fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148828853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1148828853
Directory	/workspace/44.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.rom_ctrl_smoke.2528903048
Short name	T555
Test name
Test status
Simulation time	3787197576 ps
CPU time	47.45 seconds
Started	Apr 16 02:03:23 PM PDT 24
Finished	Apr 16 02:04:12 PM PDT 24
Peak memory	217072 kb
Host	smart-64354ebc-2a3a-4138-bbf5-e65dcfb45fb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528903048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2528903048
Directory	/workspace/44.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.rom_ctrl_stress_all.2820247072
Short name	T450
Test name
Test status
Simulation time	694852946 ps
CPU time	17.01 seconds
Started	Apr 16 02:03:34 PM PDT 24
Finished	Apr 16 02:03:53 PM PDT 24
Peak memory	211220 kb
Host	smart-8890a762-37ad-4455-a96d-d615ad744196
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820247072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.rom_ctrl_stress_all.2820247072
Directory	/workspace/44.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.rom_ctrl_stress_all.4239743982
Short name	T126
Test name
Test status
Simulation time	6636421042 ps
CPU time	42.66 seconds
Started	Apr 16 12:22:35 PM PDT 24
Finished	Apr 16 12:23:23 PM PDT 24
Peak memory	219176 kb
Host	smart-9d731431-997f-4de4-9f45-4df8b870b122
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239743982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.rom_ctrl_stress_all.4239743982
Directory	/workspace/44.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.rom_ctrl_alert_test.2115379055
Short name	T273
Test name
Test status
Simulation time	15179645796 ps
CPU time	15.08 seconds
Started	Apr 16 12:23:23 PM PDT 24
Finished	Apr 16 12:23:39 PM PDT 24
Peak memory	211136 kb
Host	smart-71b05544-0069-41a6-80b9-6175e0bc744b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115379055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2115379055
Directory	/workspace/45.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.rom_ctrl_alert_test.2957952785
Short name	T243
Test name
Test status
Simulation time	609592897 ps
CPU time	12.81 seconds
Started	Apr 16 02:03:16 PM PDT 24
Finished	Apr 16 02:03:30 PM PDT 24
Peak memory	211364 kb
Host	smart-f3c56de1-8664-4ea0-81cc-8185136ce4cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957952785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2957952785
Directory	/workspace/45.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3922805356
Short name	T527
Test name
Test status
Simulation time	9259962344 ps
CPU time	304.02 seconds
Started	Apr 16 02:03:21 PM PDT 24
Finished	Apr 16 02:08:26 PM PDT 24
Peak memory	219604 kb
Host	smart-1ef739ed-c063-4dae-b215-acf8afc935e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922805356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_ corrupt_sig_fatal_chk.3922805356
Directory	/workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.401620290
Short name	T598
Test name
Test status
Simulation time	220989229631 ps
CPU time	400.74 seconds
Started	Apr 16 12:22:25 PM PDT 24
Finished	Apr 16 12:29:07 PM PDT 24
Peak memory	236736 kb
Host	smart-64bf4c57-5e91-419f-a61a-54eed0f38292
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401620290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c orrupt_sig_fatal_chk.401620290
Directory	/workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/45.rom_ctrl_kmac_err_chk.31501841
Short name	T493
Test name
Test status
Simulation time	12730863375 ps
CPU time	26.56 seconds
Started	Apr 16 12:22:11 PM PDT 24
Finished	Apr 16 12:22:38 PM PDT 24
Peak memory	214668 kb
Host	smart-0dce88a9-1a9b-443d-a664-7244fe6edd8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31501841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.31501841
Directory	/workspace/45.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/45.rom_ctrl_kmac_err_chk.95344218
Short name	T433
Test name
Test status
Simulation time	342493804 ps
CPU time	18.89 seconds
Started	Apr 16 02:03:15 PM PDT 24
Finished	Apr 16 02:03:35 PM PDT 24
Peak memory	215044 kb
Host	smart-176db2fc-30a0-4477-8fb8-de4f39144383
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95344218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.95344218
Directory	/workspace/45.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/45.rom_ctrl_max_throughput_chk.258915070
Short name	T18
Test name
Test status
Simulation time	358328271 ps
CPU time	10.46 seconds
Started	Apr 16 12:22:27 PM PDT 24
Finished	Apr 16 12:22:39 PM PDT 24
Peak memory	212544 kb
Host	smart-4bf6ef48-152c-4bfa-aa2e-10801e73e418
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=258915070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.258915070
Directory	/workspace/45.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4260251745
Short name	T298
Test name
Test status
Simulation time	179844494 ps
CPU time	10.52 seconds
Started	Apr 16 02:03:34 PM PDT 24
Finished	Apr 16 02:03:46 PM PDT 24
Peak memory	211408 kb
Host	smart-be63c154-a63a-46d7-b8eb-2ebf8e8eb671
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4260251745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4260251745
Directory	/workspace/45.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/45.rom_ctrl_smoke.1181022242
Short name	T254
Test name
Test status
Simulation time	7981939306 ps
CPU time	36.92 seconds
Started	Apr 16 12:22:37 PM PDT 24
Finished	Apr 16 12:23:19 PM PDT 24
Peak memory	218048 kb
Host	smart-e760a7d0-3fe6-495f-bed4-71a1def18ef3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181022242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1181022242
Directory	/workspace/45.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.rom_ctrl_smoke.2584795347
Short name	T286
Test name
Test status
Simulation time	12326473002 ps
CPU time	36.58 seconds
Started	Apr 16 02:03:24 PM PDT 24
Finished	Apr 16 02:04:02 PM PDT 24
Peak memory	217352 kb
Host	smart-b203870a-736f-479a-9987-d71c4f8521c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584795347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2584795347
Directory	/workspace/45.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.rom_ctrl_stress_all.1013666213
Short name	T549
Test name
Test status
Simulation time	5619201911 ps
CPU time	68.33 seconds
Started	Apr 16 12:22:04 PM PDT 24
Finished	Apr 16 12:23:14 PM PDT 24
Peak memory	219760 kb
Host	smart-2f661b0b-f43a-4ac0-93de-a28c179b8315
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013666213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.rom_ctrl_stress_all.1013666213
Directory	/workspace/45.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.rom_ctrl_stress_all.235740068
Short name	T322
Test name
Test status
Simulation time	567623849 ps
CPU time	15.42 seconds
Started	Apr 16 02:03:30 PM PDT 24
Finished	Apr 16 02:03:48 PM PDT 24
Peak memory	212512 kb
Host	smart-6c7c3ad9-18b8-4bdd-a4d5-d2ef6fec435a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235740068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.rom_ctrl_stress_all.235740068
Directory	/workspace/45.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3226833599
Short name	T52
Test name
Test status
Simulation time	66850192347 ps
CPU time	7600.11 seconds
Started	Apr 16 12:22:07 PM PDT 24
Finished	Apr 16 02:28:49 PM PDT 24
Peak memory	244020 kb
Host	smart-82a15ee5-4a9b-473c-838d-da1754ea65b0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226833599 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3226833599
Directory	/workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.rom_ctrl_alert_test.3791837371
Short name	T568
Test name
Test status
Simulation time	17563391107 ps
CPU time	32.66 seconds
Started	Apr 16 02:03:20 PM PDT 24
Finished	Apr 16 02:03:54 PM PDT 24
Peak memory	212332 kb
Host	smart-e7720986-2b51-4fda-9754-f0819d16bf1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791837371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3791837371
Directory	/workspace/46.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.rom_ctrl_alert_test.567539625
Short name	T354
Test name
Test status
Simulation time	11302862890 ps
CPU time	24.39 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:22:32 PM PDT 24
Peak memory	211388 kb
Host	smart-a821026f-44da-4980-9f6b-42be2daac937
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567539625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.567539625
Directory	/workspace/46.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2720229554
Short name	T608
Test name
Test status
Simulation time	48953550500 ps
CPU time	630.88 seconds
Started	Apr 16 12:23:25 PM PDT 24
Finished	Apr 16 12:34:02 PM PDT 24
Peak memory	238656 kb
Host	smart-09924cbf-0616-4533-ab4d-0c50c3da6ac1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720229554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_ corrupt_sig_fatal_chk.2720229554
Directory	/workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3056213799
Short name	T589
Test name
Test status
Simulation time	175145245649 ps
CPU time	501.98 seconds
Started	Apr 16 02:03:27 PM PDT 24
Finished	Apr 16 02:11:52 PM PDT 24
Peak memory	237668 kb
Host	smart-daf4ada5-f984-41d9-94e3-45656b809a9c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056213799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_ corrupt_sig_fatal_chk.3056213799
Directory	/workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3102012680
Short name	T422
Test name
Test status
Simulation time	2061125371 ps
CPU time	19.2 seconds
Started	Apr 16 02:03:26 PM PDT 24
Finished	Apr 16 02:03:46 PM PDT 24
Peak memory	214740 kb
Host	smart-e31cf9f0-e913-43d7-8fe1-9e36420d50eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102012680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3102012680
Directory	/workspace/46.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3272222957
Short name	T383
Test name
Test status
Simulation time	21681882507 ps
CPU time	52.04 seconds
Started	Apr 16 12:23:14 PM PDT 24
Finished	Apr 16 12:24:08 PM PDT 24
Peak memory	213724 kb
Host	smart-3ad932ca-65fd-4808-87b3-3ab5472eece0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272222957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3272222957
Directory	/workspace/46.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/46.rom_ctrl_max_throughput_chk.922522904
Short name	T363
Test name
Test status
Simulation time	15072783613 ps
CPU time	22.07 seconds
Started	Apr 16 02:03:32 PM PDT 24
Finished	Apr 16 02:03:56 PM PDT 24
Peak memory	212916 kb
Host	smart-411eb21d-11c0-46be-8448-876f1a2cd553
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=922522904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.922522904
Directory	/workspace/46.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/46.rom_ctrl_max_throughput_chk.99986080
Short name	T548
Test name
Test status
Simulation time	4074026893 ps
CPU time	33.92 seconds
Started	Apr 16 12:23:25 PM PDT 24
Finished	Apr 16 12:24:00 PM PDT 24
Peak memory	212224 kb
Host	smart-420f775e-1b65-41d5-8100-76978747ee3e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=99986080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.99986080
Directory	/workspace/46.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/46.rom_ctrl_smoke.2481138188
Short name	T665
Test name
Test status
Simulation time	16548608785 ps
CPU time	80.67 seconds
Started	Apr 16 02:03:22 PM PDT 24
Finished	Apr 16 02:04:44 PM PDT 24
Peak memory	215528 kb
Host	smart-637640e7-760c-4fb3-9a1e-8caaccab1702
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481138188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2481138188
Directory	/workspace/46.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.rom_ctrl_smoke.264629788
Short name	T610
Test name
Test status
Simulation time	12035551019 ps
CPU time	53.12 seconds
Started	Apr 16 12:22:06 PM PDT 24
Finished	Apr 16 12:23:01 PM PDT 24
Peak memory	218440 kb
Host	smart-1adf954e-b72b-4684-a1e1-f5ec6d0e12a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264629788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.264629788
Directory	/workspace/46.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.rom_ctrl_stress_all.132100419
Short name	T541
Test name
Test status
Simulation time	910425801 ps
CPU time	51.5 seconds
Started	Apr 16 12:23:14 PM PDT 24
Finished	Apr 16 12:24:08 PM PDT 24
Peak memory	217972 kb
Host	smart-eda9a89e-6cea-4513-aeec-a584545f8252
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132100419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.rom_ctrl_stress_all.132100419
Directory	/workspace/46.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.rom_ctrl_stress_all.2037091255
Short name	T584
Test name
Test status
Simulation time	3622711448 ps
CPU time	17.12 seconds
Started	Apr 16 02:03:34 PM PDT 24
Finished	Apr 16 02:03:54 PM PDT 24
Peak memory	212420 kb
Host	smart-77f61445-c8f1-4216-97d1-871df210e962
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037091255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.rom_ctrl_stress_all.2037091255
Directory	/workspace/46.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3488618043
Short name	T47
Test name
Test status
Simulation time	32619708883 ps
CPU time	1836.36 seconds
Started	Apr 16 02:03:43 PM PDT 24
Finished	Apr 16 02:34:21 PM PDT 24
Peak memory	230212 kb
Host	smart-428d5300-79ce-4ee6-bd6d-ec6181acfa9e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488618043 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3488618043
Directory	/workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3692668126
Short name	T105
Test name
Test status
Simulation time	56326512690 ps
CPU time	2014.94 seconds
Started	Apr 16 12:22:12 PM PDT 24
Finished	Apr 16 12:55:48 PM PDT 24
Peak memory	240396 kb
Host	smart-3ffd626d-efb5-4cad-bdaf-67bb1ad397b7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692668126 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3692668126
Directory	/workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.rom_ctrl_alert_test.101588670
Short name	T429
Test name
Test status
Simulation time	1609951070 ps
CPU time	13.07 seconds
Started	Apr 16 02:03:30 PM PDT 24
Finished	Apr 16 02:03:45 PM PDT 24
Peak memory	211388 kb
Host	smart-9174c678-76dd-442c-a675-a515407f7ead
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101588670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.101588670
Directory	/workspace/47.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.rom_ctrl_alert_test.1630335992
Short name	T367
Test name
Test status
Simulation time	1497528153 ps
CPU time	7.99 seconds
Started	Apr 16 12:22:14 PM PDT 24
Finished	Apr 16 12:22:23 PM PDT 24
Peak memory	211388 kb
Host	smart-396c4079-ed76-4443-86ee-1a6b329c719d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630335992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1630335992
Directory	/workspace/47.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1629510340
Short name	T371
Test name
Test status
Simulation time	69139548535 ps
CPU time	760.62 seconds
Started	Apr 16 02:03:26 PM PDT 24
Finished	Apr 16 02:16:09 PM PDT 24
Peak memory	238156 kb
Host	smart-377a1dc6-e9a7-446b-83fe-5087c618d856
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629510340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_ corrupt_sig_fatal_chk.1629510340
Directory	/workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1909877906
Short name	T581
Test name
Test status
Simulation time	7963998014 ps
CPU time	167.88 seconds
Started	Apr 16 12:22:12 PM PDT 24
Finished	Apr 16 12:25:01 PM PDT 24
Peak memory	240932 kb
Host	smart-f7a60495-b5e8-466c-9125-d8e6b1d96d4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909877906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_ corrupt_sig_fatal_chk.1909877906
Directory	/workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3031220513
Short name	T233
Test name
Test status
Simulation time	7677614019 ps
CPU time	62.15 seconds
Started	Apr 16 12:22:11 PM PDT 24
Finished	Apr 16 12:23:15 PM PDT 24
Peak memory	215224 kb
Host	smart-5a597e26-7500-49d0-9e3b-76ce676ab212
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031220513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3031220513
Directory	/workspace/47.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/47.rom_ctrl_kmac_err_chk.721110586
Short name	T200
Test name
Test status
Simulation time	4580676623 ps
CPU time	47.46 seconds
Started	Apr 16 02:03:27 PM PDT 24
Finished	Apr 16 02:04:16 PM PDT 24
Peak memory	215272 kb
Host	smart-833ec2ba-369c-416a-9728-3678a87e2bf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721110586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.721110586
Directory	/workspace/47.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1161065587
Short name	T275
Test name
Test status
Simulation time	187401581 ps
CPU time	10.2 seconds
Started	Apr 16 12:22:29 PM PDT 24
Finished	Apr 16 12:22:41 PM PDT 24
Peak memory	212456 kb
Host	smart-6a996f79-221f-4ebc-8cfa-e3282d5e34ce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1161065587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1161065587
Directory	/workspace/47.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/47.rom_ctrl_max_throughput_chk.313632189
Short name	T266
Test name
Test status
Simulation time	5912204945 ps
CPU time	28.35 seconds
Started	Apr 16 02:03:27 PM PDT 24
Finished	Apr 16 02:03:57 PM PDT 24
Peak memory	211960 kb
Host	smart-1a212021-af7b-416e-badd-ecf059e6ff89
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=313632189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.313632189
Directory	/workspace/47.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/47.rom_ctrl_smoke.1988802168
Short name	T359
Test name
Test status
Simulation time	2646400524 ps
CPU time	22.87 seconds
Started	Apr 16 12:23:25 PM PDT 24
Finished	Apr 16 12:23:49 PM PDT 24
Peak memory	216116 kb
Host	smart-3528e3f2-40dd-4d28-92e1-d8a3208675d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988802168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1988802168
Directory	/workspace/47.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.rom_ctrl_smoke.2719387529
Short name	T487
Test name
Test status
Simulation time	7722343099 ps
CPU time	62.32 seconds
Started	Apr 16 02:03:32 PM PDT 24
Finished	Apr 16 02:04:37 PM PDT 24
Peak memory	217744 kb
Host	smart-3e9e8007-3258-4689-86a1-38cc69208d0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719387529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2719387529
Directory	/workspace/47.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.rom_ctrl_stress_all.3391680535
Short name	T264
Test name
Test status
Simulation time	1717616717 ps
CPU time	34.02 seconds
Started	Apr 16 02:03:25 PM PDT 24
Finished	Apr 16 02:04:00 PM PDT 24
Peak memory	217940 kb
Host	smart-3768793a-5886-49ea-92f2-60cb93342f77
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391680535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.rom_ctrl_stress_all.3391680535
Directory	/workspace/47.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.rom_ctrl_stress_all.687348803
Short name	T146
Test name
Test status
Simulation time	7256886429 ps
CPU time	75.23 seconds
Started	Apr 16 12:22:46 PM PDT 24
Finished	Apr 16 12:24:07 PM PDT 24
Peak memory	215448 kb
Host	smart-e6fa542f-b2d2-460c-a28b-b2abb8990b9d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687348803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.rom_ctrl_stress_all.687348803
Directory	/workspace/47.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.330034368
Short name	T50
Test name
Test status
Simulation time	579089347958 ps
CPU time	3126.28 seconds
Started	Apr 16 02:03:28 PM PDT 24
Finished	Apr 16 02:55:37 PM PDT 24
Peak memory	252312 kb
Host	smart-6c1400eb-c938-4b89-9816-9d0875469354
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330034368 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.330034368
Directory	/workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.rom_ctrl_alert_test.2582823316
Short name	T633
Test name
Test status
Simulation time	9342774182 ps
CPU time	28.56 seconds
Started	Apr 16 02:03:25 PM PDT 24
Finished	Apr 16 02:03:54 PM PDT 24
Peak memory	211536 kb
Host	smart-13ac7461-ec4c-4598-8b7e-6332f2873aab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582823316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2582823316
Directory	/workspace/48.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.rom_ctrl_alert_test.83144753
Short name	T504
Test name
Test status
Simulation time	7895645442 ps
CPU time	20.34 seconds
Started	Apr 16 12:22:11 PM PDT 24
Finished	Apr 16 12:22:33 PM PDT 24
Peak memory	212236 kb
Host	smart-a38a2821-8381-41e5-bf4e-1a975ad602fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83144753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.83144753
Directory	/workspace/48.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2187858963
Short name	T360
Test name
Test status
Simulation time	334664263468 ps
CPU time	829.06 seconds
Started	Apr 16 02:03:30 PM PDT 24
Finished	Apr 16 02:17:22 PM PDT 24
Peak memory	239972 kb
Host	smart-a0d599a9-6fe7-4cd5-80ef-826e7eee56f1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187858963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_ corrupt_sig_fatal_chk.2187858963
Directory	/workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4133016912
Short name	T152
Test name
Test status
Simulation time	748149977036 ps
CPU time	797.38 seconds
Started	Apr 16 12:23:01 PM PDT 24
Finished	Apr 16 12:36:21 PM PDT 24
Peak memory	234340 kb
Host	smart-be4616a8-3f6e-40c9-b407-ebd8117a272c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133016912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_ corrupt_sig_fatal_chk.4133016912
Directory	/workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1616553419
Short name	T282
Test name
Test status
Simulation time	10887757122 ps
CPU time	35.94 seconds
Started	Apr 16 02:03:19 PM PDT 24
Finished	Apr 16 02:03:55 PM PDT 24
Peak memory	215112 kb
Host	smart-9968bc78-435e-4592-90b4-273e4db0670d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616553419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1616553419
Directory	/workspace/48.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4187251204
Short name	T271
Test name
Test status
Simulation time	12630136304 ps
CPU time	33.13 seconds
Started	Apr 16 12:22:14 PM PDT 24
Finished	Apr 16 12:22:48 PM PDT 24
Peak memory	215020 kb
Host	smart-abdb8ee7-9c7d-4182-b5c0-8646ef10f42c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187251204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4187251204
Directory	/workspace/48.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2823967605
Short name	T644
Test name
Test status
Simulation time	9751870638 ps
CPU time	33.85 seconds
Started	Apr 16 12:22:13 PM PDT 24
Finished	Apr 16 12:22:48 PM PDT 24
Peak memory	212488 kb
Host	smart-78158a26-0d9f-42b3-bfd6-f36e8ecee6fe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2823967605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2823967605
Directory	/workspace/48.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4209995926
Short name	T410
Test name
Test status
Simulation time	467502063 ps
CPU time	10.22 seconds
Started	Apr 16 02:03:27 PM PDT 24
Finished	Apr 16 02:03:40 PM PDT 24
Peak memory	212624 kb
Host	smart-2f649966-ba1a-4e48-a148-76865319367a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4209995926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4209995926
Directory	/workspace/48.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/48.rom_ctrl_smoke.180466567
Short name	T389
Test name
Test status
Simulation time	32832805572 ps
CPU time	36.91 seconds
Started	Apr 16 02:03:31 PM PDT 24
Finished	Apr 16 02:04:10 PM PDT 24
Peak memory	217660 kb
Host	smart-36486488-7349-48eb-ace8-e239c8ab1415
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180466567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.180466567
Directory	/workspace/48.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.rom_ctrl_smoke.283073642
Short name	T179
Test name
Test status
Simulation time	6132062691 ps
CPU time	33.01 seconds
Started	Apr 16 12:22:11 PM PDT 24
Finished	Apr 16 12:22:46 PM PDT 24
Peak memory	218788 kb
Host	smart-0dd63d3b-8af4-4b56-a910-660ef0056f20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283073642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.283073642
Directory	/workspace/48.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.rom_ctrl_stress_all.2335933366
Short name	T518
Test name
Test status
Simulation time	8021711640 ps
CPU time	118.08 seconds
Started	Apr 16 12:22:21 PM PDT 24
Finished	Apr 16 12:24:20 PM PDT 24
Peak memory	220524 kb
Host	smart-e227b5ab-1e96-476b-9e29-1e57998ebf29
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335933366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_stress_all.2335933366
Directory	/workspace/48.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.rom_ctrl_stress_all.2615924364
Short name	T486
Test name
Test status
Simulation time	4035770471 ps
CPU time	36.02 seconds
Started	Apr 16 02:03:24 PM PDT 24
Finished	Apr 16 02:04:01 PM PDT 24
Peak memory	212384 kb
Host	smart-c9a836d7-fd48-4b8f-bb7d-47428f370ec6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615924364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_stress_all.2615924364
Directory	/workspace/48.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.rom_ctrl_alert_test.204683554
Short name	T462
Test name
Test status
Simulation time	2349071862 ps
CPU time	15.87 seconds
Started	Apr 16 02:03:23 PM PDT 24
Finished	Apr 16 02:03:40 PM PDT 24
Peak memory	211396 kb
Host	smart-b7a19324-de93-4e30-ad7e-251698b659e5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204683554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.204683554
Directory	/workspace/49.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.rom_ctrl_alert_test.61108473
Short name	T435
Test name
Test status
Simulation time	3573705507 ps
CPU time	18.66 seconds
Started	Apr 16 12:22:12 PM PDT 24
Finished	Apr 16 12:22:32 PM PDT 24
Peak memory	211496 kb
Host	smart-3ab5f0f1-7232-4bfb-9a93-bd2a60752d4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61108473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.61108473
Directory	/workspace/49.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2248078823
Short name	T438
Test name
Test status
Simulation time	3162175500 ps
CPU time	232.8 seconds
Started	Apr 16 02:03:29 PM PDT 24
Finished	Apr 16 02:07:25 PM PDT 24
Peak memory	237012 kb
Host	smart-855c949a-7285-4362-be44-22ed34b3c17b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248078823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_ corrupt_sig_fatal_chk.2248078823
Directory	/workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.481541326
Short name	T613
Test name
Test status
Simulation time	142246585158 ps
CPU time	327.26 seconds
Started	Apr 16 12:22:10 PM PDT 24
Finished	Apr 16 12:27:39 PM PDT 24
Peak memory	215744 kb
Host	smart-a91dc70f-66cd-4b06-96cb-307d760fff51
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481541326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c orrupt_sig_fatal_chk.481541326
Directory	/workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1924876437
Short name	T187
Test name
Test status
Simulation time	15540951453 ps
CPU time	55.68 seconds
Started	Apr 16 12:22:13 PM PDT 24
Finished	Apr 16 12:23:10 PM PDT 24
Peak memory	215016 kb
Host	smart-c3da2cd4-0bb8-4cb3-89b5-f64dde9ef4bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924876437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1924876437
Directory	/workspace/49.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3857360827
Short name	T284
Test name
Test status
Simulation time	8572295690 ps
CPU time	32.89 seconds
Started	Apr 16 02:03:24 PM PDT 24
Finished	Apr 16 02:03:58 PM PDT 24
Peak memory	217700 kb
Host	smart-818f5ca1-21b1-4422-bfca-f45c4fd1ebde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857360827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3857360827
Directory	/workspace/49.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1347612813
Short name	T505
Test name
Test status
Simulation time	180720083 ps
CPU time	10.56 seconds
Started	Apr 16 02:03:30 PM PDT 24
Finished	Apr 16 02:03:43 PM PDT 24
Peak memory	212300 kb
Host	smart-8f4544ab-3acc-4939-af91-e592bc39a968
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1347612813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1347612813
Directory	/workspace/49.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/49.rom_ctrl_max_throughput_chk.779938102
Short name	T648
Test name
Test status
Simulation time	4388074326 ps
CPU time	34.17 seconds
Started	Apr 16 12:22:30 PM PDT 24
Finished	Apr 16 12:23:06 PM PDT 24
Peak memory	211308 kb
Host	smart-2ddfdd9e-e532-4479-b1fe-b4c704b84894
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=779938102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.779938102
Directory	/workspace/49.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/49.rom_ctrl_smoke.2674235869
Short name	T135
Test name
Test status
Simulation time	10462656575 ps
CPU time	62.24 seconds
Started	Apr 16 12:22:09 PM PDT 24
Finished	Apr 16 12:23:12 PM PDT 24
Peak memory	218388 kb
Host	smart-d65d0946-40f2-4d93-bc6c-e8baa3a1bc81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674235869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2674235869
Directory	/workspace/49.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.rom_ctrl_smoke.4248560502
Short name	T246
Test name
Test status
Simulation time	2588017382 ps
CPU time	35.25 seconds
Started	Apr 16 02:03:35 PM PDT 24
Finished	Apr 16 02:04:12 PM PDT 24
Peak memory	216928 kb
Host	smart-4f440ee0-f3c4-4fd0-bd30-ab174780ff30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248560502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4248560502
Directory	/workspace/49.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.rom_ctrl_stress_all.2739960223
Short name	T425
Test name
Test status
Simulation time	11066946939 ps
CPU time	63.67 seconds
Started	Apr 16 02:03:21 PM PDT 24
Finished	Apr 16 02:04:25 PM PDT 24
Peak memory	218660 kb
Host	smart-be421085-e8bf-449e-83ee-8b771c3707fe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739960223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.rom_ctrl_stress_all.2739960223
Directory	/workspace/49.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.rom_ctrl_stress_all.2868072472
Short name	T333
Test name
Test status
Simulation time	23300647021 ps
CPU time	54.03 seconds
Started	Apr 16 12:22:20 PM PDT 24
Finished	Apr 16 12:23:15 PM PDT 24
Peak memory	217452 kb
Host	smart-d0f1d20f-82a3-446d-91d9-91e59b4f6a52
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868072472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.rom_ctrl_stress_all.2868072472
Directory	/workspace/49.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3445368321
Short name	T21
Test name
Test status
Simulation time	22368140930 ps
CPU time	1535.89 seconds
Started	Apr 16 12:22:29 PM PDT 24
Finished	Apr 16 12:48:07 PM PDT 24
Peak memory	235772 kb
Host	smart-79b43f64-d123-4639-9900-88b56b9f591a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445368321 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3445368321
Directory	/workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.rom_ctrl_alert_test.1583515306
Short name	T281
Test name
Test status
Simulation time	691714068 ps
CPU time	12.94 seconds
Started	Apr 16 02:02:42 PM PDT 24
Finished	Apr 16 02:02:57 PM PDT 24
Peak memory	211396 kb
Host	smart-6d1b39f2-bd60-4777-922c-b8c4a442447d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583515306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1583515306
Directory	/workspace/5.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.rom_ctrl_alert_test.225413901
Short name	T351
Test name
Test status
Simulation time	1509390561 ps
CPU time	13.29 seconds
Started	Apr 16 12:21:12 PM PDT 24
Finished	Apr 16 12:21:27 PM PDT 24
Peak memory	210944 kb
Host	smart-810b1100-8b24-4966-a645-df1a4591a697
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225413901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.225413901
Directory	/workspace/5.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2305677789
Short name	T467
Test name
Test status
Simulation time	15998529328 ps
CPU time	301.28 seconds
Started	Apr 16 12:23:00 PM PDT 24
Finished	Apr 16 12:28:04 PM PDT 24
Peak memory	240468 kb
Host	smart-7ccbdb4c-3762-4e95-8152-367d46bf2c35
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305677789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c orrupt_sig_fatal_chk.2305677789
Directory	/workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3220949307
Short name	T392
Test name
Test status
Simulation time	38733700836 ps
CPU time	330.39 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:08:20 PM PDT 24
Peak memory	240884 kb
Host	smart-75ed081f-27a8-4864-b50a-45894152631d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220949307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c orrupt_sig_fatal_chk.3220949307
Directory	/workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1636629940
Short name	T201
Test name
Test status
Simulation time	10361196460 ps
CPU time	48.64 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:38 PM PDT 24
Peak memory	215556 kb
Host	smart-b9e8e728-1f25-4a20-b737-25ea1ad6eba6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636629940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1636629940
Directory	/workspace/5.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3493129061
Short name	T448
Test name
Test status
Simulation time	3180099388 ps
CPU time	33.6 seconds
Started	Apr 16 12:21:13 PM PDT 24
Finished	Apr 16 12:21:48 PM PDT 24
Peak memory	214600 kb
Host	smart-f0e37d97-8063-40fb-9ac1-e622b17eb563
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493129061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3493129061
Directory	/workspace/5.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3012098976
Short name	T642
Test name
Test status
Simulation time	6187805630 ps
CPU time	19.68 seconds
Started	Apr 16 12:22:47 PM PDT 24
Finished	Apr 16 12:23:11 PM PDT 24
Peak memory	211724 kb
Host	smart-d709935e-bd46-4b0b-9e26-0eb79a8a245d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3012098976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3012098976
Directory	/workspace/5.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4051533290
Short name	T409
Test name
Test status
Simulation time	18018188821 ps
CPU time	32.03 seconds
Started	Apr 16 02:02:47 PM PDT 24
Finished	Apr 16 02:03:19 PM PDT 24
Peak memory	212988 kb
Host	smart-434ce622-8d52-4cf0-b6b6-0d8ef4b76f36
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4051533290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4051533290
Directory	/workspace/5.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/5.rom_ctrl_smoke.2796047966
Short name	T394
Test name
Test status
Simulation time	25636587367 ps
CPU time	57.03 seconds
Started	Apr 16 12:22:38 PM PDT 24
Finished	Apr 16 12:23:41 PM PDT 24
Peak memory	217368 kb
Host	smart-d63057cb-3cd6-4b19-9203-ed3089380bfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796047966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2796047966
Directory	/workspace/5.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.rom_ctrl_smoke.3093742829
Short name	T385
Test name
Test status
Simulation time	5551306672 ps
CPU time	52.51 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:42 PM PDT 24
Peak memory	216972 kb
Host	smart-feec703c-6007-4a51-9555-f4483d63be5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093742829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3093742829
Directory	/workspace/5.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.rom_ctrl_stress_all.1978441486
Short name	T365
Test name
Test status
Simulation time	6993042957 ps
CPU time	70.88 seconds
Started	Apr 16 12:20:18 PM PDT 24
Finished	Apr 16 12:21:30 PM PDT 24
Peak memory	220256 kb
Host	smart-bb336488-a4d8-4a6c-9d5d-5559d645f076
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978441486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.rom_ctrl_stress_all.1978441486
Directory	/workspace/5.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.rom_ctrl_stress_all.3129335278
Short name	T230
Test name
Test status
Simulation time	14096029949 ps
CPU time	152.71 seconds
Started	Apr 16 02:02:42 PM PDT 24
Finished	Apr 16 02:05:16 PM PDT 24
Peak memory	220812 kb
Host	smart-dc2ad774-575c-4dc3-9f7a-13f458db0433
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129335278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.rom_ctrl_stress_all.3129335278
Directory	/workspace/5.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2997920337
Short name	T104
Test name
Test status
Simulation time	167428405363 ps
CPU time	1432.83 seconds
Started	Apr 16 02:02:43 PM PDT 24
Finished	Apr 16 02:26:38 PM PDT 24
Peak memory	236700 kb
Host	smart-d982b11a-8a1d-4c2a-8c98-5cfaeabf559c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997920337 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2997920337
Directory	/workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.rom_ctrl_alert_test.1202329302
Short name	T647
Test name
Test status
Simulation time	1104047319 ps
CPU time	15.07 seconds
Started	Apr 16 12:22:42 PM PDT 24
Finished	Apr 16 12:23:03 PM PDT 24
Peak memory	210448 kb
Host	smart-48a88110-efe7-45cc-afef-1f967fb0b7b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202329302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1202329302
Directory	/workspace/6.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.rom_ctrl_alert_test.3196544253
Short name	T420
Test name
Test status
Simulation time	13007407692 ps
CPU time	27.69 seconds
Started	Apr 16 02:03:08 PM PDT 24
Finished	Apr 16 02:03:36 PM PDT 24
Peak memory	211388 kb
Host	smart-704419fe-a9fd-40ff-a907-697d0cf0aad6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196544253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3196544253
Directory	/workspace/6.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3208163516
Short name	T205
Test name
Test status
Simulation time	18296923826 ps
CPU time	272.68 seconds
Started	Apr 16 12:21:41 PM PDT 24
Finished	Apr 16 12:26:15 PM PDT 24
Peak memory	224996 kb
Host	smart-e3525023-a9cb-401e-8733-09a858119b86
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208163516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c orrupt_sig_fatal_chk.3208163516
Directory	/workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.620845703
Short name	T562
Test name
Test status
Simulation time	73169203384 ps
CPU time	437.56 seconds
Started	Apr 16 02:02:42 PM PDT 24
Finished	Apr 16 02:10:01 PM PDT 24
Peak memory	237960 kb
Host	smart-4ac2016a-cfb6-4cf2-921e-e85317e31dbf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620845703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co rrupt_sig_fatal_chk.620845703
Directory	/workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1349839989
Short name	T579
Test name
Test status
Simulation time	14551712100 ps
CPU time	45.25 seconds
Started	Apr 16 12:21:49 PM PDT 24
Finished	Apr 16 12:22:37 PM PDT 24
Peak memory	214956 kb
Host	smart-f1c8d849-0f29-4c1f-860c-623a05c07daa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349839989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1349839989
Directory	/workspace/6.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1928904691
Short name	T599
Test name
Test status
Simulation time	342522652 ps
CPU time	19.62 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:03:30 PM PDT 24
Peak memory	214924 kb
Host	smart-ad7c6416-091b-4f2b-8559-e7988f60ae2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928904691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1928904691
Directory	/workspace/6.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2816567726
Short name	T412
Test name
Test status
Simulation time	473182269 ps
CPU time	10.08 seconds
Started	Apr 16 12:22:40 PM PDT 24
Finished	Apr 16 12:22:56 PM PDT 24
Peak memory	210312 kb
Host	smart-b81c1e62-0eec-410a-9f5b-b92e0b2da889
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2816567726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2816567726
Directory	/workspace/6.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4014670477
Short name	T632
Test name
Test status
Simulation time	24750325693 ps
CPU time	32.87 seconds
Started	Apr 16 02:03:09 PM PDT 24
Finished	Apr 16 02:03:43 PM PDT 24
Peak memory	211920 kb
Host	smart-987e58a1-f055-43ae-928a-47d27ac4e2ea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4014670477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4014670477
Directory	/workspace/6.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/6.rom_ctrl_smoke.996531737
Short name	T259
Test name
Test status
Simulation time	5257624935 ps
CPU time	50.91 seconds
Started	Apr 16 02:02:51 PM PDT 24
Finished	Apr 16 02:03:43 PM PDT 24
Peak memory	216004 kb
Host	smart-50bbdea4-fee1-4c0e-884c-0e1968186e81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996531737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.996531737
Directory	/workspace/6.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.rom_ctrl_stress_all.1629578373
Short name	T400
Test name
Test status
Simulation time	10448110648 ps
CPU time	48.01 seconds
Started	Apr 16 12:21:38 PM PDT 24
Finished	Apr 16 12:22:27 PM PDT 24
Peak memory	219240 kb
Host	smart-0633af58-4b6e-4d4e-8d21-79c8097e58ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629578373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_stress_all.1629578373
Directory	/workspace/6.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.rom_ctrl_stress_all.3764237045
Short name	T180
Test name
Test status
Simulation time	15139545044 ps
CPU time	134.31 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:05:04 PM PDT 24
Peak memory	220152 kb
Host	smart-5fc9fc38-fa32-4a16-a474-d5ad3f5d3287
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764237045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_stress_all.3764237045
Directory	/workspace/6.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.rom_ctrl_alert_test.201349376
Short name	T538
Test name
Test status
Simulation time	3298140244 ps
CPU time	13.92 seconds
Started	Apr 16 02:02:44 PM PDT 24
Finished	Apr 16 02:03:00 PM PDT 24
Peak memory	211456 kb
Host	smart-15c530cb-396c-4184-b351-23b7654f8760
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201349376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.201349376
Directory	/workspace/7.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.rom_ctrl_alert_test.4236317564
Short name	T398
Test name
Test status
Simulation time	2631679454 ps
CPU time	22.03 seconds
Started	Apr 16 12:21:43 PM PDT 24
Finished	Apr 16 12:22:08 PM PDT 24
Peak memory	210112 kb
Host	smart-86bd04d8-619d-4fa6-9395-963236f44dcf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236317564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4236317564
Directory	/workspace/7.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3207572620
Short name	T294
Test name
Test status
Simulation time	537947999020 ps
CPU time	500.46 seconds
Started	Apr 16 02:02:44 PM PDT 24
Finished	Apr 16 02:11:06 PM PDT 24
Peak memory	238052 kb
Host	smart-2d5a689e-4a93-48a2-9bbe-0ab041e112be
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207572620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c orrupt_sig_fatal_chk.3207572620
Directory	/workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4044058317
Short name	T442
Test name
Test status
Simulation time	90851052153 ps
CPU time	629.67 seconds
Started	Apr 16 12:21:43 PM PDT 24
Finished	Apr 16 12:32:16 PM PDT 24
Peak memory	240372 kb
Host	smart-0efc5e30-b54d-427c-978f-6d6369c232ca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044058317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c orrupt_sig_fatal_chk.4044058317
Directory	/workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/7.rom_ctrl_kmac_err_chk.159855783
Short name	T423
Test name
Test status
Simulation time	23715829520 ps
CPU time	53.04 seconds
Started	Apr 16 12:21:41 PM PDT 24
Finished	Apr 16 12:22:36 PM PDT 24
Peak memory	213388 kb
Host	smart-c97123ba-5899-41a5-ac71-34764193e59e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159855783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.159855783
Directory	/workspace/7.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1753349231
Short name	T167
Test name
Test status
Simulation time	5908439590 ps
CPU time	52.88 seconds
Started	Apr 16 02:02:54 PM PDT 24
Finished	Apr 16 02:03:47 PM PDT 24
Peak memory	215680 kb
Host	smart-0f8bf325-9b2b-4f1e-931e-a7949b797536
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753349231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1753349231
Directory	/workspace/7.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1620573680
Short name	T577
Test name
Test status
Simulation time	15383412142 ps
CPU time	32.47 seconds
Started	Apr 16 12:21:44 PM PDT 24
Finished	Apr 16 12:22:19 PM PDT 24
Peak memory	211500 kb
Host	smart-f220b5bc-424b-42e4-8a11-ce9c26b4f5de
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1620573680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1620573680
Directory	/workspace/7.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2310526385
Short name	T213
Test name
Test status
Simulation time	44393716063 ps
CPU time	28.51 seconds
Started	Apr 16 02:02:52 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	211348 kb
Host	smart-af1fc227-113a-4c7f-80a8-a0a151c20722
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2310526385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2310526385
Directory	/workspace/7.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/7.rom_ctrl_smoke.1864050286
Short name	T244
Test name
Test status
Simulation time	22253134072 ps
CPU time	53.91 seconds
Started	Apr 16 12:20:22 PM PDT 24
Finished	Apr 16 12:21:16 PM PDT 24
Peak memory	217724 kb
Host	smart-547f3a4a-5ed3-4d0f-afc4-85e33e8b9ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864050286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1864050286
Directory	/workspace/7.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.rom_ctrl_smoke.2645753643
Short name	T147
Test name
Test status
Simulation time	12707288046 ps
CPU time	31.14 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	218292 kb
Host	smart-8e7209b2-0f80-43fc-9fff-ac0909a78ac3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645753643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2645753643
Directory	/workspace/7.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.rom_ctrl_stress_all.1101448321
Short name	T132
Test name
Test status
Simulation time	47011724784 ps
CPU time	99.44 seconds
Started	Apr 16 12:20:27 PM PDT 24
Finished	Apr 16 12:22:07 PM PDT 24
Peak memory	220148 kb
Host	smart-3f65b876-0d6b-4c77-83f0-f167e9efb804
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101448321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.rom_ctrl_stress_all.1101448321
Directory	/workspace/7.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.rom_ctrl_stress_all.3934636114
Short name	T574
Test name
Test status
Simulation time	10005037457 ps
CPU time	89.78 seconds
Started	Apr 16 02:02:57 PM PDT 24
Finished	Apr 16 02:04:28 PM PDT 24
Peak memory	219412 kb
Host	smart-afbbcc95-91a7-416b-887b-fb61e4ab099c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934636114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.rom_ctrl_stress_all.3934636114
Directory	/workspace/7.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2237862579
Short name	T49
Test name
Test status
Simulation time	59724053340 ps
CPU time	6567.34 seconds
Started	Apr 16 02:03:02 PM PDT 24
Finished	Apr 16 03:52:30 PM PDT 24
Peak memory	238332 kb
Host	smart-e14928b5-ece7-4b27-be5b-414f9ebe6fb7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237862579 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2237862579
Directory	/workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.rom_ctrl_alert_test.1317163261
Short name	T290
Test name
Test status
Simulation time	590786865 ps
CPU time	8.19 seconds
Started	Apr 16 12:20:42 PM PDT 24
Finished	Apr 16 12:20:51 PM PDT 24
Peak memory	211396 kb
Host	smart-c2284e15-0852-40bd-81c2-d1250405fe6a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317163261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1317163261
Directory	/workspace/8.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.rom_ctrl_alert_test.1551619556
Short name	T570
Test name
Test status
Simulation time	3962074591 ps
CPU time	33.07 seconds
Started	Apr 16 02:02:48 PM PDT 24
Finished	Apr 16 02:03:22 PM PDT 24
Peak memory	212016 kb
Host	smart-e92d8cb5-d513-4f1e-ac0d-8c9815339182
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551619556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1551619556
Directory	/workspace/8.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1957939753
Short name	T377
Test name
Test status
Simulation time	27787653849 ps
CPU time	336.47 seconds
Started	Apr 16 12:20:47 PM PDT 24
Finished	Apr 16 12:26:24 PM PDT 24
Peak memory	229232 kb
Host	smart-144d517f-f53e-4d47-85ff-9afebeb835f7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957939753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c orrupt_sig_fatal_chk.1957939753
Directory	/workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.282403863
Short name	T523
Test name
Test status
Simulation time	3321456452 ps
CPU time	165.63 seconds
Started	Apr 16 02:02:51 PM PDT 24
Finished	Apr 16 02:05:38 PM PDT 24
Peak memory	219648 kb
Host	smart-c9ff1f8b-0c62-425b-a0c8-3b0ab2ee16d3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282403863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co rrupt_sig_fatal_chk.282403863
Directory	/workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2593915011
Short name	T31
Test name
Test status
Simulation time	5239526865 ps
CPU time	28.64 seconds
Started	Apr 16 02:02:47 PM PDT 24
Finished	Apr 16 02:03:17 PM PDT 24
Peak memory	215040 kb
Host	smart-fce6a1d3-262c-4a43-8b03-f8646d73e44a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593915011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2593915011
Directory	/workspace/8.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2986160225
Short name	T458
Test name
Test status
Simulation time	675952921 ps
CPU time	23.22 seconds
Started	Apr 16 12:22:48 PM PDT 24
Finished	Apr 16 12:23:16 PM PDT 24
Peak memory	214260 kb
Host	smart-d414fb02-9a92-40f4-9d60-8ff6ee7efa7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986160225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2986160225
Directory	/workspace/8.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3114244581
Short name	T639
Test name
Test status
Simulation time	3207747708 ps
CPU time	19.48 seconds
Started	Apr 16 02:02:52 PM PDT 24
Finished	Apr 16 02:03:12 PM PDT 24
Peak memory	211720 kb
Host	smart-dcc6a315-887c-44d0-8c84-f244f97bace4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3114244581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3114244581
Directory	/workspace/8.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3257319679
Short name	T602
Test name
Test status
Simulation time	18030279874 ps
CPU time	31.14 seconds
Started	Apr 16 12:20:34 PM PDT 24
Finished	Apr 16 12:21:06 PM PDT 24
Peak memory	211820 kb
Host	smart-0f187fb7-5fd3-4f17-b6b5-bb87651aefce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3257319679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3257319679
Directory	/workspace/8.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/8.rom_ctrl_smoke.1299002237
Short name	T514
Test name
Test status
Simulation time	17057094672 ps
CPU time	44.99 seconds
Started	Apr 16 02:02:42 PM PDT 24
Finished	Apr 16 02:03:29 PM PDT 24
Peak memory	217844 kb
Host	smart-08f2e127-dfc3-4c1b-9af0-57937d13a675
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299002237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1299002237
Directory	/workspace/8.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.rom_ctrl_smoke.1423709700
Short name	T133
Test name
Test status
Simulation time	5456599547 ps
CPU time	59.25 seconds
Started	Apr 16 12:21:45 PM PDT 24
Finished	Apr 16 12:22:47 PM PDT 24
Peak memory	213480 kb
Host	smart-d3d2f9ff-88dd-4379-b046-da4493cc9b33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423709700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1423709700
Directory	/workspace/8.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.rom_ctrl_stress_all.245553098
Short name	T174
Test name
Test status
Simulation time	4917382698 ps
CPU time	73.96 seconds
Started	Apr 16 12:21:41 PM PDT 24
Finished	Apr 16 12:22:57 PM PDT 24
Peak memory	214304 kb
Host	smart-76e5d986-a0c2-4af0-978c-d8ef7b21cdc6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245553098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.rom_ctrl_stress_all.245553098
Directory	/workspace/8.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.rom_ctrl_stress_all.4111782835
Short name	T127
Test name
Test status
Simulation time	32190473783 ps
CPU time	238.06 seconds
Started	Apr 16 02:02:44 PM PDT 24
Finished	Apr 16 02:06:44 PM PDT 24
Peak memory	222248 kb
Host	smart-ecd077e0-c2e0-4b7a-b446-4e7c983f49b0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111782835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.rom_ctrl_stress_all.4111782835
Directory	/workspace/8.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4073907592
Short name	T470
Test name
Test status
Simulation time	13615990605 ps
CPU time	398.39 seconds
Started	Apr 16 12:22:47 PM PDT 24
Finished	Apr 16 12:29:30 PM PDT 24
Peak memory	228132 kb
Host	smart-7c1f58a3-9663-4672-b79f-aa683490e5d5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073907592 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.4073907592
Directory	/workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.rom_ctrl_alert_test.1138853806
Short name	T532
Test name
Test status
Simulation time	8890343973 ps
CPU time	22.42 seconds
Started	Apr 16 02:02:57 PM PDT 24
Finished	Apr 16 02:03:21 PM PDT 24
Peak memory	212480 kb
Host	smart-94f9cd3e-961d-4657-8a8b-cf18c89548d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138853806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1138853806
Directory	/workspace/9.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.rom_ctrl_alert_test.2569203805
Short name	T138
Test name
Test status
Simulation time	8846865812 ps
CPU time	23.37 seconds
Started	Apr 16 12:20:50 PM PDT 24
Finished	Apr 16 12:21:14 PM PDT 24
Peak memory	211392 kb
Host	smart-b4cc687a-ea74-4742-9746-3bbf94a58de5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569203805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2569203805
Directory	/workspace/9.rom_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1988958757
Short name	T426
Test name
Test status
Simulation time	12890225925 ps
CPU time	299.56 seconds
Started	Apr 16 12:20:50 PM PDT 24
Finished	Apr 16 12:25:50 PM PDT 24
Peak memory	217936 kb
Host	smart-8b76fc16-138c-43b2-96a5-4b6d25f6d44a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988958757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c orrupt_sig_fatal_chk.1988958757
Directory	/workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.836891180
Short name	T535
Test name
Test status
Simulation time	4492594377 ps
CPU time	319.27 seconds
Started	Apr 16 02:02:46 PM PDT 24
Finished	Apr 16 02:08:06 PM PDT 24
Peak memory	249308 kb
Host	smart-748454fe-604a-4a6e-ad8a-f76b863e1610
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836891180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co rrupt_sig_fatal_chk.836891180
Directory	/workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location	/workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2267690708
Short name	T393
Test name
Test status
Simulation time	719871757 ps
CPU time	19.16 seconds
Started	Apr 16 02:02:55 PM PDT 24
Finished	Apr 16 02:03:14 PM PDT 24
Peak memory	215236 kb
Host	smart-cf711989-5ff8-4501-869c-aa5bd0dfa6c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267690708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2267690708
Directory	/workspace/9.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/9.rom_ctrl_kmac_err_chk.535604200
Short name	T27
Test name
Test status
Simulation time	480266966 ps
CPU time	19.24 seconds
Started	Apr 16 12:20:50 PM PDT 24
Finished	Apr 16 12:21:10 PM PDT 24
Peak memory	214696 kb
Host	smart-6d187fc8-03e7-43c5-a0bc-7a13ff5a33a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535604200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.535604200
Directory	/workspace/9.rom_ctrl_kmac_err_chk/latest

Test location	/workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3102113356
Short name	T178
Test name
Test status
Simulation time	23864088169 ps
CPU time	27.89 seconds
Started	Apr 16 12:20:39 PM PDT 24
Finished	Apr 16 12:21:07 PM PDT 24
Peak memory	211824 kb
Host	smart-8deee669-87ce-4aad-af24-4f4c937f6843
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3102113356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3102113356
Directory	/workspace/9.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/9.rom_ctrl_max_throughput_chk.40224886
Short name	T543
Test name
Test status
Simulation time	541987360 ps
CPU time	14.04 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:03:05 PM PDT 24
Peak memory	212412 kb
Host	smart-f40d3461-f319-41fd-8c62-9b59e14f17b6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=40224886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.40224886
Directory	/workspace/9.rom_ctrl_max_throughput_chk/latest

Test location	/workspace/coverage/default/9.rom_ctrl_smoke.2232581543
Short name	T1
Test name
Test status
Simulation time	1738120131 ps
CPU time	33.62 seconds
Started	Apr 16 02:03:12 PM PDT 24
Finished	Apr 16 02:03:47 PM PDT 24
Peak memory	217104 kb
Host	smart-5fcd09fb-75b4-41de-bf61-3f8978de7f7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232581543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2232581543
Directory	/workspace/9.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.rom_ctrl_smoke.3418447727
Short name	T416
Test name
Test status
Simulation time	32812430033 ps
CPU time	39.93 seconds
Started	Apr 16 12:22:47 PM PDT 24
Finished	Apr 16 12:23:32 PM PDT 24
Peak memory	217444 kb
Host	smart-990021c0-6237-4a6a-8150-6dfab7d9ae1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418447727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3418447727
Directory	/workspace/9.rom_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.rom_ctrl_stress_all.4129603891
Short name	T352
Test name
Test status
Simulation time	26891240151 ps
CPU time	73.83 seconds
Started	Apr 16 02:02:49 PM PDT 24
Finished	Apr 16 02:04:04 PM PDT 24
Peak memory	218608 kb
Host	smart-e44e8ec6-7c40-47a4-ade2-ef5986d3bac6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129603891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 9.rom_ctrl_stress_all.4129603891
Directory	/workspace/9.rom_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.rom_ctrl_stress_all.998242452
Short name	T269
Test name
Test status
Simulation time	17684731946 ps
CPU time	37.9 seconds
Started	Apr 16 12:20:42 PM PDT 24
Finished	Apr 16 12:21:20 PM PDT 24
Peak memory	212864 kb
Host	smart-4409ecdc-9d82-4b6e-b0d1-9705824fac8b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998242452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.rom_ctrl_stress_all.998242452
Directory	/workspace/9.rom_ctrl_stress_all/latest

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