| T558 |
/workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2313376444 |
|
|
Apr 18 12:33:30 PM PDT 24 |
Apr 18 12:33:50 PM PDT 24 |
332604177 ps |
| T559 |
/workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2673848154 |
|
|
Apr 18 12:33:34 PM PDT 24 |
Apr 18 12:34:05 PM PDT 24 |
3212232349 ps |
| T560 |
/workspace/coverage/default/10.rom_ctrl_smoke.4201882121 |
|
|
Apr 18 12:33:02 PM PDT 24 |
Apr 18 12:34:17 PM PDT 24 |
70061125650 ps |
| T561 |
/workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2395982983 |
|
|
Apr 18 02:07:16 PM PDT 24 |
Apr 18 02:08:19 PM PDT 24 |
14043839919 ps |
| T562 |
/workspace/coverage/default/49.rom_ctrl_alert_test.312547599 |
|
|
Apr 18 02:07:33 PM PDT 24 |
Apr 18 02:07:52 PM PDT 24 |
1535908368 ps |
| T563 |
/workspace/coverage/default/27.rom_ctrl_stress_all.3226121262 |
|
|
Apr 18 12:33:24 PM PDT 24 |
Apr 18 12:34:45 PM PDT 24 |
6432643292 ps |
| T564 |
/workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2404098731 |
|
|
Apr 18 12:33:06 PM PDT 24 |
Apr 18 12:36:57 PM PDT 24 |
13216850476 ps |
| T565 |
/workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1508833630 |
|
|
Apr 18 02:03:49 PM PDT 24 |
Apr 18 02:04:00 PM PDT 24 |
621759239 ps |
| T566 |
/workspace/coverage/default/39.rom_ctrl_alert_test.2914283592 |
|
|
Apr 18 12:33:36 PM PDT 24 |
Apr 18 12:34:04 PM PDT 24 |
12252401171 ps |
| T567 |
/workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2165842066 |
|
|
Apr 18 02:05:38 PM PDT 24 |
Apr 18 02:06:01 PM PDT 24 |
660231554 ps |
| T568 |
/workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2990151996 |
|
|
Apr 18 12:33:07 PM PDT 24 |
Apr 18 12:48:54 PM PDT 24 |
123266784505 ps |
| T569 |
/workspace/coverage/default/36.rom_ctrl_stress_all.2722499060 |
|
|
Apr 18 02:06:38 PM PDT 24 |
Apr 18 02:09:39 PM PDT 24 |
109434304601 ps |
| T39 |
/workspace/coverage/default/1.rom_ctrl_sec_cm.2269647509 |
|
|
Apr 18 12:33:16 PM PDT 24 |
Apr 18 12:37:04 PM PDT 24 |
1025059859 ps |
| T570 |
/workspace/coverage/default/39.rom_ctrl_smoke.233504936 |
|
|
Apr 18 02:06:49 PM PDT 24 |
Apr 18 02:07:47 PM PDT 24 |
24816335862 ps |
| T571 |
/workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2207970136 |
|
|
Apr 18 12:33:23 PM PDT 24 |
Apr 18 12:36:24 PM PDT 24 |
9854167955 ps |
| T572 |
/workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3448326742 |
|
|
Apr 18 12:33:13 PM PDT 24 |
Apr 18 12:35:57 PM PDT 24 |
8617959847 ps |
| T573 |
/workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2508702076 |
|
|
Apr 18 12:33:38 PM PDT 24 |
Apr 18 12:40:38 PM PDT 24 |
129772218726 ps |
| T574 |
/workspace/coverage/default/14.rom_ctrl_stress_all.791695262 |
|
|
Apr 18 02:04:42 PM PDT 24 |
Apr 18 02:05:26 PM PDT 24 |
7133354664 ps |
| T575 |
/workspace/coverage/default/18.rom_ctrl_alert_test.434144624 |
|
|
Apr 18 12:33:07 PM PDT 24 |
Apr 18 12:33:18 PM PDT 24 |
170848220 ps |
| T576 |
/workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1815230351 |
|
|
Apr 18 12:33:20 PM PDT 24 |
Apr 18 12:34:17 PM PDT 24 |
13006122400 ps |
| T577 |
/workspace/coverage/default/19.rom_ctrl_smoke.651278766 |
|
|
Apr 18 02:05:08 PM PDT 24 |
Apr 18 02:05:52 PM PDT 24 |
17798149869 ps |
| T578 |
/workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1017153450 |
|
|
Apr 18 12:33:15 PM PDT 24 |
Apr 18 12:33:34 PM PDT 24 |
1141932137 ps |
| T579 |
/workspace/coverage/default/0.rom_ctrl_stress_all.1701153455 |
|
|
Apr 18 02:03:12 PM PDT 24 |
Apr 18 02:05:13 PM PDT 24 |
13393218295 ps |
| T580 |
/workspace/coverage/default/39.rom_ctrl_smoke.565380448 |
|
|
Apr 18 12:33:36 PM PDT 24 |
Apr 18 12:33:57 PM PDT 24 |
1431535838 ps |
| T581 |
/workspace/coverage/default/37.rom_ctrl_stress_all.249850941 |
|
|
Apr 18 02:06:40 PM PDT 24 |
Apr 18 02:07:58 PM PDT 24 |
15617059633 ps |
| T40 |
/workspace/coverage/default/4.rom_ctrl_sec_cm.3389001676 |
|
|
Apr 18 02:03:52 PM PDT 24 |
Apr 18 02:07:55 PM PDT 24 |
75603839356 ps |
| T582 |
/workspace/coverage/default/33.rom_ctrl_smoke.1317906473 |
|
|
Apr 18 02:06:28 PM PDT 24 |
Apr 18 02:07:20 PM PDT 24 |
17746891637 ps |
| T583 |
/workspace/coverage/default/29.rom_ctrl_alert_test.4240470821 |
|
|
Apr 18 02:06:02 PM PDT 24 |
Apr 18 02:06:34 PM PDT 24 |
3675460233 ps |
| T584 |
/workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3943896972 |
|
|
Apr 18 12:33:29 PM PDT 24 |
Apr 18 12:33:49 PM PDT 24 |
346492461 ps |
| T585 |
/workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2290380105 |
|
|
Apr 18 02:06:38 PM PDT 24 |
Apr 18 02:07:43 PM PDT 24 |
42566174834 ps |
| T586 |
/workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3790983816 |
|
|
Apr 18 02:06:50 PM PDT 24 |
Apr 18 02:07:10 PM PDT 24 |
1436932722 ps |
| T587 |
/workspace/coverage/default/25.rom_ctrl_stress_all.3166903071 |
|
|
Apr 18 02:05:46 PM PDT 24 |
Apr 18 02:07:31 PM PDT 24 |
12319793418 ps |
| T588 |
/workspace/coverage/default/33.rom_ctrl_smoke.582112888 |
|
|
Apr 18 12:33:25 PM PDT 24 |
Apr 18 12:34:37 PM PDT 24 |
27793474919 ps |
| T589 |
/workspace/coverage/default/33.rom_ctrl_stress_all.196148835 |
|
|
Apr 18 02:06:26 PM PDT 24 |
Apr 18 02:06:56 PM PDT 24 |
12659096938 ps |
| T590 |
/workspace/coverage/default/14.rom_ctrl_smoke.622035594 |
|
|
Apr 18 02:04:43 PM PDT 24 |
Apr 18 02:05:04 PM PDT 24 |
362821628 ps |
| T591 |
/workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2827475361 |
|
|
Apr 18 02:06:08 PM PDT 24 |
Apr 18 02:06:31 PM PDT 24 |
4296374146 ps |
| T592 |
/workspace/coverage/default/16.rom_ctrl_smoke.366109923 |
|
|
Apr 18 02:05:01 PM PDT 24 |
Apr 18 02:06:06 PM PDT 24 |
14697632112 ps |
| T593 |
/workspace/coverage/default/21.rom_ctrl_alert_test.3652689341 |
|
|
Apr 18 02:05:23 PM PDT 24 |
Apr 18 02:05:32 PM PDT 24 |
174496024 ps |
| T594 |
/workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3691482104 |
|
|
Apr 18 02:04:16 PM PDT 24 |
Apr 18 02:09:47 PM PDT 24 |
25850159040 ps |
| T595 |
/workspace/coverage/default/1.rom_ctrl_stress_all.2141752376 |
|
|
Apr 18 12:32:52 PM PDT 24 |
Apr 18 12:33:36 PM PDT 24 |
4172398599 ps |
| T596 |
/workspace/coverage/default/35.rom_ctrl_stress_all.2601297861 |
|
|
Apr 18 02:06:35 PM PDT 24 |
Apr 18 02:08:48 PM PDT 24 |
13066798263 ps |
| T597 |
/workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3480314122 |
|
|
Apr 18 02:07:24 PM PDT 24 |
Apr 18 02:22:43 PM PDT 24 |
94220532788 ps |
| T598 |
/workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1972410402 |
|
|
Apr 18 12:33:27 PM PDT 24 |
Apr 18 12:34:12 PM PDT 24 |
35707260231 ps |
| T599 |
/workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2719463606 |
|
|
Apr 18 12:33:43 PM PDT 24 |
Apr 18 01:33:08 PM PDT 24 |
198828745332 ps |
| T600 |
/workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2100247959 |
|
|
Apr 18 12:33:07 PM PDT 24 |
Apr 18 12:33:19 PM PDT 24 |
353902371 ps |
| T601 |
/workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1893472083 |
|
|
Apr 18 12:33:07 PM PDT 24 |
Apr 18 12:33:41 PM PDT 24 |
16060111341 ps |
| T41 |
/workspace/coverage/default/1.rom_ctrl_sec_cm.992054169 |
|
|
Apr 18 02:03:27 PM PDT 24 |
Apr 18 02:05:46 PM PDT 24 |
3798502433 ps |
| T602 |
/workspace/coverage/default/47.rom_ctrl_stress_all.2995308287 |
|
|
Apr 18 12:33:48 PM PDT 24 |
Apr 18 12:35:39 PM PDT 24 |
69223149200 ps |
| T603 |
/workspace/coverage/default/38.rom_ctrl_stress_all.176772783 |
|
|
Apr 18 02:06:49 PM PDT 24 |
Apr 18 02:07:23 PM PDT 24 |
16167855168 ps |
| T604 |
/workspace/coverage/default/38.rom_ctrl_alert_test.1556611481 |
|
|
Apr 18 12:33:36 PM PDT 24 |
Apr 18 12:34:09 PM PDT 24 |
5672434100 ps |
| T605 |
/workspace/coverage/default/17.rom_ctrl_alert_test.557614193 |
|
|
Apr 18 02:05:08 PM PDT 24 |
Apr 18 02:05:39 PM PDT 24 |
10555376149 ps |
| T606 |
/workspace/coverage/default/20.rom_ctrl_alert_test.3175338358 |
|
|
Apr 18 02:05:24 PM PDT 24 |
Apr 18 02:05:33 PM PDT 24 |
1647303297 ps |
| T607 |
/workspace/coverage/default/5.rom_ctrl_stress_all.2497381039 |
|
|
Apr 18 02:03:50 PM PDT 24 |
Apr 18 02:04:38 PM PDT 24 |
1400599805 ps |
| T608 |
/workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3665469978 |
|
|
Apr 18 02:06:16 PM PDT 24 |
Apr 18 02:13:18 PM PDT 24 |
160435685050 ps |
| T609 |
/workspace/coverage/default/1.rom_ctrl_stress_all.1571843026 |
|
|
Apr 18 02:03:18 PM PDT 24 |
Apr 18 02:03:35 PM PDT 24 |
587255565 ps |
| T610 |
/workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1905140883 |
|
|
Apr 18 02:05:00 PM PDT 24 |
Apr 18 02:05:20 PM PDT 24 |
487128635 ps |
| T611 |
/workspace/coverage/default/5.rom_ctrl_alert_test.1677570883 |
|
|
Apr 18 02:04:01 PM PDT 24 |
Apr 18 02:04:28 PM PDT 24 |
3151533454 ps |
| T612 |
/workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1179869651 |
|
|
Apr 18 12:33:19 PM PDT 24 |
Apr 18 12:34:01 PM PDT 24 |
3450309972 ps |
| T613 |
/workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2922626150 |
|
|
Apr 18 12:33:26 PM PDT 24 |
Apr 18 12:33:47 PM PDT 24 |
662119643 ps |
| T614 |
/workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1135351548 |
|
|
Apr 18 12:33:11 PM PDT 24 |
Apr 18 12:33:41 PM PDT 24 |
3257789289 ps |
| T615 |
/workspace/coverage/default/36.rom_ctrl_max_throughput_chk.470093012 |
|
|
Apr 18 02:06:46 PM PDT 24 |
Apr 18 02:07:07 PM PDT 24 |
2979298649 ps |
| T616 |
/workspace/coverage/default/45.rom_ctrl_smoke.4215080400 |
|
|
Apr 18 12:33:43 PM PDT 24 |
Apr 18 12:34:26 PM PDT 24 |
3249879494 ps |
| T617 |
/workspace/coverage/default/3.rom_ctrl_max_throughput_chk.166996724 |
|
|
Apr 18 12:33:01 PM PDT 24 |
Apr 18 12:33:22 PM PDT 24 |
2042186083 ps |
| T618 |
/workspace/coverage/default/30.rom_ctrl_smoke.308803365 |
|
|
Apr 18 12:33:25 PM PDT 24 |
Apr 18 12:34:08 PM PDT 24 |
14356191892 ps |
| T619 |
/workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.129252285 |
|
|
Apr 18 12:33:02 PM PDT 24 |
Apr 18 12:36:52 PM PDT 24 |
82022325046 ps |
| T620 |
/workspace/coverage/default/3.rom_ctrl_smoke.1840158199 |
|
|
Apr 18 02:03:34 PM PDT 24 |
Apr 18 02:04:45 PM PDT 24 |
6782086901 ps |
| T621 |
/workspace/coverage/default/25.rom_ctrl_stress_all.1274249394 |
|
|
Apr 18 12:33:30 PM PDT 24 |
Apr 18 12:35:02 PM PDT 24 |
10379858446 ps |
| T622 |
/workspace/coverage/default/8.rom_ctrl_alert_test.1194271637 |
|
|
Apr 18 12:32:52 PM PDT 24 |
Apr 18 12:33:25 PM PDT 24 |
3683698783 ps |
| T623 |
/workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3950557527 |
|
|
Apr 18 12:33:50 PM PDT 24 |
Apr 18 12:34:39 PM PDT 24 |
17109410076 ps |
| T624 |
/workspace/coverage/default/47.rom_ctrl_stress_all.1566357191 |
|
|
Apr 18 02:07:26 PM PDT 24 |
Apr 18 02:08:56 PM PDT 24 |
23857183077 ps |
| T625 |
/workspace/coverage/default/43.rom_ctrl_kmac_err_chk.752838459 |
|
|
Apr 18 12:33:47 PM PDT 24 |
Apr 18 12:34:21 PM PDT 24 |
11282601636 ps |
| T626 |
/workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1827243583 |
|
|
Apr 18 02:05:08 PM PDT 24 |
Apr 18 02:06:18 PM PDT 24 |
18541080672 ps |
| T627 |
/workspace/coverage/default/17.rom_ctrl_smoke.2541607792 |
|
|
Apr 18 02:05:01 PM PDT 24 |
Apr 18 02:05:23 PM PDT 24 |
364918690 ps |
| T628 |
/workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1962231412 |
|
|
Apr 18 02:06:15 PM PDT 24 |
Apr 18 02:07:26 PM PDT 24 |
34156887956 ps |
| T629 |
/workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2354347920 |
|
|
Apr 18 12:33:43 PM PDT 24 |
Apr 18 12:34:04 PM PDT 24 |
1574911791 ps |
| T630 |
/workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1775869403 |
|
|
Apr 18 12:33:36 PM PDT 24 |
Apr 18 12:37:03 PM PDT 24 |
11211994112 ps |
| T631 |
/workspace/coverage/default/45.rom_ctrl_smoke.4157259326 |
|
|
Apr 18 02:07:10 PM PDT 24 |
Apr 18 02:08:23 PM PDT 24 |
8060764142 ps |
| T632 |
/workspace/coverage/default/20.rom_ctrl_smoke.4021023961 |
|
|
Apr 18 12:33:23 PM PDT 24 |
Apr 18 12:34:17 PM PDT 24 |
5505021975 ps |
| T633 |
/workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2829927185 |
|
|
Apr 18 02:05:53 PM PDT 24 |
Apr 18 02:17:43 PM PDT 24 |
263931958464 ps |
| T634 |
/workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2404002781 |
|
|
Apr 18 12:32:50 PM PDT 24 |
Apr 18 12:43:53 PM PDT 24 |
141336862262 ps |
| T635 |
/workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3212730929 |
|
|
Apr 18 02:06:01 PM PDT 24 |
Apr 18 02:06:25 PM PDT 24 |
8936066596 ps |
| T636 |
/workspace/coverage/default/19.rom_ctrl_smoke.1207989273 |
|
|
Apr 18 12:33:20 PM PDT 24 |
Apr 18 12:34:07 PM PDT 24 |
12694399424 ps |
| T637 |
/workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1297904764 |
|
|
Apr 18 12:33:04 PM PDT 24 |
Apr 18 12:33:20 PM PDT 24 |
2335174229 ps |
| T638 |
/workspace/coverage/default/40.rom_ctrl_alert_test.1664631877 |
|
|
Apr 18 02:06:55 PM PDT 24 |
Apr 18 02:07:05 PM PDT 24 |
1036894110 ps |
| T639 |
/workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3266334864 |
|
|
Apr 18 02:06:28 PM PDT 24 |
Apr 18 02:10:22 PM PDT 24 |
13589158626 ps |
| T640 |
/workspace/coverage/default/22.rom_ctrl_alert_test.3398664013 |
|
|
Apr 18 12:33:06 PM PDT 24 |
Apr 18 12:33:17 PM PDT 24 |
688531824 ps |
| T641 |
/workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3754538017 |
|
|
Apr 18 12:32:58 PM PDT 24 |
Apr 18 12:33:19 PM PDT 24 |
675919269 ps |
| T642 |
/workspace/coverage/default/13.rom_ctrl_stress_all.2435878528 |
|
|
Apr 18 12:33:16 PM PDT 24 |
Apr 18 12:34:57 PM PDT 24 |
48176340092 ps |
| T115 |
/workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3649757241 |
|
|
Apr 18 12:33:31 PM PDT 24 |
Apr 18 12:33:42 PM PDT 24 |
350109568 ps |
| T643 |
/workspace/coverage/default/2.rom_ctrl_alert_test.1544963894 |
|
|
Apr 18 02:03:35 PM PDT 24 |
Apr 18 02:03:50 PM PDT 24 |
1489221432 ps |
| T644 |
/workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1686375377 |
|
|
Apr 18 02:06:48 PM PDT 24 |
Apr 18 02:07:49 PM PDT 24 |
51769926877 ps |
| T645 |
/workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2067734043 |
|
|
Apr 18 12:33:01 PM PDT 24 |
Apr 18 12:33:23 PM PDT 24 |
2061879691 ps |
| T646 |
/workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3061626872 |
|
|
Apr 18 02:07:33 PM PDT 24 |
Apr 18 02:10:49 PM PDT 24 |
46932053691 ps |
| T647 |
/workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1252544681 |
|
|
Apr 18 02:05:22 PM PDT 24 |
Apr 18 02:12:53 PM PDT 24 |
124200202989 ps |
| T648 |
/workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.740804228 |
|
|
Apr 18 02:06:08 PM PDT 24 |
Apr 18 02:20:10 PM PDT 24 |
164453740126 ps |
| T649 |
/workspace/coverage/default/48.rom_ctrl_smoke.3964658632 |
|
|
Apr 18 12:33:47 PM PDT 24 |
Apr 18 12:34:08 PM PDT 24 |
359087545 ps |
| T650 |
/workspace/coverage/default/12.rom_ctrl_stress_all.1245195496 |
|
|
Apr 18 02:04:34 PM PDT 24 |
Apr 18 02:05:23 PM PDT 24 |
4543058079 ps |
| T651 |
/workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2055013917 |
|
|
Apr 18 02:06:01 PM PDT 24 |
Apr 18 02:08:44 PM PDT 24 |
2852886274 ps |
| T652 |
/workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3937485938 |
|
|
Apr 18 12:33:24 PM PDT 24 |
Apr 18 12:33:36 PM PDT 24 |
699993503 ps |
| T653 |
/workspace/coverage/default/32.rom_ctrl_alert_test.3333406818 |
|
|
Apr 18 12:33:26 PM PDT 24 |
Apr 18 12:33:35 PM PDT 24 |
590597520 ps |
| T654 |
/workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2532424932 |
|
|
Apr 18 02:06:01 PM PDT 24 |
Apr 18 02:10:36 PM PDT 24 |
117586173349 ps |
| T655 |
/workspace/coverage/default/5.rom_ctrl_smoke.1318121666 |
|
|
Apr 18 02:03:51 PM PDT 24 |
Apr 18 02:04:53 PM PDT 24 |
7506739814 ps |
| T656 |
/workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2391389534 |
|
|
Apr 18 12:33:07 PM PDT 24 |
Apr 18 12:33:20 PM PDT 24 |
826044865 ps |
| T657 |
/workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.946242993 |
|
|
Apr 18 12:33:42 PM PDT 24 |
Apr 18 12:37:28 PM PDT 24 |
2617035906 ps |
| T658 |
/workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2690554130 |
|
|
Apr 18 02:04:17 PM PDT 24 |
Apr 18 02:04:45 PM PDT 24 |
16036100939 ps |
| T659 |
/workspace/coverage/default/32.rom_ctrl_stress_all.352472028 |
|
|
Apr 18 02:06:18 PM PDT 24 |
Apr 18 02:07:14 PM PDT 24 |
1202890277 ps |
| T660 |
/workspace/coverage/default/48.rom_ctrl_max_throughput_chk.741761885 |
|
|
Apr 18 12:33:48 PM PDT 24 |
Apr 18 12:34:21 PM PDT 24 |
3555912581 ps |
| T42 |
/workspace/coverage/default/3.rom_ctrl_sec_cm.3689318471 |
|
|
Apr 18 02:03:42 PM PDT 24 |
Apr 18 02:07:39 PM PDT 24 |
12733591235 ps |
| T661 |
/workspace/coverage/default/43.rom_ctrl_smoke.1012955473 |
|
|
Apr 18 12:33:47 PM PDT 24 |
Apr 18 12:34:14 PM PDT 24 |
9564226302 ps |
| T662 |
/workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3273496352 |
|
|
Apr 18 12:33:11 PM PDT 24 |
Apr 18 12:45:29 PM PDT 24 |
142787786678 ps |
| T663 |
/workspace/coverage/default/36.rom_ctrl_smoke.2236624407 |
|
|
Apr 18 02:06:39 PM PDT 24 |
Apr 18 02:07:50 PM PDT 24 |
8907934992 ps |
| T664 |
/workspace/coverage/default/4.rom_ctrl_alert_test.3543022080 |
|
|
Apr 18 12:33:10 PM PDT 24 |
Apr 18 12:33:36 PM PDT 24 |
5604919167 ps |
| T665 |
/workspace/coverage/default/24.rom_ctrl_alert_test.867418188 |
|
|
Apr 18 02:05:38 PM PDT 24 |
Apr 18 02:06:11 PM PDT 24 |
8180155675 ps |
| T666 |
/workspace/coverage/default/7.rom_ctrl_alert_test.2940447639 |
|
|
Apr 18 12:32:59 PM PDT 24 |
Apr 18 12:33:23 PM PDT 24 |
9521399377 ps |
| T667 |
/workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2561992619 |
|
|
Apr 18 12:32:54 PM PDT 24 |
Apr 18 12:54:03 PM PDT 24 |
41597124358 ps |
| T668 |
/workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2746706837 |
|
|
Apr 18 12:33:23 PM PDT 24 |
Apr 18 12:40:53 PM PDT 24 |
181374518047 ps |
| T669 |
/workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.239049455 |
|
|
Apr 18 02:04:41 PM PDT 24 |
Apr 18 02:09:50 PM PDT 24 |
17875884999 ps |
| T670 |
/workspace/coverage/default/23.rom_ctrl_smoke.2509008184 |
|
|
Apr 18 12:33:19 PM PDT 24 |
Apr 18 12:34:03 PM PDT 24 |
18331861052 ps |
| T671 |
/workspace/coverage/default/15.rom_ctrl_stress_all.554748196 |
|
|
Apr 18 02:04:52 PM PDT 24 |
Apr 18 02:05:56 PM PDT 24 |
2172765571 ps |
| T672 |
/workspace/coverage/default/18.rom_ctrl_kmac_err_chk.116664930 |
|
|
Apr 18 12:33:07 PM PDT 24 |
Apr 18 12:34:04 PM PDT 24 |
25328021285 ps |
| T673 |
/workspace/coverage/default/49.rom_ctrl_smoke.1088453785 |
|
|
Apr 18 12:33:51 PM PDT 24 |
Apr 18 12:34:37 PM PDT 24 |
4462997141 ps |
| T674 |
/workspace/coverage/default/16.rom_ctrl_alert_test.4005825975 |
|
|
Apr 18 02:05:00 PM PDT 24 |
Apr 18 02:05:28 PM PDT 24 |
5529046591 ps |
| T675 |
/workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3241132236 |
|
|
Apr 18 02:05:31 PM PDT 24 |
Apr 18 02:16:52 PM PDT 24 |
15893387259 ps |
| T66 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.223674854 |
|
|
Apr 18 02:08:26 PM PDT 24 |
Apr 18 02:08:50 PM PDT 24 |
5237918662 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1737539090 |
|
|
Apr 18 12:32:52 PM PDT 24 |
Apr 18 12:35:33 PM PDT 24 |
17948260417 ps |
| T68 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1738705753 |
|
|
Apr 18 12:32:50 PM PDT 24 |
Apr 18 12:33:22 PM PDT 24 |
4196219058 ps |
| T676 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.235906762 |
|
|
Apr 18 12:32:58 PM PDT 24 |
Apr 18 12:33:21 PM PDT 24 |
2798397856 ps |
| T74 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.401391709 |
|
|
Apr 18 02:08:42 PM PDT 24 |
Apr 18 02:10:08 PM PDT 24 |
121024704708 ps |
| T116 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4082863200 |
|
|
Apr 18 02:07:40 PM PDT 24 |
Apr 18 02:08:04 PM PDT 24 |
1837720826 ps |
| T75 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.631223662 |
|
|
Apr 18 02:08:50 PM PDT 24 |
Apr 18 02:09:11 PM PDT 24 |
2823991665 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.630664659 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:33:14 PM PDT 24 |
11430456377 ps |
| T117 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2156995051 |
|
|
Apr 18 12:33:02 PM PDT 24 |
Apr 18 12:33:27 PM PDT 24 |
10781459506 ps |
| T77 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2191769218 |
|
|
Apr 18 12:32:48 PM PDT 24 |
Apr 18 12:33:27 PM PDT 24 |
13527455664 ps |
| T677 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1030442773 |
|
|
Apr 18 02:07:31 PM PDT 24 |
Apr 18 02:07:58 PM PDT 24 |
6480918375 ps |
| T63 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.131199923 |
|
|
Apr 18 02:08:08 PM PDT 24 |
Apr 18 02:10:48 PM PDT 24 |
382381361 ps |
| T118 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2630834741 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:36:14 PM PDT 24 |
23111593670 ps |
| T110 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.53066885 |
|
|
Apr 18 12:33:00 PM PDT 24 |
Apr 18 12:33:22 PM PDT 24 |
2197272234 ps |
| T64 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.862405100 |
|
|
Apr 18 02:08:42 PM PDT 24 |
Apr 18 02:10:09 PM PDT 24 |
1933834653 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3734709213 |
|
|
Apr 18 12:32:55 PM PDT 24 |
Apr 18 12:34:32 PM PDT 24 |
5569172260 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3930925533 |
|
|
Apr 18 12:32:49 PM PDT 24 |
Apr 18 12:34:46 PM PDT 24 |
13136958948 ps |
| T678 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3852034472 |
|
|
Apr 18 02:08:18 PM PDT 24 |
Apr 18 02:09:31 PM PDT 24 |
5841785592 ps |
| T79 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.756553476 |
|
|
Apr 18 02:08:16 PM PDT 24 |
Apr 18 02:09:58 PM PDT 24 |
25720527487 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.638662051 |
|
|
Apr 18 12:32:53 PM PDT 24 |
Apr 18 12:35:44 PM PDT 24 |
3138294790 ps |
| T679 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1818270872 |
|
|
Apr 18 02:08:17 PM PDT 24 |
Apr 18 02:08:50 PM PDT 24 |
14643536854 ps |
| T111 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3866021336 |
|
|
Apr 18 02:08:06 PM PDT 24 |
Apr 18 02:08:38 PM PDT 24 |
5891211196 ps |
| T680 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3062518692 |
|
|
Apr 18 02:08:18 PM PDT 24 |
Apr 18 02:08:54 PM PDT 24 |
4169946418 ps |
| T681 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2073639986 |
|
|
Apr 18 02:07:58 PM PDT 24 |
Apr 18 02:08:31 PM PDT 24 |
12586087969 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2133427582 |
|
|
Apr 18 02:08:35 PM PDT 24 |
Apr 18 02:10:04 PM PDT 24 |
10189219388 ps |
| T80 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4261010017 |
|
|
Apr 18 02:07:56 PM PDT 24 |
Apr 18 02:08:12 PM PDT 24 |
355600121 ps |
| T682 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.160715028 |
|
|
Apr 18 12:32:46 PM PDT 24 |
Apr 18 12:33:17 PM PDT 24 |
7180953582 ps |
| T683 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.568455277 |
|
|
Apr 18 12:32:50 PM PDT 24 |
Apr 18 12:33:26 PM PDT 24 |
4299602385 ps |
| T684 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1130539948 |
|
|
Apr 18 02:07:40 PM PDT 24 |
Apr 18 02:08:07 PM PDT 24 |
9135611416 ps |
| T685 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.961998306 |
|
|
Apr 18 12:32:50 PM PDT 24 |
Apr 18 12:33:26 PM PDT 24 |
4169445405 ps |
| T686 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1066051533 |
|
|
Apr 18 12:32:48 PM PDT 24 |
Apr 18 12:33:09 PM PDT 24 |
6226017956 ps |
| T81 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.390989857 |
|
|
Apr 18 02:08:46 PM PDT 24 |
Apr 18 02:09:14 PM PDT 24 |
3579699539 ps |
| T127 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3576641204 |
|
|
Apr 18 02:08:35 PM PDT 24 |
Apr 18 02:11:20 PM PDT 24 |
10649726615 ps |
| T112 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4279105738 |
|
|
Apr 18 02:08:52 PM PDT 24 |
Apr 18 02:09:23 PM PDT 24 |
7480275208 ps |
| T687 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1744511476 |
|
|
Apr 18 12:32:49 PM PDT 24 |
Apr 18 12:33:22 PM PDT 24 |
11120767932 ps |
| T688 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1151327558 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:33:05 PM PDT 24 |
688953562 ps |
| T122 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3795911238 |
|
|
Apr 18 02:08:07 PM PDT 24 |
Apr 18 02:10:40 PM PDT 24 |
1196834178 ps |
| T689 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1005460289 |
|
|
Apr 18 02:08:19 PM PDT 24 |
Apr 18 02:08:28 PM PDT 24 |
1057951083 ps |
| T690 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2400614827 |
|
|
Apr 18 02:08:44 PM PDT 24 |
Apr 18 02:08:54 PM PDT 24 |
1174874351 ps |
| T113 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1144122360 |
|
|
Apr 18 02:08:44 PM PDT 24 |
Apr 18 02:10:14 PM PDT 24 |
40528062331 ps |
| T691 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.227962560 |
|
|
Apr 18 12:32:43 PM PDT 24 |
Apr 18 12:33:07 PM PDT 24 |
2664312524 ps |
| T82 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2937721396 |
|
|
Apr 18 12:32:47 PM PDT 24 |
Apr 18 12:33:08 PM PDT 24 |
13442475730 ps |
| T692 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4067770395 |
|
|
Apr 18 02:07:55 PM PDT 24 |
Apr 18 02:08:04 PM PDT 24 |
2741151634 ps |
| T138 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2229039276 |
|
|
Apr 18 12:32:42 PM PDT 24 |
Apr 18 12:34:02 PM PDT 24 |
1355118785 ps |
| T693 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2048401148 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:33:27 PM PDT 24 |
16857532020 ps |
| T90 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.945919959 |
|
|
Apr 18 02:08:08 PM PDT 24 |
Apr 18 02:11:08 PM PDT 24 |
87569923379 ps |
| T97 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2266019521 |
|
|
Apr 18 02:07:49 PM PDT 24 |
Apr 18 02:09:22 PM PDT 24 |
19192530259 ps |
| T114 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1297061334 |
|
|
Apr 18 02:08:35 PM PDT 24 |
Apr 18 02:08:57 PM PDT 24 |
7847717925 ps |
| T694 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4183756731 |
|
|
Apr 18 02:07:52 PM PDT 24 |
Apr 18 02:08:01 PM PDT 24 |
331717326 ps |
| T695 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2831922942 |
|
|
Apr 18 12:32:47 PM PDT 24 |
Apr 18 12:33:18 PM PDT 24 |
3601592573 ps |
| T130 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1973797268 |
|
|
Apr 18 12:32:49 PM PDT 24 |
Apr 18 12:35:25 PM PDT 24 |
1123311889 ps |
| T123 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3755394012 |
|
|
Apr 18 02:08:55 PM PDT 24 |
Apr 18 02:11:49 PM PDT 24 |
7382824326 ps |
| T98 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2098407660 |
|
|
Apr 18 12:32:47 PM PDT 24 |
Apr 18 12:33:23 PM PDT 24 |
16378525813 ps |
| T696 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3611050362 |
|
|
Apr 18 02:08:06 PM PDT 24 |
Apr 18 02:08:38 PM PDT 24 |
15415742693 ps |
| T697 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1891481963 |
|
|
Apr 18 12:32:48 PM PDT 24 |
Apr 18 12:33:06 PM PDT 24 |
1404441632 ps |
| T129 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.581597899 |
|
|
Apr 18 02:08:16 PM PDT 24 |
Apr 18 02:10:47 PM PDT 24 |
2946244081 ps |
| T698 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2066172497 |
|
|
Apr 18 12:32:55 PM PDT 24 |
Apr 18 12:33:31 PM PDT 24 |
4173903267 ps |
| T699 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2994186223 |
|
|
Apr 18 12:32:52 PM PDT 24 |
Apr 18 12:33:31 PM PDT 24 |
1012362753 ps |
| T700 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.428778061 |
|
|
Apr 18 12:32:50 PM PDT 24 |
Apr 18 12:34:16 PM PDT 24 |
2150902403 ps |
| T701 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.630561017 |
|
|
Apr 18 12:32:50 PM PDT 24 |
Apr 18 12:33:10 PM PDT 24 |
1714231361 ps |
| T702 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3669012855 |
|
|
Apr 18 02:08:25 PM PDT 24 |
Apr 18 02:08:48 PM PDT 24 |
2228693819 ps |
| T703 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3971709933 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:33:20 PM PDT 24 |
12831621111 ps |
| T704 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1390523734 |
|
|
Apr 18 12:33:03 PM PDT 24 |
Apr 18 12:33:34 PM PDT 24 |
12141186253 ps |
| T705 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1240143365 |
|
|
Apr 18 02:08:43 PM PDT 24 |
Apr 18 02:09:00 PM PDT 24 |
2983460011 ps |
| T706 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2160301629 |
|
|
Apr 18 12:33:47 PM PDT 24 |
Apr 18 12:34:13 PM PDT 24 |
40185553478 ps |
| T91 |
/workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3371451422 |
|
|
Apr 18 02:08:50 PM PDT 24 |
Apr 18 02:09:12 PM PDT 24 |
3784551688 ps |
| T124 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.421859878 |
|
|
Apr 18 02:07:58 PM PDT 24 |
Apr 18 02:10:43 PM PDT 24 |
8643402431 ps |
| T707 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1148584570 |
|
|
Apr 18 02:08:33 PM PDT 24 |
Apr 18 02:09:06 PM PDT 24 |
4447580947 ps |
| T708 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1530764818 |
|
|
Apr 18 02:07:50 PM PDT 24 |
Apr 18 02:08:26 PM PDT 24 |
16377750298 ps |
| T709 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2492073285 |
|
|
Apr 18 12:32:46 PM PDT 24 |
Apr 18 12:33:14 PM PDT 24 |
3153230900 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1917390523 |
|
|
Apr 18 02:07:51 PM PDT 24 |
Apr 18 02:09:32 PM PDT 24 |
3359039090 ps |
| T710 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2368765670 |
|
|
Apr 18 12:32:49 PM PDT 24 |
Apr 18 12:33:22 PM PDT 24 |
11029258769 ps |
| T711 |
/workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2246702814 |
|
|
Apr 18 02:08:19 PM PDT 24 |
Apr 18 02:08:28 PM PDT 24 |
661959778 ps |
| T712 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4168657327 |
|
|
Apr 18 12:34:02 PM PDT 24 |
Apr 18 12:34:25 PM PDT 24 |
6482906546 ps |
| T713 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3855961266 |
|
|
Apr 18 02:07:53 PM PDT 24 |
Apr 18 02:08:06 PM PDT 24 |
688931285 ps |
| T714 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2477389772 |
|
|
Apr 18 12:32:49 PM PDT 24 |
Apr 18 12:33:09 PM PDT 24 |
1036258692 ps |
| T715 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.434736073 |
|
|
Apr 18 12:32:53 PM PDT 24 |
Apr 18 12:33:14 PM PDT 24 |
1723169254 ps |
| T716 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1896207040 |
|
|
Apr 18 02:07:52 PM PDT 24 |
Apr 18 02:08:15 PM PDT 24 |
12547532715 ps |
| T717 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2832547822 |
|
|
Apr 18 12:34:03 PM PDT 24 |
Apr 18 12:34:13 PM PDT 24 |
353213254 ps |
| T718 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1189933412 |
|
|
Apr 18 02:08:08 PM PDT 24 |
Apr 18 02:08:16 PM PDT 24 |
1268195281 ps |
| T719 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2420878621 |
|
|
Apr 18 12:32:45 PM PDT 24 |
Apr 18 12:33:03 PM PDT 24 |
2550093466 ps |
| T720 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.567184514 |
|
|
Apr 18 02:07:49 PM PDT 24 |
Apr 18 02:08:16 PM PDT 24 |
6669998424 ps |
| T721 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2737635394 |
|
|
Apr 18 12:33:05 PM PDT 24 |
Apr 18 12:35:00 PM PDT 24 |
177386553857 ps |
| T722 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3908012563 |
|
|
Apr 18 12:32:33 PM PDT 24 |
Apr 18 12:32:58 PM PDT 24 |
8245665445 ps |
| T723 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.833795367 |
|
|
Apr 18 12:33:03 PM PDT 24 |
Apr 18 12:35:44 PM PDT 24 |
69944462597 ps |
| T724 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2917125480 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:34:19 PM PDT 24 |
4385811250 ps |
| T725 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3312322159 |
|
|
Apr 18 02:07:52 PM PDT 24 |
Apr 18 02:08:28 PM PDT 24 |
4289417820 ps |
| T726 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2316248114 |
|
|
Apr 18 12:32:47 PM PDT 24 |
Apr 18 12:33:16 PM PDT 24 |
21559722041 ps |
| T727 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2408098602 |
|
|
Apr 18 02:08:34 PM PDT 24 |
Apr 18 02:08:45 PM PDT 24 |
1890285119 ps |
| T728 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.209089420 |
|
|
Apr 18 12:32:49 PM PDT 24 |
Apr 18 12:33:07 PM PDT 24 |
1150953296 ps |
| T729 |
/workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.740881723 |
|
|
Apr 18 02:08:44 PM PDT 24 |
Apr 18 02:08:57 PM PDT 24 |
689639276 ps |
| T133 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.26639382 |
|
|
Apr 18 12:32:43 PM PDT 24 |
Apr 18 12:34:05 PM PDT 24 |
455427569 ps |
| T730 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2724192115 |
|
|
Apr 18 12:32:43 PM PDT 24 |
Apr 18 12:33:21 PM PDT 24 |
1429138276 ps |
| T731 |
/workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4112294773 |
|
|
Apr 18 12:33:47 PM PDT 24 |
Apr 18 12:34:19 PM PDT 24 |
4026801379 ps |
| T732 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1693532254 |
|
|
Apr 18 12:32:53 PM PDT 24 |
Apr 18 12:33:04 PM PDT 24 |
697102992 ps |
| T733 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1245320070 |
|
|
Apr 18 12:33:06 PM PDT 24 |
Apr 18 12:34:49 PM PDT 24 |
6982088334 ps |
| T734 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2776991933 |
|
|
Apr 18 02:08:41 PM PDT 24 |
Apr 18 02:08:50 PM PDT 24 |
167585677 ps |
| T92 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1440274974 |
|
|
Apr 18 02:08:24 PM PDT 24 |
Apr 18 02:11:13 PM PDT 24 |
41510525513 ps |
| T735 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2561879697 |
|
|
Apr 18 12:33:05 PM PDT 24 |
Apr 18 12:34:51 PM PDT 24 |
8584351423 ps |
| T736 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4076423820 |
|
|
Apr 18 12:33:06 PM PDT 24 |
Apr 18 12:33:29 PM PDT 24 |
7818042028 ps |
| T737 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4240250061 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:33:21 PM PDT 24 |
5963892401 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.751783118 |
|
|
Apr 18 12:33:00 PM PDT 24 |
Apr 18 12:34:36 PM PDT 24 |
3018698387 ps |
| T738 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2898044389 |
|
|
Apr 18 02:07:49 PM PDT 24 |
Apr 18 02:08:10 PM PDT 24 |
1729774819 ps |
| T739 |
/workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1056709085 |
|
|
Apr 18 12:32:50 PM PDT 24 |
Apr 18 12:33:14 PM PDT 24 |
21579608702 ps |
| T740 |
/workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3296455671 |
|
|
Apr 18 12:33:02 PM PDT 24 |
Apr 18 12:33:16 PM PDT 24 |
661614249 ps |
| T741 |
/workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2316171521 |
|
|
Apr 18 02:08:46 PM PDT 24 |
Apr 18 02:08:59 PM PDT 24 |
918152356 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2450261369 |
|
|
Apr 18 12:32:52 PM PDT 24 |
Apr 18 12:34:45 PM PDT 24 |
13012106870 ps |
| T742 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.997417024 |
|
|
Apr 18 12:32:47 PM PDT 24 |
Apr 18 12:33:34 PM PDT 24 |
5579856625 ps |
| T743 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1141594488 |
|
|
Apr 18 02:08:26 PM PDT 24 |
Apr 18 02:08:44 PM PDT 24 |
762714706 ps |
| T744 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1688828430 |
|
|
Apr 18 02:08:07 PM PDT 24 |
Apr 18 02:08:29 PM PDT 24 |
7323314503 ps |
| T745 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.217429295 |
|
|
Apr 18 12:32:51 PM PDT 24 |
Apr 18 12:33:20 PM PDT 24 |
3414213010 ps |
| T746 |
/workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3729443290 |
|
|
Apr 18 02:08:27 PM PDT 24 |
Apr 18 02:11:07 PM PDT 24 |
821182351 ps |
| T94 |
/workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2463275083 |
|
|
Apr 18 12:33:06 PM PDT 24 |
Apr 18 12:35:28 PM PDT 24 |
34361755313 ps |
| T747 |
/workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2826428465 |
|
|
Apr 18 02:08:39 PM PDT 24 |
Apr 18 02:08:48 PM PDT 24 |
661952828 ps |
| T748 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3564073359 |
|
|
Apr 18 12:32:44 PM PDT 24 |
Apr 18 12:33:12 PM PDT 24 |
2022897240 ps |
| T132 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3441670192 |
|
|
Apr 18 02:07:40 PM PDT 24 |
Apr 18 02:10:37 PM PDT 24 |
4045796437 ps |
| T749 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4098677830 |
|
|
Apr 18 02:08:07 PM PDT 24 |
Apr 18 02:08:23 PM PDT 24 |
4504936189 ps |
| T750 |
/workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1297581183 |
|
|
Apr 18 12:32:56 PM PDT 24 |
Apr 18 12:33:25 PM PDT 24 |
3496645608 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.714914851 |
|
|
Apr 18 12:32:49 PM PDT 24 |
Apr 18 12:34:59 PM PDT 24 |
15743735491 ps |
| T751 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2683741727 |
|
|
Apr 18 12:32:57 PM PDT 24 |
Apr 18 12:33:22 PM PDT 24 |
30009670912 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4244980962 |
|
|
Apr 18 12:32:46 PM PDT 24 |
Apr 18 12:35:23 PM PDT 24 |
63039262718 ps |
| T752 |
/workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1991817363 |
|
|
Apr 18 12:32:46 PM PDT 24 |
Apr 18 12:32:58 PM PDT 24 |
1712744954 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3726437247 |
|
|
Apr 18 02:07:57 PM PDT 24 |
Apr 18 02:08:13 PM PDT 24 |
4075569522 ps |
| T753 |
/workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.776133532 |
|
|
Apr 18 02:08:06 PM PDT 24 |
Apr 18 02:08:23 PM PDT 24 |
12310026980 ps |
| T754 |
/workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1652270434 |
|
|
Apr 18 02:07:49 PM PDT 24 |
Apr 18 02:08:23 PM PDT 24 |
4392643560 ps |
| T755 |
/workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2681654258 |
|
|
Apr 18 02:07:48 PM PDT 24 |
Apr 18 02:08:21 PM PDT 24 |
3896507400 ps |
| T756 |
/workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.670317805 |
|
|
Apr 18 02:08:08 PM PDT 24 |
Apr 18 02:08:28 PM PDT 24 |
5675888298 ps |