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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.51 96.96 92.97 97.88 100.00 98.36 98.04 98.37


Total test records in report: 913
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T757 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.692081415 Apr 18 12:32:48 PM PDT 24 Apr 18 12:33:10 PM PDT 24 8990228480 ps
T758 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2270534164 Apr 18 12:32:48 PM PDT 24 Apr 18 12:33:01 PM PDT 24 353151917 ps
T759 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3942294808 Apr 18 02:08:18 PM PDT 24 Apr 18 02:08:30 PM PDT 24 2057985948 ps
T760 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2190678089 Apr 18 12:32:37 PM PDT 24 Apr 18 12:32:55 PM PDT 24 5345186018 ps
T761 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3515536496 Apr 18 02:08:34 PM PDT 24 Apr 18 02:09:13 PM PDT 24 700295362 ps
T762 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1780469665 Apr 18 12:32:48 PM PDT 24 Apr 18 12:33:07 PM PDT 24 916582754 ps
T763 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.494056424 Apr 18 02:08:07 PM PDT 24 Apr 18 02:08:34 PM PDT 24 2451349102 ps
T764 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3226024921 Apr 18 02:08:55 PM PDT 24 Apr 18 02:09:06 PM PDT 24 525835734 ps
T765 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3318397692 Apr 18 02:08:44 PM PDT 24 Apr 18 02:08:54 PM PDT 24 394751629 ps
T766 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.229578951 Apr 18 12:32:50 PM PDT 24 Apr 18 12:33:09 PM PDT 24 6177641742 ps
T767 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2333166813 Apr 18 02:08:45 PM PDT 24 Apr 18 02:09:03 PM PDT 24 1503780659 ps
T125 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3954966012 Apr 18 02:08:18 PM PDT 24 Apr 18 02:09:52 PM PDT 24 4326480611 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.209055843 Apr 18 02:08:07 PM PDT 24 Apr 18 02:08:16 PM PDT 24 2354308232 ps
T768 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3721639318 Apr 18 02:07:58 PM PDT 24 Apr 18 02:08:22 PM PDT 24 1474615030 ps
T769 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3736235809 Apr 18 12:32:57 PM PDT 24 Apr 18 12:33:17 PM PDT 24 5288239147 ps
T770 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2647838814 Apr 18 02:07:51 PM PDT 24 Apr 18 02:08:25 PM PDT 24 6595195880 ps
T771 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1256835825 Apr 18 12:33:46 PM PDT 24 Apr 18 12:34:19 PM PDT 24 8766977872 ps
T772 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2327841820 Apr 18 12:32:49 PM PDT 24 Apr 18 12:33:10 PM PDT 24 2050863249 ps
T773 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2213957229 Apr 18 02:09:00 PM PDT 24 Apr 18 02:09:29 PM PDT 24 12824430723 ps
T774 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4173320098 Apr 18 02:07:36 PM PDT 24 Apr 18 02:08:05 PM PDT 24 2958704108 ps
T775 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2144780572 Apr 18 02:07:30 PM PDT 24 Apr 18 02:07:48 PM PDT 24 4292183284 ps
T776 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2388249152 Apr 18 12:32:36 PM PDT 24 Apr 18 12:32:57 PM PDT 24 4768330495 ps
T777 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3798357823 Apr 18 12:32:48 PM PDT 24 Apr 18 12:33:02 PM PDT 24 689438324 ps
T778 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2174048588 Apr 18 12:32:50 PM PDT 24 Apr 18 12:33:29 PM PDT 24 710495762 ps
T779 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3255096930 Apr 18 02:07:47 PM PDT 24 Apr 18 02:09:35 PM PDT 24 17538118861 ps
T780 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4209733403 Apr 18 12:33:06 PM PDT 24 Apr 18 12:33:40 PM PDT 24 17168133825 ps
T781 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.122860655 Apr 18 02:07:50 PM PDT 24 Apr 18 02:07:59 PM PDT 24 661514944 ps
T782 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4152539465 Apr 18 12:32:46 PM PDT 24 Apr 18 12:33:01 PM PDT 24 1840282611 ps
T783 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3012583711 Apr 18 12:32:49 PM PDT 24 Apr 18 12:33:47 PM PDT 24 1037893040 ps
T784 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.68488086 Apr 18 12:32:53 PM PDT 24 Apr 18 12:33:04 PM PDT 24 823000878 ps
T785 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.927189260 Apr 18 02:08:26 PM PDT 24 Apr 18 02:09:00 PM PDT 24 4103208459 ps
T786 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3015430530 Apr 18 12:33:54 PM PDT 24 Apr 18 12:34:24 PM PDT 24 3082876780 ps
T787 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3972844760 Apr 18 12:32:45 PM PDT 24 Apr 18 12:33:06 PM PDT 24 6914052662 ps
T788 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2652360121 Apr 18 12:32:56 PM PDT 24 Apr 18 12:33:06 PM PDT 24 169241966 ps
T789 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4012601605 Apr 18 02:07:41 PM PDT 24 Apr 18 02:08:15 PM PDT 24 16880336932 ps
T790 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.417501464 Apr 18 12:32:51 PM PDT 24 Apr 18 12:33:01 PM PDT 24 181905468 ps
T791 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3189150077 Apr 18 02:08:25 PM PDT 24 Apr 18 02:08:48 PM PDT 24 1902189180 ps
T792 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3776882332 Apr 18 12:32:49 PM PDT 24 Apr 18 12:34:17 PM PDT 24 1002848868 ps
T793 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4273447596 Apr 18 02:07:32 PM PDT 24 Apr 18 02:08:56 PM PDT 24 377366788 ps
T794 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3701151949 Apr 18 02:08:09 PM PDT 24 Apr 18 02:08:29 PM PDT 24 1889862317 ps
T795 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.849190098 Apr 18 12:32:52 PM PDT 24 Apr 18 12:33:20 PM PDT 24 3169758007 ps
T796 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3501195978 Apr 18 02:07:59 PM PDT 24 Apr 18 02:10:47 PM PDT 24 5819217843 ps
T797 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2766191460 Apr 18 02:08:50 PM PDT 24 Apr 18 02:09:18 PM PDT 24 2691411640 ps
T798 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.966671988 Apr 18 12:32:48 PM PDT 24 Apr 18 12:33:10 PM PDT 24 1407438305 ps
T799 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1882839329 Apr 18 02:08:26 PM PDT 24 Apr 18 02:09:58 PM PDT 24 8886446734 ps
T800 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3839636122 Apr 18 02:07:39 PM PDT 24 Apr 18 02:08:11 PM PDT 24 4082857487 ps
T801 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3634969347 Apr 18 02:08:36 PM PDT 24 Apr 18 02:09:07 PM PDT 24 11508171473 ps
T802 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1914919751 Apr 18 12:32:46 PM PDT 24 Apr 18 12:33:20 PM PDT 24 20275873145 ps
T803 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3785252628 Apr 18 02:08:17 PM PDT 24 Apr 18 02:09:37 PM PDT 24 3035260572 ps
T804 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2250431466 Apr 18 12:32:51 PM PDT 24 Apr 18 12:35:39 PM PDT 24 5109431933 ps
T805 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.280152404 Apr 18 12:32:51 PM PDT 24 Apr 18 12:33:09 PM PDT 24 3938788618 ps
T806 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1191488240 Apr 18 02:07:33 PM PDT 24 Apr 18 02:09:25 PM PDT 24 34973423265 ps
T807 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1242635844 Apr 18 02:08:17 PM PDT 24 Apr 18 02:08:49 PM PDT 24 13137390090 ps
T808 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1313837514 Apr 18 02:08:50 PM PDT 24 Apr 18 02:11:34 PM PDT 24 4741175150 ps
T809 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1827493287 Apr 18 02:08:45 PM PDT 24 Apr 18 02:09:01 PM PDT 24 6355035141 ps
T810 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.389671562 Apr 18 12:32:57 PM PDT 24 Apr 18 12:35:01 PM PDT 24 22701662673 ps
T811 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2587095172 Apr 18 02:08:00 PM PDT 24 Apr 18 02:08:56 PM PDT 24 4111537483 ps
T812 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1453853584 Apr 18 12:33:03 PM PDT 24 Apr 18 12:33:31 PM PDT 24 13934100601 ps
T813 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3275120672 Apr 18 12:32:48 PM PDT 24 Apr 18 12:33:00 PM PDT 24 392277110 ps
T814 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3489123131 Apr 18 12:33:01 PM PDT 24 Apr 18 12:33:27 PM PDT 24 3141349584 ps
T815 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1422110885 Apr 18 02:08:42 PM PDT 24 Apr 18 02:10:33 PM PDT 24 46008130554 ps
T816 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.503267472 Apr 18 02:07:59 PM PDT 24 Apr 18 02:08:17 PM PDT 24 1494972422 ps
T817 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.625671703 Apr 18 02:07:57 PM PDT 24 Apr 18 02:08:07 PM PDT 24 346247824 ps
T818 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1304382264 Apr 18 12:32:47 PM PDT 24 Apr 18 12:33:28 PM PDT 24 38676564899 ps
T819 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1121831820 Apr 18 12:32:47 PM PDT 24 Apr 18 12:33:07 PM PDT 24 1621119484 ps
T820 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3975286294 Apr 18 12:32:48 PM PDT 24 Apr 18 12:32:58 PM PDT 24 422609272 ps
T134 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3356332387 Apr 18 12:32:49 PM PDT 24 Apr 18 12:35:34 PM PDT 24 8354867484 ps
T821 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2969538148 Apr 18 02:08:06 PM PDT 24 Apr 18 02:08:18 PM PDT 24 1323509656 ps
T822 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1488225563 Apr 18 12:32:43 PM PDT 24 Apr 18 12:33:41 PM PDT 24 8566091106 ps
T823 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2378131149 Apr 18 02:08:18 PM PDT 24 Apr 18 02:08:37 PM PDT 24 1617754396 ps
T135 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.919421987 Apr 18 12:33:01 PM PDT 24 Apr 18 12:34:22 PM PDT 24 991625311 ps
T824 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1443368508 Apr 18 02:08:34 PM PDT 24 Apr 18 02:09:04 PM PDT 24 5510053664 ps
T825 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.107771987 Apr 18 12:32:49 PM PDT 24 Apr 18 12:33:03 PM PDT 24 169206476 ps
T826 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3786795021 Apr 18 12:33:00 PM PDT 24 Apr 18 12:33:29 PM PDT 24 3858544523 ps
T827 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1470092813 Apr 18 02:07:44 PM PDT 24 Apr 18 02:08:07 PM PDT 24 18253457194 ps
T828 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1654570490 Apr 18 02:07:40 PM PDT 24 Apr 18 02:11:00 PM PDT 24 98417557701 ps
T136 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.318080617 Apr 18 12:32:52 PM PDT 24 Apr 18 12:35:37 PM PDT 24 9738212942 ps
T829 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.919290641 Apr 18 02:07:43 PM PDT 24 Apr 18 02:08:06 PM PDT 24 4664915502 ps
T830 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.450410171 Apr 18 12:33:04 PM PDT 24 Apr 18 12:33:37 PM PDT 24 3487983638 ps
T831 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2396396961 Apr 18 02:08:52 PM PDT 24 Apr 18 02:09:21 PM PDT 24 3271319229 ps
T832 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.634981513 Apr 18 12:32:50 PM PDT 24 Apr 18 12:34:21 PM PDT 24 4566026338 ps
T833 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.940571377 Apr 18 02:08:06 PM PDT 24 Apr 18 02:08:30 PM PDT 24 7898514136 ps
T834 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3870969923 Apr 18 02:08:46 PM PDT 24 Apr 18 02:10:23 PM PDT 24 12883577683 ps
T835 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2931921821 Apr 18 02:08:52 PM PDT 24 Apr 18 02:11:06 PM PDT 24 107004716976 ps
T836 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3425007462 Apr 18 02:08:19 PM PDT 24 Apr 18 02:08:47 PM PDT 24 3466758382 ps
T837 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1340110494 Apr 18 02:08:49 PM PDT 24 Apr 18 02:09:46 PM PDT 24 2026425045 ps
T838 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.751898316 Apr 18 02:08:17 PM PDT 24 Apr 18 02:08:31 PM PDT 24 739399905 ps
T839 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2074751706 Apr 18 02:08:18 PM PDT 24 Apr 18 02:08:41 PM PDT 24 15819772790 ps
T840 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1057450482 Apr 18 12:32:44 PM PDT 24 Apr 18 12:33:09 PM PDT 24 2669995601 ps
T841 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.674308255 Apr 18 12:33:04 PM PDT 24 Apr 18 12:33:17 PM PDT 24 824126708 ps
T842 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.577056073 Apr 18 12:32:53 PM PDT 24 Apr 18 12:33:23 PM PDT 24 7224481952 ps
T843 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1725022164 Apr 18 02:08:52 PM PDT 24 Apr 18 02:09:27 PM PDT 24 4256211977 ps
T844 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.404370696 Apr 18 02:08:17 PM PDT 24 Apr 18 02:08:35 PM PDT 24 3418553109 ps
T845 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1146714205 Apr 18 12:32:51 PM PDT 24 Apr 18 12:33:08 PM PDT 24 1960294350 ps
T846 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1927784760 Apr 18 12:32:52 PM PDT 24 Apr 18 12:33:07 PM PDT 24 170910132 ps
T847 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.220793242 Apr 18 12:32:51 PM PDT 24 Apr 18 12:33:01 PM PDT 24 216402243 ps
T848 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1882201906 Apr 18 02:08:06 PM PDT 24 Apr 18 02:08:29 PM PDT 24 4473319825 ps
T849 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1744465760 Apr 18 12:32:44 PM PDT 24 Apr 18 12:33:15 PM PDT 24 12769653898 ps
T850 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3841712653 Apr 18 12:33:02 PM PDT 24 Apr 18 12:33:11 PM PDT 24 331997145 ps
T851 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1512111361 Apr 18 02:08:34 PM PDT 24 Apr 18 02:08:53 PM PDT 24 16461707009 ps
T852 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4243517160 Apr 18 02:08:07 PM PDT 24 Apr 18 02:08:38 PM PDT 24 49070411054 ps
T853 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3629445108 Apr 18 12:32:46 PM PDT 24 Apr 18 12:33:14 PM PDT 24 9194110115 ps
T854 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1011609908 Apr 18 02:08:35 PM PDT 24 Apr 18 02:10:30 PM PDT 24 52519881640 ps
T855 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2429490019 Apr 18 02:07:49 PM PDT 24 Apr 18 02:08:15 PM PDT 24 4324154924 ps
T856 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.214670903 Apr 18 02:08:44 PM PDT 24 Apr 18 02:09:04 PM PDT 24 16314826952 ps
T857 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.881549611 Apr 18 12:32:53 PM PDT 24 Apr 18 12:33:28 PM PDT 24 14674497196 ps
T858 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3088523094 Apr 18 02:07:50 PM PDT 24 Apr 18 02:07:59 PM PDT 24 1177328098 ps
T859 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2007279250 Apr 18 12:32:47 PM PDT 24 Apr 18 12:35:34 PM PDT 24 17778253195 ps
T860 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2646307656 Apr 18 12:34:03 PM PDT 24 Apr 18 12:34:35 PM PDT 24 3953212896 ps
T861 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2011919100 Apr 18 02:08:28 PM PDT 24 Apr 18 02:10:10 PM PDT 24 11053699240 ps
T862 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.391620034 Apr 18 02:08:24 PM PDT 24 Apr 18 02:08:42 PM PDT 24 3038146057 ps
T863 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1609799979 Apr 18 12:33:03 PM PDT 24 Apr 18 12:33:37 PM PDT 24 4367283943 ps
T864 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.635508718 Apr 18 12:32:52 PM PDT 24 Apr 18 12:33:27 PM PDT 24 42682832939 ps
T865 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3876894957 Apr 18 12:32:51 PM PDT 24 Apr 18 12:33:10 PM PDT 24 3656360914 ps
T866 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2786786416 Apr 18 02:07:56 PM PDT 24 Apr 18 02:08:27 PM PDT 24 3704414477 ps
T867 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2823961216 Apr 18 02:08:45 PM PDT 24 Apr 18 02:08:54 PM PDT 24 332136508 ps
T868 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1020131576 Apr 18 12:33:01 PM PDT 24 Apr 18 12:33:25 PM PDT 24 1721069066 ps
T869 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1512627306 Apr 18 12:32:46 PM PDT 24 Apr 18 12:33:11 PM PDT 24 12230799041 ps
T870 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3000426320 Apr 18 02:08:36 PM PDT 24 Apr 18 02:09:06 PM PDT 24 7798487567 ps
T871 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.965683225 Apr 18 12:33:17 PM PDT 24 Apr 18 12:33:44 PM PDT 24 5970657341 ps
T872 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1050011239 Apr 18 02:08:52 PM PDT 24 Apr 18 02:09:16 PM PDT 24 10626672351 ps
T873 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.391533557 Apr 18 12:32:51 PM PDT 24 Apr 18 12:33:13 PM PDT 24 1880226029 ps
T137 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.132365834 Apr 18 12:32:52 PM PDT 24 Apr 18 12:34:15 PM PDT 24 295120249 ps
T874 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.500725481 Apr 18 02:07:48 PM PDT 24 Apr 18 02:08:03 PM PDT 24 769702966 ps
T875 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3132517939 Apr 18 02:07:50 PM PDT 24 Apr 18 02:08:17 PM PDT 24 3188292657 ps
T876 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.810802625 Apr 18 12:32:58 PM PDT 24 Apr 18 12:33:27 PM PDT 24 7929737899 ps
T877 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1266269654 Apr 18 12:33:07 PM PDT 24 Apr 18 12:34:29 PM PDT 24 264233204 ps
T878 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2500602281 Apr 18 02:08:27 PM PDT 24 Apr 18 02:10:05 PM PDT 24 7159532100 ps
T879 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.985512262 Apr 18 02:07:50 PM PDT 24 Apr 18 02:08:03 PM PDT 24 2306374234 ps
T880 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3932787346 Apr 18 02:08:21 PM PDT 24 Apr 18 02:10:55 PM PDT 24 1173189146 ps
T881 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4074190727 Apr 18 12:32:44 PM PDT 24 Apr 18 12:35:19 PM PDT 24 358794097 ps
T882 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.800998304 Apr 18 02:07:57 PM PDT 24 Apr 18 02:08:22 PM PDT 24 11772105524 ps
T883 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3400369632 Apr 18 12:32:46 PM PDT 24 Apr 18 12:33:01 PM PDT 24 682530126 ps
T884 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3837289298 Apr 18 12:32:59 PM PDT 24 Apr 18 12:33:08 PM PDT 24 386104984 ps
T885 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.632794581 Apr 18 12:32:50 PM PDT 24 Apr 18 12:34:37 PM PDT 24 11503495420 ps
T886 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1548745043 Apr 18 02:08:43 PM PDT 24 Apr 18 02:09:13 PM PDT 24 15426113872 ps
T887 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2538031272 Apr 18 02:08:52 PM PDT 24 Apr 18 02:09:13 PM PDT 24 1443522428 ps
T888 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1579884736 Apr 18 12:32:57 PM PDT 24 Apr 18 12:35:57 PM PDT 24 84208105102 ps
T889 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3052054613 Apr 18 02:07:40 PM PDT 24 Apr 18 02:08:13 PM PDT 24 3939096925 ps
T890 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.86868912 Apr 18 02:08:54 PM PDT 24 Apr 18 02:11:27 PM PDT 24 1098385407 ps
T891 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1514467872 Apr 18 02:07:48 PM PDT 24 Apr 18 02:08:12 PM PDT 24 9234307982 ps
T892 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.892088798 Apr 18 02:08:44 PM PDT 24 Apr 18 02:09:07 PM PDT 24 9209109359 ps
T893 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3124868184 Apr 18 02:08:34 PM PDT 24 Apr 18 02:09:02 PM PDT 24 6655377507 ps
T894 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3773737719 Apr 18 02:08:26 PM PDT 24 Apr 18 02:10:20 PM PDT 24 48472645270 ps
T895 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2156075463 Apr 18 12:32:56 PM PDT 24 Apr 18 12:33:15 PM PDT 24 2462254412 ps
T896 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3206195309 Apr 18 12:32:46 PM PDT 24 Apr 18 12:33:19 PM PDT 24 13423635737 ps
T897 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.956586205 Apr 18 02:08:17 PM PDT 24 Apr 18 02:08:34 PM PDT 24 902805095 ps
T898 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3663913267 Apr 18 12:32:45 PM PDT 24 Apr 18 12:33:09 PM PDT 24 1613418306 ps
T899 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3132792716 Apr 18 12:32:46 PM PDT 24 Apr 18 12:33:15 PM PDT 24 3587606766 ps
T900 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2714881622 Apr 18 12:32:50 PM PDT 24 Apr 18 12:33:12 PM PDT 24 2460532794 ps
T901 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.573328400 Apr 18 12:32:44 PM PDT 24 Apr 18 12:33:12 PM PDT 24 14317847806 ps
T902 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3462946668 Apr 18 12:33:02 PM PDT 24 Apr 18 12:35:39 PM PDT 24 3158093867 ps
T903 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2143162334 Apr 18 02:07:57 PM PDT 24 Apr 18 02:08:23 PM PDT 24 10278527858 ps
T904 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4032392010 Apr 18 02:08:50 PM PDT 24 Apr 18 02:09:00 PM PDT 24 1769023585 ps
T905 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4175108459 Apr 18 02:08:25 PM PDT 24 Apr 18 02:08:57 PM PDT 24 7650874317 ps
T906 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1931068293 Apr 18 12:32:51 PM PDT 24 Apr 18 12:33:23 PM PDT 24 3021771651 ps
T907 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2824877234 Apr 18 12:32:48 PM PDT 24 Apr 18 12:35:37 PM PDT 24 5456937255 ps
T908 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2875153416 Apr 18 02:08:29 PM PDT 24 Apr 18 02:08:42 PM PDT 24 688741049 ps
T909 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1942177078 Apr 18 12:32:48 PM PDT 24 Apr 18 12:33:10 PM PDT 24 3952791581 ps
T910 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1484178663 Apr 18 12:32:39 PM PDT 24 Apr 18 12:32:56 PM PDT 24 14457525020 ps
T911 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2080039831 Apr 18 02:08:46 PM PDT 24 Apr 18 02:09:09 PM PDT 24 5084039402 ps
T912 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2298216766 Apr 18 02:08:24 PM PDT 24 Apr 18 02:11:18 PM PDT 24 10895938257 ps
T913 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2608733119 Apr 18 12:33:03 PM PDT 24 Apr 18 12:33:22 PM PDT 24 1298427465 ps

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.85981563
Short name T1
Test name
Test status
Simulation time 60112905682 ps
CPU time 633.93 seconds
Started Apr 18 02:06:50 PM PDT 24
Finished Apr 18 02:17:24 PM PDT 24
Peak memory 236712 kb
Host smart-dda519ed-eb6a-46a0-85a4-63222e3850ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85981563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_co
rrupt_sig_fatal_chk.85981563
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3067282013
Short name T12
Test name
Test status
Simulation time 20481127775 ps
CPU time 328.89 seconds
Started Apr 18 12:33:41 PM PDT 24
Finished Apr 18 12:39:11 PM PDT 24
Peak memory 228992 kb
Host smart-bdf107b1-0dad-442d-a1b2-0c36bbb8f846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067282013 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3067282013
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1834196960
Short name T15
Test name
Test status
Simulation time 306786226665 ps
CPU time 814.72 seconds
Started Apr 18 12:33:22 PM PDT 24
Finished Apr 18 12:46:58 PM PDT 24
Peak memory 216768 kb
Host smart-236096b6-1eb8-40e2-b9ce-402ed9a8594f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834196960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1834196960
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2520936017
Short name T438
Test name
Test status
Simulation time 48981809751 ps
CPU time 320.69 seconds
Started Apr 18 12:32:54 PM PDT 24
Finished Apr 18 12:38:17 PM PDT 24
Peak memory 237792 kb
Host smart-00a84133-ebd1-4666-87ce-676aec8aba45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520936017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2520936017
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.638662051
Short name T121
Test name
Test status
Simulation time 3138294790 ps
CPU time 168.43 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 213888 kb
Host smart-d465d627-8e93-44f7-864c-c3d3f4c8e5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638662051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.638662051
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3109373715
Short name T32
Test name
Test status
Simulation time 11063453856 ps
CPU time 238.15 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:36:53 PM PDT 24
Peak memory 237504 kb
Host smart-790c1c1f-bbc2-4b3e-bc00-ca3e9f914f53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109373715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3109373715
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3477220296
Short name T4
Test name
Test status
Simulation time 3183102753 ps
CPU time 43.9 seconds
Started Apr 18 12:33:10 PM PDT 24
Finished Apr 18 12:33:56 PM PDT 24
Peak memory 214988 kb
Host smart-edc66739-eea3-4a17-ba9a-f9f740b10f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477220296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3477220296
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1737539090
Short name T67
Test name
Test status
Simulation time 17948260417 ps
CPU time 158.22 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 215576 kb
Host smart-f36fba8e-2a44-4013-9573-6d494d8655df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737539090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1737539090
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2279934869
Short name T69
Test name
Test status
Simulation time 1146490440 ps
CPU time 16.05 seconds
Started Apr 18 12:33:32 PM PDT 24
Finished Apr 18 12:33:48 PM PDT 24
Peak memory 211364 kb
Host smart-46c15b6e-ba71-4d00-b771-c923b1ab1b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279934869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2279934869
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3755394012
Short name T123
Test name
Test status
Simulation time 7382824326 ps
CPU time 174.43 seconds
Started Apr 18 02:08:55 PM PDT 24
Finished Apr 18 02:11:49 PM PDT 24
Peak memory 215392 kb
Host smart-80096064-046a-4e60-b173-67dd407525c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755394012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3755394012
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2124371470
Short name T6
Test name
Test status
Simulation time 10615251659 ps
CPU time 65.77 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:35:11 PM PDT 24
Peak memory 213748 kb
Host smart-9f3fd6da-fa82-4836-8522-0ddb3abf6771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124371470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2124371470
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.980591819
Short name T182
Test name
Test status
Simulation time 892998295 ps
CPU time 18.74 seconds
Started Apr 18 12:33:08 PM PDT 24
Finished Apr 18 12:33:29 PM PDT 24
Peak memory 214692 kb
Host smart-ddb92bf5-37b9-4f5f-8416-97a8bc5355f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980591819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.980591819
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.132365834
Short name T137
Test name
Test status
Simulation time 295120249 ps
CPU time 80.45 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:34:15 PM PDT 24
Peak memory 213544 kb
Host smart-4295aa66-e19e-46fb-b5c7-6bac3efb4ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132365834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.132365834
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.401391709
Short name T74
Test name
Test status
Simulation time 121024704708 ps
CPU time 85.42 seconds
Started Apr 18 02:08:42 PM PDT 24
Finished Apr 18 02:10:08 PM PDT 24
Peak memory 213456 kb
Host smart-4fc38171-a86e-48c9-8b0e-ae6277cf47ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401391709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.401391709
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.84649556
Short name T89
Test name
Test status
Simulation time 15419720676 ps
CPU time 163.62 seconds
Started Apr 18 02:05:17 PM PDT 24
Finished Apr 18 02:08:01 PM PDT 24
Peak memory 220964 kb
Host smart-4a236d4b-977a-497a-bf87-9ea031aa8f6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84649556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.rom_ctrl_stress_all.84649556
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.783899496
Short name T29
Test name
Test status
Simulation time 294304806044 ps
CPU time 818.23 seconds
Started Apr 18 12:33:53 PM PDT 24
Finished Apr 18 12:47:34 PM PDT 24
Peak memory 216672 kb
Host smart-ead054bf-ea20-4e3e-b8ac-b1c334930788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783899496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.783899496
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4273447596
Short name T793
Test name
Test status
Simulation time 377366788 ps
CPU time 83.64 seconds
Started Apr 18 02:07:32 PM PDT 24
Finished Apr 18 02:08:56 PM PDT 24
Peak memory 213752 kb
Host smart-a074416a-5e4e-4a0b-b855-457ee28b7ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273447596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4273447596
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1185978652
Short name T101
Test name
Test status
Simulation time 15007081080 ps
CPU time 25.56 seconds
Started Apr 18 02:03:26 PM PDT 24
Finished Apr 18 02:03:51 PM PDT 24
Peak memory 211356 kb
Host smart-1fca6200-e5bc-4242-afb1-35aa394883d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185978652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1185978652
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.750384721
Short name T19
Test name
Test status
Simulation time 271402869650 ps
CPU time 2380.82 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 01:13:34 PM PDT 24
Peak memory 244072 kb
Host smart-5044c431-0fae-4af1-89f6-6eed4535df1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750384721 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.750384721
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1146714205
Short name T845
Test name
Test status
Simulation time 1960294350 ps
CPU time 14.11 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:08 PM PDT 24
Peak memory 211088 kb
Host smart-4b8e3d1c-67ad-4ae4-80fe-a39010ed4d9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146714205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1146714205
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4012601605
Short name T789
Test name
Test status
Simulation time 16880336932 ps
CPU time 33.6 seconds
Started Apr 18 02:07:41 PM PDT 24
Finished Apr 18 02:08:15 PM PDT 24
Peak memory 212284 kb
Host smart-7278bdb4-83e0-48ff-9f07-ce732e865ba4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012601605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4012601605
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1991817363
Short name T752
Test name
Test status
Simulation time 1712744954 ps
CPU time 11.15 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:32:58 PM PDT 24
Peak memory 211248 kb
Host smart-79de41b6-9e15-4b69-bef3-8eca3ae59afd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991817363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1991817363
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3839636122
Short name T800
Test name
Test status
Simulation time 4082857487 ps
CPU time 30.75 seconds
Started Apr 18 02:07:39 PM PDT 24
Finished Apr 18 02:08:11 PM PDT 24
Peak memory 211628 kb
Host smart-12075461-cdb8-4de2-8343-ce121bf42ddf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839636122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3839636122
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2388249152
Short name T776
Test name
Test status
Simulation time 4768330495 ps
CPU time 20.16 seconds
Started Apr 18 12:32:36 PM PDT 24
Finished Apr 18 12:32:57 PM PDT 24
Peak memory 212064 kb
Host smart-f4d0aa2e-935c-4f58-8906-6a74293733ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388249152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2388249152
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4082863200
Short name T116
Test name
Test status
Simulation time 1837720826 ps
CPU time 22.94 seconds
Started Apr 18 02:07:40 PM PDT 24
Finished Apr 18 02:08:04 PM PDT 24
Peak memory 211804 kb
Host smart-71fe0edf-a780-4d15-94ee-33bbf363f2ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082863200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4082863200
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2316248114
Short name T726
Test name
Test status
Simulation time 21559722041 ps
CPU time 27.99 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:33:16 PM PDT 24
Peak memory 218204 kb
Host smart-3f37fb9d-6fdd-4e70-a31e-3b0b80b93df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316248114 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2316248114
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3052054613
Short name T889
Test name
Test status
Simulation time 3939096925 ps
CPU time 32.14 seconds
Started Apr 18 02:07:40 PM PDT 24
Finished Apr 18 02:08:13 PM PDT 24
Peak memory 216060 kb
Host smart-80e2f78a-542e-43ec-9ddd-573720558bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052054613 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3052054613
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1470092813
Short name T827
Test name
Test status
Simulation time 18253457194 ps
CPU time 22.43 seconds
Started Apr 18 02:07:44 PM PDT 24
Finished Apr 18 02:08:07 PM PDT 24
Peak memory 211968 kb
Host smart-48e82c83-a585-46fb-ae28-c78b1ebae78c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470092813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1470092813
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.227962560
Short name T691
Test name
Test status
Simulation time 2664312524 ps
CPU time 23.5 seconds
Started Apr 18 12:32:43 PM PDT 24
Finished Apr 18 12:33:07 PM PDT 24
Peak memory 211372 kb
Host smart-1a57c053-d695-466b-9fab-a26dbe4d627d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227962560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.227962560
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1030442773
Short name T677
Test name
Test status
Simulation time 6480918375 ps
CPU time 26.58 seconds
Started Apr 18 02:07:31 PM PDT 24
Finished Apr 18 02:07:58 PM PDT 24
Peak memory 211100 kb
Host smart-1f8a970a-6117-4300-8e9f-de47f8d39d3c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030442773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1030442773
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1484178663
Short name T910
Test name
Test status
Simulation time 14457525020 ps
CPU time 16.22 seconds
Started Apr 18 12:32:39 PM PDT 24
Finished Apr 18 12:32:56 PM PDT 24
Peak memory 211052 kb
Host smart-9c94a72f-fab1-4843-968c-01841f27198a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484178663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1484178663
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2144780572
Short name T775
Test name
Test status
Simulation time 4292183284 ps
CPU time 16.86 seconds
Started Apr 18 02:07:30 PM PDT 24
Finished Apr 18 02:07:48 PM PDT 24
Peak memory 211312 kb
Host smart-52d87ba5-33b7-4bee-92ba-b70d7f1da931
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144780572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2144780572
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2327841820
Short name T772
Test name
Test status
Simulation time 2050863249 ps
CPU time 19.86 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 211044 kb
Host smart-67ef9ae7-fa80-4e46-8e33-8f807b320d4e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327841820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2327841820
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1191488240
Short name T806
Test name
Test status
Simulation time 34973423265 ps
CPU time 111.6 seconds
Started Apr 18 02:07:33 PM PDT 24
Finished Apr 18 02:09:25 PM PDT 24
Peak memory 215576 kb
Host smart-9e628ae9-c307-45d7-9257-eef7f3d13438
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191488240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1191488240
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4244980962
Short name T96
Test name
Test status
Simulation time 63039262718 ps
CPU time 155.67 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:35:23 PM PDT 24
Peak memory 215440 kb
Host smart-cb5b62ef-518f-4714-b9a6-6becd0a5bdd5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244980962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4244980962
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3663913267
Short name T898
Test name
Test status
Simulation time 1613418306 ps
CPU time 17.93 seconds
Started Apr 18 12:32:45 PM PDT 24
Finished Apr 18 12:33:09 PM PDT 24
Peak memory 211916 kb
Host smart-2ce4412a-eb50-4971-888c-06861fe22f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663913267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3663913267
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.919290641
Short name T829
Test name
Test status
Simulation time 4664915502 ps
CPU time 22.88 seconds
Started Apr 18 02:07:43 PM PDT 24
Finished Apr 18 02:08:06 PM PDT 24
Peak memory 212680 kb
Host smart-05f36678-12c1-42b7-9451-08818a9fb4e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919290641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.919290641
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3798357823
Short name T777
Test name
Test status
Simulation time 689438324 ps
CPU time 12.16 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:02 PM PDT 24
Peak memory 217296 kb
Host smart-44c4453d-8557-4cf1-bcc4-e8f797289d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798357823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3798357823
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4173320098
Short name T774
Test name
Test status
Simulation time 2958704108 ps
CPU time 28.75 seconds
Started Apr 18 02:07:36 PM PDT 24
Finished Apr 18 02:08:05 PM PDT 24
Peak memory 218544 kb
Host smart-62dffd2f-be38-4f19-8be4-316120b1ba04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173320098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4173320098
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4074190727
Short name T881
Test name
Test status
Simulation time 358794097 ps
CPU time 154.13 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:35:19 PM PDT 24
Peak memory 213896 kb
Host smart-42c73c27-6699-4e65-aa45-745ec80d28a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074190727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4074190727
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2492073285
Short name T709
Test name
Test status
Simulation time 3153230900 ps
CPU time 26.17 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:14 PM PDT 24
Peak memory 211268 kb
Host smart-506eb0d9-9c9c-421b-8de8-50115323418a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492073285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2492073285
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.500725481
Short name T874
Test name
Test status
Simulation time 769702966 ps
CPU time 13.37 seconds
Started Apr 18 02:07:48 PM PDT 24
Finished Apr 18 02:08:03 PM PDT 24
Peak memory 211332 kb
Host smart-d515efc5-8339-4e39-bfdc-dd9d0f5240b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500725481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.500725481
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.160715028
Short name T682
Test name
Test status
Simulation time 7180953582 ps
CPU time 29.08 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:17 PM PDT 24
Peak memory 211772 kb
Host smart-141dea17-02e8-4398-b630-cae90e0f1a89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160715028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.160715028
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4183756731
Short name T694
Test name
Test status
Simulation time 331717326 ps
CPU time 8.48 seconds
Started Apr 18 02:07:52 PM PDT 24
Finished Apr 18 02:08:01 PM PDT 24
Peak memory 211228 kb
Host smart-36c7721f-d0c2-41f0-a344-88b1b412ee2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183756731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4183756731
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2647838814
Short name T770
Test name
Test status
Simulation time 6595195880 ps
CPU time 32.85 seconds
Started Apr 18 02:07:51 PM PDT 24
Finished Apr 18 02:08:25 PM PDT 24
Peak memory 212176 kb
Host smart-f337207a-c1b0-4118-be32-90ad7c22bb1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647838814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2647838814
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3908012563
Short name T722
Test name
Test status
Simulation time 8245665445 ps
CPU time 24.19 seconds
Started Apr 18 12:32:33 PM PDT 24
Finished Apr 18 12:32:58 PM PDT 24
Peak memory 211836 kb
Host smart-0f695a0f-d3ea-4d18-8f0d-cb4165f154a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908012563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3908012563
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3132517939
Short name T875
Test name
Test status
Simulation time 3188292657 ps
CPU time 26.99 seconds
Started Apr 18 02:07:50 PM PDT 24
Finished Apr 18 02:08:17 PM PDT 24
Peak memory 214612 kb
Host smart-95e91d4f-b1e9-4ec0-896e-55d1a940bab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132517939 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3132517939
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.692081415
Short name T757
Test name
Test status
Simulation time 8990228480 ps
CPU time 20.59 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 218480 kb
Host smart-65d9647f-a845-4caa-99f1-2b429471567c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692081415 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.692081415
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1652270434
Short name T754
Test name
Test status
Simulation time 4392643560 ps
CPU time 32.47 seconds
Started Apr 18 02:07:49 PM PDT 24
Finished Apr 18 02:08:23 PM PDT 24
Peak memory 211792 kb
Host smart-cbfb5797-45de-457e-a0d8-ff2f768e4039
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652270434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1652270434
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4152539465
Short name T782
Test name
Test status
Simulation time 1840282611 ps
CPU time 13.97 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:01 PM PDT 24
Peak memory 211112 kb
Host smart-6bbd5e6a-bbb2-45f3-823e-5998a7f09250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152539465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4152539465
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2190678089
Short name T760
Test name
Test status
Simulation time 5345186018 ps
CPU time 17.61 seconds
Started Apr 18 12:32:37 PM PDT 24
Finished Apr 18 12:32:55 PM PDT 24
Peak memory 211048 kb
Host smart-32c56d7e-0a9a-458a-b02b-89bfffa98a64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190678089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2190678089
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.985512262
Short name T879
Test name
Test status
Simulation time 2306374234 ps
CPU time 12.37 seconds
Started Apr 18 02:07:50 PM PDT 24
Finished Apr 18 02:08:03 PM PDT 24
Peak memory 211264 kb
Host smart-c90c67ef-f945-4eed-bc26-346c42889af8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985512262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.985512262
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3088523094
Short name T858
Test name
Test status
Simulation time 1177328098 ps
CPU time 8 seconds
Started Apr 18 02:07:50 PM PDT 24
Finished Apr 18 02:07:59 PM PDT 24
Peak memory 211264 kb
Host smart-06d355a4-9cc5-45b0-9de5-cf45e5be60ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088523094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3088523094
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3972844760
Short name T787
Test name
Test status
Simulation time 6914052662 ps
CPU time 18.97 seconds
Started Apr 18 12:32:45 PM PDT 24
Finished Apr 18 12:33:06 PM PDT 24
Peak memory 211112 kb
Host smart-e36b28bb-ccbe-42d6-add3-2f8c9822feb9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972844760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3972844760
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1654570490
Short name T828
Test name
Test status
Simulation time 98417557701 ps
CPU time 199.69 seconds
Started Apr 18 02:07:40 PM PDT 24
Finished Apr 18 02:11:00 PM PDT 24
Peak memory 215476 kb
Host smart-7ee021a2-34bc-412f-b044-d299324061c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654570490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1654570490
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2724192115
Short name T730
Test name
Test status
Simulation time 1429138276 ps
CPU time 37.49 seconds
Started Apr 18 12:32:43 PM PDT 24
Finished Apr 18 12:33:21 PM PDT 24
Peak memory 213220 kb
Host smart-f09eeffa-5a38-4242-aeb3-a36866bb28ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724192115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2724192115
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1057450482
Short name T840
Test name
Test status
Simulation time 2669995601 ps
CPU time 23.15 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:33:09 PM PDT 24
Peak memory 212108 kb
Host smart-b8dfdbce-a079-4994-a1a2-58445371613a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057450482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1057450482
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.567184514
Short name T720
Test name
Test status
Simulation time 6669998424 ps
CPU time 26.32 seconds
Started Apr 18 02:07:49 PM PDT 24
Finished Apr 18 02:08:16 PM PDT 24
Peak memory 212732 kb
Host smart-acc5d0c7-f66f-40e5-814c-d3f7a434435e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567184514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.567184514
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1130539948
Short name T684
Test name
Test status
Simulation time 9135611416 ps
CPU time 26.04 seconds
Started Apr 18 02:07:40 PM PDT 24
Finished Apr 18 02:08:07 PM PDT 24
Peak memory 218464 kb
Host smart-c5bba85e-bb58-438a-9d96-52f0d5e87e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130539948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1130539948
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3564073359
Short name T748
Test name
Test status
Simulation time 2022897240 ps
CPU time 26.66 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:33:12 PM PDT 24
Peak memory 218560 kb
Host smart-f92f3ad2-5ac4-4121-854e-a827fd57ff32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564073359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3564073359
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.26639382
Short name T133
Test name
Test status
Simulation time 455427569 ps
CPU time 81.43 seconds
Started Apr 18 12:32:43 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 213212 kb
Host smart-62334e2f-6cef-4f12-be64-cb29d294cb51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg
_err.26639382
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3441670192
Short name T132
Test name
Test status
Simulation time 4045796437 ps
CPU time 176.35 seconds
Started Apr 18 02:07:40 PM PDT 24
Finished Apr 18 02:10:37 PM PDT 24
Peak memory 213852 kb
Host smart-67b3b7df-0f96-4f0f-92a3-18e111f6610c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441670192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3441670192
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1693532254
Short name T732
Test name
Test status
Simulation time 697102992 ps
CPU time 9.61 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:04 PM PDT 24
Peak memory 217140 kb
Host smart-de55fa40-0949-4169-84b1-f70ed3f984b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693532254 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1693532254
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.391620034
Short name T862
Test name
Test status
Simulation time 3038146057 ps
CPU time 17.72 seconds
Started Apr 18 02:08:24 PM PDT 24
Finished Apr 18 02:08:42 PM PDT 24
Peak memory 213848 kb
Host smart-b23d391b-b9c1-4e13-8716-1d2a1538ade2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391620034 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.391620034
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1256835825
Short name T771
Test name
Test status
Simulation time 8766977872 ps
CPU time 31.46 seconds
Started Apr 18 12:33:46 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 211672 kb
Host smart-763c8524-2256-483c-9b37-4154636f793f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256835825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1256835825
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2776991933
Short name T734
Test name
Test status
Simulation time 167585677 ps
CPU time 8.13 seconds
Started Apr 18 02:08:41 PM PDT 24
Finished Apr 18 02:08:50 PM PDT 24
Peak memory 211272 kb
Host smart-fc311bbf-90e5-4baf-aee3-33a88cd0d5d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776991933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2776991933
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2500602281
Short name T878
Test name
Test status
Simulation time 7159532100 ps
CPU time 96.95 seconds
Started Apr 18 02:08:27 PM PDT 24
Finished Apr 18 02:10:05 PM PDT 24
Peak memory 215564 kb
Host smart-d203c533-8d8f-4b94-9aff-7a4907a0e2db
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500602281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2500602281
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.634981513
Short name T832
Test name
Test status
Simulation time 4566026338 ps
CPU time 89.06 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:34:21 PM PDT 24
Peak memory 215740 kb
Host smart-74728d5d-45e3-4899-8af2-c6c94f3e142b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634981513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.634981513
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1390523734
Short name T704
Test name
Test status
Simulation time 12141186253 ps
CPU time 29.8 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:33:34 PM PDT 24
Peak memory 212700 kb
Host smart-45a40cd5-7b3c-4f11-aa58-788c417cdc94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390523734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1390523734
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3189150077
Short name T791
Test name
Test status
Simulation time 1902189180 ps
CPU time 23.18 seconds
Started Apr 18 02:08:25 PM PDT 24
Finished Apr 18 02:08:48 PM PDT 24
Peak memory 212424 kb
Host smart-9d4db925-e5c0-4246-b54d-6a49d9655560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189150077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3189150077
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1141594488
Short name T743
Test name
Test status
Simulation time 762714706 ps
CPU time 17.92 seconds
Started Apr 18 02:08:26 PM PDT 24
Finished Apr 18 02:08:44 PM PDT 24
Peak memory 218672 kb
Host smart-2281a187-457d-4702-931b-6a73eb2fabab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141594488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1141594488
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.810802625
Short name T876
Test name
Test status
Simulation time 7929737899 ps
CPU time 28.42 seconds
Started Apr 18 12:32:58 PM PDT 24
Finished Apr 18 12:33:27 PM PDT 24
Peak memory 218888 kb
Host smart-f6adfecc-f3cb-4358-bc86-66cbf2ee6ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810802625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.810802625
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3729443290
Short name T746
Test name
Test status
Simulation time 821182351 ps
CPU time 158.87 seconds
Started Apr 18 02:08:27 PM PDT 24
Finished Apr 18 02:11:07 PM PDT 24
Peak memory 213940 kb
Host smart-a21f4ba4-1788-40aa-ae14-c9d5ab00c6ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729443290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3729443290
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.927189260
Short name T785
Test name
Test status
Simulation time 4103208459 ps
CPU time 32.77 seconds
Started Apr 18 02:08:26 PM PDT 24
Finished Apr 18 02:09:00 PM PDT 24
Peak memory 216816 kb
Host smart-219380ea-b502-49ef-93f6-b92e1afba27a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927189260 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.927189260
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.965683225
Short name T871
Test name
Test status
Simulation time 5970657341 ps
CPU time 26.14 seconds
Started Apr 18 12:33:17 PM PDT 24
Finished Apr 18 12:33:44 PM PDT 24
Peak memory 218080 kb
Host smart-751fd0d4-c297-46a1-b1a7-765aa670e974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965683225 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.965683225
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2098407660
Short name T98
Test name
Test status
Simulation time 16378525813 ps
CPU time 34.24 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:33:23 PM PDT 24
Peak memory 212224 kb
Host smart-e490ce0d-ba32-4ff4-a557-8b0dd41b8d83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098407660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2098407660
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4175108459
Short name T905
Test name
Test status
Simulation time 7650874317 ps
CPU time 30.93 seconds
Started Apr 18 02:08:25 PM PDT 24
Finished Apr 18 02:08:57 PM PDT 24
Peak memory 212448 kb
Host smart-c748ec7b-ef5e-43c7-8815-260e5e48d0dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175108459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4175108459
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3773737719
Short name T894
Test name
Test status
Simulation time 48472645270 ps
CPU time 113.1 seconds
Started Apr 18 02:08:26 PM PDT 24
Finished Apr 18 02:10:20 PM PDT 24
Peak memory 219532 kb
Host smart-a8ed9a67-66a6-408d-ac95-3393486b4cfe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773737719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3773737719
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.714914851
Short name T95
Test name
Test status
Simulation time 15743735491 ps
CPU time 128.29 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 214276 kb
Host smart-3309b41f-87c8-4957-88a8-119641cc4a69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714914851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.714914851
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2646307656
Short name T860
Test name
Test status
Simulation time 3953212896 ps
CPU time 29.69 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:34:35 PM PDT 24
Peak memory 211616 kb
Host smart-a5a56d8e-951b-4409-8367-c9d0aab31f48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646307656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2646307656
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3669012855
Short name T702
Test name
Test status
Simulation time 2228693819 ps
CPU time 22.76 seconds
Started Apr 18 02:08:25 PM PDT 24
Finished Apr 18 02:08:48 PM PDT 24
Peak memory 212364 kb
Host smart-d5a02491-b105-4f5e-84d1-948fba2709df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669012855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3669012855
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1020131576
Short name T868
Test name
Test status
Simulation time 1721069066 ps
CPU time 22.11 seconds
Started Apr 18 12:33:01 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 218380 kb
Host smart-26252f11-5a8d-4649-88b6-2a4cd058e0ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020131576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1020131576
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2875153416
Short name T908
Test name
Test status
Simulation time 688741049 ps
CPU time 12.71 seconds
Started Apr 18 02:08:29 PM PDT 24
Finished Apr 18 02:08:42 PM PDT 24
Peak memory 217452 kb
Host smart-5160cc6f-f8ed-4506-b147-4852d376c29d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875153416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2875153416
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1882839329
Short name T799
Test name
Test status
Simulation time 8886446734 ps
CPU time 92.06 seconds
Started Apr 18 02:08:26 PM PDT 24
Finished Apr 18 02:09:58 PM PDT 24
Peak memory 214976 kb
Host smart-82cd83a3-524c-4bd3-acdd-af11954ef637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882839329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1882839329
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3356332387
Short name T134
Test name
Test status
Simulation time 8354867484 ps
CPU time 163.67 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 214056 kb
Host smart-ef7233af-5fe6-45fe-9f6a-4b0d3a38366c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356332387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3356332387
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2408098602
Short name T727
Test name
Test status
Simulation time 1890285119 ps
CPU time 11.22 seconds
Started Apr 18 02:08:34 PM PDT 24
Finished Apr 18 02:08:45 PM PDT 24
Peak memory 215884 kb
Host smart-5c601679-20bf-4b34-a1d4-4d5920738eea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408098602 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2408098602
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.568455277
Short name T683
Test name
Test status
Simulation time 4299602385 ps
CPU time 34.15 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:26 PM PDT 24
Peak memory 218368 kb
Host smart-83094c7d-433a-4f20-992f-8a196a8c4bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568455277 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.568455277
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.223674854
Short name T66
Test name
Test status
Simulation time 5237918662 ps
CPU time 22.65 seconds
Started Apr 18 02:08:26 PM PDT 24
Finished Apr 18 02:08:50 PM PDT 24
Peak memory 212284 kb
Host smart-78bbf241-56bf-4540-9851-f587fca2a9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223674854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.223674854
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2832547822
Short name T717
Test name
Test status
Simulation time 353213254 ps
CPU time 7.69 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 210896 kb
Host smart-e22763ff-9b4f-40ee-b2db-7cfb6c9e3270
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832547822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2832547822
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1440274974
Short name T92
Test name
Test status
Simulation time 41510525513 ps
CPU time 168.05 seconds
Started Apr 18 02:08:24 PM PDT 24
Finished Apr 18 02:11:13 PM PDT 24
Peak memory 215508 kb
Host smart-c0099c40-e02e-4216-a4eb-c81f3d355684
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440274974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1440274974
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1297061334
Short name T114
Test name
Test status
Simulation time 7847717925 ps
CPU time 21.48 seconds
Started Apr 18 02:08:35 PM PDT 24
Finished Apr 18 02:08:57 PM PDT 24
Peak memory 212796 kb
Host smart-6c05344e-16b5-4866-b13f-6010065c9a91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297061334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1297061334
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3971709933
Short name T703
Test name
Test status
Simulation time 12831621111 ps
CPU time 27.32 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 212344 kb
Host smart-2e51aa0e-0d47-4b37-9ab2-b0fbe64faace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971709933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3971709933
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1512111361
Short name T851
Test name
Test status
Simulation time 16461707009 ps
CPU time 18.52 seconds
Started Apr 18 02:08:34 PM PDT 24
Finished Apr 18 02:08:53 PM PDT 24
Peak memory 218760 kb
Host smart-70c1c969-dd8d-417d-8969-f1d0f3e92637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512111361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1512111361
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4168657327
Short name T712
Test name
Test status
Simulation time 6482906546 ps
CPU time 21.18 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:25 PM PDT 24
Peak memory 218444 kb
Host smart-eea0df32-2bf4-4085-9f6a-0b23781fd6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168657327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4168657327
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2298216766
Short name T912
Test name
Test status
Simulation time 10895938257 ps
CPU time 173.44 seconds
Started Apr 18 02:08:24 PM PDT 24
Finished Apr 18 02:11:18 PM PDT 24
Peak memory 214188 kb
Host smart-ffdd9ef1-27b1-4d92-a0c1-91da1b615b37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298216766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2298216766
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.751783118
Short name T131
Test name
Test status
Simulation time 3018698387 ps
CPU time 95.43 seconds
Started Apr 18 12:33:00 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 214228 kb
Host smart-706c468c-5627-4e1e-8155-46fbd1c46f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751783118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.751783118
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3000426320
Short name T870
Test name
Test status
Simulation time 7798487567 ps
CPU time 30.5 seconds
Started Apr 18 02:08:36 PM PDT 24
Finished Apr 18 02:09:06 PM PDT 24
Peak memory 217396 kb
Host smart-c796b052-d0d5-455b-94ca-26132713117a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000426320 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3000426320
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.417501464
Short name T790
Test name
Test status
Simulation time 181905468 ps
CPU time 8.83 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:01 PM PDT 24
Peak memory 217128 kb
Host smart-9b48f29a-a78f-4f72-9028-57a43cac2990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417501464 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.417501464
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1148584570
Short name T707
Test name
Test status
Simulation time 4447580947 ps
CPU time 33.11 seconds
Started Apr 18 02:08:33 PM PDT 24
Finished Apr 18 02:09:06 PM PDT 24
Peak memory 211856 kb
Host smart-9b1d0754-c3ec-49cc-b919-84dafd6e1403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148584570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1148584570
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4112294773
Short name T731
Test name
Test status
Simulation time 4026801379 ps
CPU time 29.54 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 211336 kb
Host smart-a693288a-5137-4e05-b111-476a5298f011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112294773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4112294773
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1011609908
Short name T854
Test name
Test status
Simulation time 52519881640 ps
CPU time 114.58 seconds
Started Apr 18 02:08:35 PM PDT 24
Finished Apr 18 02:10:30 PM PDT 24
Peak memory 214356 kb
Host smart-e6e750e1-14b1-45e3-bdf5-4d7213cc2c95
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011609908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1011609908
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.389671562
Short name T810
Test name
Test status
Simulation time 22701662673 ps
CPU time 123.36 seconds
Started Apr 18 12:32:57 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 219428 kb
Host smart-902183ab-94ae-45f2-acea-7f0e84cd5921
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389671562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.389671562
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.280152404
Short name T805
Test name
Test status
Simulation time 3938788618 ps
CPU time 15.26 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:09 PM PDT 24
Peak memory 211452 kb
Host smart-e617583b-c2d9-49d4-b080-98fe741dcbb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280152404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.280152404
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3124868184
Short name T893
Test name
Test status
Simulation time 6655377507 ps
CPU time 28.07 seconds
Started Apr 18 02:08:34 PM PDT 24
Finished Apr 18 02:09:02 PM PDT 24
Peak memory 211264 kb
Host smart-b62a3a03-40d6-41e1-b598-6e219e5cbde2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124868184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3124868184
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1151327558
Short name T688
Test name
Test status
Simulation time 688953562 ps
CPU time 12.72 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:05 PM PDT 24
Peak memory 217556 kb
Host smart-64bafd8e-3817-418b-a6ff-d981e148dee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151327558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1151327558
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3634969347
Short name T801
Test name
Test status
Simulation time 11508171473 ps
CPU time 30.64 seconds
Started Apr 18 02:08:36 PM PDT 24
Finished Apr 18 02:09:07 PM PDT 24
Peak memory 218828 kb
Host smart-de525707-5cd9-497e-a928-39c88a1d6599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634969347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3634969347
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2250431466
Short name T804
Test name
Test status
Simulation time 5109431933 ps
CPU time 165.57 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 214136 kb
Host smart-60415b08-e3f1-49d9-b79c-218d0b869f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250431466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2250431466
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3576641204
Short name T127
Test name
Test status
Simulation time 10649726615 ps
CPU time 164.9 seconds
Started Apr 18 02:08:35 PM PDT 24
Finished Apr 18 02:11:20 PM PDT 24
Peak memory 214224 kb
Host smart-fad44776-ce0f-488f-8bf1-dcc029cdc96e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576641204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3576641204
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1056709085
Short name T739
Test name
Test status
Simulation time 21579608702 ps
CPU time 22.41 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:14 PM PDT 24
Peak memory 217460 kb
Host smart-5d0db4f6-8bea-4b0d-90c6-46fdd7938ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056709085 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1056709085
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1548745043
Short name T886
Test name
Test status
Simulation time 15426113872 ps
CPU time 30.19 seconds
Started Apr 18 02:08:43 PM PDT 24
Finished Apr 18 02:09:13 PM PDT 24
Peak memory 217468 kb
Host smart-e6d7e52e-33bc-4ea8-ae44-12756ca09e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548745043 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1548745043
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2400614827
Short name T690
Test name
Test status
Simulation time 1174874351 ps
CPU time 9.86 seconds
Started Apr 18 02:08:44 PM PDT 24
Finished Apr 18 02:08:54 PM PDT 24
Peak memory 211296 kb
Host smart-d4692013-4fba-41bb-ad2b-f1956c2157e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400614827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2400614827
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.674308255
Short name T841
Test name
Test status
Simulation time 824126708 ps
CPU time 11.21 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:33:17 PM PDT 24
Peak memory 211084 kb
Host smart-a3134d79-0c1b-433a-8a7d-5314bdbd3f66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674308255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.674308255
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3515536496
Short name T761
Test name
Test status
Simulation time 700295362 ps
CPU time 38.69 seconds
Started Apr 18 02:08:34 PM PDT 24
Finished Apr 18 02:09:13 PM PDT 24
Peak memory 213496 kb
Host smart-2f738b49-108c-4229-a9a6-613e42f706a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515536496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3515536496
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3930925533
Short name T78
Test name
Test status
Simulation time 13136958948 ps
CPU time 115.12 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:34:46 PM PDT 24
Peak memory 214292 kb
Host smart-c4c15595-801a-496f-9bfe-f2135dbd31ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930925533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3930925533
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.214670903
Short name T856
Test name
Test status
Simulation time 16314826952 ps
CPU time 19.99 seconds
Started Apr 18 02:08:44 PM PDT 24
Finished Apr 18 02:09:04 PM PDT 24
Peak memory 212712 kb
Host smart-29f698d1-f085-4714-a45c-2291e00a73ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214670903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.214670903
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2714881622
Short name T900
Test name
Test status
Simulation time 2460532794 ps
CPU time 20.22 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:12 PM PDT 24
Peak memory 212176 kb
Host smart-7d484d5c-09b5-4ba9-bc18-49f9bfff1e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714881622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2714881622
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1443368508
Short name T824
Test name
Test status
Simulation time 5510053664 ps
CPU time 28.88 seconds
Started Apr 18 02:08:34 PM PDT 24
Finished Apr 18 02:09:04 PM PDT 24
Peak memory 217872 kb
Host smart-5799fd32-3061-4da5-afb0-78395a468c75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443368508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1443368508
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2048401148
Short name T693
Test name
Test status
Simulation time 16857532020 ps
CPU time 32.93 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:27 PM PDT 24
Peak memory 217512 kb
Host smart-cfeaec47-142a-46c5-bfae-4cb8e1811a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048401148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2048401148
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2133427582
Short name T126
Test name
Test status
Simulation time 10189219388 ps
CPU time 88.82 seconds
Started Apr 18 02:08:35 PM PDT 24
Finished Apr 18 02:10:04 PM PDT 24
Peak memory 214820 kb
Host smart-12f07b44-c7b3-43ff-ae25-94b290db1c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133427582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2133427582
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3734709213
Short name T65
Test name
Test status
Simulation time 5569172260 ps
CPU time 95.4 seconds
Started Apr 18 12:32:55 PM PDT 24
Finished Apr 18 12:34:32 PM PDT 24
Peak memory 213708 kb
Host smart-219f654d-4781-4e75-84ec-c1a33aae29b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734709213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3734709213
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3318397692
Short name T765
Test name
Test status
Simulation time 394751629 ps
CPU time 9.09 seconds
Started Apr 18 02:08:44 PM PDT 24
Finished Apr 18 02:08:54 PM PDT 24
Peak memory 216920 kb
Host smart-992d0cf2-828a-4c52-97b1-d94fcf84c517
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318397692 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3318397692
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.635508718
Short name T864
Test name
Test status
Simulation time 42682832939 ps
CPU time 33.52 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:27 PM PDT 24
Peak memory 218400 kb
Host smart-51e3dbe1-b6f3-4001-9d79-16d1f76a1d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635508718 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.635508718
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1453853584
Short name T812
Test name
Test status
Simulation time 13934100601 ps
CPU time 26.84 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:33:31 PM PDT 24
Peak memory 212292 kb
Host smart-87caa55c-1698-4b8f-bdc0-f102e77c44b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453853584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1453853584
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.892088798
Short name T892
Test name
Test status
Simulation time 9209109359 ps
CPU time 22.05 seconds
Started Apr 18 02:08:44 PM PDT 24
Finished Apr 18 02:09:07 PM PDT 24
Peak memory 211920 kb
Host smart-befe11a6-b485-440e-92d4-cff36608b800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892088798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.892088798
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1422110885
Short name T815
Test name
Test status
Simulation time 46008130554 ps
CPU time 110.09 seconds
Started Apr 18 02:08:42 PM PDT 24
Finished Apr 18 02:10:33 PM PDT 24
Peak memory 214460 kb
Host smart-664020cf-312c-4f49-ae7c-76639a11fb7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422110885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1422110885
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2737635394
Short name T721
Test name
Test status
Simulation time 177386553857 ps
CPU time 113.29 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 215400 kb
Host smart-1f46dc09-3849-40f9-95af-5787b688acef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737635394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2737635394
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1240143365
Short name T705
Test name
Test status
Simulation time 2983460011 ps
CPU time 16.95 seconds
Started Apr 18 02:08:43 PM PDT 24
Finished Apr 18 02:09:00 PM PDT 24
Peak memory 212520 kb
Host smart-2f8faec7-56cd-49bc-83f1-d5cd8762a972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240143365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1240143365
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3876894957
Short name T865
Test name
Test status
Simulation time 3656360914 ps
CPU time 17.03 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 212548 kb
Host smart-dd9ccd66-e86b-4f98-ae79-1c6520127ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876894957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3876894957
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2333166813
Short name T767
Test name
Test status
Simulation time 1503780659 ps
CPU time 18.04 seconds
Started Apr 18 02:08:45 PM PDT 24
Finished Apr 18 02:09:03 PM PDT 24
Peak memory 217632 kb
Host smart-2e5281bd-f783-4433-9b97-0e0f0ec42c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333166813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2333166813
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3296455671
Short name T740
Test name
Test status
Simulation time 661614249 ps
CPU time 12.16 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:33:16 PM PDT 24
Peak memory 217232 kb
Host smart-c3b94799-7cf1-4473-8f0a-b2903d76629f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296455671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3296455671
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2917125480
Short name T724
Test name
Test status
Simulation time 4385811250 ps
CPU time 85.33 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 213956 kb
Host smart-564121cd-5c2e-4554-98d3-739a22783f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917125480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2917125480
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3870969923
Short name T834
Test name
Test status
Simulation time 12883577683 ps
CPU time 96.05 seconds
Started Apr 18 02:08:46 PM PDT 24
Finished Apr 18 02:10:23 PM PDT 24
Peak memory 213616 kb
Host smart-b34a5d5b-2d19-4e90-980a-4c354f2c58a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870969923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3870969923
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2080039831
Short name T911
Test name
Test status
Simulation time 5084039402 ps
CPU time 22.93 seconds
Started Apr 18 02:08:46 PM PDT 24
Finished Apr 18 02:09:09 PM PDT 24
Peak memory 217684 kb
Host smart-9b183a59-c210-4bb0-abbc-0b7ef803052d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080039831 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2080039831
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4209733403
Short name T780
Test name
Test status
Simulation time 17168133825 ps
CPU time 32.05 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 215692 kb
Host smart-b72eff8d-1bde-40ea-aaab-0c6e6977489b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209733403 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4209733403
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1609799979
Short name T863
Test name
Test status
Simulation time 4367283943 ps
CPU time 31.79 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:33:37 PM PDT 24
Peak memory 211892 kb
Host smart-b076ffdf-97dd-4ff7-abef-e26987d07dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609799979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1609799979
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1827493287
Short name T809
Test name
Test status
Simulation time 6355035141 ps
CPU time 15.75 seconds
Started Apr 18 02:08:45 PM PDT 24
Finished Apr 18 02:09:01 PM PDT 24
Peak memory 211316 kb
Host smart-b2567cf6-ad09-4bd6-bb07-4494637a50fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827493287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1827493287
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1144122360
Short name T113
Test name
Test status
Simulation time 40528062331 ps
CPU time 89.72 seconds
Started Apr 18 02:08:44 PM PDT 24
Finished Apr 18 02:10:14 PM PDT 24
Peak memory 214576 kb
Host smart-32cf3a8c-cd31-470d-8c09-d8e9d0cdc586
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144122360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1144122360
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.833795367
Short name T723
Test name
Test status
Simulation time 69944462597 ps
CPU time 159.43 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 215412 kb
Host smart-916a4538-2ba9-4c49-b7c6-189c120511d0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833795367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.833795367
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3841712653
Short name T850
Test name
Test status
Simulation time 331997145 ps
CPU time 8.18 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:33:11 PM PDT 24
Peak memory 211084 kb
Host smart-3a91294f-6ec4-4eaa-ba90-4fec3e29fa63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841712653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3841712653
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.390989857
Short name T81
Test name
Test status
Simulation time 3579699539 ps
CPU time 27.25 seconds
Started Apr 18 02:08:46 PM PDT 24
Finished Apr 18 02:09:14 PM PDT 24
Peak memory 212540 kb
Host smart-eab769f6-0dc3-4551-9c73-5febc7acbb55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390989857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.390989857
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.450410171
Short name T830
Test name
Test status
Simulation time 3487983638 ps
CPU time 31.21 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:33:37 PM PDT 24
Peak memory 217184 kb
Host smart-ae257433-296e-480a-a8c1-52af0f5056a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450410171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.450410171
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.740881723
Short name T729
Test name
Test status
Simulation time 689639276 ps
CPU time 12.63 seconds
Started Apr 18 02:08:44 PM PDT 24
Finished Apr 18 02:08:57 PM PDT 24
Peak memory 217312 kb
Host smart-2996767d-62cb-4281-be1d-e818f04e6725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740881723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.740881723
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.862405100
Short name T64
Test name
Test status
Simulation time 1933834653 ps
CPU time 86.61 seconds
Started Apr 18 02:08:42 PM PDT 24
Finished Apr 18 02:10:09 PM PDT 24
Peak memory 213636 kb
Host smart-43bf1311-44d5-4f73-afe1-f3b12e471fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862405100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.862405100
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.919421987
Short name T135
Test name
Test status
Simulation time 991625311 ps
CPU time 80.38 seconds
Started Apr 18 12:33:01 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 213172 kb
Host smart-80567a96-c6a5-4e9a-b847-9549b5bb4431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919421987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.919421987
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1050011239
Short name T872
Test name
Test status
Simulation time 10626672351 ps
CPU time 23.77 seconds
Started Apr 18 02:08:52 PM PDT 24
Finished Apr 18 02:09:16 PM PDT 24
Peak memory 218784 kb
Host smart-9c9ae76b-c244-4b59-b36d-4fa4d52906bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050011239 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1050011239
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.577056073
Short name T842
Test name
Test status
Simulation time 7224481952 ps
CPU time 28.38 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:23 PM PDT 24
Peak memory 217424 kb
Host smart-1c800d6b-0e8e-4d57-9644-a0b5bcde3a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577056073 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.577056073
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4076423820
Short name T736
Test name
Test status
Simulation time 7818042028 ps
CPU time 20.17 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:29 PM PDT 24
Peak memory 212184 kb
Host smart-0c0d0fb6-f0ce-4cd2-b1a8-04b391eb7df4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076423820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4076423820
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.631223662
Short name T75
Test name
Test status
Simulation time 2823991665 ps
CPU time 20.16 seconds
Started Apr 18 02:08:50 PM PDT 24
Finished Apr 18 02:09:11 PM PDT 24
Peak memory 212140 kb
Host smart-94d03f0a-46ae-4a27-9d6e-b642f6b3b042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631223662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.631223662
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1579884736
Short name T888
Test name
Test status
Simulation time 84208105102 ps
CPU time 178.29 seconds
Started Apr 18 12:32:57 PM PDT 24
Finished Apr 18 12:35:57 PM PDT 24
Peak memory 215452 kb
Host smart-5b633434-e84f-40b5-b334-b5cbd9b052d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579884736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1579884736
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4032392010
Short name T904
Test name
Test status
Simulation time 1769023585 ps
CPU time 10.36 seconds
Started Apr 18 02:08:50 PM PDT 24
Finished Apr 18 02:09:00 PM PDT 24
Peak memory 211476 kb
Host smart-830fc459-9360-4c98-83bf-46ddac741a8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032392010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4032392010
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.53066885
Short name T110
Test name
Test status
Simulation time 2197272234 ps
CPU time 21.59 seconds
Started Apr 18 12:33:00 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 212256 kb
Host smart-95913c75-9af0-4fbc-bd9f-2fcbe9f5cb9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53066885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ct
rl_same_csr_outstanding.53066885
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2316171521
Short name T741
Test name
Test status
Simulation time 918152356 ps
CPU time 12.87 seconds
Started Apr 18 02:08:46 PM PDT 24
Finished Apr 18 02:08:59 PM PDT 24
Peak memory 218644 kb
Host smart-6f012ac0-57af-4475-a206-c3502bca8879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316171521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2316171521
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.235906762
Short name T676
Test name
Test status
Simulation time 2798397856 ps
CPU time 21.78 seconds
Started Apr 18 12:32:58 PM PDT 24
Finished Apr 18 12:33:21 PM PDT 24
Peak memory 218680 kb
Host smart-409b02b9-a3e7-4829-9110-931f57773873
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235906762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.235906762
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1313837514
Short name T808
Test name
Test status
Simulation time 4741175150 ps
CPU time 163.07 seconds
Started Apr 18 02:08:50 PM PDT 24
Finished Apr 18 02:11:34 PM PDT 24
Peak memory 214380 kb
Host smart-7ca4dbfd-210e-487d-86c1-8aa0ddb3b2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313837514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1313837514
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2561879697
Short name T735
Test name
Test status
Simulation time 8584351423 ps
CPU time 103.88 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 213852 kb
Host smart-190f9539-9926-4064-9186-1c9bcd9e0483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561879697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2561879697
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1725022164
Short name T843
Test name
Test status
Simulation time 4256211977 ps
CPU time 35.31 seconds
Started Apr 18 02:08:52 PM PDT 24
Finished Apr 18 02:09:27 PM PDT 24
Peak memory 217128 kb
Host smart-a259591f-3551-4d7a-aeb9-c962e95ba039
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725022164 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1725022164
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.630561017
Short name T701
Test name
Test status
Simulation time 1714231361 ps
CPU time 18.71 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 216424 kb
Host smart-c21f35da-43c1-489a-ac99-4c63129bf28c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630561017 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.630561017
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2156995051
Short name T117
Test name
Test status
Simulation time 10781459506 ps
CPU time 24.05 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:33:27 PM PDT 24
Peak memory 212184 kb
Host smart-035bee02-1815-4d8b-a705-0f899517ac67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156995051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2156995051
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3226024921
Short name T764
Test name
Test status
Simulation time 525835734 ps
CPU time 10.61 seconds
Started Apr 18 02:08:55 PM PDT 24
Finished Apr 18 02:09:06 PM PDT 24
Peak memory 211344 kb
Host smart-54f35197-ddc7-4e6f-ba8e-61a3125744e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226024921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3226024921
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2463275083
Short name T94
Test name
Test status
Simulation time 34361755313 ps
CPU time 139.32 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:35:28 PM PDT 24
Peak memory 214236 kb
Host smart-a7aabc41-c5c2-4877-a612-978b90f7d6eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463275083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2463275083
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2931921821
Short name T835
Test name
Test status
Simulation time 107004716976 ps
CPU time 133.59 seconds
Started Apr 18 02:08:52 PM PDT 24
Finished Apr 18 02:11:06 PM PDT 24
Peak memory 214484 kb
Host smart-53d19dbe-ca8c-4c28-9f1c-86df69507113
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931921821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2931921821
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.220793242
Short name T847
Test name
Test status
Simulation time 216402243 ps
CPU time 8.52 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:01 PM PDT 24
Peak memory 211152 kb
Host smart-db595aac-e854-46d1-99d9-66bd9d1d7c4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220793242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.220793242
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4279105738
Short name T112
Test name
Test status
Simulation time 7480275208 ps
CPU time 30.23 seconds
Started Apr 18 02:08:52 PM PDT 24
Finished Apr 18 02:09:23 PM PDT 24
Peak memory 212280 kb
Host smart-8ac51115-2f28-4454-81a4-8fc32c6fed63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279105738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4279105738
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2368765670
Short name T710
Test name
Test status
Simulation time 11029258769 ps
CPU time 30.91 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 217604 kb
Host smart-fe0ed908-9106-4bd3-9dbd-d3a325e98d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368765670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2368765670
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2766191460
Short name T797
Test name
Test status
Simulation time 2691411640 ps
CPU time 28 seconds
Started Apr 18 02:08:50 PM PDT 24
Finished Apr 18 02:09:18 PM PDT 24
Peak memory 217596 kb
Host smart-3c79d26e-0249-4950-9edc-01dc12cff260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766191460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2766191460
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2213957229
Short name T773
Test name
Test status
Simulation time 12824430723 ps
CPU time 27.93 seconds
Started Apr 18 02:09:00 PM PDT 24
Finished Apr 18 02:09:29 PM PDT 24
Peak memory 217048 kb
Host smart-00ebf2f0-768a-408b-8811-2c180b4400d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213957229 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2213957229
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.68488086
Short name T784
Test name
Test status
Simulation time 823000878 ps
CPU time 8.5 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:04 PM PDT 24
Peak memory 215576 kb
Host smart-3d188eef-f641-4124-bb08-5b8ee6ed198e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68488086 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.68488086
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3371451422
Short name T91
Test name
Test status
Simulation time 3784551688 ps
CPU time 20.84 seconds
Started Apr 18 02:08:50 PM PDT 24
Finished Apr 18 02:09:12 PM PDT 24
Peak memory 211716 kb
Host smart-fe4bc992-68ab-41d8-a8c9-975364248f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371451422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3371451422
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3489123131
Short name T814
Test name
Test status
Simulation time 3141349584 ps
CPU time 25.19 seconds
Started Apr 18 12:33:01 PM PDT 24
Finished Apr 18 12:33:27 PM PDT 24
Peak memory 211588 kb
Host smart-8fed27b7-e62c-4520-a67a-f005d43414b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489123131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3489123131
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1340110494
Short name T837
Test name
Test status
Simulation time 2026425045 ps
CPU time 56.57 seconds
Started Apr 18 02:08:49 PM PDT 24
Finished Apr 18 02:09:46 PM PDT 24
Peak memory 214632 kb
Host smart-965d449a-24a6-4e48-b202-c34d8f50e54b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340110494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1340110494
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2994186223
Short name T699
Test name
Test status
Simulation time 1012362753 ps
CPU time 36.1 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:31 PM PDT 24
Peak memory 213192 kb
Host smart-721ca638-8ca6-4eaa-88be-75ff511fdb63
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994186223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2994186223
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2396396961
Short name T831
Test name
Test status
Simulation time 3271319229 ps
CPU time 28.49 seconds
Started Apr 18 02:08:52 PM PDT 24
Finished Apr 18 02:09:21 PM PDT 24
Peak memory 212524 kb
Host smart-5ed213f8-4286-4001-aa56-08993aba2f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396396961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2396396961
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2608733119
Short name T913
Test name
Test status
Simulation time 1298427465 ps
CPU time 16.91 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 211228 kb
Host smart-7823b021-32ff-4297-8238-fbe975ae3fec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608733119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2608733119
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1927784760
Short name T846
Test name
Test status
Simulation time 170910132 ps
CPU time 12.93 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:07 PM PDT 24
Peak memory 217228 kb
Host smart-887d3f9f-ffff-46f9-988a-8bf1933d13bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927784760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1927784760
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2538031272
Short name T887
Test name
Test status
Simulation time 1443522428 ps
CPU time 20.54 seconds
Started Apr 18 02:08:52 PM PDT 24
Finished Apr 18 02:09:13 PM PDT 24
Peak memory 217320 kb
Host smart-f37f6066-47ab-4ec3-89b4-1fda94d057e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538031272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2538031272
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3776882332
Short name T792
Test name
Test status
Simulation time 1002848868 ps
CPU time 86.08 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 213448 kb
Host smart-7cbba75c-331a-4161-a9e6-a736505a3e09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776882332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3776882332
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.86868912
Short name T890
Test name
Test status
Simulation time 1098385407 ps
CPU time 152.41 seconds
Started Apr 18 02:08:54 PM PDT 24
Finished Apr 18 02:11:27 PM PDT 24
Peak memory 214056 kb
Host smart-8601a8fe-c3cf-48d1-9395-c14bbb54f8b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86868912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_int
g_err.86868912
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3786795021
Short name T826
Test name
Test status
Simulation time 3858544523 ps
CPU time 28.6 seconds
Started Apr 18 12:33:00 PM PDT 24
Finished Apr 18 12:33:29 PM PDT 24
Peak memory 211236 kb
Host smart-232f3ac2-363f-4339-bf47-31d8eebfc3dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786795021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3786795021
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3855961266
Short name T713
Test name
Test status
Simulation time 688931285 ps
CPU time 13.01 seconds
Started Apr 18 02:07:53 PM PDT 24
Finished Apr 18 02:08:06 PM PDT 24
Peak memory 211304 kb
Host smart-cdf7f7b3-6bd5-4d9b-ba4c-468e7fd77b08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855961266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3855961266
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1896207040
Short name T716
Test name
Test status
Simulation time 12547532715 ps
CPU time 23.14 seconds
Started Apr 18 02:07:52 PM PDT 24
Finished Apr 18 02:08:15 PM PDT 24
Peak memory 211608 kb
Host smart-53fae40f-b8e3-4f22-b048-10649427dd72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896207040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1896207040
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.209089420
Short name T728
Test name
Test status
Simulation time 1150953296 ps
CPU time 16.49 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:33:07 PM PDT 24
Peak memory 211152 kb
Host smart-0c713785-f80a-4f43-96b9-b0f15405f25d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209089420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.209089420
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3132792716
Short name T899
Test name
Test status
Simulation time 3587606766 ps
CPU time 27.77 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:15 PM PDT 24
Peak memory 211972 kb
Host smart-f9d9ab1e-fcd4-4dd7-9e17-c1f8e4b470db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132792716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3132792716
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3312322159
Short name T725
Test name
Test status
Simulation time 4289417820 ps
CPU time 35.38 seconds
Started Apr 18 02:07:52 PM PDT 24
Finished Apr 18 02:08:28 PM PDT 24
Peak memory 211684 kb
Host smart-3754e61c-0971-4d7e-be64-c3c5b006075c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312322159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3312322159
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2156075463
Short name T895
Test name
Test status
Simulation time 2462254412 ps
CPU time 17.09 seconds
Started Apr 18 12:32:56 PM PDT 24
Finished Apr 18 12:33:15 PM PDT 24
Peak memory 215000 kb
Host smart-5356476c-9065-437d-a015-c1a289fda407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156075463 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2156075463
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2898044389
Short name T738
Test name
Test status
Simulation time 1729774819 ps
CPU time 20.37 seconds
Started Apr 18 02:07:49 PM PDT 24
Finished Apr 18 02:08:10 PM PDT 24
Peak memory 218876 kb
Host smart-bd0c84ba-2650-4a55-a8b9-c028959c6ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898044389 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2898044389
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1514467872
Short name T891
Test name
Test status
Simulation time 9234307982 ps
CPU time 22.81 seconds
Started Apr 18 02:07:48 PM PDT 24
Finished Apr 18 02:08:12 PM PDT 24
Peak memory 212372 kb
Host smart-11678a72-147c-4920-acb3-9797f2c9ce98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514467872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1514467872
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.573328400
Short name T901
Test name
Test status
Simulation time 14317847806 ps
CPU time 27.61 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:33:12 PM PDT 24
Peak memory 211956 kb
Host smart-18193bf5-9e3f-449d-9dae-e9af13352344
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573328400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.573328400
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1066051533
Short name T686
Test name
Test status
Simulation time 6226017956 ps
CPU time 19.53 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:09 PM PDT 24
Peak memory 211184 kb
Host smart-3b11fa58-acd1-42b3-a3e5-53803a925d96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066051533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1066051533
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.122860655
Short name T781
Test name
Test status
Simulation time 661514944 ps
CPU time 7.95 seconds
Started Apr 18 02:07:50 PM PDT 24
Finished Apr 18 02:07:59 PM PDT 24
Peak memory 211176 kb
Host smart-a3d708a7-4536-4547-a60a-e638df3ccd92
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122860655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.122860655
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2429490019
Short name T855
Test name
Test status
Simulation time 4324154924 ps
CPU time 25.34 seconds
Started Apr 18 02:07:49 PM PDT 24
Finished Apr 18 02:08:15 PM PDT 24
Peak memory 211276 kb
Host smart-1417a407-8e01-4605-aa97-9e3c6135a69a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429490019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2429490019
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2652360121
Short name T788
Test name
Test status
Simulation time 169241966 ps
CPU time 8.25 seconds
Started Apr 18 12:32:56 PM PDT 24
Finished Apr 18 12:33:06 PM PDT 24
Peak memory 211064 kb
Host smart-3c56c5e8-085b-4b24-bd91-44e8b695f0e4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652360121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2652360121
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2007279250
Short name T859
Test name
Test status
Simulation time 17778253195 ps
CPU time 165.11 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 215620 kb
Host smart-a008b6f0-2d30-4ba1-903a-a15e10c6b7ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007279250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2007279250
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3255096930
Short name T779
Test name
Test status
Simulation time 17538118861 ps
CPU time 107.65 seconds
Started Apr 18 02:07:47 PM PDT 24
Finished Apr 18 02:09:35 PM PDT 24
Peak memory 215520 kb
Host smart-f702b6f7-6360-4b8e-af67-2d0c356d6cfa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255096930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3255096930
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1121831820
Short name T819
Test name
Test status
Simulation time 1621119484 ps
CPU time 18.26 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:33:07 PM PDT 24
Peak memory 211804 kb
Host smart-6f952486-8bda-4b46-b73a-60fec7404ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121831820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1121831820
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2681654258
Short name T755
Test name
Test status
Simulation time 3896507400 ps
CPU time 31.98 seconds
Started Apr 18 02:07:48 PM PDT 24
Finished Apr 18 02:08:21 PM PDT 24
Peak memory 212200 kb
Host smart-35981dd8-539f-4b56-b082-da8d49084b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681654258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2681654258
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1530764818
Short name T708
Test name
Test status
Simulation time 16377750298 ps
CPU time 35.41 seconds
Started Apr 18 02:07:50 PM PDT 24
Finished Apr 18 02:08:26 PM PDT 24
Peak memory 218392 kb
Host smart-d3e26fb0-e423-447f-a851-76680c5a5d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530764818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1530764818
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.881549611
Short name T857
Test name
Test status
Simulation time 14674497196 ps
CPU time 32.19 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:28 PM PDT 24
Peak memory 218452 kb
Host smart-a22bfeba-6c56-4249-835b-295871300751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881549611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.881549611
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1917390523
Short name T128
Test name
Test status
Simulation time 3359039090 ps
CPU time 100.18 seconds
Started Apr 18 02:07:51 PM PDT 24
Finished Apr 18 02:09:32 PM PDT 24
Peak memory 213556 kb
Host smart-997eb1c6-77e1-4701-86d8-bc45322d674d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917390523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1917390523
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.428778061
Short name T700
Test name
Test status
Simulation time 2150902403 ps
CPU time 84.27 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 214468 kb
Host smart-4ac74844-bffb-4f34-81c6-65085a4c0ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428778061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.428778061
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1942177078
Short name T909
Test name
Test status
Simulation time 3952791581 ps
CPU time 20.61 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 211788 kb
Host smart-534e22b9-24fd-4713-b241-73f49c0824f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942177078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1942177078
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2823961216
Short name T867
Test name
Test status
Simulation time 332136508 ps
CPU time 8.24 seconds
Started Apr 18 02:08:45 PM PDT 24
Finished Apr 18 02:08:54 PM PDT 24
Peak memory 211328 kb
Host smart-a5d88dd8-d9f7-4309-b876-af7216db21f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823961216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2823961216
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2831922942
Short name T695
Test name
Test status
Simulation time 3601592573 ps
CPU time 28.87 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:33:18 PM PDT 24
Peak memory 211192 kb
Host smart-5aeabf9b-34df-40df-8b5e-191c8193d6ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831922942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2831922942
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.625671703
Short name T817
Test name
Test status
Simulation time 346247824 ps
CPU time 8.48 seconds
Started Apr 18 02:07:57 PM PDT 24
Finished Apr 18 02:08:07 PM PDT 24
Peak memory 211304 kb
Host smart-45261e2a-6144-4ddd-85fb-c416654547c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625671703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.625671703
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1931068293
Short name T906
Test name
Test status
Simulation time 3021771651 ps
CPU time 29.6 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:23 PM PDT 24
Peak memory 211244 kb
Host smart-8a70bd02-862d-435e-8b4d-90eaa37a7915
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931068293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1931068293
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4261010017
Short name T80
Test name
Test status
Simulation time 355600121 ps
CPU time 15.35 seconds
Started Apr 18 02:07:56 PM PDT 24
Finished Apr 18 02:08:12 PM PDT 24
Peak memory 212088 kb
Host smart-42f72b6f-a696-4f14-bb51-3d248c5cb7da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261010017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4261010017
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2786786416
Short name T866
Test name
Test status
Simulation time 3704414477 ps
CPU time 29.34 seconds
Started Apr 18 02:07:56 PM PDT 24
Finished Apr 18 02:08:27 PM PDT 24
Peak memory 216784 kb
Host smart-d86c185f-2a14-48fc-9d2c-c89135c5ee9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786786416 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2786786416
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.849190098
Short name T795
Test name
Test status
Simulation time 3169758007 ps
CPU time 25.68 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 216920 kb
Host smart-63b81475-bbcc-4e58-a3d0-eb0525424470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849190098 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.849190098
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3726437247
Short name T99
Test name
Test status
Simulation time 4075569522 ps
CPU time 14.6 seconds
Started Apr 18 02:07:57 PM PDT 24
Finished Apr 18 02:08:13 PM PDT 24
Peak memory 211804 kb
Host smart-7af247a0-6c3e-47b6-93e6-0c6d48914af4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726437247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3726437247
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.434736073
Short name T715
Test name
Test status
Simulation time 1723169254 ps
CPU time 18.55 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:14 PM PDT 24
Peak memory 211516 kb
Host smart-e20e7dc1-a582-4bde-8940-48c62bb8f3ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434736073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.434736073
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4067770395
Short name T692
Test name
Test status
Simulation time 2741151634 ps
CPU time 8.17 seconds
Started Apr 18 02:07:55 PM PDT 24
Finished Apr 18 02:08:04 PM PDT 24
Peak memory 211260 kb
Host smart-422fe461-0906-4376-b4ee-24c5ac26a6b8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067770395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4067770395
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4240250061
Short name T737
Test name
Test status
Simulation time 5963892401 ps
CPU time 28.15 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:21 PM PDT 24
Peak memory 211160 kb
Host smart-a0f5721f-8aec-48c5-a722-f58faf322d08
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240250061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4240250061
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2683741727
Short name T751
Test name
Test status
Simulation time 30009670912 ps
CPU time 24.27 seconds
Started Apr 18 12:32:57 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 211100 kb
Host smart-678c0888-649a-423e-86e6-fcba5e67d45b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683741727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2683741727
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.800998304
Short name T882
Test name
Test status
Simulation time 11772105524 ps
CPU time 24.51 seconds
Started Apr 18 02:07:57 PM PDT 24
Finished Apr 18 02:08:22 PM PDT 24
Peak memory 211304 kb
Host smart-b829ca93-65c9-49ca-9cae-c93630c8b642
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800998304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
800998304
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2174048588
Short name T778
Test name
Test status
Simulation time 710495762 ps
CPU time 37.4 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:29 PM PDT 24
Peak memory 213168 kb
Host smart-c7f7e829-f486-4d4b-9881-fca03e862154
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174048588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2174048588
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2266019521
Short name T97
Test name
Test status
Simulation time 19192530259 ps
CPU time 92.29 seconds
Started Apr 18 02:07:49 PM PDT 24
Finished Apr 18 02:09:22 PM PDT 24
Peak memory 213340 kb
Host smart-4f1aebbc-bded-4193-942f-6e00b86b8718
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266019521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2266019521
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2477389772
Short name T714
Test name
Test status
Simulation time 1036258692 ps
CPU time 18.54 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:33:09 PM PDT 24
Peak memory 212184 kb
Host smart-d47913c5-2597-4221-9150-5df9600fdc88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477389772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2477389772
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.503267472
Short name T816
Test name
Test status
Simulation time 1494972422 ps
CPU time 17.57 seconds
Started Apr 18 02:07:59 PM PDT 24
Finished Apr 18 02:08:17 PM PDT 24
Peak memory 211508 kb
Host smart-a8ac7692-4817-4059-95eb-737729445501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503267472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.503267472
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1744465760
Short name T849
Test name
Test status
Simulation time 12769653898 ps
CPU time 30.12 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:33:15 PM PDT 24
Peak memory 218384 kb
Host smart-a944dc82-ae8c-41a2-a918-0ea475e7aa45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744465760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1744465760
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3721639318
Short name T768
Test name
Test status
Simulation time 1474615030 ps
CPU time 23.48 seconds
Started Apr 18 02:07:58 PM PDT 24
Finished Apr 18 02:08:22 PM PDT 24
Peak memory 218184 kb
Host smart-d22c1bd6-6f69-40e5-8a9e-03b2df8753b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721639318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3721639318
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2824877234
Short name T907
Test name
Test status
Simulation time 5456937255 ps
CPU time 166.9 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 213928 kb
Host smart-a9cd0783-a4f5-4323-b112-93b65707316d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824877234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2824877234
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3501195978
Short name T796
Test name
Test status
Simulation time 5819217843 ps
CPU time 166.88 seconds
Started Apr 18 02:07:59 PM PDT 24
Finished Apr 18 02:10:47 PM PDT 24
Peak memory 214200 kb
Host smart-8d10f667-3d83-4e05-b8e4-7aa3bccf77bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501195978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3501195978
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1688828430
Short name T744
Test name
Test status
Simulation time 7323314503 ps
CPU time 21.76 seconds
Started Apr 18 02:08:07 PM PDT 24
Finished Apr 18 02:08:29 PM PDT 24
Peak memory 212112 kb
Host smart-3b06aa18-79cd-40c6-8e28-58545c7df2fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688828430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1688828430
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.630664659
Short name T76
Test name
Test status
Simulation time 11430456377 ps
CPU time 20.91 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:14 PM PDT 24
Peak memory 212076 kb
Host smart-699ca9b7-5ca0-4d7f-8ef5-780e2da166e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630664659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.630664659
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1914919751
Short name T802
Test name
Test status
Simulation time 20275873145 ps
CPU time 32.77 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 212116 kb
Host smart-5f1b6768-e995-402a-b50c-3234c63e1262
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914919751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1914919751
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2969538148
Short name T821
Test name
Test status
Simulation time 1323509656 ps
CPU time 11.12 seconds
Started Apr 18 02:08:06 PM PDT 24
Finished Apr 18 02:08:18 PM PDT 24
Peak memory 211300 kb
Host smart-321c9623-56d1-4dba-82f8-6ec869d5905c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969538148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2969538148
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2191769218
Short name T77
Test name
Test status
Simulation time 13527455664 ps
CPU time 31.93 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:27 PM PDT 24
Peak memory 212132 kb
Host smart-5e04a667-44f5-47da-b5ba-7199148a5fd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191769218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2191769218
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.940571377
Short name T833
Test name
Test status
Simulation time 7898514136 ps
CPU time 23.57 seconds
Started Apr 18 02:08:06 PM PDT 24
Finished Apr 18 02:08:30 PM PDT 24
Peak memory 212084 kb
Host smart-52c9eef6-f35a-4ac0-9a73-0d9817ea288a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940571377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.940571377
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2066172497
Short name T698
Test name
Test status
Simulation time 4173903267 ps
CPU time 34.19 seconds
Started Apr 18 12:32:55 PM PDT 24
Finished Apr 18 12:33:31 PM PDT 24
Peak memory 217484 kb
Host smart-77d789e8-a4b6-41d7-ab0b-e7f7372941e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066172497 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2066172497
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3611050362
Short name T696
Test name
Test status
Simulation time 15415742693 ps
CPU time 31 seconds
Started Apr 18 02:08:06 PM PDT 24
Finished Apr 18 02:08:38 PM PDT 24
Peak memory 217232 kb
Host smart-05be1255-c8b8-4b2f-b958-1d9880102ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611050362 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3611050362
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.209055843
Short name T100
Test name
Test status
Simulation time 2354308232 ps
CPU time 8.23 seconds
Started Apr 18 02:08:07 PM PDT 24
Finished Apr 18 02:08:16 PM PDT 24
Peak memory 211236 kb
Host smart-e9f5b9a8-38fb-4f8f-a78d-f552e43276de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209055843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.209055843
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2937721396
Short name T82
Test name
Test status
Simulation time 13442475730 ps
CPU time 19.79 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:33:08 PM PDT 24
Peak memory 212488 kb
Host smart-617527c0-68ef-4f3f-8c5d-e8a4fc68b5d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937721396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2937721396
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3629445108
Short name T853
Test name
Test status
Simulation time 9194110115 ps
CPU time 27.14 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:14 PM PDT 24
Peak memory 211012 kb
Host smart-329acd4e-41da-47df-8144-ff2c3fcf408c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629445108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3629445108
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.776133532
Short name T753
Test name
Test status
Simulation time 12310026980 ps
CPU time 16.31 seconds
Started Apr 18 02:08:06 PM PDT 24
Finished Apr 18 02:08:23 PM PDT 24
Peak memory 211244 kb
Host smart-e2cbf54b-a0ee-4fc5-88dd-d8dc6acb470c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776133532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.776133532
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2143162334
Short name T903
Test name
Test status
Simulation time 10278527858 ps
CPU time 25.67 seconds
Started Apr 18 02:07:57 PM PDT 24
Finished Apr 18 02:08:23 PM PDT 24
Peak memory 211312 kb
Host smart-1f4db642-7b6c-4d51-81b3-29d3ce2762fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143162334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2143162334
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2420878621
Short name T719
Test name
Test status
Simulation time 2550093466 ps
CPU time 15.87 seconds
Started Apr 18 12:32:45 PM PDT 24
Finished Apr 18 12:33:03 PM PDT 24
Peak memory 211056 kb
Host smart-9dd42e69-0c8f-43ba-85cb-84bc1a0aac3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420878621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2420878621
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1488225563
Short name T822
Test name
Test status
Simulation time 8566091106 ps
CPU time 56.38 seconds
Started Apr 18 12:32:43 PM PDT 24
Finished Apr 18 12:33:41 PM PDT 24
Peak memory 215416 kb
Host smart-23a88f54-079a-46b3-84b7-de17f39ac606
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488225563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1488225563
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2587095172
Short name T811
Test name
Test status
Simulation time 4111537483 ps
CPU time 56.35 seconds
Started Apr 18 02:08:00 PM PDT 24
Finished Apr 18 02:08:56 PM PDT 24
Peak memory 213976 kb
Host smart-0204c9a8-576b-4fc6-b1ed-916a817828e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587095172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2587095172
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3275120672
Short name T813
Test name
Test status
Simulation time 392277110 ps
CPU time 9.92 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:00 PM PDT 24
Peak memory 211220 kb
Host smart-9a27bae9-419c-49e2-806c-47c8a20018bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275120672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3275120672
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3701151949
Short name T794
Test name
Test status
Simulation time 1889862317 ps
CPU time 19.46 seconds
Started Apr 18 02:08:09 PM PDT 24
Finished Apr 18 02:08:29 PM PDT 24
Peak memory 211436 kb
Host smart-718f7318-a36f-49b3-bd09-cc1e9b300dd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701151949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3701151949
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1304382264
Short name T818
Test name
Test status
Simulation time 38676564899 ps
CPU time 39.47 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:33:28 PM PDT 24
Peak memory 217980 kb
Host smart-c0352489-83dc-4065-a8e7-b3294c5b9f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304382264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1304382264
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2073639986
Short name T681
Test name
Test status
Simulation time 12586087969 ps
CPU time 31.6 seconds
Started Apr 18 02:07:58 PM PDT 24
Finished Apr 18 02:08:31 PM PDT 24
Peak memory 218804 kb
Host smart-38b3fd5c-52d6-41ed-ab66-4779d598b9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073639986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2073639986
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2229039276
Short name T138
Test name
Test status
Simulation time 1355118785 ps
CPU time 78.84 seconds
Started Apr 18 12:32:42 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 212080 kb
Host smart-bc2779ca-26dd-4bf9-8f9e-fa0811d19ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229039276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2229039276
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.421859878
Short name T124
Test name
Test status
Simulation time 8643402431 ps
CPU time 164.79 seconds
Started Apr 18 02:07:58 PM PDT 24
Finished Apr 18 02:10:43 PM PDT 24
Peak memory 214252 kb
Host smart-a245e18c-f23f-40d1-ac8c-33b2b3eb3097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421859878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.421859878
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1297581183
Short name T750
Test name
Test status
Simulation time 3496645608 ps
CPU time 28.11 seconds
Started Apr 18 12:32:56 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 218220 kb
Host smart-0f0ff452-89b4-4776-967e-b3fa3a0de1f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297581183 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1297581183
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4098677830
Short name T749
Test name
Test status
Simulation time 4504936189 ps
CPU time 15.22 seconds
Started Apr 18 02:08:07 PM PDT 24
Finished Apr 18 02:08:23 PM PDT 24
Peak memory 216700 kb
Host smart-af206222-7d86-46ce-9ce0-3d35823ce573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098677830 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4098677830
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1189933412
Short name T718
Test name
Test status
Simulation time 1268195281 ps
CPU time 8.01 seconds
Started Apr 18 02:08:08 PM PDT 24
Finished Apr 18 02:08:16 PM PDT 24
Peak memory 211308 kb
Host smart-de0ad2d7-56a1-4134-aee0-6330f5007e9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189933412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1189933412
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1891481963
Short name T697
Test name
Test status
Simulation time 1404441632 ps
CPU time 16.47 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:06 PM PDT 24
Peak memory 211044 kb
Host smart-c5c7e59c-125f-4f88-ae79-3b4b0bb55290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891481963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1891481963
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.945919959
Short name T90
Test name
Test status
Simulation time 87569923379 ps
CPU time 179.59 seconds
Started Apr 18 02:08:08 PM PDT 24
Finished Apr 18 02:11:08 PM PDT 24
Peak memory 215456 kb
Host smart-3e10e2a3-1bf0-43a2-acf1-3c2c3c113121
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945919959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.945919959
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.997417024
Short name T742
Test name
Test status
Simulation time 5579856625 ps
CPU time 45.26 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:33:34 PM PDT 24
Peak memory 214272 kb
Host smart-2e2b64ea-d78e-4c4e-86ba-ac6acb2eb769
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997417024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.997417024
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1882201906
Short name T848
Test name
Test status
Simulation time 4473319825 ps
CPU time 21.26 seconds
Started Apr 18 02:08:06 PM PDT 24
Finished Apr 18 02:08:29 PM PDT 24
Peak memory 212372 kb
Host smart-9312df67-974d-4b50-9eb3-fc17d088befe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882201906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1882201906
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3736235809
Short name T769
Test name
Test status
Simulation time 5288239147 ps
CPU time 18.76 seconds
Started Apr 18 12:32:57 PM PDT 24
Finished Apr 18 12:33:17 PM PDT 24
Peak memory 212344 kb
Host smart-ce33e4c0-a0cc-4c05-a39e-4ed41cca5bd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736235809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3736235809
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.107771987
Short name T825
Test name
Test status
Simulation time 169206476 ps
CPU time 12.72 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:33:03 PM PDT 24
Peak memory 217496 kb
Host smart-5122f374-654f-4d91-b923-23b12f4ca206
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107771987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.107771987
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.494056424
Short name T763
Test name
Test status
Simulation time 2451349102 ps
CPU time 26.51 seconds
Started Apr 18 02:08:07 PM PDT 24
Finished Apr 18 02:08:34 PM PDT 24
Peak memory 217396 kb
Host smart-e3f82681-042e-496e-bf1d-efb938852f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494056424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.494056424
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.131199923
Short name T63
Test name
Test status
Simulation time 382381361 ps
CPU time 158.86 seconds
Started Apr 18 02:08:08 PM PDT 24
Finished Apr 18 02:10:48 PM PDT 24
Peak memory 214220 kb
Host smart-039866b3-a387-4a90-8781-6fe17964cf40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131199923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.131199923
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.318080617
Short name T136
Test name
Test status
Simulation time 9738212942 ps
CPU time 162.68 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 213984 kb
Host smart-61b3c796-6582-4217-b5c0-007eb58fd7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318080617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.318080617
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1738705753
Short name T68
Test name
Test status
Simulation time 4196219058 ps
CPU time 31.29 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 215288 kb
Host smart-13d6851e-fc2e-48c9-afec-e6b57e104998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738705753 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1738705753
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2378131149
Short name T823
Test name
Test status
Simulation time 1617754396 ps
CPU time 18.46 seconds
Started Apr 18 02:08:18 PM PDT 24
Finished Apr 18 02:08:37 PM PDT 24
Peak memory 216328 kb
Host smart-95b63605-2aa7-403f-bf61-1722d74867ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378131149 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2378131149
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3400369632
Short name T883
Test name
Test status
Simulation time 682530126 ps
CPU time 13.27 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:01 PM PDT 24
Peak memory 211292 kb
Host smart-ec13c616-f36a-40a8-8bfd-7fcd5c1352d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400369632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3400369632
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4243517160
Short name T852
Test name
Test status
Simulation time 49070411054 ps
CPU time 29.97 seconds
Started Apr 18 02:08:07 PM PDT 24
Finished Apr 18 02:08:38 PM PDT 24
Peak memory 212156 kb
Host smart-3cc0e32f-c9c2-4acb-a1fd-6591375847f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243517160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4243517160
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2011919100
Short name T861
Test name
Test status
Simulation time 11053699240 ps
CPU time 100.94 seconds
Started Apr 18 02:08:28 PM PDT 24
Finished Apr 18 02:10:10 PM PDT 24
Peak memory 211436 kb
Host smart-bc55f34b-3d59-4dcc-9119-28b825e8670a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011919100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2011919100
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3012583711
Short name T783
Test name
Test status
Simulation time 1037893040 ps
CPU time 56.17 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 214320 kb
Host smart-3d24e26f-8f17-415d-ad72-36afd51acc39
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012583711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3012583711
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3015430530
Short name T786
Test name
Test status
Simulation time 3082876780 ps
CPU time 25.38 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 211504 kb
Host smart-fab8dfc6-99c6-44f5-baa8-e1b795484ae7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015430530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3015430530
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3866021336
Short name T111
Test name
Test status
Simulation time 5891211196 ps
CPU time 30.59 seconds
Started Apr 18 02:08:06 PM PDT 24
Finished Apr 18 02:08:38 PM PDT 24
Peak memory 212744 kb
Host smart-833151dd-ca99-4a42-b6af-2d822e9c3678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866021336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3866021336
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1744511476
Short name T687
Test name
Test status
Simulation time 11120767932 ps
CPU time 26.7 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 218852 kb
Host smart-b84a83cb-a8c7-426a-b65b-f1ed0e07894d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744511476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1744511476
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.670317805
Short name T756
Test name
Test status
Simulation time 5675888298 ps
CPU time 19.69 seconds
Started Apr 18 02:08:08 PM PDT 24
Finished Apr 18 02:08:28 PM PDT 24
Peak memory 218944 kb
Host smart-0ff5cd5f-cc26-488b-844c-ac0397f2ba62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670317805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.670317805
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1266269654
Short name T877
Test name
Test status
Simulation time 264233204 ps
CPU time 80.14 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:34:29 PM PDT 24
Peak memory 213236 kb
Host smart-0168216d-002a-4a53-ac36-56270762a1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266269654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1266269654
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3795911238
Short name T122
Test name
Test status
Simulation time 1196834178 ps
CPU time 152.66 seconds
Started Apr 18 02:08:07 PM PDT 24
Finished Apr 18 02:10:40 PM PDT 24
Peak memory 214160 kb
Host smart-19378491-7445-447b-9eb0-0c78647c24d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795911238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3795911238
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2074751706
Short name T839
Test name
Test status
Simulation time 15819772790 ps
CPU time 23.24 seconds
Started Apr 18 02:08:18 PM PDT 24
Finished Apr 18 02:08:41 PM PDT 24
Peak memory 215592 kb
Host smart-a9de4ee9-c547-49a2-8413-34ba1d5a278c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074751706 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2074751706
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2160301629
Short name T706
Test name
Test status
Simulation time 40185553478 ps
CPU time 25.09 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 217640 kb
Host smart-25964b27-19db-4621-8c85-5efa96b14de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160301629 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2160301629
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.229578951
Short name T766
Test name
Test status
Simulation time 6177641742 ps
CPU time 17.64 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:09 PM PDT 24
Peak memory 212036 kb
Host smart-d4b42bcb-276a-4e61-87aa-182ca5d52863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229578951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.229578951
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3425007462
Short name T836
Test name
Test status
Simulation time 3466758382 ps
CPU time 27.6 seconds
Started Apr 18 02:08:19 PM PDT 24
Finished Apr 18 02:08:47 PM PDT 24
Peak memory 212008 kb
Host smart-a8c23f50-adaf-46d0-bb41-a0b7d1ec6f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425007462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3425007462
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2450261369
Short name T93
Test name
Test status
Simulation time 13012106870 ps
CPU time 110.31 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 214272 kb
Host smart-526fdac9-5cb4-49d4-970c-e2188a363325
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450261369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2450261369
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3852034472
Short name T678
Test name
Test status
Simulation time 5841785592 ps
CPU time 72.84 seconds
Started Apr 18 02:08:18 PM PDT 24
Finished Apr 18 02:09:31 PM PDT 24
Peak memory 214476 kb
Host smart-5f2aa852-0ac9-40a6-b2af-3e0a0166ff96
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852034472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3852034472
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3206195309
Short name T896
Test name
Test status
Simulation time 13423635737 ps
CPU time 31.75 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:19 PM PDT 24
Peak memory 212940 kb
Host smart-7cab2df6-6b53-4152-84ba-9bf3a6c81f25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206195309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3206195309
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3942294808
Short name T759
Test name
Test status
Simulation time 2057985948 ps
CPU time 12.03 seconds
Started Apr 18 02:08:18 PM PDT 24
Finished Apr 18 02:08:30 PM PDT 24
Peak memory 211572 kb
Host smart-2f6c3c64-b231-4963-bb7e-59dd5b4f613b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942294808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3942294808
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1780469665
Short name T762
Test name
Test status
Simulation time 916582754 ps
CPU time 17.8 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:07 PM PDT 24
Peak memory 217336 kb
Host smart-64f65cd0-7007-4068-b529-1bc45c7007c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780469665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1780469665
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.404370696
Short name T844
Test name
Test status
Simulation time 3418553109 ps
CPU time 17.02 seconds
Started Apr 18 02:08:17 PM PDT 24
Finished Apr 18 02:08:35 PM PDT 24
Peak memory 217716 kb
Host smart-74b6f039-6053-4982-a6e5-b96191bb9607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404370696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.404370696
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1973797268
Short name T130
Test name
Test status
Simulation time 1123311889 ps
CPU time 154.43 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:35:25 PM PDT 24
Peak memory 213996 kb
Host smart-8e2c60c0-25cd-47f0-b5f0-bdaac22085a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973797268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1973797268
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3932787346
Short name T880
Test name
Test status
Simulation time 1173189146 ps
CPU time 153.52 seconds
Started Apr 18 02:08:21 PM PDT 24
Finished Apr 18 02:10:55 PM PDT 24
Peak memory 214812 kb
Host smart-f620e5ed-6aad-4908-9e7d-9b78caf4ed94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932787346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3932787346
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1818270872
Short name T679
Test name
Test status
Simulation time 14643536854 ps
CPU time 32.92 seconds
Started Apr 18 02:08:17 PM PDT 24
Finished Apr 18 02:08:50 PM PDT 24
Peak memory 217676 kb
Host smart-8752f6df-3890-4497-9886-02c790f3b1d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818270872 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1818270872
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.217429295
Short name T745
Test name
Test status
Simulation time 3414213010 ps
CPU time 26.99 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 217868 kb
Host smart-b17defe7-4db5-404a-8086-f1742a4077c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217429295 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.217429295
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1512627306
Short name T869
Test name
Test status
Simulation time 12230799041 ps
CPU time 23.04 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:33:11 PM PDT 24
Peak memory 212148 kb
Host smart-e02ef9af-7779-444e-8f4b-0a16c75f2697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512627306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1512627306
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2826428465
Short name T747
Test name
Test status
Simulation time 661952828 ps
CPU time 8.2 seconds
Started Apr 18 02:08:39 PM PDT 24
Finished Apr 18 02:08:48 PM PDT 24
Peak memory 211296 kb
Host smart-349dcaf8-3036-465f-a780-b2805976e3cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826428465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2826428465
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2630834741
Short name T118
Test name
Test status
Simulation time 23111593670 ps
CPU time 201.13 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:36:14 PM PDT 24
Peak memory 215316 kb
Host smart-8e15a100-a08d-4933-8dc7-ba5e95a8ff47
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630834741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2630834741
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.756553476
Short name T79
Test name
Test status
Simulation time 25720527487 ps
CPU time 101.41 seconds
Started Apr 18 02:08:16 PM PDT 24
Finished Apr 18 02:09:58 PM PDT 24
Peak memory 219596 kb
Host smart-c7adda88-2685-477b-b9ab-3001c5a7e9e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756553476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.756553476
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1242635844
Short name T807
Test name
Test status
Simulation time 13137390090 ps
CPU time 31.61 seconds
Started Apr 18 02:08:17 PM PDT 24
Finished Apr 18 02:08:49 PM PDT 24
Peak memory 212664 kb
Host smart-a7d2eaec-6d7d-4cb5-8f74-5107bd1ba8b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242635844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1242635844
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3837289298
Short name T884
Test name
Test status
Simulation time 386104984 ps
CPU time 8.42 seconds
Started Apr 18 12:32:59 PM PDT 24
Finished Apr 18 12:33:08 PM PDT 24
Peak memory 211360 kb
Host smart-1e08f959-aba9-4fd0-98e4-d2b3d27feb81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837289298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3837289298
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3062518692
Short name T680
Test name
Test status
Simulation time 4169946418 ps
CPU time 34.99 seconds
Started Apr 18 02:08:18 PM PDT 24
Finished Apr 18 02:08:54 PM PDT 24
Peak memory 218408 kb
Host smart-c5b8f105-3d7b-4764-b2dd-2ae26b747aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062518692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3062518692
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.961998306
Short name T685
Test name
Test status
Simulation time 4169445405 ps
CPU time 34.42 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:26 PM PDT 24
Peak memory 217224 kb
Host smart-4fd67016-f3cb-44d6-a808-2f1e0f106671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961998306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.961998306
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1245320070
Short name T733
Test name
Test status
Simulation time 6982088334 ps
CPU time 101.2 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:34:49 PM PDT 24
Peak memory 212800 kb
Host smart-c225676b-e36b-4c9b-823d-2665e12e4b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245320070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1245320070
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3954966012
Short name T125
Test name
Test status
Simulation time 4326480611 ps
CPU time 94.38 seconds
Started Apr 18 02:08:18 PM PDT 24
Finished Apr 18 02:09:52 PM PDT 24
Peak memory 212940 kb
Host smart-ba80804a-e771-44aa-9ab4-dc8fb0ea7e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954966012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3954966012
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1005460289
Short name T689
Test name
Test status
Simulation time 1057951083 ps
CPU time 8.39 seconds
Started Apr 18 02:08:19 PM PDT 24
Finished Apr 18 02:08:28 PM PDT 24
Peak memory 213876 kb
Host smart-68770c1c-aea2-415f-b019-bef158561cf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005460289 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1005460289
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3975286294
Short name T820
Test name
Test status
Simulation time 422609272 ps
CPU time 8.36 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:32:58 PM PDT 24
Peak memory 216292 kb
Host smart-a5858bcb-3efa-4552-a6f8-4f9ce3eba454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975286294 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3975286294
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.391533557
Short name T873
Test name
Test status
Simulation time 1880226029 ps
CPU time 19.24 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:13 PM PDT 24
Peak memory 211132 kb
Host smart-f763e074-8502-49ca-8764-b9f91924f431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391533557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.391533557
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.751898316
Short name T838
Test name
Test status
Simulation time 739399905 ps
CPU time 13.64 seconds
Started Apr 18 02:08:17 PM PDT 24
Finished Apr 18 02:08:31 PM PDT 24
Peak memory 211312 kb
Host smart-de5df9f0-0c55-4a29-a28d-46a7c480df07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751898316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.751898316
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3785252628
Short name T803
Test name
Test status
Simulation time 3035260572 ps
CPU time 79.35 seconds
Started Apr 18 02:08:17 PM PDT 24
Finished Apr 18 02:09:37 PM PDT 24
Peak memory 213504 kb
Host smart-25107ada-792e-40a8-a170-e74acc5aec64
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785252628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3785252628
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.632794581
Short name T885
Test name
Test status
Simulation time 11503495420 ps
CPU time 104.89 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:34:37 PM PDT 24
Peak memory 215208 kb
Host smart-d118554c-3dda-49f0-a1fc-4d908600cfff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632794581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.632794581
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2246702814
Short name T711
Test name
Test status
Simulation time 661959778 ps
CPU time 8.47 seconds
Started Apr 18 02:08:19 PM PDT 24
Finished Apr 18 02:08:28 PM PDT 24
Peak memory 211316 kb
Host smart-c4a7b81d-0c5c-4e3b-9cff-6f250dac6682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246702814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2246702814
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.966671988
Short name T798
Test name
Test status
Simulation time 1407438305 ps
CPU time 19.92 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 212324 kb
Host smart-bdef1e59-680a-4eff-85a4-f1c673262191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966671988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.966671988
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2270534164
Short name T758
Test name
Test status
Simulation time 353151917 ps
CPU time 11.55 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:33:01 PM PDT 24
Peak memory 217200 kb
Host smart-b3f272e6-fc93-4920-8069-09c8802f80a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270534164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2270534164
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.956586205
Short name T897
Test name
Test status
Simulation time 902805095 ps
CPU time 17.04 seconds
Started Apr 18 02:08:17 PM PDT 24
Finished Apr 18 02:08:34 PM PDT 24
Peak memory 218272 kb
Host smart-6effd89c-af52-4817-83d7-fbaeb5bfdd07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956586205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.956586205
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3462946668
Short name T902
Test name
Test status
Simulation time 3158093867 ps
CPU time 155.1 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 214208 kb
Host smart-0789bee2-a688-44ba-a264-bdd51389bbca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462946668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3462946668
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.581597899
Short name T129
Test name
Test status
Simulation time 2946244081 ps
CPU time 150.95 seconds
Started Apr 18 02:08:16 PM PDT 24
Finished Apr 18 02:10:47 PM PDT 24
Peak memory 213988 kb
Host smart-93f159d8-a8f4-4ec4-b587-c1d91705b931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581597899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.581597899
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2708995377
Short name T444
Test name
Test status
Simulation time 687977180 ps
CPU time 8.07 seconds
Started Apr 18 12:32:57 PM PDT 24
Finished Apr 18 12:33:06 PM PDT 24
Peak memory 211284 kb
Host smart-4a9d16a2-2647-4c05-978e-1b867753a0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708995377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2708995377
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.488957793
Short name T533
Test name
Test status
Simulation time 17799745793 ps
CPU time 34.96 seconds
Started Apr 18 02:03:20 PM PDT 24
Finished Apr 18 02:03:56 PM PDT 24
Peak memory 212284 kb
Host smart-e364c691-887b-4657-b7f3-74a27517c82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488957793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.488957793
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1839150231
Short name T108
Test name
Test status
Simulation time 331672143978 ps
CPU time 810.16 seconds
Started Apr 18 02:03:13 PM PDT 24
Finished Apr 18 02:16:44 PM PDT 24
Peak memory 240528 kb
Host smart-77eda696-4961-4048-b916-bebfa936775b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839150231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1839150231
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1883089908
Short name T30
Test name
Test status
Simulation time 46728082154 ps
CPU time 461.54 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:40:34 PM PDT 24
Peak memory 239872 kb
Host smart-5bccf855-6026-435d-a506-5220a0e6d36d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883089908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1883089908
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2597684114
Short name T212
Test name
Test status
Simulation time 19753632778 ps
CPU time 47.67 seconds
Started Apr 18 02:03:13 PM PDT 24
Finished Apr 18 02:04:01 PM PDT 24
Peak memory 215240 kb
Host smart-ede5c182-663d-4155-afe7-d8551047a2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597684114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2597684114
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2599799954
Short name T411
Test name
Test status
Simulation time 4517828841 ps
CPU time 26.63 seconds
Started Apr 18 02:03:12 PM PDT 24
Finished Apr 18 02:03:40 PM PDT 24
Peak memory 212652 kb
Host smart-bea492fa-5dac-44de-8c65-e541b866300a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599799954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2599799954
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3024401921
Short name T337
Test name
Test status
Simulation time 7066788038 ps
CPU time 29.97 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:26 PM PDT 24
Peak memory 212608 kb
Host smart-05d7addd-c185-49d7-83a6-b15ccd700b5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024401921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3024401921
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2157523432
Short name T37
Test name
Test status
Simulation time 32448269855 ps
CPU time 131.09 seconds
Started Apr 18 12:33:15 PM PDT 24
Finished Apr 18 12:35:27 PM PDT 24
Peak memory 238784 kb
Host smart-ff342af3-3004-4bd9-b3fe-88c0a1e7e3b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157523432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2157523432
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2216425709
Short name T33
Test name
Test status
Simulation time 4367838901 ps
CPU time 130.82 seconds
Started Apr 18 02:03:19 PM PDT 24
Finished Apr 18 02:05:30 PM PDT 24
Peak memory 236856 kb
Host smart-6b8da20a-48a4-4dad-9c08-74d67728b599
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216425709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2216425709
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2542025426
Short name T43
Test name
Test status
Simulation time 357602442 ps
CPU time 19.8 seconds
Started Apr 18 02:03:13 PM PDT 24
Finished Apr 18 02:03:34 PM PDT 24
Peak memory 216448 kb
Host smart-f6453ffe-333a-465a-9744-a2114f43660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542025426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2542025426
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2943611800
Short name T164
Test name
Test status
Simulation time 14376026060 ps
CPU time 40.65 seconds
Started Apr 18 12:32:55 PM PDT 24
Finished Apr 18 12:33:37 PM PDT 24
Peak memory 217156 kb
Host smart-dc1abc23-3707-4e67-ad7a-3f0797b88305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943611800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2943611800
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1701153455
Short name T579
Test name
Test status
Simulation time 13393218295 ps
CPU time 120.28 seconds
Started Apr 18 02:03:12 PM PDT 24
Finished Apr 18 02:05:13 PM PDT 24
Peak memory 219408 kb
Host smart-612fbbd6-9cae-462a-87c3-8407d872f091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701153455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1701153455
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2417876481
Short name T360
Test name
Test status
Simulation time 15041830372 ps
CPU time 148.2 seconds
Started Apr 18 12:32:49 PM PDT 24
Finished Apr 18 12:35:19 PM PDT 24
Peak memory 221368 kb
Host smart-1832c53a-2a9b-40d1-9d15-e70f2ac79ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417876481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2417876481
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3404659172
Short name T48
Test name
Test status
Simulation time 55228187786 ps
CPU time 2241.06 seconds
Started Apr 18 02:03:19 PM PDT 24
Finished Apr 18 02:40:41 PM PDT 24
Peak memory 240280 kb
Host smart-e3be2696-d359-43ad-8751-383bb8a3c1f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404659172 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3404659172
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4172385048
Short name T452
Test name
Test status
Simulation time 3790316963 ps
CPU time 31.65 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 211960 kb
Host smart-35d277a4-7e12-494e-b787-0247517e8796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172385048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4172385048
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.86694284
Short name T528
Test name
Test status
Simulation time 167621836 ps
CPU time 8.3 seconds
Started Apr 18 02:03:29 PM PDT 24
Finished Apr 18 02:03:38 PM PDT 24
Peak memory 211272 kb
Host smart-28f9fd85-0c6c-4b6c-bbd5-a343161277b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86694284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.86694284
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1107553638
Short name T423
Test name
Test status
Simulation time 76715886756 ps
CPU time 810.73 seconds
Started Apr 18 02:03:19 PM PDT 24
Finished Apr 18 02:16:50 PM PDT 24
Peak memory 237900 kb
Host smart-8cb3393a-b6af-4187-bb08-5a06d8062fcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107553638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1107553638
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.217014720
Short name T264
Test name
Test status
Simulation time 58020499833 ps
CPU time 391.57 seconds
Started Apr 18 12:33:17 PM PDT 24
Finished Apr 18 12:39:49 PM PDT 24
Peak memory 240408 kb
Host smart-25b1b534-2944-4ba0-a3d9-e9488f78f1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217014720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.217014720
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1898852616
Short name T440
Test name
Test status
Simulation time 1034870392 ps
CPU time 22.84 seconds
Started Apr 18 02:03:17 PM PDT 24
Finished Apr 18 02:03:40 PM PDT 24
Peak memory 212728 kb
Host smart-e76fb35b-7c3b-44a5-9d1f-6050964edd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898852616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1898852616
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4145942197
Short name T377
Test name
Test status
Simulation time 5592737634 ps
CPU time 36.18 seconds
Started Apr 18 12:32:58 PM PDT 24
Finished Apr 18 12:33:35 PM PDT 24
Peak memory 215252 kb
Host smart-5a16bfec-18d9-4bd3-9283-c0a9aeba80de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145942197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4145942197
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3681901470
Short name T503
Test name
Test status
Simulation time 346533982 ps
CPU time 10.16 seconds
Started Apr 18 02:03:21 PM PDT 24
Finished Apr 18 02:03:32 PM PDT 24
Peak memory 212280 kb
Host smart-d4e166bd-3959-4eae-a9a7-69ee654e970f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681901470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3681901470
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.390069086
Short name T244
Test name
Test status
Simulation time 6604558887 ps
CPU time 33.07 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 212636 kb
Host smart-80d72eec-dab7-4a86-84ca-92841da2adf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390069086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.390069086
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2269647509
Short name T39
Test name
Test status
Simulation time 1025059859 ps
CPU time 227.8 seconds
Started Apr 18 12:33:16 PM PDT 24
Finished Apr 18 12:37:04 PM PDT 24
Peak memory 236660 kb
Host smart-2128b766-7250-4c51-aa56-36f60a687d81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269647509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2269647509
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.992054169
Short name T41
Test name
Test status
Simulation time 3798502433 ps
CPU time 138.89 seconds
Started Apr 18 02:03:27 PM PDT 24
Finished Apr 18 02:05:46 PM PDT 24
Peak memory 238688 kb
Host smart-b7f0c42f-f99b-41fc-aa29-0397917ac98b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992054169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.992054169
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2202015966
Short name T213
Test name
Test status
Simulation time 23962892769 ps
CPU time 64.04 seconds
Started Apr 18 02:03:18 PM PDT 24
Finished Apr 18 02:04:23 PM PDT 24
Peak memory 217324 kb
Host smart-b363bd1b-3ab5-45aa-bf1e-80bf4bbb62b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202015966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2202015966
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2706933985
Short name T344
Test name
Test status
Simulation time 7332262220 ps
CPU time 27.64 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:21 PM PDT 24
Peak memory 215924 kb
Host smart-41a6ce9f-dbdd-4216-bd7e-364dac6af8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706933985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2706933985
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1571843026
Short name T609
Test name
Test status
Simulation time 587255565 ps
CPU time 16.24 seconds
Started Apr 18 02:03:18 PM PDT 24
Finished Apr 18 02:03:35 PM PDT 24
Peak memory 212508 kb
Host smart-c569e9fc-9d40-44d9-801d-793d30da46ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571843026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1571843026
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2141752376
Short name T595
Test name
Test status
Simulation time 4172398599 ps
CPU time 42.52 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:36 PM PDT 24
Peak memory 212724 kb
Host smart-9c6d29d4-313d-425c-8f75-a2af754dbef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141752376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2141752376
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4086318824
Short name T174
Test name
Test status
Simulation time 8437841323 ps
CPU time 34.31 seconds
Started Apr 18 02:04:25 PM PDT 24
Finished Apr 18 02:04:59 PM PDT 24
Peak memory 212308 kb
Host smart-abaa112d-ed62-47b2-8a07-1d56f05842f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086318824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4086318824
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4147686330
Short name T323
Test name
Test status
Simulation time 1155116630 ps
CPU time 12.92 seconds
Started Apr 18 12:33:11 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 211364 kb
Host smart-35833dc0-3970-448e-9f32-41743c10f7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147686330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4147686330
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.31057064
Short name T263
Test name
Test status
Simulation time 140782589187 ps
CPU time 441.09 seconds
Started Apr 18 02:04:24 PM PDT 24
Finished Apr 18 02:11:46 PM PDT 24
Peak memory 215744 kb
Host smart-3d16b41a-45e9-4853-a9ab-7eec27cf1e6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_co
rrupt_sig_fatal_chk.31057064
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1644805009
Short name T270
Test name
Test status
Simulation time 33898391241 ps
CPU time 46.33 seconds
Started Apr 18 02:04:25 PM PDT 24
Finished Apr 18 02:05:12 PM PDT 24
Peak memory 216152 kb
Host smart-bba4876d-06e1-48f4-b278-47e2b9e1a7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644805009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1644805009
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1062264303
Short name T446
Test name
Test status
Simulation time 23184546651 ps
CPU time 26.21 seconds
Started Apr 18 12:32:57 PM PDT 24
Finished Apr 18 12:33:24 PM PDT 24
Peak memory 211776 kb
Host smart-f3424885-75af-40bd-bc11-c945a5cef230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062264303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1062264303
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4095218738
Short name T347
Test name
Test status
Simulation time 3237687475 ps
CPU time 26.25 seconds
Started Apr 18 02:04:23 PM PDT 24
Finished Apr 18 02:04:49 PM PDT 24
Peak memory 211392 kb
Host smart-cfe4b7c0-59b6-4640-88fd-94da413509f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095218738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4095218738
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1671349695
Short name T85
Test name
Test status
Simulation time 684588931 ps
CPU time 26.09 seconds
Started Apr 18 02:04:24 PM PDT 24
Finished Apr 18 02:04:50 PM PDT 24
Peak memory 215880 kb
Host smart-7cd3001c-d053-419c-9fe9-18e0bc7a5b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671349695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1671349695
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4201882121
Short name T560
Test name
Test status
Simulation time 70061125650 ps
CPU time 73.72 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 217708 kb
Host smart-47b00dae-006d-4e8a-8b80-5f471faddf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201882121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4201882121
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4105034725
Short name T317
Test name
Test status
Simulation time 86288733162 ps
CPU time 177.53 seconds
Started Apr 18 02:04:25 PM PDT 24
Finished Apr 18 02:07:23 PM PDT 24
Peak memory 219356 kb
Host smart-59bb7bc9-1ab3-490c-82fd-f33c0d1336a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105034725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4105034725
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.596648736
Short name T483
Test name
Test status
Simulation time 4157227422 ps
CPU time 39.65 seconds
Started Apr 18 12:33:00 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 213676 kb
Host smart-2dc1437f-653f-4616-8373-0ec61c37cfa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596648736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.596648736
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3918977823
Short name T525
Test name
Test status
Simulation time 1964033556 ps
CPU time 19.79 seconds
Started Apr 18 12:33:16 PM PDT 24
Finished Apr 18 12:33:36 PM PDT 24
Peak memory 211280 kb
Host smart-8618fe1f-2dd8-4fe6-aa33-68d8b3a9efbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918977823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3918977823
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.783974618
Short name T215
Test name
Test status
Simulation time 4444580434 ps
CPU time 33.1 seconds
Started Apr 18 02:04:36 PM PDT 24
Finished Apr 18 02:05:09 PM PDT 24
Peak memory 212368 kb
Host smart-b33eff79-0a96-461e-930d-72b9f7ac4073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783974618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.783974618
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1949468706
Short name T522
Test name
Test status
Simulation time 4812556223 ps
CPU time 159.77 seconds
Started Apr 18 02:04:34 PM PDT 24
Finished Apr 18 02:07:14 PM PDT 24
Peak memory 240212 kb
Host smart-0befeafc-6f59-4646-840b-4c440e9d187e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949468706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1949468706
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.81027999
Short name T255
Test name
Test status
Simulation time 17005492376 ps
CPU time 258.92 seconds
Started Apr 18 12:33:08 PM PDT 24
Finished Apr 18 12:37:30 PM PDT 24
Peak memory 238884 kb
Host smart-acba94fe-c052-4553-9a33-89ed0898500b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81027999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_co
rrupt_sig_fatal_chk.81027999
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3014884311
Short name T540
Test name
Test status
Simulation time 29739237304 ps
CPU time 59.92 seconds
Started Apr 18 02:04:39 PM PDT 24
Finished Apr 18 02:05:40 PM PDT 24
Peak memory 215168 kb
Host smart-f3bbc954-bb67-4673-a224-3ed7b39b1118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014884311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3014884311
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3754538017
Short name T641
Test name
Test status
Simulation time 675919269 ps
CPU time 19.75 seconds
Started Apr 18 12:32:58 PM PDT 24
Finished Apr 18 12:33:19 PM PDT 24
Peak memory 214632 kb
Host smart-b369a24b-4d6a-4862-8ec1-279a38316f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754538017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3754538017
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1900907582
Short name T259
Test name
Test status
Simulation time 223983387 ps
CPU time 10.38 seconds
Started Apr 18 02:04:37 PM PDT 24
Finished Apr 18 02:04:48 PM PDT 24
Peak memory 212572 kb
Host smart-450239fc-bdda-42f2-a374-169213cc8042
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900907582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1900907582
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1915106786
Short name T386
Test name
Test status
Simulation time 719385973 ps
CPU time 10.47 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:33:35 PM PDT 24
Peak memory 212572 kb
Host smart-6f8a2d19-1191-4ebd-9347-a42fa88e6e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915106786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1915106786
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3336483896
Short name T46
Test name
Test status
Simulation time 12256991956 ps
CPU time 59.54 seconds
Started Apr 18 02:04:23 PM PDT 24
Finished Apr 18 02:05:23 PM PDT 24
Peak memory 217156 kb
Host smart-4fd8e563-afbd-410f-82e0-3223cd1613ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336483896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3336483896
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1634328391
Short name T552
Test name
Test status
Simulation time 39220754901 ps
CPU time 109.4 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 220624 kb
Host smart-dddfebf1-ea9d-49e9-9d92-71148600f420
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634328391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1634328391
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2249435656
Short name T393
Test name
Test status
Simulation time 33770661504 ps
CPU time 157.04 seconds
Started Apr 18 02:04:33 PM PDT 24
Finished Apr 18 02:07:10 PM PDT 24
Peak memory 222756 kb
Host smart-ba243bf1-e213-48d6-be84-2cdb5d94e13d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249435656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2249435656
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.142556190
Short name T233
Test name
Test status
Simulation time 3942664830 ps
CPU time 23.15 seconds
Started Apr 18 02:04:42 PM PDT 24
Finished Apr 18 02:05:06 PM PDT 24
Peak memory 211480 kb
Host smart-132aff99-cb7b-408e-8f95-0fea130bf285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142556190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.142556190
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2605577453
Short name T234
Test name
Test status
Simulation time 1877330122 ps
CPU time 17.57 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:26 PM PDT 24
Peak memory 211792 kb
Host smart-a94ea7e2-f790-4c16-9ce3-f6f10d9418f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605577453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2605577453
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1619838496
Short name T554
Test name
Test status
Simulation time 65013141228 ps
CPU time 212.02 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:36:38 PM PDT 24
Peak memory 227644 kb
Host smart-45145a62-6cd4-4bc4-b4e4-3c9ef372b7a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619838496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1619838496
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.239049455
Short name T669
Test name
Test status
Simulation time 17875884999 ps
CPU time 308.36 seconds
Started Apr 18 02:04:41 PM PDT 24
Finished Apr 18 02:09:50 PM PDT 24
Peak memory 239956 kb
Host smart-bcada451-a38d-4797-9505-ce0e60985e13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239049455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.239049455
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1323976426
Short name T250
Test name
Test status
Simulation time 6932499802 ps
CPU time 31.43 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 215372 kb
Host smart-6131c0ba-6a6d-4ef3-b0c1-289c1090c286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323976426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1323976426
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1595172856
Short name T371
Test name
Test status
Simulation time 675863466 ps
CPU time 23.68 seconds
Started Apr 18 02:04:42 PM PDT 24
Finished Apr 18 02:05:06 PM PDT 24
Peak memory 213636 kb
Host smart-2ee632fd-b177-4452-af91-a18b4cedf4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595172856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1595172856
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3541609294
Short name T247
Test name
Test status
Simulation time 699971827 ps
CPU time 10.56 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 212128 kb
Host smart-003cb783-75ab-4c0e-a753-f5b451ad6625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541609294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3541609294
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.471690075
Short name T287
Test name
Test status
Simulation time 10758864219 ps
CPU time 19.08 seconds
Started Apr 18 02:04:35 PM PDT 24
Finished Apr 18 02:04:54 PM PDT 24
Peak memory 211940 kb
Host smart-57b74157-b18e-4833-8f1b-5b6f237d49ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471690075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.471690075
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1786941758
Short name T203
Test name
Test status
Simulation time 510514499 ps
CPU time 24.01 seconds
Started Apr 18 02:04:35 PM PDT 24
Finished Apr 18 02:04:59 PM PDT 24
Peak memory 215852 kb
Host smart-50bfbf82-5351-487f-b499-1acb9a2bc7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786941758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1786941758
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1245195496
Short name T650
Test name
Test status
Simulation time 4543058079 ps
CPU time 47.9 seconds
Started Apr 18 02:04:34 PM PDT 24
Finished Apr 18 02:05:23 PM PDT 24
Peak memory 216720 kb
Host smart-e9a4da31-08f9-4602-8afd-46d03ce8ea94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245195496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1245195496
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2816498293
Short name T432
Test name
Test status
Simulation time 14365762325 ps
CPU time 79.27 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:34:28 PM PDT 24
Peak memory 227516 kb
Host smart-b908b0fb-7ef6-4b46-a2e7-36f04943792a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816498293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2816498293
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.185284120
Short name T148
Test name
Test status
Simulation time 1373419480 ps
CPU time 16.85 seconds
Started Apr 18 02:04:40 PM PDT 24
Finished Apr 18 02:04:58 PM PDT 24
Peak memory 211388 kb
Host smart-58b37dfa-597f-4148-a948-51973ea5701e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185284120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.185284120
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2146102458
Short name T278
Test name
Test status
Simulation time 6867849087 ps
CPU time 19.58 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:33:28 PM PDT 24
Peak memory 212308 kb
Host smart-cf01bdf5-d711-4aac-8845-876f3b9ad1d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146102458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2146102458
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3277634190
Short name T271
Test name
Test status
Simulation time 7245448890 ps
CPU time 270.06 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:37:37 PM PDT 24
Peak memory 237840 kb
Host smart-00b91d7f-6c85-4ace-a92d-3dc3ecc1e17e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277634190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3277634190
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4254826884
Short name T189
Test name
Test status
Simulation time 50158673093 ps
CPU time 245.72 seconds
Started Apr 18 02:04:41 PM PDT 24
Finished Apr 18 02:08:48 PM PDT 24
Peak memory 219612 kb
Host smart-ebb17eb9-7af9-409b-a47f-38db5153e9bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254826884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4254826884
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3988157468
Short name T251
Test name
Test status
Simulation time 2407318749 ps
CPU time 28.02 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:38 PM PDT 24
Peak memory 214948 kb
Host smart-6e60fce9-d287-4045-9566-abecbd7bb143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988157468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3988157468
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4005138461
Short name T242
Test name
Test status
Simulation time 4353878732 ps
CPU time 33.61 seconds
Started Apr 18 02:04:41 PM PDT 24
Finished Apr 18 02:05:16 PM PDT 24
Peak memory 215244 kb
Host smart-4c4c4c1e-449f-433d-92f3-0075e27e0137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005138461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4005138461
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1110829338
Short name T435
Test name
Test status
Simulation time 4308386906 ps
CPU time 24.6 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:34 PM PDT 24
Peak memory 211312 kb
Host smart-37420389-e954-49a1-a27c-5e83a184cf65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110829338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1110829338
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1254508185
Short name T513
Test name
Test status
Simulation time 6557714082 ps
CPU time 23.87 seconds
Started Apr 18 02:04:44 PM PDT 24
Finished Apr 18 02:05:08 PM PDT 24
Peak memory 211376 kb
Host smart-e21151c3-d5da-4695-a8a2-2f8792c5891c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254508185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1254508185
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1093547120
Short name T318
Test name
Test status
Simulation time 53044867882 ps
CPU time 60.95 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 218872 kb
Host smart-7737d556-0b72-42f7-b469-cf901d2c78be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093547120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1093547120
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.712808306
Short name T557
Test name
Test status
Simulation time 12455089645 ps
CPU time 39.49 seconds
Started Apr 18 02:04:41 PM PDT 24
Finished Apr 18 02:05:21 PM PDT 24
Peak memory 217064 kb
Host smart-79657b64-e652-4be4-a384-0de6bf2659d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712808306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.712808306
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2435878528
Short name T642
Test name
Test status
Simulation time 48176340092 ps
CPU time 101.12 seconds
Started Apr 18 12:33:16 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 219292 kb
Host smart-2fc9cde5-ae3e-4dca-8e50-b2bfe1cbabc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435878528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2435878528
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2463149207
Short name T488
Test name
Test status
Simulation time 20689308205 ps
CPU time 60.35 seconds
Started Apr 18 02:04:42 PM PDT 24
Finished Apr 18 02:05:43 PM PDT 24
Peak memory 218952 kb
Host smart-adad2171-3ee3-43f9-9aab-36f8d34d4fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463149207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2463149207
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2990151996
Short name T568
Test name
Test status
Simulation time 123266784505 ps
CPU time 944.57 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:48:54 PM PDT 24
Peak memory 237004 kb
Host smart-be4744ad-06c5-485c-95e2-dbf0f816283d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990151996 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2990151996
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2064120570
Short name T462
Test name
Test status
Simulation time 9885877095 ps
CPU time 23.09 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:33:28 PM PDT 24
Peak memory 211716 kb
Host smart-07ef3037-37c5-47cf-9f30-1c7d678efe15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064120570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2064120570
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2734930698
Short name T238
Test name
Test status
Simulation time 2345063628 ps
CPU time 16.83 seconds
Started Apr 18 02:04:52 PM PDT 24
Finished Apr 18 02:05:09 PM PDT 24
Peak memory 211524 kb
Host smart-32793e0f-77d0-4121-bf8f-fd90674bf510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734930698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2734930698
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.18385171
Short name T105
Test name
Test status
Simulation time 214337571450 ps
CPU time 660.74 seconds
Started Apr 18 02:04:51 PM PDT 24
Finished Apr 18 02:15:52 PM PDT 24
Peak memory 219740 kb
Host smart-34ce0dce-e583-41dd-ad83-f3e9c8f7aefb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.18385171
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2404098731
Short name T564
Test name
Test status
Simulation time 13216850476 ps
CPU time 227.96 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:36:57 PM PDT 24
Peak memory 240056 kb
Host smart-5d180018-936a-44ae-be98-cb1f987914bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404098731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2404098731
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2714812410
Short name T156
Test name
Test status
Simulation time 28829673040 ps
CPU time 64.53 seconds
Started Apr 18 12:33:15 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 215052 kb
Host smart-a10842d2-452d-4371-88a8-3a9ec2031772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714812410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2714812410
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.60731341
Short name T430
Test name
Test status
Simulation time 27612042102 ps
CPU time 61.74 seconds
Started Apr 18 02:04:53 PM PDT 24
Finished Apr 18 02:05:55 PM PDT 24
Peak memory 215256 kb
Host smart-470cfb20-50cf-4186-98e5-516a2b9e95d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60731341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.60731341
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3383261519
Short name T401
Test name
Test status
Simulation time 1404223445 ps
CPU time 12.65 seconds
Started Apr 18 02:04:53 PM PDT 24
Finished Apr 18 02:05:06 PM PDT 24
Peak memory 211572 kb
Host smart-ab327416-e161-4124-9f9e-5b4a7213d9af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383261519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3383261519
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.56550874
Short name T168
Test name
Test status
Simulation time 2101074143 ps
CPU time 22.63 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:33:28 PM PDT 24
Peak memory 212176 kb
Host smart-3528319b-9fee-42d7-a103-5bfa74cd0741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56550874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.56550874
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2844417596
Short name T155
Test name
Test status
Simulation time 20546107881 ps
CPU time 50.89 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:34:00 PM PDT 24
Peak memory 217864 kb
Host smart-cf0bf0bd-675a-479a-a7fa-fb6873c82372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844417596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2844417596
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.622035594
Short name T590
Test name
Test status
Simulation time 362821628 ps
CPU time 20.58 seconds
Started Apr 18 02:04:43 PM PDT 24
Finished Apr 18 02:05:04 PM PDT 24
Peak memory 217044 kb
Host smart-d27ae012-76b6-46d2-8611-29ed5b64f870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622035594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.622035594
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3152547530
Short name T459
Test name
Test status
Simulation time 8033173103 ps
CPU time 72.37 seconds
Started Apr 18 12:33:22 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 219128 kb
Host smart-27360d21-391a-430a-91d8-9384f2d52d5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152547530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3152547530
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.791695262
Short name T574
Test name
Test status
Simulation time 7133354664 ps
CPU time 43.47 seconds
Started Apr 18 02:04:42 PM PDT 24
Finished Apr 18 02:05:26 PM PDT 24
Peak memory 219888 kb
Host smart-02cd634f-cf6b-4e09-b5aa-43a963a1a32c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791695262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.791695262
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2856354195
Short name T34
Test name
Test status
Simulation time 1891100958 ps
CPU time 20.51 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:33:45 PM PDT 24
Peak memory 211184 kb
Host smart-4ac1b323-0877-4cc2-963c-b78057d7240a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856354195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2856354195
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.539611730
Short name T402
Test name
Test status
Simulation time 2067338774 ps
CPU time 21.11 seconds
Started Apr 18 02:05:03 PM PDT 24
Finished Apr 18 02:05:24 PM PDT 24
Peak memory 211944 kb
Host smart-9f51bcc9-3f06-4e3f-a579-6035462643ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539611730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.539611730
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3115847479
Short name T140
Test name
Test status
Simulation time 73904764045 ps
CPU time 327.85 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:38:37 PM PDT 24
Peak memory 217832 kb
Host smart-b0532dd1-780b-4f87-af22-52e4d26aa347
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115847479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3115847479
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3812607002
Short name T11
Test name
Test status
Simulation time 226856013286 ps
CPU time 532.24 seconds
Started Apr 18 02:05:01 PM PDT 24
Finished Apr 18 02:13:54 PM PDT 24
Peak memory 240372 kb
Host smart-dfdd4e9a-a046-4292-ad43-a5af41ed0e44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812607002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3812607002
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3830617855
Short name T413
Test name
Test status
Simulation time 9309687871 ps
CPU time 67.82 seconds
Started Apr 18 02:05:01 PM PDT 24
Finished Apr 18 02:06:10 PM PDT 24
Peak memory 215216 kb
Host smart-223305e8-37c2-4c72-9c07-28159279cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830617855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3830617855
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3836209590
Short name T521
Test name
Test status
Simulation time 17047282036 ps
CPU time 46.24 seconds
Started Apr 18 12:33:18 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 215056 kb
Host smart-6c7515e3-b9f3-4944-90c7-abde573dfc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836209590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3836209590
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2391389534
Short name T656
Test name
Test status
Simulation time 826044865 ps
CPU time 10.09 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 212232 kb
Host smart-a714e49c-2573-42c9-9a79-da481abf58e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391389534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2391389534
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3039089504
Short name T288
Test name
Test status
Simulation time 12377174768 ps
CPU time 27.97 seconds
Started Apr 18 02:04:53 PM PDT 24
Finished Apr 18 02:05:21 PM PDT 24
Peak memory 211424 kb
Host smart-9f57eb43-2f31-4bb1-87b0-74dd1c8a1897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039089504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3039089504
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.479557149
Short name T538
Test name
Test status
Simulation time 8056946013 ps
CPU time 76.96 seconds
Started Apr 18 02:04:52 PM PDT 24
Finished Apr 18 02:06:09 PM PDT 24
Peak memory 215288 kb
Host smart-a9288475-5c55-4a01-883a-87872cd3969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479557149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.479557149
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.489544058
Short name T205
Test name
Test status
Simulation time 7613233513 ps
CPU time 81.92 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:34:46 PM PDT 24
Peak memory 215148 kb
Host smart-88d13c44-9ba4-437d-ba7f-7b4243fdea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489544058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.489544058
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1608585822
Short name T316
Test name
Test status
Simulation time 4485920114 ps
CPU time 45.98 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:56 PM PDT 24
Peak memory 220100 kb
Host smart-c3b8f64d-7563-4239-8380-c7293c666dcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608585822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1608585822
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.554748196
Short name T671
Test name
Test status
Simulation time 2172765571 ps
CPU time 62.61 seconds
Started Apr 18 02:04:52 PM PDT 24
Finished Apr 18 02:05:56 PM PDT 24
Peak memory 219448 kb
Host smart-ce2d5863-daf1-4fb3-a596-5e396db4e4f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554748196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.554748196
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3214300889
Short name T56
Test name
Test status
Simulation time 142620224624 ps
CPU time 3167.2 seconds
Started Apr 18 02:04:59 PM PDT 24
Finished Apr 18 02:57:47 PM PDT 24
Peak memory 235928 kb
Host smart-f128a7d7-fc6b-47dd-95e1-1cb60f685790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214300889 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3214300889
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3207231365
Short name T482
Test name
Test status
Simulation time 2173660247 ps
CPU time 20 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:29 PM PDT 24
Peak memory 212036 kb
Host smart-65a23b7d-a12e-492a-81f7-463ef6f91eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207231365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3207231365
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4005825975
Short name T674
Test name
Test status
Simulation time 5529046591 ps
CPU time 28 seconds
Started Apr 18 02:05:00 PM PDT 24
Finished Apr 18 02:05:28 PM PDT 24
Peak memory 212344 kb
Host smart-b18b2eb8-06cd-4631-9a85-28e11be88eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005825975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4005825975
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1303639507
Short name T286
Test name
Test status
Simulation time 406691170570 ps
CPU time 718.8 seconds
Started Apr 18 02:05:03 PM PDT 24
Finished Apr 18 02:17:02 PM PDT 24
Peak memory 217040 kb
Host smart-747f29dd-3700-493e-a01e-5f180e53cc27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303639507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1303639507
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3384112830
Short name T149
Test name
Test status
Simulation time 46173931482 ps
CPU time 572.78 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:42:42 PM PDT 24
Peak memory 217092 kb
Host smart-aa3d9796-1662-4e81-8582-96f3867f97c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384112830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3384112830
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1905140883
Short name T610
Test name
Test status
Simulation time 487128635 ps
CPU time 19.24 seconds
Started Apr 18 02:05:00 PM PDT 24
Finished Apr 18 02:05:20 PM PDT 24
Peak memory 214764 kb
Host smart-416b5ab0-0660-45c2-a4b5-b1a9d25d4195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905140883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1905140883
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2473689152
Short name T103
Test name
Test status
Simulation time 5350115194 ps
CPU time 36.84 seconds
Started Apr 18 12:33:22 PM PDT 24
Finished Apr 18 12:34:00 PM PDT 24
Peak memory 215084 kb
Host smart-9dab3f4d-2d06-4154-b2fa-7e57a884463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473689152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2473689152
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.137870199
Short name T170
Test name
Test status
Simulation time 14496559288 ps
CPU time 31.85 seconds
Started Apr 18 02:05:02 PM PDT 24
Finished Apr 18 02:05:35 PM PDT 24
Peak memory 211844 kb
Host smart-342145fe-7341-488e-b31a-d00c99b06069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137870199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.137870199
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.600298235
Short name T237
Test name
Test status
Simulation time 2215655727 ps
CPU time 23.68 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:32 PM PDT 24
Peak memory 212584 kb
Host smart-26b3a521-bc5d-4fce-b457-7998d1a258ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600298235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.600298235
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.366109923
Short name T592
Test name
Test status
Simulation time 14697632112 ps
CPU time 65.12 seconds
Started Apr 18 02:05:01 PM PDT 24
Finished Apr 18 02:06:06 PM PDT 24
Peak memory 217872 kb
Host smart-3549e476-8c45-4176-9a43-1c90fe68c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366109923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.366109923
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3743939680
Short name T309
Test name
Test status
Simulation time 32347065301 ps
CPU time 72.82 seconds
Started Apr 18 12:33:15 PM PDT 24
Finished Apr 18 12:34:29 PM PDT 24
Peak memory 218212 kb
Host smart-4bd65f4e-1a11-418c-a1e9-ed2fbdcbfa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743939680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3743939680
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2960992322
Short name T529
Test name
Test status
Simulation time 1071448206 ps
CPU time 42.49 seconds
Started Apr 18 12:32:55 PM PDT 24
Finished Apr 18 12:33:39 PM PDT 24
Peak memory 219184 kb
Host smart-8ea0cd5d-fb4f-4d07-a162-5e211f8a246f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960992322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2960992322
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3418132020
Short name T209
Test name
Test status
Simulation time 8117718073 ps
CPU time 72.75 seconds
Started Apr 18 02:05:03 PM PDT 24
Finished Apr 18 02:06:16 PM PDT 24
Peak memory 220304 kb
Host smart-e9071366-3c55-45c1-88c6-e37d6da46d62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418132020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3418132020
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2494041760
Short name T18
Test name
Test status
Simulation time 71263379161 ps
CPU time 670.09 seconds
Started Apr 18 12:33:28 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 235796 kb
Host smart-166df181-fa75-43e9-9f52-6627f2f43c0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494041760 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2494041760
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1391806970
Short name T551
Test name
Test status
Simulation time 9730177656 ps
CPU time 23.22 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:32 PM PDT 24
Peak memory 211648 kb
Host smart-a7f044cf-a386-40f6-94e2-71da88fc29d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391806970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1391806970
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.557614193
Short name T605
Test name
Test status
Simulation time 10555376149 ps
CPU time 30.2 seconds
Started Apr 18 02:05:08 PM PDT 24
Finished Apr 18 02:05:39 PM PDT 24
Peak memory 212224 kb
Host smart-d862cfa9-a376-457b-9529-be72bad8e5e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557614193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.557614193
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.182669826
Short name T458
Test name
Test status
Simulation time 80010525648 ps
CPU time 289.56 seconds
Started Apr 18 02:05:00 PM PDT 24
Finished Apr 18 02:09:50 PM PDT 24
Peak memory 227928 kb
Host smart-10de8acc-d2ca-4e13-ad80-57d0ce4122e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182669826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.182669826
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.591229946
Short name T24
Test name
Test status
Simulation time 57955480685 ps
CPU time 717.04 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:45:05 PM PDT 24
Peak memory 240720 kb
Host smart-4545b2e8-6030-43f3-beee-378f3669f362
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591229946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.591229946
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1557520810
Short name T232
Test name
Test status
Simulation time 2060595119 ps
CPU time 19.31 seconds
Started Apr 18 12:33:08 PM PDT 24
Finished Apr 18 12:33:29 PM PDT 24
Peak memory 214948 kb
Host smart-00277a67-3a17-4c53-b9f5-b2fa9addc466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557520810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1557520810
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3794118254
Short name T260
Test name
Test status
Simulation time 44996693329 ps
CPU time 54.39 seconds
Started Apr 18 02:05:07 PM PDT 24
Finished Apr 18 02:06:02 PM PDT 24
Peak memory 214084 kb
Host smart-6af5b51d-6376-447b-bdf6-e13aadf97106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794118254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3794118254
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3718258716
Short name T338
Test name
Test status
Simulation time 8904433122 ps
CPU time 22.73 seconds
Started Apr 18 02:05:02 PM PDT 24
Finished Apr 18 02:05:26 PM PDT 24
Peak memory 212956 kb
Host smart-2e4496d9-384c-4a0a-8b1f-cf86488aeacd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718258716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3718258716
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.709246483
Short name T537
Test name
Test status
Simulation time 6732218230 ps
CPU time 29.68 seconds
Started Apr 18 12:33:08 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 211292 kb
Host smart-058d5c6f-b1a3-41fa-a77c-1ea026ccbbd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709246483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.709246483
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.195892722
Short name T84
Test name
Test status
Simulation time 30110927159 ps
CPU time 73.42 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:34:23 PM PDT 24
Peak memory 217216 kb
Host smart-82d69cf3-5e89-4af3-90b4-bbe868faad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195892722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.195892722
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2541607792
Short name T627
Test name
Test status
Simulation time 364918690 ps
CPU time 20.97 seconds
Started Apr 18 02:05:01 PM PDT 24
Finished Apr 18 02:05:23 PM PDT 24
Peak memory 216808 kb
Host smart-802cbcfa-c48a-4ff4-b7c9-97bbd7f071b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541607792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2541607792
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3153971784
Short name T406
Test name
Test status
Simulation time 14981189072 ps
CPU time 76.22 seconds
Started Apr 18 12:32:59 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 216488 kb
Host smart-3b5a82f7-01ad-4bda-9ee6-0b03ba58dba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153971784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3153971784
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.698921310
Short name T224
Test name
Test status
Simulation time 4354635246 ps
CPU time 44.02 seconds
Started Apr 18 02:04:59 PM PDT 24
Finished Apr 18 02:05:43 PM PDT 24
Peak memory 214088 kb
Host smart-94a6e185-ace5-4c87-9d65-c04dbe6815ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698921310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.698921310
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3694771656
Short name T543
Test name
Test status
Simulation time 17113740269 ps
CPU time 31.25 seconds
Started Apr 18 02:05:08 PM PDT 24
Finished Apr 18 02:05:39 PM PDT 24
Peak memory 211564 kb
Host smart-381ced2d-923f-454b-8155-95fecf792e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694771656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3694771656
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.434144624
Short name T575
Test name
Test status
Simulation time 170848220 ps
CPU time 8.17 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:18 PM PDT 24
Peak memory 211208 kb
Host smart-2fd21672-0d91-40c7-a2b2-43d4b60dad40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434144624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.434144624
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1088994321
Short name T196
Test name
Test status
Simulation time 169486461835 ps
CPU time 481.87 seconds
Started Apr 18 02:05:07 PM PDT 24
Finished Apr 18 02:13:09 PM PDT 24
Peak memory 239100 kb
Host smart-8d5d9e06-03e9-401c-9694-ba5be60f11a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088994321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1088994321
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2380437120
Short name T27
Test name
Test status
Simulation time 214350013814 ps
CPU time 652.56 seconds
Started Apr 18 12:33:17 PM PDT 24
Finished Apr 18 12:44:10 PM PDT 24
Peak memory 225464 kb
Host smart-5715cf5b-cc46-4a20-84db-1f02d187e571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380437120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2380437120
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.116664930
Short name T672
Test name
Test status
Simulation time 25328021285 ps
CPU time 54.9 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 215016 kb
Host smart-2b16e8d5-7bbe-40ec-9bdb-6071c8763229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116664930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.116664930
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1827243583
Short name T626
Test name
Test status
Simulation time 18541080672 ps
CPU time 69.72 seconds
Started Apr 18 02:05:08 PM PDT 24
Finished Apr 18 02:06:18 PM PDT 24
Peak memory 215088 kb
Host smart-beba0ded-aaf2-4462-bf5b-fc0867310f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827243583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1827243583
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1893472083
Short name T601
Test name
Test status
Simulation time 16060111341 ps
CPU time 31.55 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:41 PM PDT 24
Peak memory 212772 kb
Host smart-ac98da57-994b-45bb-ab51-63e589497beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893472083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1893472083
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.74640817
Short name T343
Test name
Test status
Simulation time 14682074454 ps
CPU time 30.99 seconds
Started Apr 18 02:05:07 PM PDT 24
Finished Apr 18 02:05:38 PM PDT 24
Peak memory 211416 kb
Host smart-c101232a-9199-43c3-93cc-3351592555a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74640817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.74640817
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4128185179
Short name T191
Test name
Test status
Simulation time 9679169549 ps
CPU time 27.15 seconds
Started Apr 18 12:33:08 PM PDT 24
Finished Apr 18 12:33:37 PM PDT 24
Peak memory 217372 kb
Host smart-a68a2f18-155d-4da2-91cc-0147181be01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128185179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4128185179
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.959429035
Short name T352
Test name
Test status
Simulation time 1400585465 ps
CPU time 20.24 seconds
Started Apr 18 02:05:10 PM PDT 24
Finished Apr 18 02:05:31 PM PDT 24
Peak memory 216624 kb
Host smart-559f5ddc-07a5-403b-a642-2e1f63286715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959429035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.959429035
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.219750467
Short name T293
Test name
Test status
Simulation time 3661804606 ps
CPU time 36.62 seconds
Started Apr 18 02:05:07 PM PDT 24
Finished Apr 18 02:05:44 PM PDT 24
Peak memory 219428 kb
Host smart-5edd05d8-3664-4758-9cc3-9b3387b67c54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219750467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.219750467
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3555028068
Short name T394
Test name
Test status
Simulation time 3271777865 ps
CPU time 43.84 seconds
Started Apr 18 12:33:09 PM PDT 24
Finished Apr 18 12:33:55 PM PDT 24
Peak memory 218092 kb
Host smart-2f9d8963-71c4-4243-b1d9-c81a448fbed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555028068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3555028068
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2410723944
Short name T454
Test name
Test status
Simulation time 332032543 ps
CPU time 8.25 seconds
Started Apr 18 02:05:24 PM PDT 24
Finished Apr 18 02:05:33 PM PDT 24
Peak memory 211420 kb
Host smart-a3b887a9-2507-42c6-b5bd-975af3c70b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410723944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2410723944
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.917735368
Short name T219
Test name
Test status
Simulation time 495649717 ps
CPU time 9.95 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:33:16 PM PDT 24
Peak memory 211280 kb
Host smart-10347128-57cc-44df-89ad-a2b0e523ae84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917735368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.917735368
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2746706837
Short name T668
Test name
Test status
Simulation time 181374518047 ps
CPU time 448.31 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:40:53 PM PDT 24
Peak memory 237752 kb
Host smart-b882fe52-2280-4b9f-9999-f5df2b668399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746706837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2746706837
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2857779838
Short name T363
Test name
Test status
Simulation time 6508495231 ps
CPU time 58.28 seconds
Started Apr 18 12:33:09 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 215068 kb
Host smart-925d3787-3949-4c90-b177-68c1cedc9941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857779838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2857779838
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.321116934
Short name T47
Test name
Test status
Simulation time 2864623548 ps
CPU time 36.94 seconds
Started Apr 18 02:05:17 PM PDT 24
Finished Apr 18 02:05:54 PM PDT 24
Peak memory 214732 kb
Host smart-db17b335-7e6e-4a8f-a11f-3909c1a358da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321116934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.321116934
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2781129143
Short name T436
Test name
Test status
Simulation time 27633708833 ps
CPU time 30.63 seconds
Started Apr 18 12:33:16 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 211676 kb
Host smart-368dccd6-ea4a-4d40-9e66-44c90f39191b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781129143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2781129143
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.930003359
Short name T161
Test name
Test status
Simulation time 12630508691 ps
CPU time 29.81 seconds
Started Apr 18 02:05:17 PM PDT 24
Finished Apr 18 02:05:48 PM PDT 24
Peak memory 211924 kb
Host smart-e0296d3e-8a6d-47ba-a59f-6191919f2624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930003359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.930003359
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1207989273
Short name T636
Test name
Test status
Simulation time 12694399424 ps
CPU time 45.86 seconds
Started Apr 18 12:33:20 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 218008 kb
Host smart-de7d7375-d2f3-40ee-9411-b5a1159e4878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207989273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1207989273
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.651278766
Short name T577
Test name
Test status
Simulation time 17798149869 ps
CPU time 43.9 seconds
Started Apr 18 02:05:08 PM PDT 24
Finished Apr 18 02:05:52 PM PDT 24
Peak memory 218300 kb
Host smart-f6627fea-bc47-4ff7-8d92-9fa7ccc1a4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651278766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.651278766
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2256205518
Short name T181
Test name
Test status
Simulation time 5355584352 ps
CPU time 33 seconds
Started Apr 18 12:33:12 PM PDT 24
Finished Apr 18 12:33:46 PM PDT 24
Peak memory 213024 kb
Host smart-725d6630-28bb-4fd9-bf18-949792b3c5a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256205518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2256205518
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1544963894
Short name T643
Test name
Test status
Simulation time 1489221432 ps
CPU time 14.06 seconds
Started Apr 18 02:03:35 PM PDT 24
Finished Apr 18 02:03:50 PM PDT 24
Peak memory 211388 kb
Host smart-87b4eeee-c381-428b-ae91-c156e716d85e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544963894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1544963894
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2259188812
Short name T535
Test name
Test status
Simulation time 3073295028 ps
CPU time 25.99 seconds
Started Apr 18 12:32:57 PM PDT 24
Finished Apr 18 12:33:24 PM PDT 24
Peak memory 211520 kb
Host smart-1cd95abe-8347-47b6-bcf7-4b0cc0261598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259188812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2259188812
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.129252285
Short name T619
Test name
Test status
Simulation time 82022325046 ps
CPU time 227.75 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:36:52 PM PDT 24
Peak memory 215684 kb
Host smart-53abc5bf-38bd-40bc-b037-017d9666f152
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129252285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.129252285
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3947538858
Short name T414
Test name
Test status
Simulation time 31153689522 ps
CPU time 423.68 seconds
Started Apr 18 02:03:33 PM PDT 24
Finished Apr 18 02:10:37 PM PDT 24
Peak memory 239284 kb
Host smart-81ea943d-6fb0-4e28-a55f-825daccc112f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947538858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3947538858
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1816066535
Short name T468
Test name
Test status
Simulation time 27903484485 ps
CPU time 62.29 seconds
Started Apr 18 02:03:34 PM PDT 24
Finished Apr 18 02:04:37 PM PDT 24
Peak memory 215188 kb
Host smart-68a0edf8-cc14-4049-8479-03a3365eb8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816066535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1816066535
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2067734043
Short name T645
Test name
Test status
Simulation time 2061879691 ps
CPU time 21.55 seconds
Started Apr 18 12:33:01 PM PDT 24
Finished Apr 18 12:33:23 PM PDT 24
Peak memory 214696 kb
Host smart-07ff4fff-17bc-4b4b-ba15-b13530b77861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067734043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2067734043
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1135351548
Short name T614
Test name
Test status
Simulation time 3257789289 ps
CPU time 28.2 seconds
Started Apr 18 12:33:11 PM PDT 24
Finished Apr 18 12:33:41 PM PDT 24
Peak memory 211300 kb
Host smart-551c8f1b-1c0d-4f1c-bb56-f46d5729dedd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135351548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1135351548
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1490237608
Short name T31
Test name
Test status
Simulation time 3336372314 ps
CPU time 134.65 seconds
Started Apr 18 02:03:35 PM PDT 24
Finished Apr 18 02:05:50 PM PDT 24
Peak memory 236876 kb
Host smart-a0418435-c5a6-4f53-81b0-6fefd86d8102
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490237608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1490237608
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3845286141
Short name T36
Test name
Test status
Simulation time 14198953205 ps
CPU time 135.72 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:35:19 PM PDT 24
Peak memory 238636 kb
Host smart-54a9ef90-c543-46f3-8e30-7cf240535166
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845286141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3845286141
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.221128758
Short name T481
Test name
Test status
Simulation time 1318445893 ps
CPU time 19.99 seconds
Started Apr 18 02:03:26 PM PDT 24
Finished Apr 18 02:03:46 PM PDT 24
Peak memory 217228 kb
Host smart-2bc63c44-5748-4948-8221-1acee17b32d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221128758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.221128758
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.342376565
Short name T511
Test name
Test status
Simulation time 1369236309 ps
CPU time 19.62 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 217108 kb
Host smart-370a478c-2dad-48a8-9afc-6f4da8f6608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342376565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.342376565
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1532872185
Short name T431
Test name
Test status
Simulation time 2007991170 ps
CPU time 44.6 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:33:50 PM PDT 24
Peak memory 219176 kb
Host smart-5339c6e9-d851-4c94-947a-5e2a81c85e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532872185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1532872185
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2289834311
Short name T311
Test name
Test status
Simulation time 25955329171 ps
CPU time 140.97 seconds
Started Apr 18 02:03:27 PM PDT 24
Finished Apr 18 02:05:48 PM PDT 24
Peak memory 227636 kb
Host smart-f6846e9d-ac90-48f7-a46e-561cee18ab80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289834311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2289834311
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2277115687
Short name T333
Test name
Test status
Simulation time 10773341049 ps
CPU time 25.09 seconds
Started Apr 18 12:33:09 PM PDT 24
Finished Apr 18 12:33:36 PM PDT 24
Peak memory 211380 kb
Host smart-b9b5999f-9e6c-4c15-9de0-160b871cbb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277115687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2277115687
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3175338358
Short name T606
Test name
Test status
Simulation time 1647303297 ps
CPU time 8.3 seconds
Started Apr 18 02:05:24 PM PDT 24
Finished Apr 18 02:05:33 PM PDT 24
Peak memory 211316 kb
Host smart-17007699-11d8-4317-9b12-5c9204c5602b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175338358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3175338358
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1252544681
Short name T647
Test name
Test status
Simulation time 124200202989 ps
CPU time 450.1 seconds
Started Apr 18 02:05:22 PM PDT 24
Finished Apr 18 02:12:53 PM PDT 24
Peak memory 240748 kb
Host smart-dbe05ea7-168e-44ad-a653-e8009895de14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252544681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1252544681
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2115398147
Short name T252
Test name
Test status
Simulation time 158599822027 ps
CPU time 541.09 seconds
Started Apr 18 12:33:24 PM PDT 24
Finished Apr 18 12:42:26 PM PDT 24
Peak memory 240516 kb
Host smart-3f78d728-07bb-43e6-bcc1-9a638bad7c98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115398147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2115398147
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2674464481
Short name T273
Test name
Test status
Simulation time 9812527323 ps
CPU time 49.31 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:57 PM PDT 24
Peak memory 215076 kb
Host smart-3276d829-ed53-441f-8e1f-e55e4f351356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674464481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2674464481
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.816799299
Short name T225
Test name
Test status
Simulation time 12229774266 ps
CPU time 54.97 seconds
Started Apr 18 02:05:26 PM PDT 24
Finished Apr 18 02:06:22 PM PDT 24
Peak memory 215080 kb
Host smart-9470f1ad-6923-4c89-b6c7-ea4f1aca84bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816799299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.816799299
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1879380533
Short name T315
Test name
Test status
Simulation time 24536717065 ps
CPU time 28.21 seconds
Started Apr 18 12:33:10 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 212808 kb
Host smart-8b421b75-5fb7-4761-b02a-70dc256d9124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879380533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1879380533
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4170581234
Short name T429
Test name
Test status
Simulation time 64394209370 ps
CPU time 35.73 seconds
Started Apr 18 02:05:23 PM PDT 24
Finished Apr 18 02:05:59 PM PDT 24
Peak memory 211916 kb
Host smart-5550dd3b-2674-4565-8da1-447486165ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170581234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4170581234
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.226309578
Short name T545
Test name
Test status
Simulation time 1492382480 ps
CPU time 20.68 seconds
Started Apr 18 02:05:16 PM PDT 24
Finished Apr 18 02:05:37 PM PDT 24
Peak memory 217168 kb
Host smart-6de660ce-a7fd-4dc1-9935-0c80987b77fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226309578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.226309578
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4021023961
Short name T632
Test name
Test status
Simulation time 5505021975 ps
CPU time 53.07 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 217800 kb
Host smart-7ce857d5-ed0b-4fd7-ab34-41d9034a736b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021023961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4021023961
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3108670962
Short name T420
Test name
Test status
Simulation time 7246809910 ps
CPU time 109.91 seconds
Started Apr 18 02:05:16 PM PDT 24
Finished Apr 18 02:07:06 PM PDT 24
Peak memory 220456 kb
Host smart-59fccb09-01b4-460c-9ece-82c3c511cc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108670962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3108670962
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.586123330
Short name T314
Test name
Test status
Simulation time 17530138948 ps
CPU time 110.17 seconds
Started Apr 18 12:33:17 PM PDT 24
Finished Apr 18 12:35:08 PM PDT 24
Peak memory 219276 kb
Host smart-5ff67068-b451-45f6-89da-79656272d5dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586123330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.586123330
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1592649450
Short name T443
Test name
Test status
Simulation time 55414673830 ps
CPU time 10184.9 seconds
Started Apr 18 12:33:16 PM PDT 24
Finished Apr 18 03:23:03 PM PDT 24
Peak memory 244120 kb
Host smart-ab99939c-e118-4d69-86fc-d911ee801531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592649450 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1592649450
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3417623382
Short name T192
Test name
Test status
Simulation time 10629490318 ps
CPU time 24.11 seconds
Started Apr 18 12:33:22 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 212196 kb
Host smart-fcc5e267-29dd-40ec-9037-cb6f5e6c0740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417623382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3417623382
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3652689341
Short name T593
Test name
Test status
Simulation time 174496024 ps
CPU time 8.56 seconds
Started Apr 18 02:05:23 PM PDT 24
Finished Apr 18 02:05:32 PM PDT 24
Peak memory 211388 kb
Host smart-80e44cea-ca32-46f7-aa86-19929ad26014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652689341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3652689341
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.122501558
Short name T519
Test name
Test status
Simulation time 17240342947 ps
CPU time 274.92 seconds
Started Apr 18 12:33:17 PM PDT 24
Finished Apr 18 12:37:53 PM PDT 24
Peak memory 239932 kb
Host smart-81b1cd3b-f935-40ec-9faa-c043be31806a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122501558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.122501558
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.448478209
Short name T206
Test name
Test status
Simulation time 30254368531 ps
CPU time 206.52 seconds
Started Apr 18 02:05:23 PM PDT 24
Finished Apr 18 02:08:50 PM PDT 24
Peak memory 215856 kb
Host smart-32a4465a-bbb4-442f-89d6-95e6e96fe4fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448478209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.448478209
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2841292544
Short name T353
Test name
Test status
Simulation time 1320644218 ps
CPU time 18.96 seconds
Started Apr 18 12:33:10 PM PDT 24
Finished Apr 18 12:33:31 PM PDT 24
Peak memory 214620 kb
Host smart-ddeecf0a-49eb-471f-8468-ebb1a479f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841292544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2841292544
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.287736415
Short name T187
Test name
Test status
Simulation time 4876142394 ps
CPU time 47.93 seconds
Started Apr 18 02:05:22 PM PDT 24
Finished Apr 18 02:06:11 PM PDT 24
Peak memory 215136 kb
Host smart-da86e03a-f612-4b6a-baee-b2f0df239f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287736415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.287736415
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1017153450
Short name T578
Test name
Test status
Simulation time 1141932137 ps
CPU time 17.88 seconds
Started Apr 18 12:33:15 PM PDT 24
Finished Apr 18 12:33:34 PM PDT 24
Peak memory 211268 kb
Host smart-051ed3e9-bd26-4c4b-a4c0-3237807a5a51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017153450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1017153450
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1555479234
Short name T348
Test name
Test status
Simulation time 28969115339 ps
CPU time 34.76 seconds
Started Apr 18 02:05:28 PM PDT 24
Finished Apr 18 02:06:03 PM PDT 24
Peak memory 211420 kb
Host smart-2e63d03b-21e8-4f6f-8f06-b5343dc8e495
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555479234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1555479234
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.207178435
Short name T44
Test name
Test status
Simulation time 7452973060 ps
CPU time 62.84 seconds
Started Apr 18 12:33:09 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 216604 kb
Host smart-a844d3f0-5cda-473e-a5d4-8c1c16c76a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207178435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.207178435
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3723955862
Short name T340
Test name
Test status
Simulation time 7895981321 ps
CPU time 34.93 seconds
Started Apr 18 02:05:24 PM PDT 24
Finished Apr 18 02:05:59 PM PDT 24
Peak memory 217464 kb
Host smart-38fce75b-05ea-4701-b9e5-addb3ed48b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723955862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3723955862
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1288591713
Short name T152
Test name
Test status
Simulation time 6103470823 ps
CPU time 65.56 seconds
Started Apr 18 02:05:24 PM PDT 24
Finished Apr 18 02:06:30 PM PDT 24
Peak memory 219448 kb
Host smart-2e2aae0a-691e-4460-b6e8-6519eac1e7cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288591713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1288591713
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2371949680
Short name T332
Test name
Test status
Simulation time 9476349259 ps
CPU time 48.66 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:58 PM PDT 24
Peak memory 219736 kb
Host smart-7dc3ccc7-9ebc-4cd9-a176-53fe0884e4cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371949680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2371949680
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3398664013
Short name T640
Test name
Test status
Simulation time 688531824 ps
CPU time 8.25 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:17 PM PDT 24
Peak memory 211256 kb
Host smart-58133cf5-6ff3-4f38-b1fe-1c57dd5878f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398664013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3398664013
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3511770639
Short name T240
Test name
Test status
Simulation time 8471491036 ps
CPU time 23.55 seconds
Started Apr 18 02:05:32 PM PDT 24
Finished Apr 18 02:05:56 PM PDT 24
Peak memory 212444 kb
Host smart-013a09a3-8d49-403a-9003-597667483263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511770639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3511770639
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3193876693
Short name T296
Test name
Test status
Simulation time 55409757094 ps
CPU time 274.58 seconds
Started Apr 18 02:05:33 PM PDT 24
Finished Apr 18 02:10:08 PM PDT 24
Peak memory 239968 kb
Host smart-d90c1a7b-c9ed-4afc-86f1-f8f46eeb3906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193876693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3193876693
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1054925758
Short name T359
Test name
Test status
Simulation time 7627473690 ps
CPU time 61.28 seconds
Started Apr 18 02:05:32 PM PDT 24
Finished Apr 18 02:06:34 PM PDT 24
Peak memory 216048 kb
Host smart-82d7564c-15c8-4c79-8ad6-d16c1d0f2601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054925758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1054925758
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1179869651
Short name T612
Test name
Test status
Simulation time 3450309972 ps
CPU time 41.78 seconds
Started Apr 18 12:33:19 PM PDT 24
Finished Apr 18 12:34:01 PM PDT 24
Peak memory 214796 kb
Host smart-1b98f350-c4a6-47b2-bdd9-47824c00d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179869651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1179869651
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3980727332
Short name T387
Test name
Test status
Simulation time 1145456193 ps
CPU time 17.52 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:33:57 PM PDT 24
Peak memory 211204 kb
Host smart-57585b14-a5f0-4fad-8d4e-5c3d98088a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980727332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3980727332
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4190680833
Short name T376
Test name
Test status
Simulation time 1238740751 ps
CPU time 18.54 seconds
Started Apr 18 02:05:23 PM PDT 24
Finished Apr 18 02:05:42 PM PDT 24
Peak memory 212268 kb
Host smart-aaecc11e-a418-449b-9f5e-acfd6a16a8d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190680833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4190680833
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1429924509
Short name T141
Test name
Test status
Simulation time 357483179 ps
CPU time 19.25 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:33:44 PM PDT 24
Peak memory 216980 kb
Host smart-212c06ca-8129-482d-bbe7-f1ce01b1ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429924509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1429924509
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2942559740
Short name T364
Test name
Test status
Simulation time 26087358185 ps
CPU time 74.02 seconds
Started Apr 18 02:05:23 PM PDT 24
Finished Apr 18 02:06:37 PM PDT 24
Peak memory 217700 kb
Host smart-b84cfff1-4218-4409-86ea-2529f72378c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942559740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2942559740
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1005864634
Short name T305
Test name
Test status
Simulation time 15704485320 ps
CPU time 40.78 seconds
Started Apr 18 02:05:23 PM PDT 24
Finished Apr 18 02:06:04 PM PDT 24
Peak memory 213104 kb
Host smart-05349b6f-d6c4-43f1-bacf-aa66b04e2b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005864634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1005864634
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4066638731
Short name T217
Test name
Test status
Simulation time 20641039993 ps
CPU time 72.2 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 219320 kb
Host smart-96826709-6d7b-483a-98bf-46cfac2ef0ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066638731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4066638731
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3241132236
Short name T675
Test name
Test status
Simulation time 15893387259 ps
CPU time 680.23 seconds
Started Apr 18 02:05:31 PM PDT 24
Finished Apr 18 02:16:52 PM PDT 24
Peak memory 235964 kb
Host smart-b58b041f-4eaf-47ce-8576-193396ad6429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241132236 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3241132236
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2819711182
Short name T208
Test name
Test status
Simulation time 3454676428 ps
CPU time 22.9 seconds
Started Apr 18 02:05:40 PM PDT 24
Finished Apr 18 02:06:04 PM PDT 24
Peak memory 211920 kb
Host smart-2b97ea8d-8a7a-4558-8862-b63b74c6651d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819711182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2819711182
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3049251009
Short name T378
Test name
Test status
Simulation time 44545246794 ps
CPU time 22.24 seconds
Started Apr 18 12:33:11 PM PDT 24
Finished Apr 18 12:33:35 PM PDT 24
Peak memory 212348 kb
Host smart-cf4317d0-ae96-4bcc-b9c8-673443ecd894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049251009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3049251009
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4235006809
Short name T515
Test name
Test status
Simulation time 98255287015 ps
CPU time 272.02 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:37:35 PM PDT 24
Peak memory 228224 kb
Host smart-b7e9289e-3a0c-4b8e-9431-e9965c0e6d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235006809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4235006809
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4243593796
Short name T487
Test name
Test status
Simulation time 74172279644 ps
CPU time 456.59 seconds
Started Apr 18 02:05:36 PM PDT 24
Finished Apr 18 02:13:13 PM PDT 24
Peak memory 216724 kb
Host smart-5ce699cb-bccd-41b8-bb3b-2bf1ed518393
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243593796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4243593796
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1684031369
Short name T223
Test name
Test status
Simulation time 17051488065 ps
CPU time 70.49 seconds
Started Apr 18 02:05:31 PM PDT 24
Finished Apr 18 02:06:42 PM PDT 24
Peak memory 215204 kb
Host smart-b4c2e848-5511-4557-bac8-3ec693479b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684031369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1684031369
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2578758397
Short name T336
Test name
Test status
Simulation time 332499347 ps
CPU time 19.04 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:33:28 PM PDT 24
Peak memory 214636 kb
Host smart-838553a0-1192-4990-9b1c-4fabbea06b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578758397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2578758397
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1878655156
Short name T10
Test name
Test status
Simulation time 4226813911 ps
CPU time 23.09 seconds
Started Apr 18 02:05:31 PM PDT 24
Finished Apr 18 02:05:54 PM PDT 24
Peak memory 212488 kb
Host smart-f96caf9e-e10e-4625-af20-514bb0f18199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878655156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1878655156
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3310762508
Short name T479
Test name
Test status
Simulation time 498955010 ps
CPU time 13.63 seconds
Started Apr 18 12:33:09 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 212152 kb
Host smart-07812768-c538-4df9-978c-d60109f675b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310762508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3310762508
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2509008184
Short name T670
Test name
Test status
Simulation time 18331861052 ps
CPU time 43.28 seconds
Started Apr 18 12:33:19 PM PDT 24
Finished Apr 18 12:34:03 PM PDT 24
Peak memory 217304 kb
Host smart-00d8dcd0-e650-4b7a-b627-eadcb37fe50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509008184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2509008184
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3209879797
Short name T497
Test name
Test status
Simulation time 11700789101 ps
CPU time 60.12 seconds
Started Apr 18 02:05:30 PM PDT 24
Finished Apr 18 02:06:30 PM PDT 24
Peak memory 218204 kb
Host smart-4dd65a8a-a0e6-4aae-81df-3a2e09b50a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209879797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3209879797
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3552504256
Short name T367
Test name
Test status
Simulation time 4010207580 ps
CPU time 88.12 seconds
Started Apr 18 02:05:32 PM PDT 24
Finished Apr 18 02:07:00 PM PDT 24
Peak memory 220140 kb
Host smart-3b20f0af-f901-4ecc-87e2-1b25688fe964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552504256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3552504256
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.583633014
Short name T358
Test name
Test status
Simulation time 23524118972 ps
CPU time 207.9 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:36:37 PM PDT 24
Peak memory 227532 kb
Host smart-84335b04-22de-441a-93ee-e60200d8f4a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583633014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.583633014
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.542979062
Short name T281
Test name
Test status
Simulation time 3273658868 ps
CPU time 27.74 seconds
Started Apr 18 12:33:12 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 211320 kb
Host smart-f752af5c-7421-4dc3-a714-f26ed964b466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542979062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.542979062
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.867418188
Short name T665
Test name
Test status
Simulation time 8180155675 ps
CPU time 32.83 seconds
Started Apr 18 02:05:38 PM PDT 24
Finished Apr 18 02:06:11 PM PDT 24
Peak memory 212276 kb
Host smart-61d2df14-8838-4bfb-aff3-35f03ea35acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867418188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.867418188
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1948126495
Short name T373
Test name
Test status
Simulation time 60906656564 ps
CPU time 590.31 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:42:58 PM PDT 24
Peak memory 237764 kb
Host smart-0a4d7481-8bd4-450b-acc2-9d9488b783fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948126495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1948126495
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3556172247
Short name T520
Test name
Test status
Simulation time 79345371036 ps
CPU time 824.53 seconds
Started Apr 18 02:05:41 PM PDT 24
Finished Apr 18 02:19:26 PM PDT 24
Peak memory 234936 kb
Host smart-2a4848a9-2fbd-43e5-ae17-a885987ec4cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556172247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3556172247
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2165842066
Short name T567
Test name
Test status
Simulation time 660231554 ps
CPU time 23.3 seconds
Started Apr 18 02:05:38 PM PDT 24
Finished Apr 18 02:06:01 PM PDT 24
Peak memory 214744 kb
Host smart-9be162fd-b27b-4feb-8758-34d81462d5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165842066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2165842066
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4033483273
Short name T176
Test name
Test status
Simulation time 7290300023 ps
CPU time 60.13 seconds
Started Apr 18 12:33:20 PM PDT 24
Finished Apr 18 12:34:21 PM PDT 24
Peak memory 214920 kb
Host smart-5282dbe3-6d2e-4d10-a8ab-4087ea1e0b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033483273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4033483273
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1297904764
Short name T637
Test name
Test status
Simulation time 2335174229 ps
CPU time 14.26 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 211600 kb
Host smart-322f42b5-b3dc-4b68-bce9-1952780678c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1297904764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1297904764
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1339632617
Short name T274
Test name
Test status
Simulation time 3420808212 ps
CPU time 31.12 seconds
Started Apr 18 02:05:38 PM PDT 24
Finished Apr 18 02:06:09 PM PDT 24
Peak memory 211504 kb
Host smart-d2f611e5-9b65-448f-b83a-e9ef54101f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339632617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1339632617
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.237050006
Short name T143
Test name
Test status
Simulation time 3325229939 ps
CPU time 39.23 seconds
Started Apr 18 02:05:43 PM PDT 24
Finished Apr 18 02:06:22 PM PDT 24
Peak memory 218408 kb
Host smart-007f9c66-ee92-4765-b501-4351518cfb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237050006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.237050006
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3828608956
Short name T49
Test name
Test status
Simulation time 12647816309 ps
CPU time 63.38 seconds
Started Apr 18 12:33:08 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 217840 kb
Host smart-ab3405ca-ac82-446c-bfee-a809b6cc07e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828608956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3828608956
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2647085603
Short name T169
Test name
Test status
Simulation time 3010333575 ps
CPU time 35.41 seconds
Started Apr 18 02:05:39 PM PDT 24
Finished Apr 18 02:06:15 PM PDT 24
Peak memory 212772 kb
Host smart-ca43d0fa-254d-4fd1-b922-fa51e0373e11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647085603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2647085603
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3533589919
Short name T269
Test name
Test status
Simulation time 2157898361 ps
CPU time 52.52 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 219332 kb
Host smart-42d5b104-121a-47d2-9067-3c39bf7c900c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533589919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3533589919
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3328034797
Short name T183
Test name
Test status
Simulation time 4431353996 ps
CPU time 15.34 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 211396 kb
Host smart-a7224c07-3f96-4214-a936-f2ada3c4b5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328034797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3328034797
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.529738609
Short name T20
Test name
Test status
Simulation time 10654300210 ps
CPU time 21.67 seconds
Started Apr 18 02:05:45 PM PDT 24
Finished Apr 18 02:06:07 PM PDT 24
Peak memory 211512 kb
Host smart-578707df-f52c-422c-8e58-6dce1f1c1143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529738609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.529738609
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1814038720
Short name T52
Test name
Test status
Simulation time 31897273272 ps
CPU time 386.02 seconds
Started Apr 18 12:33:20 PM PDT 24
Finished Apr 18 12:39:47 PM PDT 24
Peak memory 236748 kb
Host smart-3a8e98e6-83d4-4b0a-bf3c-22d1179f2bd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814038720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1814038720
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.530420538
Short name T324
Test name
Test status
Simulation time 169232596362 ps
CPU time 846.81 seconds
Started Apr 18 02:05:44 PM PDT 24
Finished Apr 18 02:19:51 PM PDT 24
Peak memory 228184 kb
Host smart-da48b490-f734-4edd-a236-895a50aec6bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530420538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.530420538
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1815230351
Short name T576
Test name
Test status
Simulation time 13006122400 ps
CPU time 55.84 seconds
Started Apr 18 12:33:20 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 215600 kb
Host smart-db6f232f-ea9b-4c4e-a3ec-fc4b1d58a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815230351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1815230351
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2202147456
Short name T514
Test name
Test status
Simulation time 2862683278 ps
CPU time 28.46 seconds
Started Apr 18 02:05:45 PM PDT 24
Finished Apr 18 02:06:14 PM PDT 24
Peak memory 215372 kb
Host smart-d3cd4eba-3493-42c2-a321-ec01a583aea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202147456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2202147456
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1254818296
Short name T199
Test name
Test status
Simulation time 3491106964 ps
CPU time 31.12 seconds
Started Apr 18 02:05:48 PM PDT 24
Finished Apr 18 02:06:19 PM PDT 24
Peak memory 211492 kb
Host smart-24958549-e940-4e72-b5fb-b06d1fd29a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254818296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1254818296
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2897866345
Short name T166
Test name
Test status
Simulation time 6257541569 ps
CPU time 28.81 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:33:59 PM PDT 24
Peak memory 211496 kb
Host smart-dc14288b-2523-4f68-96ae-db13b70cb919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897866345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2897866345
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1401020017
Short name T449
Test name
Test status
Simulation time 361479973 ps
CPU time 20.46 seconds
Started Apr 18 02:05:45 PM PDT 24
Finished Apr 18 02:06:06 PM PDT 24
Peak memory 216768 kb
Host smart-919938fb-1738-4e41-9afe-80d4dacfd9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401020017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1401020017
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1741479330
Short name T374
Test name
Test status
Simulation time 14072496584 ps
CPU time 62.2 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:34:29 PM PDT 24
Peak memory 218116 kb
Host smart-07abb332-29b2-45ac-bafc-c9d98c660f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741479330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1741479330
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1274249394
Short name T621
Test name
Test status
Simulation time 10379858446 ps
CPU time 91.38 seconds
Started Apr 18 12:33:30 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 219336 kb
Host smart-fc0ea7e3-5503-44fd-ab70-f567e7c0faa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274249394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1274249394
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3166903071
Short name T587
Test name
Test status
Simulation time 12319793418 ps
CPU time 104.41 seconds
Started Apr 18 02:05:46 PM PDT 24
Finished Apr 18 02:07:31 PM PDT 24
Peak memory 221576 kb
Host smart-cad8caf9-b7f3-4e4e-84ab-c1d1f1dd758a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166903071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3166903071
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.517710448
Short name T425
Test name
Test status
Simulation time 450331266730 ps
CPU time 7894.11 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 02:45:02 PM PDT 24
Peak memory 235920 kb
Host smart-02037a9e-a0e2-4aa3-896f-ddc368b68252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517710448 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.517710448
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.217457813
Short name T235
Test name
Test status
Simulation time 353509261 ps
CPU time 8.49 seconds
Started Apr 18 02:05:54 PM PDT 24
Finished Apr 18 02:06:03 PM PDT 24
Peak memory 211364 kb
Host smart-ad9f2de1-5912-499f-af65-66a0535e2cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217457813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.217457813
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3088742611
Short name T384
Test name
Test status
Simulation time 2933653532 ps
CPU time 25.07 seconds
Started Apr 18 12:33:32 PM PDT 24
Finished Apr 18 12:33:58 PM PDT 24
Peak memory 211380 kb
Host smart-7da8614c-3823-44ab-803a-f95490a60419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088742611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3088742611
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1975220054
Short name T153
Test name
Test status
Simulation time 3143173796 ps
CPU time 198.48 seconds
Started Apr 18 12:33:10 PM PDT 24
Finished Apr 18 12:36:30 PM PDT 24
Peak memory 228728 kb
Host smart-caba706c-3261-48d1-b4d7-8269c9519985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975220054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1975220054
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.507661483
Short name T146
Test name
Test status
Simulation time 312117408850 ps
CPU time 602.32 seconds
Started Apr 18 02:05:47 PM PDT 24
Finished Apr 18 02:15:49 PM PDT 24
Peak memory 237948 kb
Host smart-7a76ce7f-be8f-4f84-8398-4a0ba18ebfb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507661483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.507661483
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2922626150
Short name T613
Test name
Test status
Simulation time 662119643 ps
CPU time 19.19 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 215032 kb
Host smart-458e39b2-2363-4369-b4de-68a30a5d5d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922626150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2922626150
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3584950110
Short name T398
Test name
Test status
Simulation time 1373954292 ps
CPU time 19.29 seconds
Started Apr 18 02:05:53 PM PDT 24
Finished Apr 18 02:06:13 PM PDT 24
Peak memory 214728 kb
Host smart-79619cd3-36fa-45b9-85ce-a80b829c08bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584950110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3584950110
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3218569916
Short name T518
Test name
Test status
Simulation time 9286469832 ps
CPU time 23.45 seconds
Started Apr 18 02:05:48 PM PDT 24
Finished Apr 18 02:06:12 PM PDT 24
Peak memory 211504 kb
Host smart-e86753b5-85ee-4cec-85a2-c70792256337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218569916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3218569916
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4010619941
Short name T184
Test name
Test status
Simulation time 2481662467 ps
CPU time 26.53 seconds
Started Apr 18 12:33:09 PM PDT 24
Finished Apr 18 12:33:38 PM PDT 24
Peak memory 211432 kb
Host smart-2598a825-27c3-4068-8e36-5e52410cb460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010619941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4010619941
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1105066238
Short name T361
Test name
Test status
Simulation time 7805344012 ps
CPU time 79.33 seconds
Started Apr 18 02:05:45 PM PDT 24
Finished Apr 18 02:07:05 PM PDT 24
Peak memory 217180 kb
Host smart-a7123a19-4fc7-4c44-9ac2-de9d173df3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105066238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1105066238
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1717112604
Short name T256
Test name
Test status
Simulation time 19216827776 ps
CPU time 53.6 seconds
Started Apr 18 12:33:19 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 216688 kb
Host smart-02a5c204-c4ad-448d-91b0-b06bb78b0166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717112604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1717112604
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1410602470
Short name T486
Test name
Test status
Simulation time 2792584640 ps
CPU time 31.07 seconds
Started Apr 18 02:05:46 PM PDT 24
Finished Apr 18 02:06:18 PM PDT 24
Peak memory 213952 kb
Host smart-567cc50c-4891-4b2f-ba6f-01718febdd9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410602470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1410602470
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4294096582
Short name T412
Test name
Test status
Simulation time 3260895348 ps
CPU time 35.29 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:34:00 PM PDT 24
Peak memory 219420 kb
Host smart-954550d9-fefa-4899-8827-f2ad52ad9be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294096582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4294096582
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2480945977
Short name T308
Test name
Test status
Simulation time 24613213248 ps
CPU time 23.84 seconds
Started Apr 18 12:33:27 PM PDT 24
Finished Apr 18 12:33:52 PM PDT 24
Peak memory 212304 kb
Host smart-47ce1765-8759-41ee-bd0f-f8b5db978259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480945977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2480945977
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2731436434
Short name T495
Test name
Test status
Simulation time 2478890837 ps
CPU time 11.92 seconds
Started Apr 18 02:06:01 PM PDT 24
Finished Apr 18 02:06:13 PM PDT 24
Peak memory 211532 kb
Host smart-2665779f-a240-4b58-a818-36cb1af06b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731436434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2731436434
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1689985507
Short name T282
Test name
Test status
Simulation time 173549327001 ps
CPU time 853.59 seconds
Started Apr 18 12:33:33 PM PDT 24
Finished Apr 18 12:47:47 PM PDT 24
Peak memory 217128 kb
Host smart-ed773805-a861-42c9-a345-8eca1b4f591d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689985507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1689985507
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2829927185
Short name T633
Test name
Test status
Simulation time 263931958464 ps
CPU time 709.56 seconds
Started Apr 18 02:05:53 PM PDT 24
Finished Apr 18 02:17:43 PM PDT 24
Peak memory 237556 kb
Host smart-4f6db372-dc82-4525-b71a-e0c96ca35dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829927185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2829927185
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1094208100
Short name T207
Test name
Test status
Simulation time 78775157020 ps
CPU time 44.13 seconds
Started Apr 18 02:06:02 PM PDT 24
Finished Apr 18 02:06:46 PM PDT 24
Peak memory 215252 kb
Host smart-0853f57d-0af2-4a1e-9184-bba45723a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094208100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1094208100
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2449375488
Short name T365
Test name
Test status
Simulation time 11161391142 ps
CPU time 40.05 seconds
Started Apr 18 12:33:10 PM PDT 24
Finished Apr 18 12:33:52 PM PDT 24
Peak memory 214932 kb
Host smart-a7a7e64f-680c-4976-8cbc-4f49435b7cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449375488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2449375488
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2121078183
Short name T175
Test name
Test status
Simulation time 15162146350 ps
CPU time 32.79 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 12:34:00 PM PDT 24
Peak memory 211380 kb
Host smart-67993cd3-0cab-49ec-ba2e-8525f88185c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121078183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2121078183
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3945060437
Short name T239
Test name
Test status
Simulation time 14176605914 ps
CPU time 30.58 seconds
Started Apr 18 02:05:55 PM PDT 24
Finished Apr 18 02:06:27 PM PDT 24
Peak memory 212932 kb
Host smart-cec597bf-05cb-4f91-af91-b9ddb5098b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945060437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3945060437
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2827230513
Short name T516
Test name
Test status
Simulation time 10983591347 ps
CPU time 37.57 seconds
Started Apr 18 12:33:08 PM PDT 24
Finished Apr 18 12:33:48 PM PDT 24
Peak memory 217624 kb
Host smart-3f113d48-580a-4eb5-ad18-20863fa2a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827230513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2827230513
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.985915932
Short name T427
Test name
Test status
Simulation time 19352598216 ps
CPU time 56.24 seconds
Started Apr 18 02:05:54 PM PDT 24
Finished Apr 18 02:06:51 PM PDT 24
Peak memory 217216 kb
Host smart-38cf24ee-5cac-4f8e-8ae1-a311abd42de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985915932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.985915932
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1959973814
Short name T534
Test name
Test status
Simulation time 9560003447 ps
CPU time 64.64 seconds
Started Apr 18 02:05:52 PM PDT 24
Finished Apr 18 02:06:57 PM PDT 24
Peak memory 221188 kb
Host smart-58e4911e-8902-4b7a-a8e6-e738013a998e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959973814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1959973814
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3226121262
Short name T563
Test name
Test status
Simulation time 6432643292 ps
CPU time 80.13 seconds
Started Apr 18 12:33:24 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 215612 kb
Host smart-e314fd1e-cfbf-42f2-a24e-fd252c9c302d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226121262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3226121262
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2595327763
Short name T55
Test name
Test status
Simulation time 377068396165 ps
CPU time 2165.46 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 01:09:30 PM PDT 24
Peak memory 248368 kb
Host smart-a15ccc46-0f7a-4e3d-aeb9-651d30f7ce9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595327763 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2595327763
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.235276673
Short name T450
Test name
Test status
Simulation time 3947353128 ps
CPU time 31.75 seconds
Started Apr 18 02:06:02 PM PDT 24
Finished Apr 18 02:06:34 PM PDT 24
Peak memory 211548 kb
Host smart-255ff10f-295f-42db-a687-3382713f8bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235276673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.235276673
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.569383229
Short name T505
Test name
Test status
Simulation time 769762258 ps
CPU time 13.48 seconds
Started Apr 18 12:33:28 PM PDT 24
Finished Apr 18 12:33:43 PM PDT 24
Peak memory 211280 kb
Host smart-7ea9d034-55e4-4a38-9264-b58aac993973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569383229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.569383229
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2207970136
Short name T571
Test name
Test status
Simulation time 9854167955 ps
CPU time 179.48 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:36:24 PM PDT 24
Peak memory 218900 kb
Host smart-619d5ce7-55e2-4b8a-8325-984593bb339a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207970136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2207970136
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2532424932
Short name T654
Test name
Test status
Simulation time 117586173349 ps
CPU time 274.08 seconds
Started Apr 18 02:06:01 PM PDT 24
Finished Apr 18 02:10:36 PM PDT 24
Peak memory 237308 kb
Host smart-d3f5b078-bebd-4458-82f7-1523aae68681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532424932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2532424932
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1199032442
Short name T389
Test name
Test status
Simulation time 23456267631 ps
CPU time 52.72 seconds
Started Apr 18 12:33:12 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 214932 kb
Host smart-58df152e-5ace-46f2-a604-3b82096bee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199032442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1199032442
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2266680331
Short name T302
Test name
Test status
Simulation time 24609895385 ps
CPU time 59.89 seconds
Started Apr 18 02:06:01 PM PDT 24
Finished Apr 18 02:07:01 PM PDT 24
Peak memory 215184 kb
Host smart-f8bd9415-4929-4fd0-8531-0e916bc3655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266680331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2266680331
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2806617744
Short name T297
Test name
Test status
Simulation time 705447259 ps
CPU time 10.78 seconds
Started Apr 18 12:33:30 PM PDT 24
Finished Apr 18 12:33:42 PM PDT 24
Peak memory 211460 kb
Host smart-ad1277a8-fadc-40b0-8761-4209509e8b94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806617744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2806617744
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3212730929
Short name T635
Test name
Test status
Simulation time 8936066596 ps
CPU time 23.27 seconds
Started Apr 18 02:06:01 PM PDT 24
Finished Apr 18 02:06:25 PM PDT 24
Peak memory 211920 kb
Host smart-cdbf3cb6-81fe-4f5d-a761-a826ffc03e08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212730929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3212730929
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1233031352
Short name T500
Test name
Test status
Simulation time 1412912638 ps
CPU time 20.75 seconds
Started Apr 18 02:06:48 PM PDT 24
Finished Apr 18 02:07:10 PM PDT 24
Peak memory 217792 kb
Host smart-3fae7d56-06d5-45dc-b497-d39dcf609e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233031352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1233031352
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3025559547
Short name T295
Test name
Test status
Simulation time 28822582770 ps
CPU time 73.85 seconds
Started Apr 18 12:33:12 PM PDT 24
Finished Apr 18 12:34:27 PM PDT 24
Peak memory 215044 kb
Host smart-29c36f72-3f4a-4d7c-8749-84b8729e401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025559547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3025559547
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1313490577
Short name T549
Test name
Test status
Simulation time 16753694802 ps
CPU time 197.37 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 12:36:45 PM PDT 24
Peak memory 219716 kb
Host smart-d6b64b45-c5b2-45be-8692-127f91c77c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313490577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1313490577
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1435677513
Short name T467
Test name
Test status
Simulation time 23392752432 ps
CPU time 26.08 seconds
Started Apr 18 12:33:35 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 212292 kb
Host smart-82a68dbc-382b-442a-86fe-9909a1146782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435677513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1435677513
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4240470821
Short name T583
Test name
Test status
Simulation time 3675460233 ps
CPU time 30.79 seconds
Started Apr 18 02:06:02 PM PDT 24
Finished Apr 18 02:06:34 PM PDT 24
Peak memory 212096 kb
Host smart-fa2f70bf-168d-4226-abc6-91a663d6f611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240470821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4240470821
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2055013917
Short name T651
Test name
Test status
Simulation time 2852886274 ps
CPU time 161.78 seconds
Started Apr 18 02:06:01 PM PDT 24
Finished Apr 18 02:08:44 PM PDT 24
Peak memory 228760 kb
Host smart-1eaaa513-c945-4032-9789-8df836079cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055013917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2055013917
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3273496352
Short name T662
Test name
Test status
Simulation time 142787786678 ps
CPU time 736.27 seconds
Started Apr 18 12:33:11 PM PDT 24
Finished Apr 18 12:45:29 PM PDT 24
Peak memory 236528 kb
Host smart-ab607fc5-231a-44c7-9ace-6896ebe8f243
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273496352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3273496352
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1972410402
Short name T598
Test name
Test status
Simulation time 35707260231 ps
CPU time 44.29 seconds
Started Apr 18 12:33:27 PM PDT 24
Finished Apr 18 12:34:12 PM PDT 24
Peak memory 215072 kb
Host smart-3ac28c71-e95f-4d5c-b7d8-37ee2e4b039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972410402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1972410402
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4082111243
Short name T504
Test name
Test status
Simulation time 6852505251 ps
CPU time 62.63 seconds
Started Apr 18 02:06:02 PM PDT 24
Finished Apr 18 02:07:05 PM PDT 24
Peak memory 215084 kb
Host smart-1b7a347b-7ba8-4dd1-a74f-43752e2cd9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082111243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4082111243
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1158551666
Short name T298
Test name
Test status
Simulation time 4086134970 ps
CPU time 33.97 seconds
Started Apr 18 02:06:01 PM PDT 24
Finished Apr 18 02:06:35 PM PDT 24
Peak memory 211752 kb
Host smart-0819e3fb-221c-4238-bc50-dd56bf75d3b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158551666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1158551666
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1448717308
Short name T532
Test name
Test status
Simulation time 8732497387 ps
CPU time 35.24 seconds
Started Apr 18 12:33:35 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 211752 kb
Host smart-8bba4759-8dea-4c6d-a68a-1f95ad7e1a50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448717308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1448717308
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2566858698
Short name T222
Test name
Test status
Simulation time 709820985 ps
CPU time 19.71 seconds
Started Apr 18 12:33:44 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 215788 kb
Host smart-f931a739-33ff-4f08-926e-a9593fb122ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566858698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2566858698
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3159532847
Short name T220
Test name
Test status
Simulation time 361731333 ps
CPU time 19.73 seconds
Started Apr 18 02:06:02 PM PDT 24
Finished Apr 18 02:06:22 PM PDT 24
Peak memory 213768 kb
Host smart-eb114433-ede0-458d-899e-129e0fe8f5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159532847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3159532847
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2855775515
Short name T470
Test name
Test status
Simulation time 1095849229 ps
CPU time 68.03 seconds
Started Apr 18 02:06:00 PM PDT 24
Finished Apr 18 02:07:09 PM PDT 24
Peak memory 219932 kb
Host smart-476b8392-42d8-4f99-a8b7-e2905ddc3e5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855775515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2855775515
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.744588061
Short name T231
Test name
Test status
Simulation time 5455494098 ps
CPU time 62.01 seconds
Started Apr 18 12:33:53 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 219488 kb
Host smart-f354229a-c77e-4479-ad23-7de7a969ac16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744588061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.744588061
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2348638115
Short name T396
Test name
Test status
Simulation time 5460370745 ps
CPU time 16.75 seconds
Started Apr 18 02:03:44 PM PDT 24
Finished Apr 18 02:04:01 PM PDT 24
Peak memory 211480 kb
Host smart-4daa6861-11c5-4673-b2b7-6c5ae41c502e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348638115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2348638115
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2360147365
Short name T243
Test name
Test status
Simulation time 203561918 ps
CPU time 8.25 seconds
Started Apr 18 12:32:58 PM PDT 24
Finished Apr 18 12:33:07 PM PDT 24
Peak memory 211284 kb
Host smart-bb0d7f0d-4758-4fad-9ef3-c2c9f0694e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360147365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2360147365
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1135307747
Short name T306
Test name
Test status
Simulation time 39036355022 ps
CPU time 385.9 seconds
Started Apr 18 02:03:35 PM PDT 24
Finished Apr 18 02:10:02 PM PDT 24
Peak memory 215856 kb
Host smart-37e43f0b-d377-4042-b867-f9e5fa367cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135307747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1135307747
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2404002781
Short name T634
Test name
Test status
Simulation time 141336862262 ps
CPU time 661.18 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:43:53 PM PDT 24
Peak memory 217636 kb
Host smart-d89b72c9-4c0b-4012-8f5a-5d0aaeab0cea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404002781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2404002781
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1180809827
Short name T163
Test name
Test status
Simulation time 5262824909 ps
CPU time 50.23 seconds
Started Apr 18 02:03:34 PM PDT 24
Finished Apr 18 02:04:25 PM PDT 24
Peak memory 217868 kb
Host smart-77c86735-a98e-40ac-91ad-58b527b5f9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180809827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1180809827
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.273874217
Short name T200
Test name
Test status
Simulation time 10579895103 ps
CPU time 38.54 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:32 PM PDT 24
Peak memory 215076 kb
Host smart-be17e3b8-791c-4a96-b31d-ee60644b498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273874217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.273874217
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.166996724
Short name T617
Test name
Test status
Simulation time 2042186083 ps
CPU time 19.82 seconds
Started Apr 18 12:33:01 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 211156 kb
Host smart-0c52a4ce-37a8-49ce-be27-ed34b82c2744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166996724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.166996724
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2616556033
Short name T550
Test name
Test status
Simulation time 9263488597 ps
CPU time 23.39 seconds
Started Apr 18 02:03:37 PM PDT 24
Finished Apr 18 02:04:02 PM PDT 24
Peak memory 211988 kb
Host smart-071be774-adda-4b7b-9b49-f6b5b6d7f4b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616556033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2616556033
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3315837686
Short name T38
Test name
Test status
Simulation time 17714970287 ps
CPU time 245.35 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:37:15 PM PDT 24
Peak memory 239280 kb
Host smart-1ad95d39-9814-4a2c-9a35-8047ced17f4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315837686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3315837686
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3689318471
Short name T42
Test name
Test status
Simulation time 12733591235 ps
CPU time 236.78 seconds
Started Apr 18 02:03:42 PM PDT 24
Finished Apr 18 02:07:39 PM PDT 24
Peak memory 236852 kb
Host smart-ae3d7f49-0220-4b35-8980-5527d63107af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689318471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3689318471
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1840158199
Short name T620
Test name
Test status
Simulation time 6782086901 ps
CPU time 70.32 seconds
Started Apr 18 02:03:34 PM PDT 24
Finished Apr 18 02:04:45 PM PDT 24
Peak memory 215312 kb
Host smart-1ba663ad-b5e8-4510-9eba-08dbe7259d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840158199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1840158199
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2788522291
Short name T195
Test name
Test status
Simulation time 353628768 ps
CPU time 20.61 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:33:27 PM PDT 24
Peak memory 217264 kb
Host smart-3ac1bfbb-c68d-46a3-8ba2-baaf0201251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788522291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2788522291
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2123824301
Short name T107
Test name
Test status
Simulation time 65424412969 ps
CPU time 105.74 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 219328 kb
Host smart-fe6d2245-4ea0-46af-86e0-bfc51ae8869b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123824301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2123824301
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.278196411
Short name T460
Test name
Test status
Simulation time 12144981357 ps
CPU time 52.2 seconds
Started Apr 18 02:03:35 PM PDT 24
Finished Apr 18 02:04:28 PM PDT 24
Peak memory 217652 kb
Host smart-836d3678-7cc8-4687-be7c-1ed82e29a13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278196411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.278196411
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3860371312
Short name T186
Test name
Test status
Simulation time 1578367492 ps
CPU time 18.48 seconds
Started Apr 18 02:06:11 PM PDT 24
Finished Apr 18 02:06:30 PM PDT 24
Peak memory 211364 kb
Host smart-a9915f8d-15fa-47ab-b7c5-9939a4d90981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860371312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3860371312
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.740804228
Short name T648
Test name
Test status
Simulation time 164453740126 ps
CPU time 840.38 seconds
Started Apr 18 02:06:08 PM PDT 24
Finished Apr 18 02:20:10 PM PDT 24
Peak memory 229328 kb
Host smart-3e99204b-9307-4419-bc9d-0a17a67d7212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740804228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.740804228
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.946242993
Short name T657
Test name
Test status
Simulation time 2617035906 ps
CPU time 225.48 seconds
Started Apr 18 12:33:42 PM PDT 24
Finished Apr 18 12:37:28 PM PDT 24
Peak memory 240916 kb
Host smart-92a31625-f825-4d2f-bbf6-7c7ee89abc6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946242993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.946242993
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1488068245
Short name T21
Test name
Test status
Simulation time 2741782749 ps
CPU time 23.66 seconds
Started Apr 18 12:33:14 PM PDT 24
Finished Apr 18 12:33:39 PM PDT 24
Peak memory 213596 kb
Host smart-94773fe7-980c-448b-9767-5b4d37f4c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488068245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1488068245
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.17089969
Short name T202
Test name
Test status
Simulation time 16348913804 ps
CPU time 39.02 seconds
Started Apr 18 02:06:08 PM PDT 24
Finished Apr 18 02:06:48 PM PDT 24
Peak memory 215216 kb
Host smart-cbc1d91a-9d5d-4e02-8ee1-65d5bd159e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17089969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.17089969
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1861844798
Short name T326
Test name
Test status
Simulation time 3027973656 ps
CPU time 19.49 seconds
Started Apr 18 12:33:30 PM PDT 24
Finished Apr 18 12:33:51 PM PDT 24
Peak memory 211488 kb
Host smart-fbeb9d5c-224a-4afc-b3c5-94039bfe83ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861844798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1861844798
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2827475361
Short name T591
Test name
Test status
Simulation time 4296374146 ps
CPU time 22.43 seconds
Started Apr 18 02:06:08 PM PDT 24
Finished Apr 18 02:06:31 PM PDT 24
Peak memory 211924 kb
Host smart-bb8c805c-0183-481c-97e1-4d42f9c8427b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827475361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2827475361
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.308803365
Short name T618
Test name
Test status
Simulation time 14356191892 ps
CPU time 41.2 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 217728 kb
Host smart-896d9b5f-29d6-453e-a4f1-c4b821ae782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308803365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.308803365
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4232687901
Short name T428
Test name
Test status
Simulation time 30132774052 ps
CPU time 74.8 seconds
Started Apr 18 02:06:07 PM PDT 24
Finished Apr 18 02:07:23 PM PDT 24
Peak memory 217216 kb
Host smart-5abd09a0-288f-4b8b-a293-22b2c152aaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232687901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4232687901
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.344787746
Short name T249
Test name
Test status
Simulation time 13928842706 ps
CPU time 57.68 seconds
Started Apr 18 12:33:28 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 216232 kb
Host smart-5b0a829a-9ffa-4216-befb-570acda7ddcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344787746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.344787746
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1081011420
Short name T58
Test name
Test status
Simulation time 207130047726 ps
CPU time 2117.52 seconds
Started Apr 18 02:06:09 PM PDT 24
Finished Apr 18 02:41:27 PM PDT 24
Peak memory 245908 kb
Host smart-e342597f-d786-4e83-83f0-18a11bef9a56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081011420 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1081011420
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2505348360
Short name T536
Test name
Test status
Simulation time 7549467655 ps
CPU time 29.98 seconds
Started Apr 18 02:06:16 PM PDT 24
Finished Apr 18 02:06:46 PM PDT 24
Peak memory 212312 kb
Host smart-db41db19-0bcc-4619-b74a-fcc8944b5646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505348360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2505348360
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.671658358
Short name T453
Test name
Test status
Simulation time 281670887 ps
CPU time 8.16 seconds
Started Apr 18 12:33:24 PM PDT 24
Finished Apr 18 12:33:33 PM PDT 24
Peak memory 211280 kb
Host smart-fa185c31-a25e-4f48-af68-fa8d5e853764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671658358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.671658358
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.144568968
Short name T193
Test name
Test status
Simulation time 119160526073 ps
CPU time 298.09 seconds
Started Apr 18 02:06:07 PM PDT 24
Finished Apr 18 02:11:06 PM PDT 24
Peak memory 239600 kb
Host smart-c6c35470-c675-4d15-9b88-9a66dbe2c748
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144568968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.144568968
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3448326742
Short name T572
Test name
Test status
Simulation time 8617959847 ps
CPU time 163.19 seconds
Started Apr 18 12:33:13 PM PDT 24
Finished Apr 18 12:35:57 PM PDT 24
Peak memory 236492 kb
Host smart-f06784c0-45ba-437f-9a4c-d76f824fe2a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448326742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3448326742
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2313376444
Short name T558
Test name
Test status
Simulation time 332604177 ps
CPU time 19.52 seconds
Started Apr 18 12:33:30 PM PDT 24
Finished Apr 18 12:33:50 PM PDT 24
Peak memory 214680 kb
Host smart-d49666e1-a75d-4cc6-a174-144530dcb7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313376444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2313376444
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2427773869
Short name T154
Test name
Test status
Simulation time 8193525649 ps
CPU time 68.22 seconds
Started Apr 18 02:06:08 PM PDT 24
Finished Apr 18 02:07:16 PM PDT 24
Peak memory 215192 kb
Host smart-c4816dc4-8ae5-495c-b612-3254914aaf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427773869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2427773869
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1131904842
Short name T475
Test name
Test status
Simulation time 12724511340 ps
CPU time 30.38 seconds
Started Apr 18 12:33:31 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 211296 kb
Host smart-0e6dce68-6955-499b-a95e-21e281181a93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131904842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1131904842
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3980061659
Short name T399
Test name
Test status
Simulation time 12949640134 ps
CPU time 32.76 seconds
Started Apr 18 02:06:09 PM PDT 24
Finished Apr 18 02:06:42 PM PDT 24
Peak memory 211852 kb
Host smart-efbf2539-587e-4666-a239-075d929a39dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980061659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3980061659
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2478668797
Short name T471
Test name
Test status
Simulation time 671452380 ps
CPU time 20.27 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:33:46 PM PDT 24
Peak memory 214764 kb
Host smart-c95249ff-cb73-44a4-ab49-d49f45564eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478668797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2478668797
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3809905739
Short name T2
Test name
Test status
Simulation time 4759803708 ps
CPU time 53.28 seconds
Started Apr 18 02:06:09 PM PDT 24
Finished Apr 18 02:07:03 PM PDT 24
Peak memory 215180 kb
Host smart-a4e425fa-a70a-474c-9460-cf6a245cfa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809905739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3809905739
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2520972743
Short name T147
Test name
Test status
Simulation time 16802661066 ps
CPU time 89.09 seconds
Started Apr 18 12:33:27 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 221184 kb
Host smart-da8e1ef9-47d5-45d4-b895-e90ef393970d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520972743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2520972743
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3211181153
Short name T276
Test name
Test status
Simulation time 29642555183 ps
CPU time 158.83 seconds
Started Apr 18 02:06:11 PM PDT 24
Finished Apr 18 02:08:51 PM PDT 24
Peak memory 221332 kb
Host smart-86e019dc-44a7-4cda-9741-3f66fe66e415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211181153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3211181153
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3333406818
Short name T653
Test name
Test status
Simulation time 590597520 ps
CPU time 8.42 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 12:33:35 PM PDT 24
Peak memory 211268 kb
Host smart-081fd68f-0a30-4809-a526-65860844a98b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333406818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3333406818
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3857720436
Short name T73
Test name
Test status
Simulation time 2862723457 ps
CPU time 24.95 seconds
Started Apr 18 02:06:23 PM PDT 24
Finished Apr 18 02:06:49 PM PDT 24
Peak memory 211400 kb
Host smart-ad232377-ec05-410d-8ca1-34ac761c3ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857720436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3857720436
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3290784787
Short name T294
Test name
Test status
Simulation time 118619822062 ps
CPU time 295.55 seconds
Started Apr 18 12:33:34 PM PDT 24
Finished Apr 18 12:38:31 PM PDT 24
Peak memory 228004 kb
Host smart-25f87969-57e9-4bbc-aeb3-153dc2cdb4f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290784787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3290784787
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3665469978
Short name T608
Test name
Test status
Simulation time 160435685050 ps
CPU time 421.66 seconds
Started Apr 18 02:06:16 PM PDT 24
Finished Apr 18 02:13:18 PM PDT 24
Peak memory 236908 kb
Host smart-a85e097b-594f-498a-a38c-34968e77a7a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665469978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3665469978
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1962231412
Short name T628
Test name
Test status
Simulation time 34156887956 ps
CPU time 70.15 seconds
Started Apr 18 02:06:15 PM PDT 24
Finished Apr 18 02:07:26 PM PDT 24
Peak memory 213056 kb
Host smart-04411b8d-754c-43bc-b9c3-938ae8f868a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962231412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1962231412
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2975010422
Short name T23
Test name
Test status
Simulation time 1433350654 ps
CPU time 19.74 seconds
Started Apr 18 12:33:29 PM PDT 24
Finished Apr 18 12:33:50 PM PDT 24
Peak memory 214644 kb
Host smart-437ad17a-32be-4840-be7d-69556004be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975010422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2975010422
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2365495034
Short name T502
Test name
Test status
Simulation time 2733442447 ps
CPU time 27.2 seconds
Started Apr 18 02:06:15 PM PDT 24
Finished Apr 18 02:06:43 PM PDT 24
Peak memory 211428 kb
Host smart-6c15c182-d3ee-4346-98f2-41029a8eaad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365495034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2365495034
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3570902943
Short name T385
Test name
Test status
Simulation time 17691423085 ps
CPU time 24.4 seconds
Started Apr 18 12:33:27 PM PDT 24
Finished Apr 18 12:33:53 PM PDT 24
Peak memory 211796 kb
Host smart-14eb94b0-9212-4926-8f4f-01f2c923b2e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570902943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3570902943
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1028753613
Short name T392
Test name
Test status
Simulation time 19404184756 ps
CPU time 53.61 seconds
Started Apr 18 02:06:16 PM PDT 24
Finished Apr 18 02:07:10 PM PDT 24
Peak memory 215436 kb
Host smart-b2072f66-d904-4525-abee-48128f87f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028753613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1028753613
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1034153655
Short name T465
Test name
Test status
Simulation time 5473300695 ps
CPU time 51.42 seconds
Started Apr 18 12:33:13 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 217648 kb
Host smart-dc26e103-fe53-4cf3-84bb-cad9447c264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034153655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1034153655
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1259952405
Short name T506
Test name
Test status
Simulation time 22203904698 ps
CPU time 111.75 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 219140 kb
Host smart-2f28e2c0-4164-498d-a271-e1b358fb5b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259952405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1259952405
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.352472028
Short name T659
Test name
Test status
Simulation time 1202890277 ps
CPU time 56.31 seconds
Started Apr 18 02:06:18 PM PDT 24
Finished Apr 18 02:07:14 PM PDT 24
Peak memory 219300 kb
Host smart-47a47894-1364-49e0-9901-969abc5bec2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352472028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.352472028
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2583169962
Short name T451
Test name
Test status
Simulation time 5173935864 ps
CPU time 20.78 seconds
Started Apr 18 02:06:21 PM PDT 24
Finished Apr 18 02:06:42 PM PDT 24
Peak memory 212524 kb
Host smart-9148dda8-b155-4557-a70a-bf190230f30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583169962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2583169962
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4102771439
Short name T292
Test name
Test status
Simulation time 7885543164 ps
CPU time 20.45 seconds
Started Apr 18 12:33:42 PM PDT 24
Finished Apr 18 12:34:03 PM PDT 24
Peak memory 212408 kb
Host smart-fab0dda1-4cb2-441a-ba9f-303e07cb63a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102771439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4102771439
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.155179060
Short name T501
Test name
Test status
Simulation time 26710519055 ps
CPU time 349.16 seconds
Started Apr 18 12:33:33 PM PDT 24
Finished Apr 18 12:39:23 PM PDT 24
Peak memory 237908 kb
Host smart-880bd1f5-09ef-4e69-9acb-f67080f46ee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155179060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.155179060
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2854927151
Short name T369
Test name
Test status
Simulation time 102330907556 ps
CPU time 991.05 seconds
Started Apr 18 02:06:23 PM PDT 24
Finished Apr 18 02:22:55 PM PDT 24
Peak memory 225532 kb
Host smart-6c5e6a0c-c7e2-41f2-a543-40ebaf8de2f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854927151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2854927151
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3048864200
Short name T214
Test name
Test status
Simulation time 6332967199 ps
CPU time 39.55 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 214976 kb
Host smart-21d3b379-7956-4942-8509-9b60a77feea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048864200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3048864200
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3625221012
Short name T335
Test name
Test status
Simulation time 1473633575 ps
CPU time 28.72 seconds
Started Apr 18 02:06:22 PM PDT 24
Finished Apr 18 02:06:52 PM PDT 24
Peak memory 215744 kb
Host smart-3a877f1a-3c7d-445d-810a-df25172abe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625221012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3625221012
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2890740468
Short name T319
Test name
Test status
Simulation time 3126721340 ps
CPU time 15.36 seconds
Started Apr 18 02:06:22 PM PDT 24
Finished Apr 18 02:06:38 PM PDT 24
Peak memory 212668 kb
Host smart-a983de54-aa5f-4a4b-aee8-285765cce790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890740468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2890740468
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3937485938
Short name T652
Test name
Test status
Simulation time 699993503 ps
CPU time 10.41 seconds
Started Apr 18 12:33:24 PM PDT 24
Finished Apr 18 12:33:36 PM PDT 24
Peak memory 212524 kb
Host smart-33596819-b170-49fe-a154-6a74dc3e1a09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3937485938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3937485938
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1317906473
Short name T582
Test name
Test status
Simulation time 17746891637 ps
CPU time 50.99 seconds
Started Apr 18 02:06:28 PM PDT 24
Finished Apr 18 02:07:20 PM PDT 24
Peak memory 218596 kb
Host smart-e81240d5-df19-4dd1-83c2-dca74c4c2e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317906473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1317906473
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.582112888
Short name T588
Test name
Test status
Simulation time 27793474919 ps
CPU time 70.37 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:34:37 PM PDT 24
Peak memory 216800 kb
Host smart-7f4102b7-b599-4b85-b8a7-9f777c6eb5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582112888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.582112888
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.196148835
Short name T589
Test name
Test status
Simulation time 12659096938 ps
CPU time 29.58 seconds
Started Apr 18 02:06:26 PM PDT 24
Finished Apr 18 02:06:56 PM PDT 24
Peak memory 213968 kb
Host smart-c787525e-04bb-40f8-835f-11f5b72207e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196148835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.196148835
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.811112108
Short name T304
Test name
Test status
Simulation time 22315992068 ps
CPU time 68.26 seconds
Started Apr 18 12:33:28 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 221124 kb
Host smart-8978ac26-7efa-4c94-8b50-bb180d7ece0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811112108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.811112108
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2327491316
Short name T173
Test name
Test status
Simulation time 250110302 ps
CPU time 9.9 seconds
Started Apr 18 02:06:32 PM PDT 24
Finished Apr 18 02:06:42 PM PDT 24
Peak memory 211356 kb
Host smart-7a502c65-820a-4bc1-a0f5-907118908450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327491316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2327491316
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2983698419
Short name T179
Test name
Test status
Simulation time 2137027690 ps
CPU time 22.97 seconds
Started Apr 18 12:33:27 PM PDT 24
Finished Apr 18 12:33:51 PM PDT 24
Peak memory 211892 kb
Host smart-979f8421-da0e-44bb-857b-462e44f24aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983698419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2983698419
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.310916525
Short name T284
Test name
Test status
Simulation time 7796638396 ps
CPU time 181.26 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 12:36:28 PM PDT 24
Peak memory 237596 kb
Host smart-bddbca9c-24a5-48e1-bee9-e6f5abc3e34e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310916525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.310916525
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3266334864
Short name T639
Test name
Test status
Simulation time 13589158626 ps
CPU time 232.76 seconds
Started Apr 18 02:06:28 PM PDT 24
Finished Apr 18 02:10:22 PM PDT 24
Peak memory 240708 kb
Host smart-8473fdf1-7550-492b-a4cd-ca9d14dad33a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266334864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3266334864
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1659206078
Short name T491
Test name
Test status
Simulation time 674981002 ps
CPU time 19.06 seconds
Started Apr 18 02:06:32 PM PDT 24
Finished Apr 18 02:06:52 PM PDT 24
Peak memory 214732 kb
Host smart-83ae2315-bf11-4866-b44b-a8900ddfcce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659206078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1659206078
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.564082428
Short name T265
Test name
Test status
Simulation time 8033466170 ps
CPU time 44.57 seconds
Started Apr 18 12:33:29 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 214460 kb
Host smart-b1645740-b3a9-4f93-ab5c-30e0a2a5240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564082428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.564082428
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3051552114
Short name T201
Test name
Test status
Simulation time 6816773127 ps
CPU time 20.44 seconds
Started Apr 18 02:06:22 PM PDT 24
Finished Apr 18 02:06:43 PM PDT 24
Peak memory 212948 kb
Host smart-d4677b1b-2319-4ccc-ad5b-a210f1f32807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3051552114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3051552114
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3649757241
Short name T115
Test name
Test status
Simulation time 350109568 ps
CPU time 10.44 seconds
Started Apr 18 12:33:31 PM PDT 24
Finished Apr 18 12:33:42 PM PDT 24
Peak memory 212256 kb
Host smart-a6c2f71e-3401-46ea-83f2-3534e5bd4daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649757241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3649757241
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3301387924
Short name T368
Test name
Test status
Simulation time 19067272978 ps
CPU time 50.4 seconds
Started Apr 18 02:06:22 PM PDT 24
Finished Apr 18 02:07:13 PM PDT 24
Peak memory 217908 kb
Host smart-36cc271b-d025-408d-a886-c9dafea4d0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301387924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3301387924
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1700748887
Short name T345
Test name
Test status
Simulation time 26068347749 ps
CPU time 77.82 seconds
Started Apr 18 02:06:23 PM PDT 24
Finished Apr 18 02:07:42 PM PDT 24
Peak memory 221252 kb
Host smart-33748dd4-0c05-409f-97e0-26b0002eaafc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700748887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1700748887
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.489601553
Short name T158
Test name
Test status
Simulation time 7900671887 ps
CPU time 74.28 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:34:41 PM PDT 24
Peak memory 219324 kb
Host smart-7867e2a6-0dca-4861-ac9d-f05f6fa44575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489601553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.489601553
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3645974712
Short name T416
Test name
Test status
Simulation time 4004176860 ps
CPU time 27.79 seconds
Started Apr 18 12:33:28 PM PDT 24
Finished Apr 18 12:33:57 PM PDT 24
Peak memory 212000 kb
Host smart-e3ce062a-7c09-48c7-8a2a-f5f63defa0d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645974712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3645974712
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.566733705
Short name T395
Test name
Test status
Simulation time 3169676153 ps
CPU time 26.93 seconds
Started Apr 18 02:06:38 PM PDT 24
Finished Apr 18 02:07:05 PM PDT 24
Peak memory 211980 kb
Host smart-c2d736f9-5f94-4b68-b6bb-06b06be9a904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566733705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.566733705
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2577619874
Short name T510
Test name
Test status
Simulation time 10504032291 ps
CPU time 208.24 seconds
Started Apr 18 12:33:36 PM PDT 24
Finished Apr 18 12:37:05 PM PDT 24
Peak memory 240088 kb
Host smart-f72b9f69-0e8f-4230-b6e5-08742bcd1056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577619874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2577619874
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3576507069
Short name T342
Test name
Test status
Simulation time 107784033825 ps
CPU time 368.61 seconds
Started Apr 18 02:06:30 PM PDT 24
Finished Apr 18 02:12:39 PM PDT 24
Peak memory 237956 kb
Host smart-0708c8ac-5df9-4f86-9cd6-f440cce7fbb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576507069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3576507069
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2307896365
Short name T221
Test name
Test status
Simulation time 24452749680 ps
CPU time 57.91 seconds
Started Apr 18 02:06:36 PM PDT 24
Finished Apr 18 02:07:35 PM PDT 24
Peak memory 215328 kb
Host smart-858656e8-bc9d-4da8-a4e9-4bf9b4f85cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307896365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2307896365
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3446766361
Short name T178
Test name
Test status
Simulation time 336034149 ps
CPU time 19.24 seconds
Started Apr 18 12:33:23 PM PDT 24
Finished Apr 18 12:33:44 PM PDT 24
Peak memory 215168 kb
Host smart-0e10aede-cd8a-474d-be56-4a8a42ad2eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446766361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3446766361
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2146685877
Short name T262
Test name
Test status
Simulation time 6028643003 ps
CPU time 26.83 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:33:53 PM PDT 24
Peak memory 211476 kb
Host smart-85a68a5d-64d5-4807-a6cf-e1c299819016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146685877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2146685877
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2310145604
Short name T167
Test name
Test status
Simulation time 1980738057 ps
CPU time 21.36 seconds
Started Apr 18 02:06:31 PM PDT 24
Finished Apr 18 02:06:53 PM PDT 24
Peak memory 211340 kb
Host smart-9ea56a5b-7e3d-4112-8a2f-5b0316e7d46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310145604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2310145604
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1142084111
Short name T86
Test name
Test status
Simulation time 26069214038 ps
CPU time 65.63 seconds
Started Apr 18 12:33:34 PM PDT 24
Finished Apr 18 12:34:41 PM PDT 24
Peak memory 217728 kb
Host smart-fc53917e-45c7-4a6d-b4a2-4ec9b90b0c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142084111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1142084111
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3520249342
Short name T120
Test name
Test status
Simulation time 7850569616 ps
CPU time 52.61 seconds
Started Apr 18 02:06:29 PM PDT 24
Finished Apr 18 02:07:22 PM PDT 24
Peak memory 217856 kb
Host smart-8d8dc8ea-da18-4223-993c-be15f8b55fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520249342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3520249342
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2601297861
Short name T596
Test name
Test status
Simulation time 13066798263 ps
CPU time 133.19 seconds
Started Apr 18 02:06:35 PM PDT 24
Finished Apr 18 02:08:48 PM PDT 24
Peak memory 221332 kb
Host smart-3840548f-6c0c-4591-bbe9-23e3c6548060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601297861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2601297861
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.754561208
Short name T445
Test name
Test status
Simulation time 12871793105 ps
CPU time 65.6 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:34:32 PM PDT 24
Peak memory 220824 kb
Host smart-07834c5c-ff7e-4c69-b584-3c1b774aeeac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754561208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.754561208
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2953586188
Short name T480
Test name
Test status
Simulation time 473209903 ps
CPU time 8.37 seconds
Started Apr 18 02:06:37 PM PDT 24
Finished Apr 18 02:06:46 PM PDT 24
Peak memory 211404 kb
Host smart-3fd239e2-9d37-4476-a5fe-077f198acd5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953586188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2953586188
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.880618052
Short name T180
Test name
Test status
Simulation time 26312262397 ps
CPU time 24.05 seconds
Started Apr 18 12:33:28 PM PDT 24
Finished Apr 18 12:33:53 PM PDT 24
Peak memory 212308 kb
Host smart-ef873787-ac68-4e26-ad34-98c30b6eb182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880618052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.880618052
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.32924103
Short name T354
Test name
Test status
Simulation time 20707889025 ps
CPU time 463.22 seconds
Started Apr 18 02:06:36 PM PDT 24
Finished Apr 18 02:14:20 PM PDT 24
Peak memory 237964 kb
Host smart-1096ef48-832b-456a-9cfe-00874446f159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32924103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_co
rrupt_sig_fatal_chk.32924103
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3701148652
Short name T28
Test name
Test status
Simulation time 117655239220 ps
CPU time 560.47 seconds
Started Apr 18 12:33:29 PM PDT 24
Finished Apr 18 12:42:50 PM PDT 24
Peak memory 217760 kb
Host smart-e8dbd02a-1a76-4f97-8828-cdd35d68ceed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701148652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3701148652
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2290380105
Short name T585
Test name
Test status
Simulation time 42566174834 ps
CPU time 64.81 seconds
Started Apr 18 02:06:38 PM PDT 24
Finished Apr 18 02:07:43 PM PDT 24
Peak memory 214732 kb
Host smart-a7a6207b-8c75-484b-a458-272b3d93913b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290380105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2290380105
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.732467407
Short name T380
Test name
Test status
Simulation time 17408155184 ps
CPU time 70.46 seconds
Started Apr 18 12:33:34 PM PDT 24
Finished Apr 18 12:34:46 PM PDT 24
Peak memory 213940 kb
Host smart-436ff2cd-ca6b-426d-86e9-de6965a204e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732467407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.732467407
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.355587801
Short name T16
Test name
Test status
Simulation time 30011674182 ps
CPU time 26.38 seconds
Started Apr 18 12:33:22 PM PDT 24
Finished Apr 18 12:33:50 PM PDT 24
Peak memory 211336 kb
Host smart-6afa08e3-84a2-4179-a488-50c71af4b94b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355587801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.355587801
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.470093012
Short name T615
Test name
Test status
Simulation time 2979298649 ps
CPU time 21.15 seconds
Started Apr 18 02:06:46 PM PDT 24
Finished Apr 18 02:07:07 PM PDT 24
Peak memory 211692 kb
Host smart-01373af1-3f4d-40a3-80a2-dc8b4a8cb8ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470093012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.470093012
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2236624407
Short name T663
Test name
Test status
Simulation time 8907934992 ps
CPU time 70.38 seconds
Started Apr 18 02:06:39 PM PDT 24
Finished Apr 18 02:07:50 PM PDT 24
Peak memory 217908 kb
Host smart-d6568d4f-74d6-4f66-b8f4-d80cec9585ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236624407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2236624407
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.605736758
Short name T88
Test name
Test status
Simulation time 21659445124 ps
CPU time 56.23 seconds
Started Apr 18 12:33:25 PM PDT 24
Finished Apr 18 12:34:23 PM PDT 24
Peak memory 216708 kb
Host smart-d017b363-76ce-4009-9ee0-4cf0f939d0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605736758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.605736758
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1881995450
Short name T476
Test name
Test status
Simulation time 32233642001 ps
CPU time 60.46 seconds
Started Apr 18 12:33:32 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 215772 kb
Host smart-5cc241ea-1c8d-4bd9-97be-bdb358152293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881995450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1881995450
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2722499060
Short name T569
Test name
Test status
Simulation time 109434304601 ps
CPU time 181.02 seconds
Started Apr 18 02:06:38 PM PDT 24
Finished Apr 18 02:09:39 PM PDT 24
Peak memory 230288 kb
Host smart-0db7bfec-8d6c-4d8e-8578-533d6330e399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722499060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2722499060
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1642179064
Short name T35
Test name
Test status
Simulation time 1565717605 ps
CPU time 17.95 seconds
Started Apr 18 12:33:40 PM PDT 24
Finished Apr 18 12:33:59 PM PDT 24
Peak memory 211368 kb
Host smart-f3f5650b-c456-4be7-ad3d-d49a1021f5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642179064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1642179064
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3632049310
Short name T71
Test name
Test status
Simulation time 1806077572 ps
CPU time 20.22 seconds
Started Apr 18 02:06:48 PM PDT 24
Finished Apr 18 02:07:09 PM PDT 24
Peak memory 211384 kb
Host smart-ccd94537-9454-487d-96ed-cb555278c910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632049310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3632049310
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2508702076
Short name T573
Test name
Test status
Simulation time 129772218726 ps
CPU time 419.43 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:40:38 PM PDT 24
Peak memory 240540 kb
Host smart-bc4e93c8-6d10-4fd2-9494-e826c046c2e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508702076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2508702076
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3943896972
Short name T584
Test name
Test status
Simulation time 346492461 ps
CPU time 19.21 seconds
Started Apr 18 12:33:29 PM PDT 24
Finished Apr 18 12:33:49 PM PDT 24
Peak memory 214784 kb
Host smart-269894fc-5528-406d-bb19-2e13d2f08e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943896972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3943896972
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.572656722
Short name T7
Test name
Test status
Simulation time 7657935517 ps
CPU time 62.45 seconds
Started Apr 18 02:06:49 PM PDT 24
Finished Apr 18 02:07:52 PM PDT 24
Peak memory 215092 kb
Host smart-dd77882d-16c8-4280-b07a-700ec1dbb522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572656722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.572656722
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3046956791
Short name T241
Test name
Test status
Simulation time 73838555612 ps
CPU time 33.45 seconds
Started Apr 18 02:06:37 PM PDT 24
Finished Apr 18 02:07:11 PM PDT 24
Peak memory 212940 kb
Host smart-e8a4b64a-01d5-4913-b0e7-b68688bd6fcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046956791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3046956791
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4270855989
Short name T291
Test name
Test status
Simulation time 184805703 ps
CPU time 10.35 seconds
Started Apr 18 12:33:42 PM PDT 24
Finished Apr 18 12:33:53 PM PDT 24
Peak memory 212488 kb
Host smart-22e25bbf-f562-41cb-acbe-4f0a6bd7455b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270855989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4270855989
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1075373054
Short name T9
Test name
Test status
Simulation time 1229033797 ps
CPU time 19.76 seconds
Started Apr 18 02:06:38 PM PDT 24
Finished Apr 18 02:06:58 PM PDT 24
Peak memory 216440 kb
Host smart-388b11bb-84b6-48e7-80b1-450e1c403be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075373054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1075373054
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2901379849
Short name T322
Test name
Test status
Simulation time 7538612974 ps
CPU time 61.87 seconds
Started Apr 18 12:33:26 PM PDT 24
Finished Apr 18 12:34:29 PM PDT 24
Peak memory 217940 kb
Host smart-ebb15473-cc49-4e95-b0eb-7ea53eb08867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901379849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2901379849
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1111908609
Short name T527
Test name
Test status
Simulation time 8589858391 ps
CPU time 72.12 seconds
Started Apr 18 12:33:34 PM PDT 24
Finished Apr 18 12:34:47 PM PDT 24
Peak memory 219036 kb
Host smart-30fd87bb-66a4-431c-b3e6-7b2739d8b83e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111908609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1111908609
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.249850941
Short name T581
Test name
Test status
Simulation time 15617059633 ps
CPU time 77.94 seconds
Started Apr 18 02:06:40 PM PDT 24
Finished Apr 18 02:07:58 PM PDT 24
Peak memory 227608 kb
Host smart-7069a247-ebab-477f-9ac5-3b2792a6e40c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249850941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.249850941
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1556611481
Short name T604
Test name
Test status
Simulation time 5672434100 ps
CPU time 32.02 seconds
Started Apr 18 12:33:36 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 212448 kb
Host smart-f710befb-876d-44cf-a46c-9a2d3304c4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556611481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1556611481
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2344535730
Short name T289
Test name
Test status
Simulation time 2311186556 ps
CPU time 21.81 seconds
Started Apr 18 02:06:47 PM PDT 24
Finished Apr 18 02:07:09 PM PDT 24
Peak memory 211548 kb
Host smart-7f922297-473b-4ece-abf5-0e80c3c09824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344535730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2344535730
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1578485864
Short name T372
Test name
Test status
Simulation time 99610281365 ps
CPU time 493.9 seconds
Started Apr 18 12:33:34 PM PDT 24
Finished Apr 18 12:41:49 PM PDT 24
Peak memory 237600 kb
Host smart-4c1a6bea-2211-46c6-b757-dd40647ea8b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578485864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1578485864
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2104330071
Short name T139
Test name
Test status
Simulation time 213665863700 ps
CPU time 460.76 seconds
Started Apr 18 02:06:50 PM PDT 24
Finished Apr 18 02:14:31 PM PDT 24
Peak memory 240556 kb
Host smart-addeab40-0fc1-44db-be4c-77735a1891f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104330071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2104330071
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1686375377
Short name T644
Test name
Test status
Simulation time 51769926877 ps
CPU time 60.53 seconds
Started Apr 18 02:06:48 PM PDT 24
Finished Apr 18 02:07:49 PM PDT 24
Peak memory 215096 kb
Host smart-de27de4c-8bc0-41c7-8184-5a01b9446382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686375377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1686375377
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3579343675
Short name T228
Test name
Test status
Simulation time 339164367 ps
CPU time 19.15 seconds
Started Apr 18 12:33:41 PM PDT 24
Finished Apr 18 12:34:01 PM PDT 24
Peak memory 214604 kb
Host smart-48107078-9a52-4435-8538-61c0a72abbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579343675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3579343675
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2181666598
Short name T285
Test name
Test status
Simulation time 1596323170 ps
CPU time 21 seconds
Started Apr 18 02:06:49 PM PDT 24
Finished Apr 18 02:07:10 PM PDT 24
Peak memory 211300 kb
Host smart-a6bb2f32-d838-46c5-a64d-9f0dee8528f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181666598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2181666598
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3473434312
Short name T283
Test name
Test status
Simulation time 178742552 ps
CPU time 10.5 seconds
Started Apr 18 12:33:33 PM PDT 24
Finished Apr 18 12:33:44 PM PDT 24
Peak memory 212152 kb
Host smart-c29d0cdb-406b-40bf-b01a-2986f9373d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473434312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3473434312
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2160956365
Short name T254
Test name
Test status
Simulation time 345375008 ps
CPU time 19.67 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:33:59 PM PDT 24
Peak memory 216948 kb
Host smart-03be0af2-4ce2-4952-8cf5-21057d42f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160956365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2160956365
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.497698844
Short name T405
Test name
Test status
Simulation time 2325192034 ps
CPU time 30.86 seconds
Started Apr 18 02:06:50 PM PDT 24
Finished Apr 18 02:07:21 PM PDT 24
Peak memory 217392 kb
Host smart-b10326da-779c-4f4f-baf1-96853a3dcb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497698844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.497698844
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.176772783
Short name T603
Test name
Test status
Simulation time 16167855168 ps
CPU time 34 seconds
Started Apr 18 02:06:49 PM PDT 24
Finished Apr 18 02:07:23 PM PDT 24
Peak memory 214244 kb
Host smart-e3e46adc-904a-4526-964f-98626365c1f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176772783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.176772783
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2279324871
Short name T426
Test name
Test status
Simulation time 13639578492 ps
CPU time 78.68 seconds
Started Apr 18 12:33:37 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 219712 kb
Host smart-c5017a5d-48d2-494b-b9e9-c684db444638
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279324871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2279324871
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2914283592
Short name T566
Test name
Test status
Simulation time 12252401171 ps
CPU time 27.01 seconds
Started Apr 18 12:33:36 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 212260 kb
Host smart-bb06149e-7101-45bd-8012-3bfff3b081f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914283592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2914283592
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3571230309
Short name T403
Test name
Test status
Simulation time 15655984515 ps
CPU time 31.01 seconds
Started Apr 18 02:06:54 PM PDT 24
Finished Apr 18 02:07:26 PM PDT 24
Peak memory 212372 kb
Host smart-b92a9af9-219e-417c-85fe-2444bfc7ae50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571230309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3571230309
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1422156608
Short name T523
Test name
Test status
Simulation time 19154473464 ps
CPU time 333.91 seconds
Started Apr 18 02:06:47 PM PDT 24
Finished Apr 18 02:12:22 PM PDT 24
Peak memory 240888 kb
Host smart-24222cf7-d9dc-4ffc-b20e-17dc81dfb0dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422156608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1422156608
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2437317511
Short name T50
Test name
Test status
Simulation time 63780754877 ps
CPU time 447.26 seconds
Started Apr 18 12:33:40 PM PDT 24
Finished Apr 18 12:41:08 PM PDT 24
Peak memory 240360 kb
Host smart-06aca57a-09e5-4bbf-b511-0f2b44696bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437317511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2437317511
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2042912167
Short name T280
Test name
Test status
Simulation time 13791534581 ps
CPU time 32.33 seconds
Started Apr 18 12:33:41 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 215164 kb
Host smart-7fe5c9ad-729f-4844-ad0a-b3c240698282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042912167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2042912167
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3790983816
Short name T586
Test name
Test status
Simulation time 1436932722 ps
CPU time 19.46 seconds
Started Apr 18 02:06:50 PM PDT 24
Finished Apr 18 02:07:10 PM PDT 24
Peak memory 214692 kb
Host smart-508cdc7b-0d3a-48f3-b437-f11d66d6f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790983816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3790983816
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1767970691
Short name T194
Test name
Test status
Simulation time 797208810 ps
CPU time 10.15 seconds
Started Apr 18 12:33:32 PM PDT 24
Finished Apr 18 12:33:43 PM PDT 24
Peak memory 212436 kb
Host smart-58a7013f-fc64-44e2-8d54-ffcc7ae5b9bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767970691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1767970691
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.34622772
Short name T45
Test name
Test status
Simulation time 718965414 ps
CPU time 10.11 seconds
Started Apr 18 02:06:49 PM PDT 24
Finished Apr 18 02:07:00 PM PDT 24
Peak memory 212644 kb
Host smart-879046b9-09d5-4cfa-8d84-89c1a8696127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34622772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.34622772
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.233504936
Short name T570
Test name
Test status
Simulation time 24816335862 ps
CPU time 57.52 seconds
Started Apr 18 02:06:49 PM PDT 24
Finished Apr 18 02:07:47 PM PDT 24
Peak memory 217516 kb
Host smart-29900544-7a26-4705-9a4e-7c435e103f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233504936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.233504936
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.565380448
Short name T580
Test name
Test status
Simulation time 1431535838 ps
CPU time 19.93 seconds
Started Apr 18 12:33:36 PM PDT 24
Finished Apr 18 12:33:57 PM PDT 24
Peak memory 216796 kb
Host smart-258d48e0-d53d-4aab-9741-b5391f8fc5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565380448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.565380448
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2497884145
Short name T307
Test name
Test status
Simulation time 36870673304 ps
CPU time 32.41 seconds
Started Apr 18 02:06:49 PM PDT 24
Finished Apr 18 02:07:22 PM PDT 24
Peak memory 213916 kb
Host smart-90404e8b-0124-41c3-9e50-ad9773ea6287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497884145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2497884145
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.794548826
Short name T469
Test name
Test status
Simulation time 6014087166 ps
CPU time 50.07 seconds
Started Apr 18 12:33:35 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 219152 kb
Host smart-337343ca-2e5d-4f8f-a708-a40450161d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794548826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.794548826
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1842794106
Short name T328
Test name
Test status
Simulation time 4176686384 ps
CPU time 21.44 seconds
Started Apr 18 02:03:51 PM PDT 24
Finished Apr 18 02:04:13 PM PDT 24
Peak memory 211560 kb
Host smart-1596b3c9-17b2-40cb-9753-1831856047ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842794106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1842794106
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3543022080
Short name T664
Test name
Test status
Simulation time 5604919167 ps
CPU time 24.05 seconds
Started Apr 18 12:33:10 PM PDT 24
Finished Apr 18 12:33:36 PM PDT 24
Peak memory 211352 kb
Host smart-111ab5f0-0194-4053-8e67-7739ad51b0d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543022080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3543022080
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2313545939
Short name T51
Test name
Test status
Simulation time 58915502223 ps
CPU time 582.31 seconds
Started Apr 18 02:03:42 PM PDT 24
Finished Apr 18 02:13:25 PM PDT 24
Peak memory 237796 kb
Host smart-c7d0902c-d05f-4cc7-9d7c-6d990e3dd5fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313545939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2313545939
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3671726463
Short name T321
Test name
Test status
Simulation time 53266247085 ps
CPU time 320.69 seconds
Started Apr 18 12:33:11 PM PDT 24
Finished Apr 18 12:38:33 PM PDT 24
Peak memory 240680 kb
Host smart-6969190d-6590-4c1c-a5cd-cc939632acbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671726463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3671726463
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2354533219
Short name T279
Test name
Test status
Simulation time 6841469271 ps
CPU time 40.96 seconds
Started Apr 18 02:03:49 PM PDT 24
Finished Apr 18 02:04:31 PM PDT 24
Peak memory 215400 kb
Host smart-67b9c342-47ce-40bd-ab15-332082061440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354533219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2354533219
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2401342501
Short name T157
Test name
Test status
Simulation time 8017889628 ps
CPU time 43.21 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:37 PM PDT 24
Peak memory 215504 kb
Host smart-a1142f57-4cfd-4f89-9fa4-16d4f19f5d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401342501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2401342501
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2462313266
Short name T494
Test name
Test status
Simulation time 11982877263 ps
CPU time 28.75 seconds
Started Apr 18 02:03:43 PM PDT 24
Finished Apr 18 02:04:12 PM PDT 24
Peak memory 212968 kb
Host smart-921b3346-de47-4739-bb72-c512e34fedc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462313266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2462313266
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2778735923
Short name T499
Test name
Test status
Simulation time 747957105 ps
CPU time 10 seconds
Started Apr 18 12:32:54 PM PDT 24
Finished Apr 18 12:33:06 PM PDT 24
Peak memory 212236 kb
Host smart-ffd164b7-9790-43af-915b-a5c090daae72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2778735923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2778735923
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3389001676
Short name T40
Test name
Test status
Simulation time 75603839356 ps
CPU time 242.94 seconds
Started Apr 18 02:03:52 PM PDT 24
Finished Apr 18 02:07:55 PM PDT 24
Peak memory 238504 kb
Host smart-391d3b00-716b-45f8-b84e-5ca74c1af395
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389001676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3389001676
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2046482463
Short name T341
Test name
Test status
Simulation time 12757858703 ps
CPU time 57.94 seconds
Started Apr 18 02:03:44 PM PDT 24
Finished Apr 18 02:04:42 PM PDT 24
Peak memory 217936 kb
Host smart-7a2c1929-c54b-4041-a8eb-3aea00418c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046482463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2046482463
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2636244974
Short name T351
Test name
Test status
Simulation time 4141653679 ps
CPU time 35.76 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:30 PM PDT 24
Peak memory 216560 kb
Host smart-73d58f6b-2b4c-4970-8b55-f8a75617fc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636244974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2636244974
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1980495176
Short name T418
Test name
Test status
Simulation time 27771289804 ps
CPU time 84.96 seconds
Started Apr 18 02:03:49 PM PDT 24
Finished Apr 18 02:05:15 PM PDT 24
Peak memory 215712 kb
Host smart-f2673dac-97de-4d5b-9d89-b804f92d3a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980495176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1980495176
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.871936911
Short name T383
Test name
Test status
Simulation time 199231558 ps
CPU time 10.87 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:33:15 PM PDT 24
Peak memory 212456 kb
Host smart-cc98ad9a-1e7f-4a87-ad8a-9c1446a3571a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871936911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.871936911
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1664631877
Short name T638
Test name
Test status
Simulation time 1036894110 ps
CPU time 9.91 seconds
Started Apr 18 02:06:55 PM PDT 24
Finished Apr 18 02:07:05 PM PDT 24
Peak memory 211364 kb
Host smart-3f156676-c0d8-4ae8-8200-512071cf9459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664631877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1664631877
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3922980029
Short name T484
Test name
Test status
Simulation time 4336324541 ps
CPU time 13.59 seconds
Started Apr 18 12:33:36 PM PDT 24
Finished Apr 18 12:33:51 PM PDT 24
Peak memory 211416 kb
Host smart-1660ca8d-dd94-4e92-b971-fc5352f194ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922980029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3922980029
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2188490784
Short name T272
Test name
Test status
Simulation time 48894809637 ps
CPU time 193.22 seconds
Started Apr 18 02:06:55 PM PDT 24
Finished Apr 18 02:10:08 PM PDT 24
Peak memory 236912 kb
Host smart-787c7440-3995-42a4-8a88-d06f4748329a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188490784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2188490784
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2475370118
Short name T526
Test name
Test status
Simulation time 37984142392 ps
CPU time 409.21 seconds
Started Apr 18 12:33:37 PM PDT 24
Finished Apr 18 12:40:27 PM PDT 24
Peak memory 217200 kb
Host smart-d68a155e-142a-45c2-86ee-197a382f10c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475370118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2475370118
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2673848154
Short name T559
Test name
Test status
Simulation time 3212232349 ps
CPU time 29.38 seconds
Started Apr 18 12:33:34 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 214880 kb
Host smart-68ee29cd-2882-4dc2-a72c-31b2e6df8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673848154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2673848154
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2676189278
Short name T310
Test name
Test status
Simulation time 1737568198 ps
CPU time 19.44 seconds
Started Apr 18 02:06:55 PM PDT 24
Finished Apr 18 02:07:15 PM PDT 24
Peak memory 214740 kb
Host smart-5e0f0d36-4616-4572-b2d8-77a4c8a001b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676189278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2676189278
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1076553642
Short name T381
Test name
Test status
Simulation time 2202851086 ps
CPU time 10.46 seconds
Started Apr 18 02:06:53 PM PDT 24
Finished Apr 18 02:07:04 PM PDT 24
Peak memory 212852 kb
Host smart-4c8edbdf-49eb-45c2-8af5-47ce3b7eb7cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076553642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1076553642
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2672997577
Short name T119
Test name
Test status
Simulation time 1770961626 ps
CPU time 20.96 seconds
Started Apr 18 12:33:44 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 211580 kb
Host smart-6edf089a-fa66-4c12-925e-fefc0fcf3056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672997577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2672997577
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2035102489
Short name T218
Test name
Test status
Simulation time 77998786721 ps
CPU time 51.57 seconds
Started Apr 18 12:33:41 PM PDT 24
Finished Apr 18 12:34:34 PM PDT 24
Peak memory 216616 kb
Host smart-05e6e842-b96c-4034-8f3e-715000f86570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035102489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2035102489
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3760204301
Short name T350
Test name
Test status
Simulation time 16763595463 ps
CPU time 78.18 seconds
Started Apr 18 02:06:54 PM PDT 24
Finished Apr 18 02:08:13 PM PDT 24
Peak memory 218048 kb
Host smart-d3979fdc-3372-4e2d-922c-2cb36cfd2a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760204301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3760204301
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3612767822
Short name T355
Test name
Test status
Simulation time 54132795037 ps
CPU time 140.51 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 221036 kb
Host smart-fd0893fc-5c34-40cf-a483-d53309b49318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612767822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3612767822
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.887026278
Short name T463
Test name
Test status
Simulation time 81187826204 ps
CPU time 138.6 seconds
Started Apr 18 02:06:53 PM PDT 24
Finished Apr 18 02:09:12 PM PDT 24
Peak memory 221980 kb
Host smart-cf27d84a-6366-4c1f-9794-f44caaed88e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887026278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.887026278
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1323256003
Short name T334
Test name
Test status
Simulation time 346333698 ps
CPU time 8.45 seconds
Started Apr 18 02:06:53 PM PDT 24
Finished Apr 18 02:07:02 PM PDT 24
Peak memory 211388 kb
Host smart-41619917-f95d-40c0-b4ff-cb9453ef6788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323256003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1323256003
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2986977385
Short name T512
Test name
Test status
Simulation time 3814836545 ps
CPU time 31.04 seconds
Started Apr 18 12:33:45 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 211464 kb
Host smart-8b60584a-80f7-4b98-aa89-3e9852ef36db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986977385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2986977385
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1775869403
Short name T630
Test name
Test status
Simulation time 11211994112 ps
CPU time 205.61 seconds
Started Apr 18 12:33:36 PM PDT 24
Finished Apr 18 12:37:03 PM PDT 24
Peak memory 239828 kb
Host smart-44af4747-4e90-4a54-9f7f-715f19662e55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775869403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1775869403
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4261841102
Short name T404
Test name
Test status
Simulation time 4269272198 ps
CPU time 141.8 seconds
Started Apr 18 02:06:53 PM PDT 24
Finished Apr 18 02:09:16 PM PDT 24
Peak memory 228932 kb
Host smart-0908aecb-8eb7-44ec-a409-9f21b2eb0a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261841102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4261841102
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1567589553
Short name T5
Test name
Test status
Simulation time 2141461726 ps
CPU time 34.42 seconds
Started Apr 18 02:06:54 PM PDT 24
Finished Apr 18 02:07:29 PM PDT 24
Peak memory 214772 kb
Host smart-cf56a9ba-111c-44fc-8ebc-3fe0dcc645f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567589553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1567589553
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.709686799
Short name T498
Test name
Test status
Simulation time 16069493164 ps
CPU time 67.9 seconds
Started Apr 18 12:33:41 PM PDT 24
Finished Apr 18 12:34:49 PM PDT 24
Peak memory 215040 kb
Host smart-279b81a9-539f-48d6-84ca-81d37f12100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709686799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.709686799
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1734876860
Short name T109
Test name
Test status
Simulation time 751506591 ps
CPU time 15.66 seconds
Started Apr 18 12:33:44 PM PDT 24
Finished Apr 18 12:34:00 PM PDT 24
Peak memory 212312 kb
Host smart-7c93f51b-320f-45a1-b74c-255368c6806b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734876860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1734876860
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2731756501
Short name T236
Test name
Test status
Simulation time 1451366273 ps
CPU time 10.71 seconds
Started Apr 18 02:06:54 PM PDT 24
Finished Apr 18 02:07:05 PM PDT 24
Peak memory 211716 kb
Host smart-fda05d2b-137f-43bd-9c5c-4f0a1800ce83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731756501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2731756501
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.263912327
Short name T300
Test name
Test status
Simulation time 4512997986 ps
CPU time 46.41 seconds
Started Apr 18 02:06:52 PM PDT 24
Finished Apr 18 02:07:39 PM PDT 24
Peak memory 215364 kb
Host smart-b9ddccc6-3973-45ea-bc15-80b2b8d61c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263912327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.263912327
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3412165898
Short name T409
Test name
Test status
Simulation time 5806717257 ps
CPU time 49.32 seconds
Started Apr 18 12:33:43 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 214072 kb
Host smart-7d31e05b-942f-4fbc-aaae-315a7b8deb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412165898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3412165898
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1097738854
Short name T144
Test name
Test status
Simulation time 8859270371 ps
CPU time 77.59 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 217664 kb
Host smart-0598a4d2-e06c-4e2e-bfde-620a801f503b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097738854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1097738854
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1785044890
Short name T400
Test name
Test status
Simulation time 5638420658 ps
CPU time 52.79 seconds
Started Apr 18 02:06:54 PM PDT 24
Finished Apr 18 02:07:47 PM PDT 24
Peak memory 217252 kb
Host smart-727b44d1-8406-4d62-b5ff-277a8f7e3ea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785044890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1785044890
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2719463606
Short name T599
Test name
Test status
Simulation time 198828745332 ps
CPU time 3563.87 seconds
Started Apr 18 12:33:43 PM PDT 24
Finished Apr 18 01:33:08 PM PDT 24
Peak memory 248568 kb
Host smart-5812850b-c2c5-46d2-9921-e82d026bb4b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719463606 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2719463606
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3300295540
Short name T17
Test name
Test status
Simulation time 78087035057 ps
CPU time 651.76 seconds
Started Apr 18 02:06:53 PM PDT 24
Finished Apr 18 02:17:46 PM PDT 24
Peak memory 235928 kb
Host smart-26f2a4ae-dd40-4460-a8c4-8226af7e8748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300295540 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3300295540
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2154565792
Short name T177
Test name
Test status
Simulation time 21594527182 ps
CPU time 33.9 seconds
Started Apr 18 12:33:51 PM PDT 24
Finished Apr 18 12:34:28 PM PDT 24
Peak memory 211432 kb
Host smart-7e62a2aa-0640-4238-9c55-7446715c19e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154565792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2154565792
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2873348584
Short name T346
Test name
Test status
Simulation time 12407343383 ps
CPU time 27.1 seconds
Started Apr 18 02:06:59 PM PDT 24
Finished Apr 18 02:07:26 PM PDT 24
Peak memory 212432 kb
Host smart-4bea1bd0-4960-49c7-877f-39d640e4f701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873348584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2873348584
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3229098638
Short name T370
Test name
Test status
Simulation time 18142957332 ps
CPU time 276.88 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:38:16 PM PDT 24
Peak memory 227876 kb
Host smart-a6300ec1-8858-4ce2-a223-2ec87f0e5b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229098638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3229098638
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.908393204
Short name T410
Test name
Test status
Simulation time 206995292286 ps
CPU time 581.13 seconds
Started Apr 18 02:07:00 PM PDT 24
Finished Apr 18 02:16:42 PM PDT 24
Peak memory 217108 kb
Host smart-11607458-7733-46e1-a349-ffbc1c839155
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908393204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.908393204
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1394894304
Short name T339
Test name
Test status
Simulation time 28983922452 ps
CPU time 64.46 seconds
Started Apr 18 02:07:00 PM PDT 24
Finished Apr 18 02:08:05 PM PDT 24
Peak memory 215176 kb
Host smart-b45cb9ba-4b39-42dc-824a-c85831a014b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394894304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1394894304
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.847699553
Short name T230
Test name
Test status
Simulation time 335846703 ps
CPU time 19.26 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:33:59 PM PDT 24
Peak memory 214616 kb
Host smart-68abcce3-6c0d-48f4-94b5-f3bf25d69a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847699553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.847699553
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2354347920
Short name T629
Test name
Test status
Simulation time 1574911791 ps
CPU time 19.8 seconds
Started Apr 18 12:33:43 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 212160 kb
Host smart-8c5f8727-fb34-4241-99c2-9014a246f0af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354347920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2354347920
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3727209872
Short name T390
Test name
Test status
Simulation time 2293493395 ps
CPU time 13.87 seconds
Started Apr 18 02:07:01 PM PDT 24
Finished Apr 18 02:07:15 PM PDT 24
Peak memory 211672 kb
Host smart-3556ad2a-12a4-42a8-bae9-2e9f1e1e4979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727209872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3727209872
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1106646125
Short name T524
Test name
Test status
Simulation time 23727915756 ps
CPU time 43.74 seconds
Started Apr 18 12:33:37 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 217700 kb
Host smart-7ce22924-e2df-4ca8-be6e-48a8a0ca9c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106646125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1106646125
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3144943044
Short name T190
Test name
Test status
Simulation time 9703673643 ps
CPU time 37.06 seconds
Started Apr 18 02:07:00 PM PDT 24
Finished Apr 18 02:07:37 PM PDT 24
Peak memory 215628 kb
Host smart-5e719b71-116e-40f4-95f9-8ffac46cd8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144943044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3144943044
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1018134305
Short name T530
Test name
Test status
Simulation time 3978331934 ps
CPU time 32.22 seconds
Started Apr 18 02:07:01 PM PDT 24
Finished Apr 18 02:07:34 PM PDT 24
Peak memory 212308 kb
Host smart-24599578-6773-496c-bcf9-a80816e1d4b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018134305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1018134305
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3121543592
Short name T229
Test name
Test status
Simulation time 25663012861 ps
CPU time 77.89 seconds
Started Apr 18 12:33:38 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 219436 kb
Host smart-fbe50caa-6dac-452e-912e-077dd03107e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121543592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3121543592
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2158850250
Short name T70
Test name
Test status
Simulation time 3454347930 ps
CPU time 28.5 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 211904 kb
Host smart-4e21ffce-bd00-49bd-a270-dd56f719c1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158850250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2158850250
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.951613999
Short name T441
Test name
Test status
Simulation time 2149199356 ps
CPU time 22.19 seconds
Started Apr 18 02:07:08 PM PDT 24
Finished Apr 18 02:07:31 PM PDT 24
Peak memory 211528 kb
Host smart-b71dc8dd-6852-4a36-8f09-04ce308cf7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951613999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.951613999
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.55005919
Short name T245
Test name
Test status
Simulation time 9682914544 ps
CPU time 152.29 seconds
Started Apr 18 02:06:59 PM PDT 24
Finished Apr 18 02:09:32 PM PDT 24
Peak memory 217536 kb
Host smart-6a3a4a6f-5fb7-474e-9474-143fa32db1ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55005919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_co
rrupt_sig_fatal_chk.55005919
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.982281048
Short name T312
Test name
Test status
Simulation time 187750188755 ps
CPU time 457.83 seconds
Started Apr 18 12:33:46 PM PDT 24
Finished Apr 18 12:41:24 PM PDT 24
Peak memory 238268 kb
Host smart-a45f4f8b-e908-4ca7-8ad6-d2287e78d456
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982281048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.982281048
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2513731787
Short name T531
Test name
Test status
Simulation time 14597714966 ps
CPU time 35.5 seconds
Started Apr 18 02:07:10 PM PDT 24
Finished Apr 18 02:07:46 PM PDT 24
Peak memory 215196 kb
Host smart-a5ee3ebb-b128-450b-9cee-13ea4a41229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513731787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2513731787
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.752838459
Short name T625
Test name
Test status
Simulation time 11282601636 ps
CPU time 32.55 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:21 PM PDT 24
Peak memory 215088 kb
Host smart-dc2e224d-784e-4234-9f06-289a1a191a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752838459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.752838459
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1301467470
Short name T330
Test name
Test status
Simulation time 179770251 ps
CPU time 10.48 seconds
Started Apr 18 12:33:45 PM PDT 24
Finished Apr 18 12:33:56 PM PDT 24
Peak memory 212240 kb
Host smart-55101c4a-5c91-4311-bae3-03eaaa3d7dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301467470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1301467470
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2607041321
Short name T382
Test name
Test status
Simulation time 3921575665 ps
CPU time 33.14 seconds
Started Apr 18 02:07:01 PM PDT 24
Finished Apr 18 02:07:35 PM PDT 24
Peak memory 211400 kb
Host smart-64114c13-64fb-4ae4-afad-7df0bca3eec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607041321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2607041321
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1011662088
Short name T261
Test name
Test status
Simulation time 1384173506 ps
CPU time 20.04 seconds
Started Apr 18 02:07:01 PM PDT 24
Finished Apr 18 02:07:21 PM PDT 24
Peak memory 217176 kb
Host smart-1f0e4a74-7582-484c-9d09-bc7744f9d182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011662088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1011662088
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1012955473
Short name T661
Test name
Test status
Simulation time 9564226302 ps
CPU time 24.66 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 218068 kb
Host smart-12ee27d4-0ae5-4d3e-9b20-984bfe820133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012955473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1012955473
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1601145143
Short name T325
Test name
Test status
Simulation time 16255541696 ps
CPU time 82.45 seconds
Started Apr 18 12:33:46 PM PDT 24
Finished Apr 18 12:35:09 PM PDT 24
Peak memory 219244 kb
Host smart-d84b90aa-87ae-4469-b3be-2d9bacff21d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601145143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1601145143
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3497618721
Short name T87
Test name
Test status
Simulation time 372580516 ps
CPU time 23.78 seconds
Started Apr 18 02:07:00 PM PDT 24
Finished Apr 18 02:07:24 PM PDT 24
Peak memory 219260 kb
Host smart-ff8fa51a-7a93-4146-9c9b-7decd8d4a4d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497618721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3497618721
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3720948961
Short name T57
Test name
Test status
Simulation time 89248137422 ps
CPU time 5489.5 seconds
Started Apr 18 12:33:49 PM PDT 24
Finished Apr 18 02:05:22 PM PDT 24
Peak memory 220948 kb
Host smart-2dc0de8c-a7d7-4368-a258-a9eab8855ff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720948961 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3720948961
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2140441940
Short name T150
Test name
Test status
Simulation time 15767805795 ps
CPU time 23.47 seconds
Started Apr 18 02:07:08 PM PDT 24
Finished Apr 18 02:07:32 PM PDT 24
Peak memory 212428 kb
Host smart-4238cb39-a1b6-46e8-a0f0-4e9251c85c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140441940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2140441940
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2622883262
Short name T489
Test name
Test status
Simulation time 689496652 ps
CPU time 8.4 seconds
Started Apr 18 12:33:41 PM PDT 24
Finished Apr 18 12:33:50 PM PDT 24
Peak memory 211280 kb
Host smart-26ed6344-3cc8-4bfd-a090-3e089d224840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622883262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2622883262
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3887903962
Short name T456
Test name
Test status
Simulation time 35496117929 ps
CPU time 420.83 seconds
Started Apr 18 02:07:08 PM PDT 24
Finished Apr 18 02:14:10 PM PDT 24
Peak memory 237904 kb
Host smart-8d7a7fd6-3b44-4071-97af-e4718fcf2cb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887903962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3887903962
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.396999940
Short name T473
Test name
Test status
Simulation time 34065107179 ps
CPU time 405.08 seconds
Started Apr 18 12:33:46 PM PDT 24
Finished Apr 18 12:40:31 PM PDT 24
Peak memory 237816 kb
Host smart-becec993-a54b-4972-aee6-e6fcb0fcc961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396999940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.396999940
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1064927731
Short name T210
Test name
Test status
Simulation time 675018979 ps
CPU time 19.37 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 12:34:12 PM PDT 24
Peak memory 214608 kb
Host smart-8c0ac21e-5754-4de9-8ad5-98873f27caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064927731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1064927731
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1398551980
Short name T356
Test name
Test status
Simulation time 1832827955 ps
CPU time 18.78 seconds
Started Apr 18 02:07:08 PM PDT 24
Finished Apr 18 02:07:28 PM PDT 24
Peak memory 214748 kb
Host smart-f614ee63-947a-4e20-b52e-c4b3522c2ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398551980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1398551980
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1980761426
Short name T303
Test name
Test status
Simulation time 5182808936 ps
CPU time 25.89 seconds
Started Apr 18 12:33:45 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 211512 kb
Host smart-7284645a-5c66-4c4f-9f5f-897efdc5ff00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980761426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1980761426
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2297600085
Short name T415
Test name
Test status
Simulation time 184830719 ps
CPU time 10.71 seconds
Started Apr 18 02:07:09 PM PDT 24
Finished Apr 18 02:07:20 PM PDT 24
Peak memory 212256 kb
Host smart-bf3b35b8-bcdb-4006-a488-d7efa45c3e07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297600085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2297600085
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1684512932
Short name T102
Test name
Test status
Simulation time 46164871224 ps
CPU time 67.21 seconds
Started Apr 18 02:07:08 PM PDT 24
Finished Apr 18 02:08:16 PM PDT 24
Peak memory 218508 kb
Host smart-f6b710b5-3692-4389-aba7-abf18067889d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684512932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1684512932
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3852180551
Short name T546
Test name
Test status
Simulation time 9214726397 ps
CPU time 49.99 seconds
Started Apr 18 12:33:45 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 218340 kb
Host smart-b8d42c45-4aa9-4c87-9aab-f8de8920cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852180551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3852180551
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3188301155
Short name T83
Test name
Test status
Simulation time 26691203412 ps
CPU time 71.19 seconds
Started Apr 18 12:33:48 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 218904 kb
Host smart-43f8044a-43bc-4af2-8d88-e2ac259172ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188301155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3188301155
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4110048867
Short name T313
Test name
Test status
Simulation time 3061640359 ps
CPU time 34.14 seconds
Started Apr 18 02:07:09 PM PDT 24
Finished Apr 18 02:07:44 PM PDT 24
Peak memory 213692 kb
Host smart-08be9316-4e9d-473c-9b5c-31842df1c743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110048867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4110048867
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2254687951
Short name T408
Test name
Test status
Simulation time 1243090289 ps
CPU time 16.23 seconds
Started Apr 18 12:33:53 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 211808 kb
Host smart-a11f2ea1-4609-4f11-a416-860aab9e6157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254687951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2254687951
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2944294551
Short name T198
Test name
Test status
Simulation time 916728475 ps
CPU time 8.45 seconds
Started Apr 18 02:07:16 PM PDT 24
Finished Apr 18 02:07:25 PM PDT 24
Peak memory 211424 kb
Host smart-17ce9cc6-ca49-46f1-b976-fcd9eb71bda7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944294551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2944294551
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1350245143
Short name T439
Test name
Test status
Simulation time 4252295364 ps
CPU time 303.95 seconds
Started Apr 18 02:07:16 PM PDT 24
Finished Apr 18 02:12:21 PM PDT 24
Peak memory 238956 kb
Host smart-bf0a8937-889e-422a-871d-1cb9bf6618da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350245143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1350245143
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.709680478
Short name T508
Test name
Test status
Simulation time 4576961752 ps
CPU time 313.51 seconds
Started Apr 18 12:33:46 PM PDT 24
Finished Apr 18 12:39:00 PM PDT 24
Peak memory 239384 kb
Host smart-966e32f4-6a82-4029-aeef-0c6019f1116b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709680478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.709680478
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2395982983
Short name T561
Test name
Test status
Simulation time 14043839919 ps
CPU time 62.27 seconds
Started Apr 18 02:07:16 PM PDT 24
Finished Apr 18 02:08:19 PM PDT 24
Peak memory 215064 kb
Host smart-1492afe1-38f8-461e-9209-2b7cfe2c5fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395982983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2395982983
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2667011053
Short name T548
Test name
Test status
Simulation time 6330792956 ps
CPU time 53.96 seconds
Started Apr 18 12:33:49 PM PDT 24
Finished Apr 18 12:34:46 PM PDT 24
Peak memory 215764 kb
Host smart-be7091ef-3c8b-47ef-a3c5-7b92d5cf4757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667011053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2667011053
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1706341853
Short name T160
Test name
Test status
Simulation time 672184373 ps
CPU time 12.39 seconds
Started Apr 18 02:07:18 PM PDT 24
Finished Apr 18 02:07:31 PM PDT 24
Peak memory 211248 kb
Host smart-10720f5e-df0f-48e3-bc63-abe4bd246d21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706341853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1706341853
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.322452323
Short name T14
Test name
Test status
Simulation time 10779008343 ps
CPU time 26.48 seconds
Started Apr 18 12:33:46 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 211800 kb
Host smart-6a14d9e7-a14e-4586-8b75-63ca2e4afbd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=322452323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.322452323
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4157259326
Short name T631
Test name
Test status
Simulation time 8060764142 ps
CPU time 72.64 seconds
Started Apr 18 02:07:10 PM PDT 24
Finished Apr 18 02:08:23 PM PDT 24
Peak memory 217888 kb
Host smart-8f450ff8-ad33-488b-b80f-2caab5ccaae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157259326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4157259326
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4215080400
Short name T616
Test name
Test status
Simulation time 3249879494 ps
CPU time 42.81 seconds
Started Apr 18 12:33:43 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 217148 kb
Host smart-f8295a42-286a-4f40-9c51-fa1030c43a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215080400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4215080400
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.155364007
Short name T366
Test name
Test status
Simulation time 5737575230 ps
CPU time 67.52 seconds
Started Apr 18 02:07:09 PM PDT 24
Finished Apr 18 02:08:17 PM PDT 24
Peak memory 219144 kb
Host smart-b606f01b-a766-4a1b-bf30-c2f301399c0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155364007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.155364007
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4285073725
Short name T474
Test name
Test status
Simulation time 1052839305 ps
CPU time 65.31 seconds
Started Apr 18 12:33:42 PM PDT 24
Finished Apr 18 12:34:48 PM PDT 24
Peak memory 219196 kb
Host smart-dcc8f559-c150-4623-913f-5eb0289b16d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285073725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4285073725
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1624065424
Short name T197
Test name
Test status
Simulation time 3771235544 ps
CPU time 14.41 seconds
Started Apr 18 02:07:31 PM PDT 24
Finished Apr 18 02:07:45 PM PDT 24
Peak memory 211516 kb
Host smart-b39453e0-1c31-42a7-b445-c8005eabbe8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624065424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1624065424
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1635150617
Short name T424
Test name
Test status
Simulation time 8210773862 ps
CPU time 20.55 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 212248 kb
Host smart-9793ac0e-f40e-490c-930f-87f5618e38d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635150617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1635150617
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3781218738
Short name T422
Test name
Test status
Simulation time 53850992139 ps
CPU time 483.29 seconds
Started Apr 18 02:07:15 PM PDT 24
Finished Apr 18 02:15:18 PM PDT 24
Peak memory 219708 kb
Host smart-c64500e0-5632-481f-a721-bf3f85b95b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781218738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3781218738
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1713384895
Short name T22
Test name
Test status
Simulation time 1377688354 ps
CPU time 19.42 seconds
Started Apr 18 02:07:23 PM PDT 24
Finished Apr 18 02:07:43 PM PDT 24
Peak memory 214784 kb
Host smart-b342b640-8f51-47dd-a66f-1b00d2bae171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713384895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1713384895
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.888157175
Short name T246
Test name
Test status
Simulation time 41487782592 ps
CPU time 69.52 seconds
Started Apr 18 12:33:58 PM PDT 24
Finished Apr 18 12:35:10 PM PDT 24
Peak memory 215024 kb
Host smart-43d17572-abd2-49de-a04b-229473c797c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888157175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.888157175
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1957087060
Short name T142
Test name
Test status
Simulation time 2269754893 ps
CPU time 15.95 seconds
Started Apr 18 02:07:18 PM PDT 24
Finished Apr 18 02:07:35 PM PDT 24
Peak memory 212840 kb
Host smart-ce4936cc-cc9a-4e2d-bbb9-e0e23e7d457a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957087060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1957087060
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.690615835
Short name T327
Test name
Test status
Simulation time 9054642201 ps
CPU time 15.96 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 212864 kb
Host smart-935da6db-ca0a-44ef-93b6-2bf81f575936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690615835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.690615835
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.231409761
Short name T517
Test name
Test status
Simulation time 2573520517 ps
CPU time 35.72 seconds
Started Apr 18 02:07:18 PM PDT 24
Finished Apr 18 02:07:54 PM PDT 24
Peak memory 217072 kb
Host smart-d7bfdbdd-da60-4127-8f8f-4d6c0b1f6bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231409761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.231409761
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.259857069
Short name T419
Test name
Test status
Simulation time 10411603703 ps
CPU time 89.9 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 12:35:24 PM PDT 24
Peak memory 215368 kb
Host smart-52724b84-79be-4a12-aeab-5c846ebb1d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259857069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.259857069
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1030042362
Short name T211
Test name
Test status
Simulation time 1921790521 ps
CPU time 31.32 seconds
Started Apr 18 02:07:16 PM PDT 24
Finished Apr 18 02:07:48 PM PDT 24
Peak memory 216612 kb
Host smart-12996532-9035-448a-a700-5571daf109d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030042362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1030042362
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.521663778
Short name T492
Test name
Test status
Simulation time 74027785906 ps
CPU time 198.68 seconds
Started Apr 18 12:33:51 PM PDT 24
Finished Apr 18 12:37:13 PM PDT 24
Peak memory 220016 kb
Host smart-ac49cd95-b7cc-46ce-b106-91c49ef27a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521663778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.521663778
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2138879399
Short name T72
Test name
Test status
Simulation time 751585118 ps
CPU time 8.35 seconds
Started Apr 18 02:07:25 PM PDT 24
Finished Apr 18 02:07:34 PM PDT 24
Peak memory 211400 kb
Host smart-9db4a769-6f8b-410a-8e57-1f548bd355b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138879399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2138879399
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3304433395
Short name T477
Test name
Test status
Simulation time 20215517421 ps
CPU time 34.63 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 211496 kb
Host smart-730965c1-3011-49f1-b8f6-e2fca6c3d0c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304433395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3304433395
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3480314122
Short name T597
Test name
Test status
Simulation time 94220532788 ps
CPU time 917.57 seconds
Started Apr 18 02:07:24 PM PDT 24
Finished Apr 18 02:22:43 PM PDT 24
Peak memory 234476 kb
Host smart-07e2958c-54d0-4174-8109-3edc9de72831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480314122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3480314122
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.447965353
Short name T442
Test name
Test status
Simulation time 18017960473 ps
CPU time 384.71 seconds
Started Apr 18 12:33:46 PM PDT 24
Finished Apr 18 12:40:12 PM PDT 24
Peak memory 225456 kb
Host smart-21941bdb-63ab-4da6-bcfc-44c535c8dc24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447965353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.447965353
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2994266231
Short name T106
Test name
Test status
Simulation time 1224097688 ps
CPU time 18.98 seconds
Started Apr 18 02:07:24 PM PDT 24
Finished Apr 18 02:07:44 PM PDT 24
Peak memory 215468 kb
Host smart-bd2dd237-06b4-4ce4-9174-cfa980d9bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994266231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2994266231
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4185103952
Short name T204
Test name
Test status
Simulation time 1008173506 ps
CPU time 22.44 seconds
Started Apr 18 12:33:52 PM PDT 24
Finished Apr 18 12:34:18 PM PDT 24
Peak memory 214704 kb
Host smart-7c5b3270-8c7a-45b9-8039-1f47f9fe0ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185103952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4185103952
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4092952614
Short name T299
Test name
Test status
Simulation time 3305922715 ps
CPU time 15.68 seconds
Started Apr 18 02:07:24 PM PDT 24
Finished Apr 18 02:07:40 PM PDT 24
Peak memory 211788 kb
Host smart-d65d9f4b-02be-40fa-9487-2281667c5433
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092952614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4092952614
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.991049408
Short name T547
Test name
Test status
Simulation time 17102392063 ps
CPU time 36.51 seconds
Started Apr 18 12:33:52 PM PDT 24
Finished Apr 18 12:34:31 PM PDT 24
Peak memory 212624 kb
Host smart-33397ff1-6083-4a1e-9baf-6547e048f4a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991049408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.991049408
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2453172519
Short name T8
Test name
Test status
Simulation time 10619298399 ps
CPU time 50.41 seconds
Started Apr 18 12:33:52 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 217788 kb
Host smart-983a17cc-f52c-497e-8a9f-4f51f365c858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453172519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2453172519
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3706867567
Short name T421
Test name
Test status
Simulation time 33829739020 ps
CPU time 65.57 seconds
Started Apr 18 02:07:24 PM PDT 24
Finished Apr 18 02:08:30 PM PDT 24
Peak memory 217928 kb
Host smart-0e43a9ec-144c-4cf0-9df5-886ae0b3c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706867567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3706867567
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1566357191
Short name T624
Test name
Test status
Simulation time 23857183077 ps
CPU time 89.44 seconds
Started Apr 18 02:07:26 PM PDT 24
Finished Apr 18 02:08:56 PM PDT 24
Peak memory 219928 kb
Host smart-9ab40007-33c3-4409-a3a3-fe1a13ffde11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566357191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1566357191
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2995308287
Short name T602
Test name
Test status
Simulation time 69223149200 ps
CPU time 109.78 seconds
Started Apr 18 12:33:48 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 219340 kb
Host smart-2f88bf04-dee2-4b69-992b-119e29c39da1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995308287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2995308287
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1501405077
Short name T59
Test name
Test status
Simulation time 27015396084 ps
CPU time 6309.01 seconds
Started Apr 18 02:07:25 PM PDT 24
Finished Apr 18 03:52:35 PM PDT 24
Peak memory 235968 kb
Host smart-7110c4e4-16ca-42f4-b9de-89679fb72e73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501405077 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1501405077
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2707884494
Short name T407
Test name
Test status
Simulation time 24451535534 ps
CPU time 980.78 seconds
Started Apr 18 12:33:48 PM PDT 24
Finished Apr 18 12:50:11 PM PDT 24
Peak memory 235868 kb
Host smart-8d4e0f8b-d270-43e2-987f-d923eab5ce1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707884494 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2707884494
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2236266442
Short name T544
Test name
Test status
Simulation time 4485820487 ps
CPU time 11.97 seconds
Started Apr 18 02:07:25 PM PDT 24
Finished Apr 18 02:07:37 PM PDT 24
Peak memory 211536 kb
Host smart-8f8cf63b-4e15-4264-bc69-e1bc088e7033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236266442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2236266442
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3825083672
Short name T248
Test name
Test status
Simulation time 1315445853 ps
CPU time 10.51 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 12:34:03 PM PDT 24
Peak memory 211200 kb
Host smart-9b7b9aa9-e0c8-47fc-819d-f44dbf0c2b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825083672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3825083672
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2638273732
Short name T320
Test name
Test status
Simulation time 35344835628 ps
CPU time 332.37 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 12:39:26 PM PDT 24
Peak memory 239872 kb
Host smart-5018f9b2-3628-4b0a-b959-cfad30266c97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638273732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2638273732
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3639025616
Short name T26
Test name
Test status
Simulation time 35372982301 ps
CPU time 383.47 seconds
Started Apr 18 02:07:31 PM PDT 24
Finished Apr 18 02:13:55 PM PDT 24
Peak memory 229024 kb
Host smart-c1bb2b3e-4008-4507-9f4d-aae5fcdb0f81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639025616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3639025616
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.331112396
Short name T159
Test name
Test status
Simulation time 8893975198 ps
CPU time 69.14 seconds
Started Apr 18 12:33:48 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 215000 kb
Host smart-4cb07baf-63b5-4422-a99b-0bd3497555fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331112396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.331112396
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3466542807
Short name T258
Test name
Test status
Simulation time 2542773301 ps
CPU time 36.2 seconds
Started Apr 18 02:07:25 PM PDT 24
Finished Apr 18 02:08:02 PM PDT 24
Peak memory 214804 kb
Host smart-7b56a876-721b-4a58-b3d0-a6cda8585d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466542807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3466542807
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2955576156
Short name T433
Test name
Test status
Simulation time 7029600147 ps
CPU time 13.47 seconds
Started Apr 18 02:07:24 PM PDT 24
Finished Apr 18 02:07:38 PM PDT 24
Peak memory 211840 kb
Host smart-9f00c040-2b89-429a-80f4-b20d7b28e941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955576156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2955576156
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.741761885
Short name T660
Test name
Test status
Simulation time 3555912581 ps
CPU time 31.22 seconds
Started Apr 18 12:33:48 PM PDT 24
Finished Apr 18 12:34:21 PM PDT 24
Peak memory 211236 kb
Host smart-be323342-6b20-48cd-81d5-8683e890154d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741761885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.741761885
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1791854237
Short name T541
Test name
Test status
Simulation time 9858277153 ps
CPU time 41.76 seconds
Started Apr 18 02:07:26 PM PDT 24
Finished Apr 18 02:08:08 PM PDT 24
Peak memory 218056 kb
Host smart-e1462ba8-c903-4b57-bb8e-3686254e4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791854237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1791854237
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3964658632
Short name T649
Test name
Test status
Simulation time 359087545 ps
CPU time 19.49 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 215736 kb
Host smart-b141aeae-1929-40b2-86f8-370ff8b2d8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964658632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3964658632
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.185453121
Short name T165
Test name
Test status
Simulation time 48745010037 ps
CPU time 113.77 seconds
Started Apr 18 12:33:49 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 219676 kb
Host smart-8490c672-fe00-4de8-a148-1a05fdedd2c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185453121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.185453121
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.787209514
Short name T13
Test name
Test status
Simulation time 31311322429 ps
CPU time 56.27 seconds
Started Apr 18 02:07:31 PM PDT 24
Finished Apr 18 02:08:27 PM PDT 24
Peak memory 216040 kb
Host smart-f11310bb-0ee7-457f-9d64-b6e2bc19e6fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787209514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.787209514
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2302571011
Short name T188
Test name
Test status
Simulation time 19109433674 ps
CPU time 33.78 seconds
Started Apr 18 12:33:49 PM PDT 24
Finished Apr 18 12:34:25 PM PDT 24
Peak memory 212228 kb
Host smart-b304ff22-6b62-49e9-93b3-f1bea233beb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302571011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2302571011
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.312547599
Short name T562
Test name
Test status
Simulation time 1535908368 ps
CPU time 18.44 seconds
Started Apr 18 02:07:33 PM PDT 24
Finished Apr 18 02:07:52 PM PDT 24
Peak memory 211932 kb
Host smart-a0fd305a-6992-4b73-8cd8-a48492950b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312547599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.312547599
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3061626872
Short name T646
Test name
Test status
Simulation time 46932053691 ps
CPU time 195.84 seconds
Started Apr 18 02:07:33 PM PDT 24
Finished Apr 18 02:10:49 PM PDT 24
Peak memory 227732 kb
Host smart-6eb0dd0b-5f3c-4dc6-a297-1377f615c02a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061626872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3061626872
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.69026668
Short name T553
Test name
Test status
Simulation time 179998422101 ps
CPU time 569 seconds
Started Apr 18 12:33:53 PM PDT 24
Finished Apr 18 12:43:25 PM PDT 24
Peak memory 240412 kb
Host smart-4c09ec11-3656-4f9a-a799-d7b8a68694d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69026668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_co
rrupt_sig_fatal_chk.69026668
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3462878206
Short name T349
Test name
Test status
Simulation time 92521180043 ps
CPU time 74.86 seconds
Started Apr 18 02:07:32 PM PDT 24
Finished Apr 18 02:08:48 PM PDT 24
Peak memory 215128 kb
Host smart-41815fb1-69d2-4c4d-ae84-471ab5bfd056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462878206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3462878206
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3950557527
Short name T623
Test name
Test status
Simulation time 17109410076 ps
CPU time 44.9 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 215136 kb
Host smart-ea8282f2-3579-45f8-b8fe-8b361d8a66e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950557527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3950557527
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2433190093
Short name T62
Test name
Test status
Simulation time 6162718396 ps
CPU time 18.81 seconds
Started Apr 18 12:33:47 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 212956 kb
Host smart-5fbeecc1-bd7a-4374-ab92-de00c6083955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433190093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2433190093
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.789366165
Short name T61
Test name
Test status
Simulation time 8812278287 ps
CPU time 18.86 seconds
Started Apr 18 02:07:31 PM PDT 24
Finished Apr 18 02:07:50 PM PDT 24
Peak memory 212988 kb
Host smart-86d5a60d-8d68-4354-ae57-c64ff0de0874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789366165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.789366165
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1088453785
Short name T673
Test name
Test status
Simulation time 4462997141 ps
CPU time 43.55 seconds
Started Apr 18 12:33:51 PM PDT 24
Finished Apr 18 12:34:37 PM PDT 24
Peak memory 216764 kb
Host smart-a7cda602-52a4-40c0-8dcb-0a001255f225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088453785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1088453785
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2806870940
Short name T391
Test name
Test status
Simulation time 710743520 ps
CPU time 19.37 seconds
Started Apr 18 02:07:25 PM PDT 24
Finished Apr 18 02:07:45 PM PDT 24
Peak memory 216816 kb
Host smart-11e692fd-7ec9-4d1b-a742-055c187fa443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806870940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2806870940
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1798369090
Short name T555
Test name
Test status
Simulation time 21831161470 ps
CPU time 121.2 seconds
Started Apr 18 02:07:32 PM PDT 24
Finished Apr 18 02:09:34 PM PDT 24
Peak memory 221764 kb
Host smart-60602ffa-4dcc-448d-b2c6-6feec15274a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798369090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1798369090
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1951153482
Short name T493
Test name
Test status
Simulation time 68367335336 ps
CPU time 73.77 seconds
Started Apr 18 12:33:48 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 216016 kb
Host smart-1a7f1e8f-2ae9-481e-b122-76d292fe4f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951153482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1951153482
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2352452585
Short name T464
Test name
Test status
Simulation time 35263384259 ps
CPU time 1362.18 seconds
Started Apr 18 02:07:30 PM PDT 24
Finished Apr 18 02:30:13 PM PDT 24
Peak memory 235940 kb
Host smart-533499d7-2355-41b8-a131-919a3a9fcacc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352452585 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2352452585
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1677570883
Short name T611
Test name
Test status
Simulation time 3151533454 ps
CPU time 26.21 seconds
Started Apr 18 02:04:01 PM PDT 24
Finished Apr 18 02:04:28 PM PDT 24
Peak memory 212016 kb
Host smart-8c2a975f-6c25-4e1b-86de-8aaee10adb17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677570883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1677570883
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.884438186
Short name T275
Test name
Test status
Simulation time 868532074 ps
CPU time 8.19 seconds
Started Apr 18 12:32:56 PM PDT 24
Finished Apr 18 12:33:05 PM PDT 24
Peak memory 211364 kb
Host smart-57706566-6ac2-45b5-bc57-ab39f7564cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884438186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.884438186
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2105111463
Short name T54
Test name
Test status
Simulation time 26104140413 ps
CPU time 399.46 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:39:43 PM PDT 24
Peak memory 240240 kb
Host smart-79bbe06e-da96-4035-a495-6f2643481161
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105111463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2105111463
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3774017800
Short name T447
Test name
Test status
Simulation time 56242545092 ps
CPU time 667.07 seconds
Started Apr 18 02:03:51 PM PDT 24
Finished Apr 18 02:14:59 PM PDT 24
Peak memory 240468 kb
Host smart-d718bc7c-9670-41c6-9ef5-bc19867b5106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774017800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3774017800
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.182916514
Short name T301
Test name
Test status
Simulation time 1662886623 ps
CPU time 29.58 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:24 PM PDT 24
Peak memory 214808 kb
Host smart-2c38bb25-1822-43af-811f-da58009135f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182916514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.182916514
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.579237479
Short name T277
Test name
Test status
Simulation time 3047743884 ps
CPU time 35.19 seconds
Started Apr 18 02:04:01 PM PDT 24
Finished Apr 18 02:04:36 PM PDT 24
Peak memory 215768 kb
Host smart-2b034fb1-6197-4105-a969-31c0c96be225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579237479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.579237479
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1107612872
Short name T556
Test name
Test status
Simulation time 4252713230 ps
CPU time 22.38 seconds
Started Apr 18 12:33:33 PM PDT 24
Finished Apr 18 12:33:56 PM PDT 24
Peak memory 212640 kb
Host smart-b0d54a09-1ebc-4659-a762-aedc255484aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107612872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1107612872
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1508833630
Short name T565
Test name
Test status
Simulation time 621759239 ps
CPU time 10.55 seconds
Started Apr 18 02:03:49 PM PDT 24
Finished Apr 18 02:04:00 PM PDT 24
Peak memory 212692 kb
Host smart-7d691631-f2f4-4db4-9b30-e792a849bbe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508833630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1508833630
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1185650449
Short name T437
Test name
Test status
Simulation time 9218517591 ps
CPU time 43.01 seconds
Started Apr 18 12:33:18 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 217212 kb
Host smart-d0c11b85-023e-4790-b88b-974490d78d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185650449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1185650449
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1318121666
Short name T655
Test name
Test status
Simulation time 7506739814 ps
CPU time 61.6 seconds
Started Apr 18 02:03:51 PM PDT 24
Finished Apr 18 02:04:53 PM PDT 24
Peak memory 217724 kb
Host smart-9fcc81d7-b95b-4405-bafd-2e40f0d0cc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318121666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1318121666
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2482423246
Short name T496
Test name
Test status
Simulation time 910550041 ps
CPU time 42.77 seconds
Started Apr 18 12:33:02 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 219180 kb
Host smart-03228886-d757-4e71-b443-e48030dde6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482423246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2482423246
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2497381039
Short name T607
Test name
Test status
Simulation time 1400599805 ps
CPU time 46.6 seconds
Started Apr 18 02:03:50 PM PDT 24
Finished Apr 18 02:04:38 PM PDT 24
Peak memory 219316 kb
Host smart-ed298664-ed62-4cee-9173-d021f3497b06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497381039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2497381039
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1131454989
Short name T539
Test name
Test status
Simulation time 1979538074 ps
CPU time 21.21 seconds
Started Apr 18 02:04:01 PM PDT 24
Finished Apr 18 02:04:23 PM PDT 24
Peak memory 211968 kb
Host smart-91df4747-3f20-4ee2-b7c8-4a95d20dec30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131454989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1131454989
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2047588594
Short name T457
Test name
Test status
Simulation time 842420001 ps
CPU time 13.97 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:33:19 PM PDT 24
Peak memory 211212 kb
Host smart-6f05e768-b695-4eb8-90b7-1bdfc4937813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047588594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2047588594
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3878965040
Short name T290
Test name
Test status
Simulation time 231697792164 ps
CPU time 545.54 seconds
Started Apr 18 02:04:01 PM PDT 24
Finished Apr 18 02:13:07 PM PDT 24
Peak memory 238048 kb
Host smart-1a83846b-163b-4ec3-aa22-e94f99787949
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878965040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3878965040
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.848166505
Short name T357
Test name
Test status
Simulation time 23823919940 ps
CPU time 259.84 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:37:25 PM PDT 24
Peak memory 233892 kb
Host smart-ca7cc52c-4ab2-4f28-8a5e-8f5427e58aef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848166505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.848166505
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3821626072
Short name T509
Test name
Test status
Simulation time 8425646542 ps
CPU time 68.7 seconds
Started Apr 18 02:04:00 PM PDT 24
Finished Apr 18 02:05:09 PM PDT 24
Peak memory 215280 kb
Host smart-7afa8340-1650-408c-b9d8-ab703159b1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821626072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3821626072
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4083144668
Short name T253
Test name
Test status
Simulation time 7679742701 ps
CPU time 63.42 seconds
Started Apr 18 12:33:05 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 215260 kb
Host smart-c1a9d503-5329-4534-8318-8edb0bde28bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083144668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4083144668
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2575087620
Short name T434
Test name
Test status
Simulation time 353236639 ps
CPU time 10.16 seconds
Started Apr 18 12:32:51 PM PDT 24
Finished Apr 18 12:33:03 PM PDT 24
Peak memory 212324 kb
Host smart-904157af-1c85-48b5-bc6a-b2f90b8be47a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2575087620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2575087620
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.278895193
Short name T216
Test name
Test status
Simulation time 18546418354 ps
CPU time 29.97 seconds
Started Apr 18 02:04:00 PM PDT 24
Finished Apr 18 02:04:30 PM PDT 24
Peak memory 213028 kb
Host smart-534bd6a2-b900-485d-b2f9-bdc7d1e260d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278895193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.278895193
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2095139401
Short name T388
Test name
Test status
Simulation time 47370317133 ps
CPU time 83.7 seconds
Started Apr 18 02:03:59 PM PDT 24
Finished Apr 18 02:05:23 PM PDT 24
Peak memory 218072 kb
Host smart-e9c0eb99-4cfa-49bb-91d5-2e28935abf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095139401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2095139401
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3832725876
Short name T25
Test name
Test status
Simulation time 24638636902 ps
CPU time 61.81 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:57 PM PDT 24
Peak memory 217568 kb
Host smart-77d1d7ce-6fcf-416e-b8f8-4d17f2c027ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832725876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3832725876
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1541106732
Short name T151
Test name
Test status
Simulation time 14926587345 ps
CPU time 52.97 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:48 PM PDT 24
Peak memory 219264 kb
Host smart-10da5cb6-038a-4e19-9078-af70c9cf6003
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541106732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1541106732
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.850974107
Short name T268
Test name
Test status
Simulation time 10051051618 ps
CPU time 90.76 seconds
Started Apr 18 02:03:59 PM PDT 24
Finished Apr 18 02:05:30 PM PDT 24
Peak memory 217168 kb
Host smart-81bb3e2e-080f-414c-942c-6f2b8f5c6338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850974107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.850974107
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1432246989
Short name T266
Test name
Test status
Simulation time 6971683192 ps
CPU time 27.93 seconds
Started Apr 18 02:04:09 PM PDT 24
Finished Apr 18 02:04:37 PM PDT 24
Peak memory 212308 kb
Host smart-852824dd-a2d8-4e7d-b930-dd4a6a72abba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432246989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1432246989
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2940447639
Short name T666
Test name
Test status
Simulation time 9521399377 ps
CPU time 23.78 seconds
Started Apr 18 12:32:59 PM PDT 24
Finished Apr 18 12:33:23 PM PDT 24
Peak memory 211520 kb
Host smart-a72bdbda-a7ba-4a08-9043-547683ccedc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940447639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2940447639
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1442866198
Short name T466
Test name
Test status
Simulation time 305722032716 ps
CPU time 287.37 seconds
Started Apr 18 12:33:13 PM PDT 24
Finished Apr 18 12:38:01 PM PDT 24
Peak memory 237480 kb
Host smart-4be2cb47-6850-4613-8ed0-325a59f681d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442866198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1442866198
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3695713180
Short name T104
Test name
Test status
Simulation time 83696120836 ps
CPU time 246.64 seconds
Started Apr 18 02:04:08 PM PDT 24
Finished Apr 18 02:08:15 PM PDT 24
Peak memory 227680 kb
Host smart-45458483-0276-4e1a-8226-7dfcf55c58cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695713180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3695713180
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.189559808
Short name T227
Test name
Test status
Simulation time 1848898761 ps
CPU time 32.68 seconds
Started Apr 18 02:04:09 PM PDT 24
Finished Apr 18 02:04:42 PM PDT 24
Peak memory 214780 kb
Host smart-5008bfec-2f2c-4d2f-96ba-5791ed1fbec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189559808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.189559808
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.303334032
Short name T267
Test name
Test status
Simulation time 34310910040 ps
CPU time 65.11 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:35:09 PM PDT 24
Peak memory 214712 kb
Host smart-05275a58-4ae0-4354-9f49-500b3e6f71f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303334032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.303334032
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1944685742
Short name T485
Test name
Test status
Simulation time 14362845198 ps
CPU time 29.84 seconds
Started Apr 18 12:32:58 PM PDT 24
Finished Apr 18 12:33:29 PM PDT 24
Peak memory 212828 kb
Host smart-7359ea36-ab22-453a-8e5e-c4d29b3a9b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944685742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1944685742
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3226334377
Short name T478
Test name
Test status
Simulation time 8054041291 ps
CPU time 32.94 seconds
Started Apr 18 02:04:00 PM PDT 24
Finished Apr 18 02:04:34 PM PDT 24
Peak memory 211808 kb
Host smart-8765f853-0580-4b4b-8791-be358069225f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226334377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3226334377
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3713136275
Short name T329
Test name
Test status
Simulation time 3797068273 ps
CPU time 19.16 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:33:11 PM PDT 24
Peak memory 213540 kb
Host smart-f6b15c69-0776-4198-bd60-b0fb17873623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713136275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3713136275
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.995908090
Short name T226
Test name
Test status
Simulation time 7000870876 ps
CPU time 67.41 seconds
Started Apr 18 02:04:00 PM PDT 24
Finished Apr 18 02:05:07 PM PDT 24
Peak memory 216568 kb
Host smart-c2ccf9f9-2ec4-426b-a359-a90c5474e62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995908090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.995908090
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2892030009
Short name T455
Test name
Test status
Simulation time 61713162373 ps
CPU time 137.65 seconds
Started Apr 18 02:04:01 PM PDT 24
Finished Apr 18 02:06:19 PM PDT 24
Peak memory 220904 kb
Host smart-0fd479ec-9fdc-4f2e-b1bb-f5058f2989c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892030009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2892030009
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1194271637
Short name T622
Test name
Test status
Simulation time 3683698783 ps
CPU time 30.1 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 211920 kb
Host smart-ac7c074e-8854-44e8-9810-931f6bbba461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194271637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1194271637
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2670996155
Short name T417
Test name
Test status
Simulation time 8925223674 ps
CPU time 15.45 seconds
Started Apr 18 02:04:18 PM PDT 24
Finished Apr 18 02:04:34 PM PDT 24
Peak memory 212264 kb
Host smart-997d7703-8c6f-494e-b944-e81044172a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670996155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2670996155
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2525043804
Short name T542
Test name
Test status
Simulation time 86794656489 ps
CPU time 833.9 seconds
Started Apr 18 12:32:54 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 225616 kb
Host smart-79f52737-029b-4d19-9129-b02f7c88d73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525043804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2525043804
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3691482104
Short name T594
Test name
Test status
Simulation time 25850159040 ps
CPU time 329.89 seconds
Started Apr 18 02:04:16 PM PDT 24
Finished Apr 18 02:09:47 PM PDT 24
Peak memory 216768 kb
Host smart-40e5cf49-655a-4f99-aa90-edf9771d81ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691482104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3691482104
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2577669197
Short name T3
Test name
Test status
Simulation time 2704120327 ps
CPU time 36.17 seconds
Started Apr 18 02:04:16 PM PDT 24
Finished Apr 18 02:04:53 PM PDT 24
Peak memory 213728 kb
Host smart-4a77f30d-170b-4389-8370-c0f379bdd873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577669197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2577669197
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3937513224
Short name T172
Test name
Test status
Simulation time 636842182 ps
CPU time 18.68 seconds
Started Apr 18 12:33:00 PM PDT 24
Finished Apr 18 12:33:20 PM PDT 24
Peak memory 214732 kb
Host smart-7101cd9c-6c98-4af0-a117-9d6508f86d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937513224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3937513224
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2901768479
Short name T375
Test name
Test status
Simulation time 687131009 ps
CPU time 14.68 seconds
Started Apr 18 12:32:53 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 211108 kb
Host smart-7bf66ed3-ec88-423b-8371-9eb95c84d45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901768479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2901768479
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.611985999
Short name T185
Test name
Test status
Simulation time 9987856840 ps
CPU time 24.8 seconds
Started Apr 18 02:04:07 PM PDT 24
Finished Apr 18 02:04:32 PM PDT 24
Peak memory 211916 kb
Host smart-a66838f7-b414-4ff3-9c98-8d85c1cb45f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611985999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.611985999
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2991983630
Short name T379
Test name
Test status
Simulation time 20513503731 ps
CPU time 55.81 seconds
Started Apr 18 12:33:06 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 218296 kb
Host smart-45db7535-0efd-45fc-a509-ac199749fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991983630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2991983630
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3359593811
Short name T472
Test name
Test status
Simulation time 19917606395 ps
CPU time 46.58 seconds
Started Apr 18 02:04:08 PM PDT 24
Finished Apr 18 02:04:55 PM PDT 24
Peak memory 217724 kb
Host smart-ad554f29-9d2a-4e85-8c3c-dfcd4ac01b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359593811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3359593811
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1875460371
Short name T331
Test name
Test status
Simulation time 20536119361 ps
CPU time 145.24 seconds
Started Apr 18 02:04:08 PM PDT 24
Finished Apr 18 02:06:34 PM PDT 24
Peak memory 219496 kb
Host smart-b216bece-d226-4f7e-afc4-43e161aa3687
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875460371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1875460371
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2823813461
Short name T362
Test name
Test status
Simulation time 1236815296 ps
CPU time 43.32 seconds
Started Apr 18 12:32:54 PM PDT 24
Finished Apr 18 12:33:39 PM PDT 24
Peak memory 219164 kb
Host smart-44a17cd5-13c7-4f8e-9d03-ddbff62a1acf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823813461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2823813461
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2561992619
Short name T667
Test name
Test status
Simulation time 41597124358 ps
CPU time 1267.04 seconds
Started Apr 18 12:32:54 PM PDT 24
Finished Apr 18 12:54:03 PM PDT 24
Peak memory 233668 kb
Host smart-fc87554b-8b0a-4a01-b2d1-ab6f02a6e000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561992619 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2561992619
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.277700129
Short name T162
Test name
Test status
Simulation time 14386586303 ps
CPU time 26.86 seconds
Started Apr 18 12:32:54 PM PDT 24
Finished Apr 18 12:33:23 PM PDT 24
Peak memory 212376 kb
Host smart-7449c8fb-ce6d-46ff-beec-863528b64787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277700129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.277700129
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4050904995
Short name T397
Test name
Test status
Simulation time 1842643968 ps
CPU time 14.23 seconds
Started Apr 18 02:04:18 PM PDT 24
Finished Apr 18 02:04:32 PM PDT 24
Peak memory 211388 kb
Host smart-90d47336-68e2-4d58-b9f5-e9e45a69637d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050904995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4050904995
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1705946349
Short name T257
Test name
Test status
Simulation time 239686346153 ps
CPU time 962.15 seconds
Started Apr 18 02:04:15 PM PDT 24
Finished Apr 18 02:20:18 PM PDT 24
Peak memory 234240 kb
Host smart-d82ce7de-365c-4f4c-a2d5-462e275a7699
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705946349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1705946349
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3867367550
Short name T53
Test name
Test status
Simulation time 392069525752 ps
CPU time 367.01 seconds
Started Apr 18 12:33:04 PM PDT 24
Finished Apr 18 12:39:13 PM PDT 24
Peak memory 217648 kb
Host smart-b39b6c86-bb52-429e-90d1-77934a680a69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867367550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3867367550
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1251639125
Short name T490
Test name
Test status
Simulation time 28353039920 ps
CPU time 47.62 seconds
Started Apr 18 02:04:17 PM PDT 24
Finished Apr 18 02:05:05 PM PDT 24
Peak memory 214008 kb
Host smart-851dcf18-cda6-4dd1-96c5-f60a749d780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251639125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1251639125
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.329362364
Short name T171
Test name
Test status
Simulation time 30151151442 ps
CPU time 62.16 seconds
Started Apr 18 12:32:52 PM PDT 24
Finished Apr 18 12:33:57 PM PDT 24
Peak memory 215068 kb
Host smart-87fea1d0-2903-4cc3-a2cd-9455f6d0e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329362364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.329362364
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2100247959
Short name T600
Test name
Test status
Simulation time 353902371 ps
CPU time 9.9 seconds
Started Apr 18 12:33:07 PM PDT 24
Finished Apr 18 12:33:19 PM PDT 24
Peak memory 212224 kb
Host smart-38ac0043-a4e3-4328-9532-8d312ea2f358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100247959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2100247959
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2690554130
Short name T658
Test name
Test status
Simulation time 16036100939 ps
CPU time 26.52 seconds
Started Apr 18 02:04:17 PM PDT 24
Finished Apr 18 02:04:45 PM PDT 24
Peak memory 211804 kb
Host smart-fdf8dbe2-894d-4e8d-8b6d-f937ac021f0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2690554130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2690554130
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.131851862
Short name T145
Test name
Test status
Simulation time 5793086274 ps
CPU time 63.01 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:35:07 PM PDT 24
Peak memory 216268 kb
Host smart-4fa12a1a-f9ab-4748-b265-545cc2609a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131851862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.131851862
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4082634661
Short name T448
Test name
Test status
Simulation time 3982735733 ps
CPU time 27.73 seconds
Started Apr 18 02:04:16 PM PDT 24
Finished Apr 18 02:04:44 PM PDT 24
Peak memory 217592 kb
Host smart-4e8e57ae-6146-435d-bba3-90c8d2104250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082634661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4082634661
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2065215378
Short name T507
Test name
Test status
Simulation time 13956108253 ps
CPU time 29.67 seconds
Started Apr 18 02:04:16 PM PDT 24
Finished Apr 18 02:04:47 PM PDT 24
Peak memory 211972 kb
Host smart-ce991a50-6422-4516-9e30-fa104e1fff4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065215378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2065215378
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4054475225
Short name T461
Test name
Test status
Simulation time 36064670442 ps
CPU time 88.31 seconds
Started Apr 18 12:33:03 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 220676 kb
Host smart-821c7d59-6e34-44cb-8eaa-bcae7d41f14a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054475225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4054475225
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3562011553
Short name T60
Test name
Test status
Simulation time 1132961517705 ps
CPU time 4850.93 seconds
Started Apr 18 02:04:19 PM PDT 24
Finished Apr 18 03:25:10 PM PDT 24
Peak memory 248184 kb
Host smart-4a8888c3-0cba-4be4-8abc-0ceb9dd6ddf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562011553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3562011553
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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