Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3442437

1

T2

54

T4

70

T8

74

full_word

2186259

1

T1

2

T2

8

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5628086	1			T1	2		T2	62		T4	78
auto[TlIntgErrCmd]	211	1			T63	5		T64	2		T65	3
auto[TlIntgErrData]	198	1			T63	9		T64	4		T65	4
auto[TlIntgErrBoth]	201	1			T63	6		T64	4		T65	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

911156

1

T1

2

T2

62

T4

78

auto[1]

4717540

1

T12

68534

T17

95219

T18

99641

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	392066	1			T2	54		T4	70		T8	74
auto[TlIntgErrNone]	partial	auto[1]	3049804	1			T12	43928		T17	61429		T18	64754
auto[TlIntgErrNone]	full_word	auto[0]	518809	1			T1	2		T2	8		T4	8
auto[TlIntgErrNone]	full_word	auto[1]	1667407	1			T12	24606		T17	33790		T18	34887
auto[TlIntgErrCmd]	partial	auto[0]	80	1			T63	2		T64	1		T121	1
auto[TlIntgErrCmd]	partial	auto[1]	117	1			T63	3		T64	1		T65	3
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T121	1		T129	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T121	1		T134	1		T135	1
auto[TlIntgErrData]	partial	auto[0]	102	1			T63	5		T64	3		T121	5
auto[TlIntgErrData]	partial	auto[1]	85	1			T63	3		T64	1		T65	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T63	1		T65	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T135	1		T136	2		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	77	1			T63	4		T64	2		T121	1
auto[TlIntgErrBoth]	partial	auto[1]	106	1			T63	2		T64	2		T65	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T121	1		T124	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T65	1		T127	1		T138	3