Unified Coverage Report :: Module :: tlul_data_integ_enc

Module : tlul_data_integ_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tl_adapter_rom.u_tlul_data_integ_enc_instr
tb.dut.u_tl_adapter_rom.u_tlul_data_integ_enc_data
tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc

---

Module Instance : tb.dut.u_tl_adapter_rom.u_tlul_data_integ_enc_instr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.22	96.92	83.05			88.89	100.00	u_tl_adapter_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_tl_adapter_rom.u_tlul_data_integ_enc_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.22	96.92	83.05			88.89	100.00	u_tl_adapter_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	0.00	0.00

---

Module Instance : tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_rsp_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_gen	100.00	100.00