Line Coverage for Module :
tlul_err
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 26 | 26 | 100.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
| ALWAYS | 57 | 17 | 17 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 32 |
1 |
1 |
| 36 |
1 |
1 |
| 39 |
1 |
1 |
| 42 |
1 |
1 |
| 54 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 66 |
1 |
1 |
| 70 |
1 |
1 |
| 72 |
1 |
1 |
| 74 |
1 |
1 |
| 78 |
1 |
1 |
| 79 |
1 |
1 |
| 80 |
1 |
1 |
| 90 |
1 |
1 |
| 91 |
1 |
1 |
| 92 |
1 |
1 |
| 96 |
1 |
1 |
Cond Coverage for Module :
tlul_err
| Total | Covered | Percent |
|---|
| Conditions | 35 | 35 | 100.00 |
| Logical | 35 | 35 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 26
EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 27
EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 28
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 39
EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
--------------------1-------------------- ------2----- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T12,T17,T18 |
| 0 | 1 | 0 | Covered | T12,T17,T18 |
| 1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 39
SUB-EXPRESSION (opcode_allowed & a_config_allowed)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T17,T18 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 42
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
---------------1-------------- ----------------2---------------- -----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T12,T17,T18 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 74
EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
-----1----- ----2--- ------------------3-----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T12,T17,T18 |
| 1 | 0 | 1 | Covered | T12,T17,T18 |
| 1 | 1 | 0 | Covered | T12,T17,T18 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
---1-- -----2---- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T4,T5 |
| 0 | 0 | 1 | Covered | T12,T34,T20 |
| 0 | 1 | 0 | Covered | T1,T4,T5 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
Branch Coverage for Module :
tlul_err
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| IF |
61 |
8 |
8 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 61 if (tl_i.a_valid)
-2-: 62 case (tl_i.a_size)
-3-: 72 (tl_i.a_address[1]) ?
-4-: 74 (tl_i.a_address[1]) ?
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
'h0 |
- |
- |
Covered |
T1,T2,T4 |
| 1 |
'h1 |
1 |
- |
Covered |
T1,T2,T3 |
| 1 |
'h1 |
0 |
- |
Covered |
T1,T2,T4 |
| 1 |
'h1 |
- |
1 |
Covered |
T1,T2,T3 |
| 1 |
'h1 |
- |
0 |
Covered |
T1,T2,T4 |
| 1 |
'h00000002 |
- |
- |
Covered |
T1,T2,T4 |
| 1 |
default |
- |
- |
Covered |
T12,T17,T18 |
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_err
Assertion Details
dataWidthOnly32_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1536 |
1536 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.u_err
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 26 | 26 | 100.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
| ALWAYS | 57 | 17 | 17 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 32 |
1 |
1 |
| 36 |
1 |
1 |
| 39 |
1 |
1 |
| 42 |
1 |
1 |
| 54 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 66 |
1 |
1 |
| 70 |
1 |
1 |
| 72 |
1 |
1 |
| 74 |
1 |
1 |
| 78 |
1 |
1 |
| 79 |
1 |
1 |
| 80 |
1 |
1 |
| 90 |
1 |
1 |
| 91 |
1 |
1 |
| 92 |
1 |
1 |
| 96 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_rom.u_err
| Total | Covered | Percent |
|---|
| Conditions | 35 | 35 | 100.00 |
| Logical | 35 | 35 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 26
EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T12,T15 |
LINE 27
EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T12,T15 |
LINE 28
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 39
EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
--------------------1-------------------- ------2----- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T4 |
| 0 | 0 | 1 | Covered | T12,T17,T18 |
| 0 | 1 | 0 | Covered | T12,T17,T18 |
| 1 | 0 | 0 | Covered | T4,T12,T15 |
LINE 39
SUB-EXPRESSION (opcode_allowed & a_config_allowed)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T17,T18 |
| 1 | 0 | Covered | T4,T12,T15 |
| 1 | 1 | Covered | T1,T2,T4 |
LINE 42
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
---------------1-------------- ----------------2---------------- -----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T12,T17,T18 |
| 0 | 0 | 1 | Covered | T1,T2,T4 |
| 0 | 1 | 0 | Covered | T4,T12,T15 |
| 1 | 0 | 0 | Covered | T4,T12,T15 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T12,T15 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T12,T15 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T4 |
LINE 72
EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T8 |
| 1 | Covered | T2,T4,T8 |
LINE 74
EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T4,T8 |
| 1 | Covered | T2,T4,T8 |
LINE 96
EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
-----1----- ----2--- ------------------3-----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T12,T17,T18 |
| 1 | 0 | 1 | Covered | T12,T17,T18 |
| 1 | 1 | 0 | Covered | T12,T17,T18 |
| 1 | 1 | 1 | Covered | T1,T2,T4 |
LINE 96
SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
---1-- -----2---- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T4,T12,T15 |
| 0 | 0 | 1 | Covered | T12,T17,T18 |
| 0 | 1 | 0 | Covered | T4,T12,T15 |
| 1 | 0 | 0 | Covered | T2,T4,T8 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_rom.u_err
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| IF |
61 |
8 |
8 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 61 if (tl_i.a_valid)
-2-: 62 case (tl_i.a_size)
-3-: 72 (tl_i.a_address[1]) ?
-4-: 74 (tl_i.a_address[1]) ?
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
'h0 |
- |
- |
Covered |
T2,T4,T8 |
| 1 |
'h1 |
1 |
- |
Covered |
T2,T4,T8 |
| 1 |
'h1 |
0 |
- |
Covered |
T2,T4,T8 |
| 1 |
'h1 |
- |
1 |
Covered |
T2,T4,T8 |
| 1 |
'h1 |
- |
0 |
Covered |
T2,T4,T8 |
| 1 |
'h00000002 |
- |
- |
Covered |
T1,T2,T4 |
| 1 |
default |
- |
- |
Covered |
T12,T17,T18 |
| 0 |
- |
- |
- |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_rom.u_err
Assertion Details
dataWidthOnly32_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
623 |
623 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_err
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 26 | 26 | 100.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
| ALWAYS | 57 | 17 | 17 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 26 |
1 |
1 |
| 27 |
1 |
1 |
| 28 |
1 |
1 |
| 32 |
1 |
1 |
| 36 |
1 |
1 |
| 39 |
1 |
1 |
| 42 |
1 |
1 |
| 54 |
1 |
1 |
| 57 |
1 |
1 |
| 58 |
1 |
1 |
| 59 |
1 |
1 |
| 61 |
1 |
1 |
| 62 |
1 |
1 |
| 64 |
1 |
1 |
| 65 |
1 |
1 |
| 66 |
1 |
1 |
| 70 |
1 |
1 |
| 72 |
1 |
1 |
| 74 |
1 |
1 |
| 78 |
1 |
1 |
| 79 |
1 |
1 |
| 80 |
1 |
1 |
| 90 |
1 |
1 |
| 91 |
1 |
1 |
| 92 |
1 |
1 |
| 96 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_err
| Total | Covered | Percent |
|---|
| Conditions | 35 | 35 | 100.00 |
| Logical | 35 | 35 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 26
EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T12 |
LINE 27
EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T12 |
LINE 28
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 39
EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
--------------------1-------------------- ------2----- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T12,T17,T18 |
| 0 | 1 | 0 | Covered | T12,T17,T18 |
| 1 | 0 | 0 | Covered | T1,T5,T12 |
LINE 39
SUB-EXPRESSION (opcode_allowed & a_config_allowed)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T17,T18 |
| 1 | 0 | Covered | T1,T5,T12 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 42
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
---------------1-------------- ----------------2---------------- -----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T12,T17,T18 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T1,T5,T12 |
| 1 | 0 | 0 | Covered | T1,T5,T12 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T12 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T12 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 74
EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
-----1----- ----2--- ------------------3-----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T12,T17,T18 |
| 1 | 0 | 1 | Covered | T12,T17,T18 |
| 1 | 1 | 0 | Covered | T12,T17,T18 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
---1-- -----2---- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T5,T12 |
| 0 | 0 | 1 | Covered | T12,T34,T20 |
| 0 | 1 | 0 | Covered | T1,T5,T12 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_err
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| IF |
61 |
8 |
8 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 61 if (tl_i.a_valid)
-2-: 62 case (tl_i.a_size)
-3-: 72 (tl_i.a_address[1]) ?
-4-: 74 (tl_i.a_address[1]) ?
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
'h0 |
- |
- |
Covered |
T1,T2,T4 |
| 1 |
'h1 |
1 |
- |
Covered |
T1,T2,T3 |
| 1 |
'h1 |
0 |
- |
Covered |
T1,T2,T4 |
| 1 |
'h1 |
- |
1 |
Covered |
T1,T2,T3 |
| 1 |
'h1 |
- |
0 |
Covered |
T1,T2,T4 |
| 1 |
'h00000002 |
- |
- |
Covered |
T1,T2,T4 |
| 1 |
default |
- |
- |
Covered |
T12,T17,T18 |
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_err
Assertion Details
dataWidthOnly32_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
913 |
913 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |