Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1550190

1

T2

153014

T4

5

T5

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	425452	1			T2	38813		T4	68		T5	163
values[0x0]	584072	1			T2	57678		T16	19663		T17	16461
values[0x1]	606320	1			T2	60109		T16	20623		T17	17001

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1582116

1

T2

154557

T4

43

T5

97

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5824	1			T2	628		T16	205		T11	1
valid_sources[0x01]	5676	1			T2	609		T7	7		T15	1
valid_sources[0x02]	6200	1			T2	615		T7	2		T10	1
valid_sources[0x03]	5740	1			T2	595		T10	3		T14	2
valid_sources[0x04]	6740	1			T2	624		T36	3		T16	211
valid_sources[0x05]	5988	1			T2	598		T5	3		T6	5
valid_sources[0x06]	6763	1			T2	633		T7	1		T13	1
valid_sources[0x07]	6872	1			T2	672		T5	1		T6	9
valid_sources[0x08]	6315	1			T2	594		T5	2		T14	1
valid_sources[0x09]	6094	1			T2	621		T8	1		T14	1
valid_sources[0x0a]	6200	1			T2	562		T4	1		T5	2
valid_sources[0x0b]	5874	1			T2	558		T4	1		T10	2
valid_sources[0x0c]	6184	1			T2	637		T14	1		T15	1
valid_sources[0x0d]	6115	1			T2	632		T8	1		T10	1
valid_sources[0x0e]	5726	1			T2	621		T14	1		T50	2
valid_sources[0x0f]	6266	1			T2	605		T5	1		T8	1
valid_sources[0x10]	6086	1			T2	619		T5	1		T8	1
valid_sources[0x11]	7158	1			T2	651		T5	1		T14	2
valid_sources[0x12]	6489	1			T2	579		T5	2		T16	204
valid_sources[0x13]	5969	1			T2	620		T10	1		T14	1
valid_sources[0x14]	6560	1			T2	650		T4	2		T5	1
valid_sources[0x15]	5833	1			T2	625		T5	1		T10	1
valid_sources[0x16]	6923	1			T2	570		T5	1		T7	2
valid_sources[0x17]	5754	1			T2	544		T7	4		T8	4
valid_sources[0x18]	6487	1			T2	622		T5	1		T7	1
valid_sources[0x19]	6125	1			T2	582		T4	1		T5	1
valid_sources[0x1a]	5806	1			T2	609		T5	1		T8	3
valid_sources[0x1b]	5951	1			T2	635		T5	3		T7	7
valid_sources[0x1c]	6739	1			T2	574		T6	1		T14	1
valid_sources[0x1d]	5831	1			T2	636		T6	9		T8	1
valid_sources[0x1e]	6157	1			T2	583		T4	3		T5	1
valid_sources[0x1f]	5594	1			T2	621		T6	1		T7	1
valid_sources[0x20]	5799	1			T2	597		T5	1		T14	1
valid_sources[0x21]	6251	1			T2	624		T36	1		T80	20
valid_sources[0x22]	7096	1			T2	646		T6	13		T12	3
valid_sources[0x23]	6205	1			T2	612		T5	1		T7	1
valid_sources[0x24]	6221	1			T2	563		T5	1		T10	2
valid_sources[0x25]	6304	1			T2	607		T4	1		T14	2
valid_sources[0x26]	5690	1			T2	584		T6	4		T10	3
valid_sources[0x27]	5702	1			T2	596		T5	1		T8	1
valid_sources[0x28]	6000	1			T2	601		T5	2		T8	1
valid_sources[0x29]	6764	1			T2	610		T5	5		T8	2
valid_sources[0x2a]	6740	1			T2	626		T7	3		T14	1
valid_sources[0x2b]	7131	1			T2	626		T13	1		T14	2
valid_sources[0x2c]	6959	1			T2	651		T14	2		T50	4
valid_sources[0x2d]	6218	1			T2	562		T4	1		T5	1
valid_sources[0x2e]	7305	1			T2	630		T5	1		T15	1
valid_sources[0x2f]	6377	1			T2	594		T5	1		T6	3
valid_sources[0x30]	6488	1			T2	587		T5	1		T10	1
valid_sources[0x31]	6687	1			T2	605		T4	1		T7	1
valid_sources[0x32]	5632	1			T2	593		T10	1		T14	2
valid_sources[0x33]	5518	1			T2	615		T5	2		T10	1
valid_sources[0x34]	6599	1			T2	613		T5	2		T8	1
valid_sources[0x35]	6498	1			T2	625		T10	1		T15	2
valid_sources[0x36]	5844	1			T2	635		T4	1		T14	2
valid_sources[0x37]	5751	1			T2	626		T5	1		T10	1
valid_sources[0x38]	5564	1			T2	605		T4	3		T6	1
valid_sources[0x39]	6862	1			T2	643		T14	1		T79	1
valid_sources[0x3a]	5584	1			T2	620		T6	6		T8	1
valid_sources[0x3b]	6668	1			T2	614		T5	3		T8	1
valid_sources[0x3c]	6142	1			T2	596		T5	1		T6	1
valid_sources[0x3d]	5820	1			T2	620		T7	5		T36	1
valid_sources[0x3e]	6208	1			T2	607		T8	1		T13	2
valid_sources[0x3f]	6431	1			T2	602		T5	1		T6	6
valid_sources[0x40]	5916	1			T2	628		T5	1		T6	15
valid_sources[0x41]	6448	1			T2	592		T14	1		T79	2
valid_sources[0x42]	6285	1			T2	579		T5	1		T7	4
valid_sources[0x43]	6181	1			T2	559		T5	1		T7	2
valid_sources[0x44]	5911	1			T2	598		T7	4		T8	1
valid_sources[0x45]	6764	1			T2	600		T5	2		T15	2
valid_sources[0x46]	6287	1			T2	604		T5	1		T14	1
valid_sources[0x47]	6272	1			T2	600		T5	1		T10	1
valid_sources[0x48]	5798	1			T2	657		T14	2		T113	22
valid_sources[0x49]	7504	1			T2	646		T13	3		T15	2
valid_sources[0x4a]	6725	1			T2	613		T7	5		T10	1
valid_sources[0x4b]	6266	1			T2	565		T5	1		T7	1
valid_sources[0x4c]	5798	1			T2	569		T14	1		T16	208
valid_sources[0x4d]	5781	1			T2	616		T5	1		T10	1
valid_sources[0x4e]	6123	1			T2	577		T5	2		T7	4
valid_sources[0x4f]	6008	1			T2	613		T4	1		T8	1
valid_sources[0x50]	6185	1			T2	629		T8	1		T13	1
valid_sources[0x51]	6643	1			T2	611		T5	2		T14	1
valid_sources[0x52]	5889	1			T2	611		T4	4		T5	2
valid_sources[0x53]	6085	1			T2	584		T4	1		T5	2
valid_sources[0x54]	6741	1			T2	613		T8	4		T14	1
valid_sources[0x55]	5925	1			T2	604		T6	5		T14	1
valid_sources[0x56]	6152	1			T2	680		T14	1		T16	214
valid_sources[0x57]	5760	1			T2	606		T5	2		T6	5
valid_sources[0x58]	6252	1			T2	556		T5	1		T6	2
valid_sources[0x59]	6231	1			T2	611		T5	1		T10	1
valid_sources[0x5a]	6478	1			T2	626		T4	1		T10	1
valid_sources[0x5b]	6914	1			T2	582		T4	1		T5	1
valid_sources[0x5c]	5584	1			T2	595		T36	1		T16	243
valid_sources[0x5d]	6420	1			T2	609		T6	13		T8	2
valid_sources[0x5e]	5950	1			T2	565		T15	2		T36	1
valid_sources[0x5f]	5765	1			T2	585		T8	1		T10	1
valid_sources[0x60]	6475	1			T2	610		T5	2		T15	3
valid_sources[0x61]	5817	1			T2	641		T8	1		T14	4
valid_sources[0x62]	6912	1			T2	611		T5	2		T15	1
valid_sources[0x63]	6157	1			T2	655		T4	1		T8	3
valid_sources[0x64]	6238	1			T2	608		T6	2		T7	13
valid_sources[0x65]	5720	1			T2	620		T5	2		T6	1
valid_sources[0x66]	6315	1			T2	646		T4	1		T6	15
valid_sources[0x67]	5861	1			T2	603		T50	1		T16	190
valid_sources[0x68]	6501	1			T2	609		T4	1		T5	1
valid_sources[0x69]	6989	1			T2	664		T4	1		T8	2
valid_sources[0x6a]	6199	1			T2	599		T13	1		T14	1
valid_sources[0x6b]	5815	1			T2	637		T5	2		T10	2
valid_sources[0x6c]	6392	1			T2	617		T7	7		T8	4
valid_sources[0x6d]	5965	1			T2	654		T5	3		T7	5
valid_sources[0x6e]	6270	1			T2	631		T7	12		T8	3
valid_sources[0x6f]	5948	1			T2	665		T15	3		T36	2
valid_sources[0x70]	5704	1			T2	611		T5	2		T7	1
valid_sources[0x71]	5801	1			T2	599		T5	2		T14	4
valid_sources[0x72]	6588	1			T2	600		T5	1		T8	1
valid_sources[0x73]	7253	1			T2	600		T4	1		T5	2
valid_sources[0x74]	6118	1			T2	635		T6	10		T14	1
valid_sources[0x75]	7203	1			T2	655		T6	5		T10	4
valid_sources[0x76]	6279	1			T2	562		T8	2		T13	3
valid_sources[0x77]	7480	1			T2	650		T10	3		T14	1
valid_sources[0x78]	7008	1			T2	615		T5	1		T8	2
valid_sources[0x79]	5729	1			T2	631		T5	2		T36	1
valid_sources[0x7a]	6437	1			T2	584		T5	1		T10	1
valid_sources[0x7b]	6464	1			T2	638		T4	1		T5	1
valid_sources[0x7c]	6529	1			T2	578		T4	2		T14	1
valid_sources[0x7d]	6898	1			T2	643		T4	1		T50	1
valid_sources[0x7e]	6750	1			T2	630		T4	1		T5	2
valid_sources[0x7f]	5574	1			T2	614		T8	1		T15	1
valid_sources[0x80]	7197	1			T2	631		T5	1		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

390848

1

T2

38286

T4

5

T5

14

values[0x0]

all_enables

biggest_size

578971

1

T2

57181

T16

19502

T17

16294

values[0x1]

all_enables

biggest_size

580371

1

T2

57547

T16

19755

T17

16283

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	114481	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1158859

1

T2

112118

T4

16

T5

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	317850	1			T1	1		T2	29790		T4	32
values[0x0]	442414	1			T2	42746		T34	8		T35	12
values[0x1]	513076	1			T2	49940		T3	4		T34	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51930	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1221410

1

T2

117977

T4

21

T5

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5534	1			T2	411		T5	1		T34	2
valid_sources[0x01]	4592	1			T2	491		T51	1		T16	8
valid_sources[0x02]	4692	1			T2	501		T5	3		T28	1
valid_sources[0x03]	4831	1			T2	432		T5	2		T16	93
valid_sources[0x04]	5381	1			T2	479		T16	148		T41	2
valid_sources[0x05]	4511	1			T2	444		T8	2		T16	168
valid_sources[0x06]	5325	1			T2	478		T68	2		T16	219
valid_sources[0x07]	5229	1			T2	475		T51	2		T113	5
valid_sources[0x08]	5216	1			T2	475		T67	2		T16	1
valid_sources[0x09]	4440	1			T2	509		T51	2		T16	187
valid_sources[0x0a]	4996	1			T2	534		T28	1		T16	215
valid_sources[0x0b]	5226	1			T2	480		T4	1		T36	1
valid_sources[0x0c]	5031	1			T2	535		T5	1		T16	2
valid_sources[0x0d]	5540	1			T2	429		T51	1		T113	12
valid_sources[0x0e]	5380	1			T2	511		T10	2		T16	1
valid_sources[0x0f]	4553	1			T2	527		T16	1		T43	3
valid_sources[0x10]	4701	1			T2	407		T51	3		T16	292
valid_sources[0x11]	4462	1			T2	490		T5	1		T113	1
valid_sources[0x12]	4108	1			T2	490		T36	1		T83	3
valid_sources[0x13]	5605	1			T2	586		T36	1		T51	1
valid_sources[0x14]	5127	1			T2	417		T28	2		T113	3
valid_sources[0x15]	5695	1			T2	503		T67	2		T16	213
valid_sources[0x16]	4632	1			T2	469		T5	1		T36	1
valid_sources[0x17]	4850	1			T2	428		T3	1		T36	2
valid_sources[0x18]	5123	1			T2	468		T113	9		T16	152
valid_sources[0x19]	5341	1			T2	500		T10	1		T28	1
valid_sources[0x1a]	4912	1			T2	459		T51	2		T16	149
valid_sources[0x1b]	4440	1			T2	491		T4	1		T5	1
valid_sources[0x1c]	4458	1			T2	540		T17	120		T53	264
valid_sources[0x1d]	4619	1			T2	495		T16	102		T131	1
valid_sources[0x1e]	4818	1			T2	552		T4	3		T16	99
valid_sources[0x1f]	5230	1			T2	539		T36	1		T29	1
valid_sources[0x20]	5534	1			T2	466		T8	2		T113	2
valid_sources[0x21]	5236	1			T2	541		T36	1		T28	1
valid_sources[0x22]	5072	1			T2	389		T10	5		T16	119
valid_sources[0x23]	4747	1			T2	469		T28	1		T16	1
valid_sources[0x24]	5098	1			T2	436		T5	1		T16	581
valid_sources[0x25]	5695	1			T2	439		T28	1		T16	247
valid_sources[0x26]	4226	1			T2	436		T16	4		T22	1
valid_sources[0x27]	5398	1			T2	461		T4	3		T5	2
valid_sources[0x28]	4824	1			T2	392		T10	2		T51	1
valid_sources[0x29]	4753	1			T2	484		T34	2		T36	1
valid_sources[0x2a]	5027	1			T2	515		T10	1		T36	1
valid_sources[0x2b]	4550	1			T2	329		T10	5		T51	1
valid_sources[0x2c]	4439	1			T2	458		T51	1		T16	125
valid_sources[0x2d]	4611	1			T2	507		T51	1		T16	96
valid_sources[0x2e]	4916	1			T2	464		T8	1		T16	458
valid_sources[0x2f]	5173	1			T2	465		T13	7		T68	4
valid_sources[0x30]	4575	1			T2	457		T8	3		T36	2
valid_sources[0x31]	5086	1			T2	456		T4	3		T51	1
valid_sources[0x32]	5050	1			T2	546		T8	7		T16	10
valid_sources[0x33]	4472	1			T2	486		T28	1		T16	2
valid_sources[0x34]	4566	1			T2	511		T16	157		T40	3
valid_sources[0x35]	5497	1			T2	463		T5	2		T10	1
valid_sources[0x36]	5009	1			T2	512		T16	516		T133	1
valid_sources[0x37]	4778	1			T2	461		T16	217		T44	1
valid_sources[0x38]	4767	1			T2	460		T5	1		T31	3
valid_sources[0x39]	4944	1			T2	468		T51	1		T16	350
valid_sources[0x3a]	4460	1			T2	463		T51	2		T67	3
valid_sources[0x3b]	5715	1			T2	469		T5	1		T51	2
valid_sources[0x3c]	5099	1			T2	434		T134	1		T17	258
valid_sources[0x3d]	4807	1			T2	458		T16	344		T43	2
valid_sources[0x3e]	4586	1			T2	434		T51	2		T16	227
valid_sources[0x3f]	5337	1			T1	1		T2	494		T36	1
valid_sources[0x40]	5161	1			T2	568		T36	1		T25	1
valid_sources[0x41]	5269	1			T2	478		T5	1		T34	1
valid_sources[0x42]	5274	1			T2	511		T4	1		T16	371
valid_sources[0x43]	3999	1			T2	498		T5	1		T36	1
valid_sources[0x44]	4371	1			T2	480		T51	1		T16	5
valid_sources[0x45]	4929	1			T2	547		T27	1		T16	117
valid_sources[0x46]	4217	1			T2	503		T36	1		T51	2
valid_sources[0x47]	4851	1			T2	520		T16	8		T131	1
valid_sources[0x48]	5347	1			T2	498		T36	1		T16	94
valid_sources[0x49]	5115	1			T2	435		T16	184		T31	1
valid_sources[0x4a]	4449	1			T2	432		T36	2		T16	2
valid_sources[0x4b]	5500	1			T2	486		T8	5		T133	1
valid_sources[0x4c]	5536	1			T2	497		T16	191		T40	2
valid_sources[0x4d]	5195	1			T2	441		T5	1		T28	2
valid_sources[0x4e]	5837	1			T2	416		T5	1		T10	1
valid_sources[0x4f]	4351	1			T2	525		T13	4		T16	202
valid_sources[0x50]	5144	1			T2	456		T51	1		T16	4
valid_sources[0x51]	5222	1			T2	480		T51	1		T16	3
valid_sources[0x52]	4654	1			T2	500		T36	1		T113	5
valid_sources[0x53]	5134	1			T2	471		T40	2		T134	1
valid_sources[0x54]	4611	1			T2	534		T16	12		T17	84
valid_sources[0x55]	5340	1			T2	510		T35	2		T16	4
valid_sources[0x56]	5837	1			T2	531		T28	1		T16	993
valid_sources[0x57]	5160	1			T2	472		T28	1		T16	796
valid_sources[0x58]	5133	1			T2	469		T5	1		T29	1
valid_sources[0x59]	3750	1			T2	469		T16	27		T22	1
valid_sources[0x5a]	4539	1			T2	529		T9	1		T28	1
valid_sources[0x5b]	5180	1			T2	509		T16	111		T40	1
valid_sources[0x5c]	4786	1			T2	511		T5	1		T29	4
valid_sources[0x5d]	4965	1			T2	501		T10	12		T16	1
valid_sources[0x5e]	5409	1			T2	494		T4	1		T16	20
valid_sources[0x5f]	5509	1			T2	481		T36	1		T16	75
valid_sources[0x60]	4541	1			T2	457		T41	1		T17	137
valid_sources[0x61]	4664	1			T2	454		T5	1		T16	205
valid_sources[0x62]	4503	1			T2	574		T16	82		T22	1
valid_sources[0x63]	5372	1			T2	409		T16	266		T40	1
valid_sources[0x64]	4776	1			T2	492		T3	1		T10	3
valid_sources[0x65]	4868	1			T2	450		T5	1		T40	1
valid_sources[0x66]	5527	1			T2	604		T36	1		T16	708
valid_sources[0x67]	5008	1			T2	488		T3	1		T51	2
valid_sources[0x68]	4686	1			T2	450		T51	1		T16	127
valid_sources[0x69]	5730	1			T2	448		T10	2		T66	1
valid_sources[0x6a]	4849	1			T2	411		T27	2		T16	186
valid_sources[0x6b]	4750	1			T2	424		T5	4		T113	1
valid_sources[0x6c]	4905	1			T2	538		T5	1		T36	1
valid_sources[0x6d]	4709	1			T2	486		T36	1		T51	1
valid_sources[0x6e]	5330	1			T2	585		T16	14		T17	122
valid_sources[0x6f]	4623	1			T2	441		T51	1		T16	157
valid_sources[0x70]	5071	1			T2	537		T36	1		T68	5
valid_sources[0x71]	5366	1			T2	470		T36	1		T51	1
valid_sources[0x72]	3956	1			T2	507		T28	1		T16	8
valid_sources[0x73]	5496	1			T2	468		T34	1		T16	21
valid_sources[0x74]	5086	1			T2	458		T28	1		T51	2
valid_sources[0x75]	5159	1			T2	454		T51	1		T17	59
valid_sources[0x76]	4251	1			T2	395		T4	4		T10	1
valid_sources[0x77]	4931	1			T2	409		T8	2		T10	3
valid_sources[0x78]	5357	1			T2	438		T36	2		T68	2
valid_sources[0x79]	5040	1			T2	512		T51	1		T16	2
valid_sources[0x7a]	4682	1			T2	418		T16	156		T17	127
valid_sources[0x7b]	4855	1			T2	486		T12	27		T26	21
valid_sources[0x7c]	4892	1			T2	492		T36	2		T51	1
valid_sources[0x7d]	4520	1			T2	436		T5	2		T16	131
valid_sources[0x7e]	5006	1			T2	437		T16	136		T41	1
valid_sources[0x7f]	5683	1			T2	530		T16	180		T22	2
valid_sources[0x80]	4368	1			T2	423		T10	5		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

292218

1

T2

28131

T4

16

T5

36

values[0x0]

all_enables

biggest_size

433001

1

T2

41879

T34

2

T35

2

values[0x1]

all_enables

biggest_size

433640

1

T2

42108

T34

1

T16

14090