Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2764363

1

T2

266514

T4

63

T5

149

full_word

1801897

1

T2

177411

T4

5

T5

14

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4565970	1			T2	443925		T4	68		T5	163
auto[TlIntgErrCmd]	91	1			T59	2		T60	8		T61	7
auto[TlIntgErrData]	107	1			T59	4		T60	7		T61	10
auto[TlIntgErrBoth]	92	1			T59	4		T60	5		T61	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

729980

1

T2

68071

T4

68

T5

163

auto[1]

3836280

1

T2

375854

T16

127924

T17

102633

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	302730	1			T2	26226		T4	63		T5	149
auto[TlIntgErrNone]	partial	auto[1]	2461359	1			T2	240288		T16	81518		T17	64445
auto[TlIntgErrNone]	full_word	auto[0]	427118	1			T2	41845		T4	5		T5	14
auto[TlIntgErrNone]	full_word	auto[1]	1374763	1			T2	135566		T16	46406		T17	38188
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T59	1		T60	5		T61	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T59	1		T60	3		T61	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T116	1		T117	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T118	1		T119	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T59	4		T60	4		T61	4
auto[TlIntgErrData]	partial	auto[1]	49	1			T60	3		T61	3		T118	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T61	3		T118	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T116	1		T122	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T59	2		T60	1		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T59	2		T60	4		T61	3
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T117	1		T124	1		-	-