ROM_CTRL/32KB Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	45.360s	4.351ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.420s	2.646ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.830s	4.349ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.820s	8.883ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.670s	2.036ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.400s	3.916ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.830s	4.349ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.670s	2.036ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.080s	2.088ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.710s	3.279ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.520s	2.179ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.565m	21.145ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.850s	25.163ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	16.810s	40.790ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.350s	3.410ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.350s	3.410ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.420s	2.646ms	5	5	100.00
		rom_ctrl_csr_rw	16.830s	4.349ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.670s	2.036ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.070s	2.088ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.420s	2.646ms	5	5	100.00
		rom_ctrl_csr_rw	16.830s	4.349ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.670s	2.036ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.070s	2.088ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.632m	50.518ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.767m	2.494ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.311m	2.157ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.767m	2.494ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.767m	2.494ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.767m	2.494ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	45.360s	4.351ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	45.360s	4.351ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	45.360s	4.351ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.311m	2.157ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
		rom_ctrl_kmac_err_chk	34.850s	25.163ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.471m	183.793ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.632m	50.518ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.767m	2.494ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.574h	53.322ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	96.97	93.01	97.88	100.00	98.37	98.04	98.83

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 29 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.2598783196140803727402913897750148601040121868843749330434144995274937125972
      Line 776, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 116727147620 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 116727147620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.rom_ctrl_stress_all_with_rand_reset.85777635717189679287474116785730277100994674080495276878428879292010419244033
      Line 273, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7547599368 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7547599368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

    • 21.rom_ctrl_stress_all_with_rand_reset.10106027959858941904824469743367509995915326685722377553416998834813632437060
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:3e8711e8-47c2-40ab-be9b-c41e7f887f23
      

    • 22.rom_ctrl_stress_all_with_rand_reset.12342976571776710861048700624397776750348668044642401778548832061687372291227
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:2752353b-98a8-4318-bcaf-4219359b665c
      

    • ... and 2 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 3 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 11.rom_ctrl_stress_all_with_rand_reset.18879214514390429989497257389550199420038272453491671126617342323168992188184
      Line 957, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1040502652758 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 1040502652758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 12.rom_ctrl_corrupt_sig_fatal_chk.40908977609786533740412731733422275714333604825271453705286925973971615281041
      Line 280, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 21568355374 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 21568355374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 14.rom_ctrl_kmac_err_chk.29347292169337018003782422242940224281447849797205160654590435180883310898123
      Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest/run.log

        UVM_ERROR @ 2765395348 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 2765395348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 2 failures.

    • 6.rom_ctrl_stress_all_with_rand_reset.37575536722565120305568691309010251884445545353877178334504584870542788258358
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10016345262 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x616308a2
        UVM_INFO @ 10016345262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.rom_ctrl_stress_all_with_rand_reset.69465442178290089569395754267734115618376004447801972133687914517033436038032
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10016545761 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x35dcf752
        UVM_INFO @ 10016545761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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