ROM_CTRL/32KB Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	9.760s	179.302us	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.330s	294.625us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.980s	168.683us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.190s	165.650us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.130s	164.278us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	10.570s	195.767us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.980s	168.683us	20	20	100.00
		rom_ctrl_csr_aliasing	8.130s	164.278us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.810s	372.591us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.080s	535.187us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	14.280s	548.849us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	31.390s	723.380us	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	17.050s	291.094us	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	12.030s	6.123ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.140s	2.079ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.140s	2.079ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.330s	294.625us	5	5	100.00
		rom_ctrl_csr_rw	8.980s	168.683us	20	20	100.00
		rom_ctrl_csr_aliasing	8.130s	164.278us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.650s	326.025us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.330s	294.625us	5	5	100.00
		rom_ctrl_csr_rw	8.980s	168.683us	20	20	100.00
		rom_ctrl_csr_aliasing	8.130s	164.278us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.650s	326.025us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	50.640s	12.530ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.002m	2.496ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.551m	730.891us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.002m	2.496ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.002m	2.496ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.002m	2.496ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	9.760s	179.302us	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	9.760s	179.302us	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	9.760s	179.302us	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.551m	730.891us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
		rom_ctrl_kmac_err_chk	17.050s	291.094us	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.324m	20.089ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	50.640s	12.530ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.002m	2.496ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.592m	12.333ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			456	460	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.83	99.36	92.28	97.67	100.00	98.55	97.91	99.06

Failure Buckets

• UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 4 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.61580018954046340865693002986140119507587184214825220704379302552580265331534
      Line 79, in log /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 154387402 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 154387402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.rom_ctrl_stress_all_with_rand_reset.78782047268602434113224665486407239734022938246732962698722222540929702439886
      Line 91, in log /workspaces/repo/scratch/os_regression_2024_10_14/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 2671210683 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 2671210683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

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