ROM_CTRL/32KB Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	14.110s	2.012ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.000s	1.052ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	10.350s	2.057ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.200s	263.352us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.270s	492.886us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	11.400s	1.054ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	10.350s	2.057ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.270s	492.886us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.770s	145.790us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.890s	335.877us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	12.430s	531.659us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	30.970s	3.466ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	23.940s	981.686us	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	13.140s	513.238us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.090s	584.793us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.090s	584.793us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.000s	1.052ms	5	5	100.00
		rom_ctrl_csr_rw	10.350s	2.057ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.270s	492.886us	5	5	100.00
		rom_ctrl_same_csr_outstanding	12.870s	508.076us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.000s	1.052ms	5	5	100.00
		rom_ctrl_csr_rw	10.350s	2.057ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.270s	492.886us	5	5	100.00
		rom_ctrl_same_csr_outstanding	12.870s	508.076us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	59.440s	3.071ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.420m	195.549us	5	5	100.00
		rom_ctrl_tl_intg_err	1.858m	856.802us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.420m	195.549us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.420m	195.549us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.420m	195.549us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	14.110s	2.012ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	14.110s	2.012ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	14.110s	2.012ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.858m	856.802us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
		rom_ctrl_kmac_err_chk	23.940s	981.686us	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.149m	3.781ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	59.440s	3.071ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.420m	195.549us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.214h	38.039ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			427	460	92.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	96.89	91.85	97.67	100.00	98.28	97.45	98.37

Failure Buckets

Job timed out after * minutes has 18 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 18 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.44442120208095296880958594741450380101344517678855598475534638660481121401220
    Log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 2.rom_ctrl_stress_all_with_rand_reset.56859953021880252844400375629801261473897344072552198906789024426157133898025
    Log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 16 more failures.
UVM_ERROR (rom_ctrl_base_vseq.sv:95) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 7.rom_ctrl_stress_all_with_rand_reset.114480145422237366463599205778111372187385380884469506475781817411698954405262
    Line 525, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45005389586 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 45005389586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rom_ctrl_stress_all_with_rand_reset.54984855375232846691576208176150444750036026861241601898474171248303348652480
    Line 242, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17415147586 ps: (rom_ctrl_base_vseq.sv:95) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 17415147586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.81746278011186331961506857646537817007631189202842517973152245322876355962385
    Line 960, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 63100264941 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 63100264941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.rom_ctrl_stress_all_with_rand_reset.65173374380303201610086961792914895292572282182550227960382563720816806399669
    Line 143, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 25719832097 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 25719832097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.110400756039594008877854764655062808998439795149078189997116145147888731704646
    Line 159, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8867287978 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8867287978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rom_ctrl_stress_all_with_rand_reset.92274925594229815507889129367375239712237364591351446020246422876499450548090
    Line 67, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105046375 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105046375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:254) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 3.rom_ctrl_corrupt_sig_fatal_chk.59485708973833498636767630829461747845848335365836700159866919216916306686180
    Line 91, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 22258376450 ps: (rom_ctrl_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 22258376450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_base_vseq.sv:91) [rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 23.rom_ctrl_stress_all_with_rand_reset.45179003216220901546213318313521482752096953820729394081718432886757662013562
    Line 210, in log /workspaces/repo/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13436715961 ps: (rom_ctrl_base_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 13436715961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9f20940d49`