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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 96.97 93.01 97.88 100.00 98.69 98.03 98.37


Total test records in report: 464
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T306 /workspace/coverage/default/25.rom_ctrl_alert_test.666686482 Apr 23 02:12:56 PM PDT 24 Apr 23 02:13:01 PM PDT 24 89290609 ps
T307 /workspace/coverage/default/46.rom_ctrl_smoke.1182848000 Apr 23 02:13:40 PM PDT 24 Apr 23 02:14:14 PM PDT 24 4060953112 ps
T308 /workspace/coverage/default/39.rom_ctrl_alert_test.3512206133 Apr 23 02:13:30 PM PDT 24 Apr 23 02:13:46 PM PDT 24 7902821348 ps
T309 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.46698890 Apr 23 02:13:26 PM PDT 24 Apr 23 02:13:32 PM PDT 24 918284080 ps
T310 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1657142309 Apr 23 02:13:16 PM PDT 24 Apr 23 02:13:33 PM PDT 24 9155448956 ps
T311 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3058822591 Apr 23 02:12:43 PM PDT 24 Apr 23 02:12:59 PM PDT 24 1870197203 ps
T312 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3060445124 Apr 23 02:12:44 PM PDT 24 Apr 23 02:14:43 PM PDT 24 1755760066 ps
T313 /workspace/coverage/default/31.rom_ctrl_stress_all.3296638500 Apr 23 02:13:12 PM PDT 24 Apr 23 02:13:36 PM PDT 24 1885176454 ps
T314 /workspace/coverage/default/8.rom_ctrl_alert_test.778527196 Apr 23 02:12:34 PM PDT 24 Apr 23 02:12:46 PM PDT 24 2060673379 ps
T315 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1160498592 Apr 23 02:13:11 PM PDT 24 Apr 23 02:13:20 PM PDT 24 785822939 ps
T316 /workspace/coverage/default/42.rom_ctrl_smoke.2956063705 Apr 23 02:13:31 PM PDT 24 Apr 23 02:14:07 PM PDT 24 17507281954 ps
T317 /workspace/coverage/default/31.rom_ctrl_alert_test.2943440965 Apr 23 02:13:12 PM PDT 24 Apr 23 02:13:28 PM PDT 24 8103272089 ps
T318 /workspace/coverage/default/40.rom_ctrl_smoke.2921679098 Apr 23 02:13:28 PM PDT 24 Apr 23 02:13:39 PM PDT 24 184441883 ps
T319 /workspace/coverage/default/49.rom_ctrl_stress_all.26451407 Apr 23 02:13:45 PM PDT 24 Apr 23 02:14:20 PM PDT 24 26059868519 ps
T320 /workspace/coverage/default/31.rom_ctrl_smoke.100081003 Apr 23 02:13:11 PM PDT 24 Apr 23 02:13:33 PM PDT 24 1984852161 ps
T321 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.156389953 Apr 23 02:12:49 PM PDT 24 Apr 23 02:13:00 PM PDT 24 667441350 ps
T322 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4234715279 Apr 23 02:13:31 PM PDT 24 Apr 23 02:13:48 PM PDT 24 8351517107 ps
T323 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.732076415 Apr 23 02:12:41 PM PDT 24 Apr 23 02:12:59 PM PDT 24 26330948593 ps
T324 /workspace/coverage/default/45.rom_ctrl_alert_test.3102160203 Apr 23 02:13:38 PM PDT 24 Apr 23 02:13:43 PM PDT 24 85721097 ps
T325 /workspace/coverage/default/47.rom_ctrl_alert_test.2181290713 Apr 23 02:13:42 PM PDT 24 Apr 23 02:13:47 PM PDT 24 87458846 ps
T326 /workspace/coverage/default/43.rom_ctrl_smoke.1218758011 Apr 23 02:13:33 PM PDT 24 Apr 23 02:14:11 PM PDT 24 19688684832 ps
T327 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4098499482 Apr 23 02:12:39 PM PDT 24 Apr 23 02:12:53 PM PDT 24 578862197 ps
T328 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.761013181 Apr 23 02:12:42 PM PDT 24 Apr 23 02:13:11 PM PDT 24 3476197842 ps
T329 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.509212391 Apr 23 02:12:33 PM PDT 24 Apr 23 02:15:12 PM PDT 24 37922426350 ps
T330 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.204206878 Apr 23 02:13:29 PM PDT 24 Apr 23 02:16:40 PM PDT 24 87161981110 ps
T331 /workspace/coverage/default/11.rom_ctrl_smoke.2037754166 Apr 23 02:12:36 PM PDT 24 Apr 23 02:13:11 PM PDT 24 11015488243 ps
T332 /workspace/coverage/default/4.rom_ctrl_alert_test.1438459986 Apr 23 02:12:31 PM PDT 24 Apr 23 02:12:44 PM PDT 24 9953593999 ps
T333 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.425327626 Apr 23 02:13:22 PM PDT 24 Apr 23 02:13:38 PM PDT 24 7724070569 ps
T334 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1183663611 Apr 23 02:12:29 PM PDT 24 Apr 23 02:12:43 PM PDT 24 4968561892 ps
T335 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.216632992 Apr 23 02:13:33 PM PDT 24 Apr 23 02:13:47 PM PDT 24 1207260603 ps
T336 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2088245418 Apr 23 02:13:44 PM PDT 24 Apr 23 02:14:17 PM PDT 24 8142109604 ps
T337 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3268248326 Apr 23 02:13:00 PM PDT 24 Apr 23 02:13:31 PM PDT 24 72127580539 ps
T338 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2234212968 Apr 23 02:13:18 PM PDT 24 Apr 23 02:13:24 PM PDT 24 382276540 ps
T339 /workspace/coverage/default/48.rom_ctrl_alert_test.4112597861 Apr 23 02:13:44 PM PDT 24 Apr 23 02:13:57 PM PDT 24 1449704193 ps
T21 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2871261809 Apr 23 02:12:34 PM PDT 24 Apr 23 02:12:51 PM PDT 24 5010659499 ps
T340 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1108112189 Apr 23 02:12:57 PM PDT 24 Apr 23 02:13:27 PM PDT 24 7368656612 ps
T341 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3051102350 Apr 23 02:13:25 PM PDT 24 Apr 23 02:13:35 PM PDT 24 692335882 ps
T342 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3020717418 Apr 23 02:13:11 PM PDT 24 Apr 23 02:13:21 PM PDT 24 584945396 ps
T343 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1609478924 Apr 23 02:12:37 PM PDT 24 Apr 23 02:13:11 PM PDT 24 4092342662 ps
T344 /workspace/coverage/default/3.rom_ctrl_stress_all.1066521485 Apr 23 02:12:26 PM PDT 24 Apr 23 02:12:58 PM PDT 24 586420867 ps
T345 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.605794917 Apr 23 02:13:21 PM PDT 24 Apr 23 02:14:57 PM PDT 24 2891907815 ps
T346 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1575341340 Apr 23 02:12:39 PM PDT 24 Apr 23 02:14:19 PM PDT 24 37612961030 ps
T347 /workspace/coverage/default/32.rom_ctrl_alert_test.82181324 Apr 23 02:13:15 PM PDT 24 Apr 23 02:13:30 PM PDT 24 19383620350 ps
T348 /workspace/coverage/default/18.rom_ctrl_stress_all.3852598011 Apr 23 02:13:00 PM PDT 24 Apr 23 02:13:25 PM PDT 24 4500950329 ps
T349 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1539635063 Apr 23 02:13:26 PM PDT 24 Apr 23 02:15:41 PM PDT 24 3718179448 ps
T350 /workspace/coverage/default/6.rom_ctrl_alert_test.1596215873 Apr 23 02:12:32 PM PDT 24 Apr 23 02:12:36 PM PDT 24 89941143 ps
T351 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4181516966 Apr 23 02:12:55 PM PDT 24 Apr 23 02:17:27 PM PDT 24 30841915610 ps
T32 /workspace/coverage/default/4.rom_ctrl_sec_cm.1715232840 Apr 23 02:12:34 PM PDT 24 Apr 23 02:13:28 PM PDT 24 215666447 ps
T352 /workspace/coverage/default/13.rom_ctrl_stress_all.1023408463 Apr 23 02:12:41 PM PDT 24 Apr 23 02:12:52 PM PDT 24 3779942633 ps
T353 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3310125237 Apr 23 02:13:17 PM PDT 24 Apr 23 02:13:44 PM PDT 24 2880810955 ps
T354 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4225589876 Apr 23 02:13:03 PM PDT 24 Apr 23 02:15:59 PM PDT 24 34755818406 ps
T355 /workspace/coverage/default/35.rom_ctrl_smoke.2821249323 Apr 23 02:13:20 PM PDT 24 Apr 23 02:13:35 PM PDT 24 4197859552 ps
T356 /workspace/coverage/default/14.rom_ctrl_stress_all.3912620587 Apr 23 02:12:43 PM PDT 24 Apr 23 02:13:16 PM PDT 24 12102216632 ps
T357 /workspace/coverage/default/34.rom_ctrl_stress_all.2185111215 Apr 23 02:13:19 PM PDT 24 Apr 23 02:14:56 PM PDT 24 23117167403 ps
T358 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.586651769 Apr 23 02:12:28 PM PDT 24 Apr 23 03:13:01 PM PDT 24 95073315353 ps
T359 /workspace/coverage/default/10.rom_ctrl_stress_all.778371319 Apr 23 02:12:38 PM PDT 24 Apr 23 02:14:00 PM PDT 24 7631608661 ps
T360 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2893222179 Apr 23 02:13:38 PM PDT 24 Apr 23 02:13:55 PM PDT 24 4243574587 ps
T361 /workspace/coverage/default/19.rom_ctrl_stress_all.762849467 Apr 23 02:13:01 PM PDT 24 Apr 23 02:13:21 PM PDT 24 3955520415 ps
T362 /workspace/coverage/default/15.rom_ctrl_stress_all.2774193473 Apr 23 02:12:42 PM PDT 24 Apr 23 02:13:07 PM PDT 24 1920539028 ps
T363 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.258486029 Apr 23 02:13:32 PM PDT 24 Apr 23 02:14:03 PM PDT 24 3659819106 ps
T364 /workspace/coverage/default/1.rom_ctrl_smoke.3932764438 Apr 23 02:12:30 PM PDT 24 Apr 23 02:12:57 PM PDT 24 4449617785 ps
T365 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3069548026 Apr 23 02:13:47 PM PDT 24 Apr 23 02:16:42 PM PDT 24 58481650141 ps
T366 /workspace/coverage/default/32.rom_ctrl_smoke.1981378308 Apr 23 02:13:14 PM PDT 24 Apr 23 02:13:26 PM PDT 24 4406038542 ps
T367 /workspace/coverage/default/10.rom_ctrl_smoke.1363090717 Apr 23 02:12:36 PM PDT 24 Apr 23 02:13:09 PM PDT 24 13536364376 ps
T368 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.188891199 Apr 23 02:12:37 PM PDT 24 Apr 23 02:12:44 PM PDT 24 99096458 ps
T369 /workspace/coverage/default/43.rom_ctrl_alert_test.561633266 Apr 23 02:13:42 PM PDT 24 Apr 23 02:13:58 PM PDT 24 5579395456 ps
T370 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2788758598 Apr 23 02:12:50 PM PDT 24 Apr 23 02:15:23 PM PDT 24 2691444845 ps
T371 /workspace/coverage/default/39.rom_ctrl_smoke.3328994200 Apr 23 02:13:30 PM PDT 24 Apr 23 02:13:53 PM PDT 24 7904405908 ps
T372 /workspace/coverage/default/41.rom_ctrl_stress_all.4169698474 Apr 23 02:13:31 PM PDT 24 Apr 23 02:13:52 PM PDT 24 2526863337 ps
T373 /workspace/coverage/default/25.rom_ctrl_smoke.3744102606 Apr 23 02:12:55 PM PDT 24 Apr 23 02:13:26 PM PDT 24 3863992262 ps
T54 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3934977538 Apr 23 01:09:14 PM PDT 24 Apr 23 01:10:30 PM PDT 24 1452172452 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1003324069 Apr 23 01:08:53 PM PDT 24 Apr 23 01:08:58 PM PDT 24 91745794 ps
T55 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1316479824 Apr 23 01:09:06 PM PDT 24 Apr 23 01:09:53 PM PDT 24 2013988870 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2250867384 Apr 23 01:09:12 PM PDT 24 Apr 23 01:09:17 PM PDT 24 332591937 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.320360834 Apr 23 01:09:01 PM PDT 24 Apr 23 01:09:09 PM PDT 24 1256870670 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3224831030 Apr 23 01:09:24 PM PDT 24 Apr 23 01:09:34 PM PDT 24 429138539 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.979314996 Apr 23 01:09:29 PM PDT 24 Apr 23 01:09:42 PM PDT 24 9736650386 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3353582829 Apr 23 01:08:58 PM PDT 24 Apr 23 01:09:04 PM PDT 24 342978806 ps
T108 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2658699324 Apr 23 01:08:48 PM PDT 24 Apr 23 01:08:58 PM PDT 24 2266971665 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.845843357 Apr 23 01:08:54 PM PDT 24 Apr 23 01:09:11 PM PDT 24 7302610937 ps
T56 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2474340561 Apr 23 01:08:50 PM PDT 24 Apr 23 01:10:03 PM PDT 24 1010905461 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1768572749 Apr 23 01:08:47 PM PDT 24 Apr 23 01:08:52 PM PDT 24 297710083 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1356992512 Apr 23 01:09:12 PM PDT 24 Apr 23 01:09:23 PM PDT 24 3759677490 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2846279380 Apr 23 01:09:03 PM PDT 24 Apr 23 01:09:18 PM PDT 24 3051968095 ps
T380 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3333643478 Apr 23 01:09:06 PM PDT 24 Apr 23 01:09:23 PM PDT 24 1540268970 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4124157239 Apr 23 01:09:03 PM PDT 24 Apr 23 01:09:14 PM PDT 24 951326492 ps
T120 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2245287830 Apr 23 01:08:48 PM PDT 24 Apr 23 01:09:38 PM PDT 24 2321662072 ps
T66 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2498185238 Apr 23 01:08:46 PM PDT 24 Apr 23 01:09:01 PM PDT 24 1285124572 ps
T121 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4138897072 Apr 23 01:09:19 PM PDT 24 Apr 23 01:10:34 PM PDT 24 2905709317 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3522948181 Apr 23 01:08:55 PM PDT 24 Apr 23 01:09:05 PM PDT 24 5691125688 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.999283217 Apr 23 01:08:42 PM PDT 24 Apr 23 01:08:48 PM PDT 24 304579126 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.66315135 Apr 23 01:09:13 PM PDT 24 Apr 23 01:09:30 PM PDT 24 8006826772 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1950841362 Apr 23 01:09:00 PM PDT 24 Apr 23 01:09:12 PM PDT 24 4640192714 ps
T68 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3320784467 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:25 PM PDT 24 9038768377 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4244523849 Apr 23 01:08:43 PM PDT 24 Apr 23 01:08:59 PM PDT 24 1806861757 ps
T126 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4070066731 Apr 23 01:09:12 PM PDT 24 Apr 23 01:09:58 PM PDT 24 1446475892 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3708925296 Apr 23 01:08:44 PM PDT 24 Apr 23 01:09:01 PM PDT 24 2725969037 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3895534454 Apr 23 01:08:42 PM PDT 24 Apr 23 01:09:00 PM PDT 24 5949799279 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4030222029 Apr 23 01:09:28 PM PDT 24 Apr 23 01:09:40 PM PDT 24 2404288635 ps
T386 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.420625350 Apr 23 01:09:19 PM PDT 24 Apr 23 01:09:34 PM PDT 24 861657183 ps
T69 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4253335107 Apr 23 01:09:08 PM PDT 24 Apr 23 01:09:27 PM PDT 24 745681125 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3214595163 Apr 23 01:08:43 PM PDT 24 Apr 23 01:08:59 PM PDT 24 2055503043 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3036926143 Apr 23 01:09:00 PM PDT 24 Apr 23 01:09:10 PM PDT 24 353630016 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3232043071 Apr 23 01:08:44 PM PDT 24 Apr 23 01:08:57 PM PDT 24 6606470701 ps
T70 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.880723747 Apr 23 01:09:00 PM PDT 24 Apr 23 01:09:14 PM PDT 24 7008821453 ps
T390 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.828974947 Apr 23 01:09:01 PM PDT 24 Apr 23 01:09:21 PM PDT 24 1935626011 ps
T71 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2601156506 Apr 23 01:09:06 PM PDT 24 Apr 23 01:09:22 PM PDT 24 1784502219 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1031956199 Apr 23 01:08:55 PM PDT 24 Apr 23 01:09:09 PM PDT 24 1328198923 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2550331299 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:03 PM PDT 24 3968637541 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4113980302 Apr 23 01:09:04 PM PDT 24 Apr 23 01:09:11 PM PDT 24 88231429 ps
T73 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2999847518 Apr 23 01:09:00 PM PDT 24 Apr 23 01:09:12 PM PDT 24 763721748 ps
T393 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3257241708 Apr 23 01:08:48 PM PDT 24 Apr 23 01:08:56 PM PDT 24 194414150 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.765905127 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:08 PM PDT 24 15737363907 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.278966835 Apr 23 01:09:09 PM PDT 24 Apr 23 01:09:21 PM PDT 24 1211327174 ps
T395 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2671340084 Apr 23 01:09:01 PM PDT 24 Apr 23 01:10:17 PM PDT 24 8270301763 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3959564176 Apr 23 01:08:50 PM PDT 24 Apr 23 01:09:06 PM PDT 24 1144604157 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1897026971 Apr 23 01:08:46 PM PDT 24 Apr 23 01:08:55 PM PDT 24 1793187676 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2310661406 Apr 23 01:09:09 PM PDT 24 Apr 23 01:10:32 PM PDT 24 37587106361 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3044342906 Apr 23 01:08:56 PM PDT 24 Apr 23 01:09:06 PM PDT 24 839070399 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2033765423 Apr 23 01:09:20 PM PDT 24 Apr 23 01:09:38 PM PDT 24 8236968830 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2264774778 Apr 23 01:09:14 PM PDT 24 Apr 23 01:10:31 PM PDT 24 9611049890 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.668964635 Apr 23 01:08:55 PM PDT 24 Apr 23 01:09:11 PM PDT 24 1685513744 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1829958574 Apr 23 01:09:15 PM PDT 24 Apr 23 01:09:22 PM PDT 24 424985558 ps
T82 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3534249403 Apr 23 01:09:12 PM PDT 24 Apr 23 01:09:26 PM PDT 24 1538144036 ps
T404 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.878571619 Apr 23 01:09:01 PM PDT 24 Apr 23 01:09:13 PM PDT 24 1801934613 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3123671742 Apr 23 01:09:19 PM PDT 24 Apr 23 01:09:25 PM PDT 24 103148580 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.498585659 Apr 23 01:09:05 PM PDT 24 Apr 23 01:09:21 PM PDT 24 7736612108 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1168164529 Apr 23 01:08:58 PM PDT 24 Apr 23 01:09:15 PM PDT 24 10246233956 ps
T117 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3422932198 Apr 23 01:09:00 PM PDT 24 Apr 23 01:09:20 PM PDT 24 388258738 ps
T124 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3702425128 Apr 23 01:08:44 PM PDT 24 Apr 23 01:09:32 PM PDT 24 2092794778 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2684699229 Apr 23 01:08:56 PM PDT 24 Apr 23 01:09:08 PM PDT 24 1168876578 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4073873153 Apr 23 01:08:51 PM PDT 24 Apr 23 01:09:09 PM PDT 24 8435008155 ps
T410 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.646703287 Apr 23 01:09:18 PM PDT 24 Apr 23 01:09:32 PM PDT 24 1696310530 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2278557840 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:00 PM PDT 24 2764575463 ps
T122 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3744567461 Apr 23 01:09:04 PM PDT 24 Apr 23 01:09:49 PM PDT 24 6018350777 ps
T125 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1955276730 Apr 23 01:09:28 PM PDT 24 Apr 23 01:10:06 PM PDT 24 229338276 ps
T127 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2686693372 Apr 23 01:08:58 PM PDT 24 Apr 23 01:09:37 PM PDT 24 1580519230 ps
T128 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3228796886 Apr 23 01:08:58 PM PDT 24 Apr 23 01:10:17 PM PDT 24 15697628117 ps
T118 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3225885333 Apr 23 01:08:57 PM PDT 24 Apr 23 01:09:28 PM PDT 24 8303852430 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.225543358 Apr 23 01:08:59 PM PDT 24 Apr 23 01:09:05 PM PDT 24 89160401 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.955635015 Apr 23 01:08:41 PM PDT 24 Apr 23 01:08:46 PM PDT 24 87223726 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3004034440 Apr 23 01:08:59 PM PDT 24 Apr 23 01:09:15 PM PDT 24 6447490951 ps
T415 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2967609211 Apr 23 01:09:07 PM PDT 24 Apr 23 01:09:25 PM PDT 24 1408905442 ps
T416 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2297973405 Apr 23 01:09:06 PM PDT 24 Apr 23 01:09:12 PM PDT 24 383799329 ps
T129 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1791974292 Apr 23 01:09:16 PM PDT 24 Apr 23 01:10:29 PM PDT 24 1244578600 ps
T417 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.110719566 Apr 23 01:09:27 PM PDT 24 Apr 23 01:09:39 PM PDT 24 1453118459 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2769556683 Apr 23 01:09:09 PM PDT 24 Apr 23 01:09:23 PM PDT 24 5593784320 ps
T418 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.76624725 Apr 23 01:09:30 PM PDT 24 Apr 23 01:09:45 PM PDT 24 8609413998 ps
T419 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4185450755 Apr 23 01:09:03 PM PDT 24 Apr 23 01:09:11 PM PDT 24 479367854 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.755030256 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:00 PM PDT 24 102176709 ps
T420 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.177518702 Apr 23 01:09:16 PM PDT 24 Apr 23 01:10:04 PM PDT 24 10971049332 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1826124762 Apr 23 01:08:56 PM PDT 24 Apr 23 01:09:13 PM PDT 24 2458385276 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4050623653 Apr 23 01:08:57 PM PDT 24 Apr 23 01:09:11 PM PDT 24 1485540840 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3568961074 Apr 23 01:08:47 PM PDT 24 Apr 23 01:09:01 PM PDT 24 6496515233 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2985660618 Apr 23 01:08:59 PM PDT 24 Apr 23 01:09:15 PM PDT 24 3420573532 ps
T85 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3682292833 Apr 23 01:09:03 PM PDT 24 Apr 23 01:10:09 PM PDT 24 6526103654 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1858450092 Apr 23 01:09:19 PM PDT 24 Apr 23 01:09:36 PM PDT 24 1657533651 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1833719343 Apr 23 01:08:42 PM PDT 24 Apr 23 01:08:56 PM PDT 24 2009739470 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.283266436 Apr 23 01:08:54 PM PDT 24 Apr 23 01:09:03 PM PDT 24 424177908 ps
T119 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2705262658 Apr 23 01:08:51 PM PDT 24 Apr 23 01:09:26 PM PDT 24 1074971075 ps
T427 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1208937008 Apr 23 01:09:10 PM PDT 24 Apr 23 01:09:25 PM PDT 24 1945709599 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4084759879 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:02 PM PDT 24 1010525440 ps
T429 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3620337034 Apr 23 01:08:59 PM PDT 24 Apr 23 01:09:05 PM PDT 24 362674185 ps
T87 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2846209211 Apr 23 01:09:06 PM PDT 24 Apr 23 01:09:55 PM PDT 24 4992963367 ps
T430 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2197392586 Apr 23 01:08:56 PM PDT 24 Apr 23 01:09:13 PM PDT 24 15341980317 ps
T431 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1762595508 Apr 23 01:09:20 PM PDT 24 Apr 23 01:09:24 PM PDT 24 168725281 ps
T432 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.733095807 Apr 23 01:09:09 PM PDT 24 Apr 23 01:09:24 PM PDT 24 9559990667 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1260890408 Apr 23 01:09:14 PM PDT 24 Apr 23 01:09:25 PM PDT 24 946063830 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3796945115 Apr 23 01:09:14 PM PDT 24 Apr 23 01:09:27 PM PDT 24 2727029706 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2554549597 Apr 23 01:08:46 PM PDT 24 Apr 23 01:09:14 PM PDT 24 567942990 ps
T130 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3195860719 Apr 23 01:09:16 PM PDT 24 Apr 23 01:10:04 PM PDT 24 4138440343 ps
T435 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2178262258 Apr 23 01:09:22 PM PDT 24 Apr 23 01:10:49 PM PDT 24 10087523798 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4081296297 Apr 23 01:08:55 PM PDT 24 Apr 23 01:09:11 PM PDT 24 1902919672 ps
T98 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3446572089 Apr 23 01:08:59 PM PDT 24 Apr 23 01:10:18 PM PDT 24 127043578482 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1109258724 Apr 23 01:09:19 PM PDT 24 Apr 23 01:09:26 PM PDT 24 3446490386 ps
T131 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1694621779 Apr 23 01:09:25 PM PDT 24 Apr 23 01:10:39 PM PDT 24 2158078416 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3728968367 Apr 23 01:09:27 PM PDT 24 Apr 23 01:09:33 PM PDT 24 96045027 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3533096095 Apr 23 01:08:59 PM PDT 24 Apr 23 01:09:05 PM PDT 24 346391266 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.882860317 Apr 23 01:09:16 PM PDT 24 Apr 23 01:09:21 PM PDT 24 175448149 ps
T95 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3341914428 Apr 23 01:09:30 PM PDT 24 Apr 23 01:10:45 PM PDT 24 32911543642 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.997039631 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:10 PM PDT 24 4274459143 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3420926334 Apr 23 01:09:01 PM PDT 24 Apr 23 01:09:16 PM PDT 24 7243057237 ps
T442 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1091927548 Apr 23 01:09:00 PM PDT 24 Apr 23 01:09:46 PM PDT 24 1659210015 ps
T132 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.954672399 Apr 23 01:09:04 PM PDT 24 Apr 23 01:10:17 PM PDT 24 745778638 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.97376330 Apr 23 01:09:07 PM PDT 24 Apr 23 01:09:12 PM PDT 24 690064476 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.79683276 Apr 23 01:08:45 PM PDT 24 Apr 23 01:08:57 PM PDT 24 1115633315 ps
T91 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3175697114 Apr 23 01:08:59 PM PDT 24 Apr 23 01:09:10 PM PDT 24 21408499037 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4287186031 Apr 23 01:08:37 PM PDT 24 Apr 23 01:08:42 PM PDT 24 1186569375 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2937479921 Apr 23 01:08:50 PM PDT 24 Apr 23 01:08:55 PM PDT 24 333316500 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3068409438 Apr 23 01:08:38 PM PDT 24 Apr 23 01:08:55 PM PDT 24 1191097189 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1502026939 Apr 23 01:09:13 PM PDT 24 Apr 23 01:09:17 PM PDT 24 347023871 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1153095206 Apr 23 01:08:56 PM PDT 24 Apr 23 01:09:01 PM PDT 24 333601518 ps
T450 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.468999413 Apr 23 01:09:14 PM PDT 24 Apr 23 01:09:29 PM PDT 24 3413979941 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3921391976 Apr 23 01:08:48 PM PDT 24 Apr 23 01:09:04 PM PDT 24 8168881998 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2732888910 Apr 23 01:08:44 PM PDT 24 Apr 23 01:09:40 PM PDT 24 6224345914 ps
T452 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1128720783 Apr 23 01:09:08 PM PDT 24 Apr 23 01:09:26 PM PDT 24 3330188748 ps
T453 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1165105617 Apr 23 01:09:11 PM PDT 24 Apr 23 01:09:22 PM PDT 24 3425690158 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4029731379 Apr 23 01:08:49 PM PDT 24 Apr 23 01:09:05 PM PDT 24 1766784931 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1163304607 Apr 23 01:08:56 PM PDT 24 Apr 23 01:10:16 PM PDT 24 9184377617 ps
T456 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2952286843 Apr 23 01:09:30 PM PDT 24 Apr 23 01:09:49 PM PDT 24 2121002836 ps
T457 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3722900618 Apr 23 01:09:07 PM PDT 24 Apr 23 01:09:14 PM PDT 24 1325453278 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1998183604 Apr 23 01:08:52 PM PDT 24 Apr 23 01:09:03 PM PDT 24 5461701878 ps
T123 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3838433708 Apr 23 01:08:36 PM PDT 24 Apr 23 01:09:52 PM PDT 24 1508851236 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.700700051 Apr 23 01:09:10 PM PDT 24 Apr 23 01:09:41 PM PDT 24 6664677024 ps
T458 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3505395812 Apr 23 01:08:55 PM PDT 24 Apr 23 01:09:08 PM PDT 24 1386508113 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2611868517 Apr 23 01:08:37 PM PDT 24 Apr 23 01:09:09 PM PDT 24 8289681469 ps
T459 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2249696075 Apr 23 01:09:11 PM PDT 24 Apr 23 01:10:56 PM PDT 24 53226391695 ps
T460 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2300351514 Apr 23 01:09:30 PM PDT 24 Apr 23 01:09:38 PM PDT 24 2690489568 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1616890058 Apr 23 01:08:46 PM PDT 24 Apr 23 01:08:58 PM PDT 24 1807212380 ps
T461 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1794588522 Apr 23 01:09:21 PM PDT 24 Apr 23 01:09:35 PM PDT 24 6457098220 ps
T97 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.519492537 Apr 23 01:09:00 PM PDT 24 Apr 23 01:10:09 PM PDT 24 48548950883 ps
T462 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1540444628 Apr 23 01:09:06 PM PDT 24 Apr 23 01:10:24 PM PDT 24 3694480935 ps
T463 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3818997183 Apr 23 01:08:56 PM PDT 24 Apr 23 01:09:35 PM PDT 24 1784806773 ps
T464 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.656919315 Apr 23 01:09:15 PM PDT 24 Apr 23 01:09:27 PM PDT 24 1239327362 ps

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2933224322
Short name T6
Test name
Test status
Simulation time 15054499223 ps
CPU time 2490.72 seconds
Started Apr 23 02:12:32 PM PDT 24
Finished Apr 23 02:54:03 PM PDT 24
Peak memory 225356 kb
Host smart-9720b269-4a11-4ddd-8a2e-46fe7a3767c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933224322 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2933224322
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.946463205
Short name T12
Test name
Test status
Simulation time 63261398220 ps
CPU time 575.06 seconds
Started Apr 23 02:13:41 PM PDT 24
Finished Apr 23 02:23:17 PM PDT 24
Peak memory 233292 kb
Host smart-80f4e9bd-f289-498f-93d3-c6a5f45cbe9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946463205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.946463205
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1191180361
Short name T20
Test name
Test status
Simulation time 58879604386 ps
CPU time 309.07 seconds
Started Apr 23 02:13:45 PM PDT 24
Finished Apr 23 02:18:55 PM PDT 24
Peak memory 236388 kb
Host smart-b2a093af-8e16-45d2-b71a-3099bfd8a920
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191180361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1191180361
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4138897072
Short name T121
Test name
Test status
Simulation time 2905709317 ps
CPU time 74.65 seconds
Started Apr 23 01:09:19 PM PDT 24
Finished Apr 23 01:10:34 PM PDT 24
Peak memory 211032 kb
Host smart-0e1bc18c-acad-4cae-962f-19545597ca50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138897072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4138897072
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4054963508
Short name T27
Test name
Test status
Simulation time 1736889187 ps
CPU time 106.33 seconds
Started Apr 23 02:12:26 PM PDT 24
Finished Apr 23 02:14:13 PM PDT 24
Peak memory 238528 kb
Host smart-96378b9e-e137-4c34-9733-b40be12952c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054963508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4054963508
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3838433708
Short name T123
Test name
Test status
Simulation time 1508851236 ps
CPU time 75.25 seconds
Started Apr 23 01:08:36 PM PDT 24
Finished Apr 23 01:09:52 PM PDT 24
Peak memory 211944 kb
Host smart-bcc45abb-aa8a-4364-84a2-655b6b33678d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838433708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3838433708
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.801589137
Short name T4
Test name
Test status
Simulation time 3510516012 ps
CPU time 14.87 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:12:55 PM PDT 24
Peak memory 211596 kb
Host smart-80ffef73-0663-4124-afc0-93f8d1a1c18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801589137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.801589137
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2846209211
Short name T87
Test name
Test status
Simulation time 4992963367 ps
CPU time 48.08 seconds
Started Apr 23 01:09:06 PM PDT 24
Finished Apr 23 01:09:55 PM PDT 24
Peak memory 210288 kb
Host smart-e0c59bbe-2f4b-4e38-a420-69eabc0f1144
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846209211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2846209211
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.167309346
Short name T77
Test name
Test status
Simulation time 8230377931 ps
CPU time 25.54 seconds
Started Apr 23 02:12:58 PM PDT 24
Finished Apr 23 02:13:25 PM PDT 24
Peak memory 214724 kb
Host smart-a789c6a0-2ebb-471a-90cf-a95673d36e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167309346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.167309346
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3818997183
Short name T463
Test name
Test status
Simulation time 1784806773 ps
CPU time 38.95 seconds
Started Apr 23 01:08:56 PM PDT 24
Finished Apr 23 01:09:35 PM PDT 24
Peak memory 210212 kb
Host smart-23d94696-658f-481b-98ff-08f47d74fad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818997183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3818997183
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2053983624
Short name T8
Test name
Test status
Simulation time 3669105448 ps
CPU time 30.33 seconds
Started Apr 23 02:13:32 PM PDT 24
Finished Apr 23 02:14:03 PM PDT 24
Peak memory 211992 kb
Host smart-699b9918-fdb7-4e2a-be6d-c74b6f3a7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053983624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2053983624
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3232980766
Short name T16
Test name
Test status
Simulation time 355376540 ps
CPU time 9.76 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:12:41 PM PDT 24
Peak memory 212076 kb
Host smart-4bc6739b-1e40-4d6e-8fa6-145e2bcf94e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232980766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3232980766
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2871261809
Short name T21
Test name
Test status
Simulation time 5010659499 ps
CPU time 15.69 seconds
Started Apr 23 02:12:34 PM PDT 24
Finished Apr 23 02:12:51 PM PDT 24
Peak memory 212340 kb
Host smart-4f48d927-5409-4afa-ac80-accbdedcefbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871261809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2871261809
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.999283217
Short name T67
Test name
Test status
Simulation time 304579126 ps
CPU time 6.2 seconds
Started Apr 23 01:08:42 PM PDT 24
Finished Apr 23 01:08:48 PM PDT 24
Peak memory 210240 kb
Host smart-b566174b-0edb-4270-8d3b-f0fe41fa1222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999283217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.999283217
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2611868517
Short name T93
Test name
Test status
Simulation time 8289681469 ps
CPU time 31.25 seconds
Started Apr 23 01:08:37 PM PDT 24
Finished Apr 23 01:09:09 PM PDT 24
Peak memory 210316 kb
Host smart-3c6f8f41-a366-4ff1-bd57-8ca6286ac9bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611868517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2611868517
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.864371628
Short name T11
Test name
Test status
Simulation time 34855233826 ps
CPU time 76.03 seconds
Started Apr 23 02:13:12 PM PDT 24
Finished Apr 23 02:14:29 PM PDT 24
Peak memory 217704 kb
Host smart-d185fdbb-9914-4619-981c-ecb2b3c8dc39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864371628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.864371628
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4070066731
Short name T126
Test name
Test status
Simulation time 1446475892 ps
CPU time 45.05 seconds
Started Apr 23 01:09:12 PM PDT 24
Finished Apr 23 01:09:58 PM PDT 24
Peak memory 210624 kb
Host smart-45e31c59-513c-432f-b34c-b6883a0fa222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070066731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4070066731
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1616890058
Short name T94
Test name
Test status
Simulation time 1807212380 ps
CPU time 11.98 seconds
Started Apr 23 01:08:46 PM PDT 24
Finished Apr 23 01:08:58 PM PDT 24
Peak memory 210132 kb
Host smart-4e16e6fc-da9d-4602-af70-1629835b7f6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616890058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1616890058
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3562384845
Short name T99
Test name
Test status
Simulation time 5893196763 ps
CPU time 14.24 seconds
Started Apr 23 02:13:03 PM PDT 24
Finished Apr 23 02:13:17 PM PDT 24
Peak memory 211384 kb
Host smart-9bb7226a-c45d-405e-9914-0523aa36bc9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562384845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3562384845
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2658699324
Short name T108
Test name
Test status
Simulation time 2266971665 ps
CPU time 9.52 seconds
Started Apr 23 01:08:48 PM PDT 24
Finished Apr 23 01:08:58 PM PDT 24
Peak memory 210260 kb
Host smart-a08ee8bc-2967-4ec4-ba91-40ad51255f8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658699324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2658699324
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3232043071
Short name T389
Test name
Test status
Simulation time 6606470701 ps
CPU time 12.49 seconds
Started Apr 23 01:08:44 PM PDT 24
Finished Apr 23 01:08:57 PM PDT 24
Peak memory 210212 kb
Host smart-dc19f151-0235-4ae2-a0b4-8367b291c363
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232043071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3232043071
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3214595163
Short name T387
Test name
Test status
Simulation time 2055503043 ps
CPU time 16.13 seconds
Started Apr 23 01:08:43 PM PDT 24
Finished Apr 23 01:08:59 PM PDT 24
Peak memory 210180 kb
Host smart-06c79e91-fc2a-4dff-a0af-c727474ed674
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214595163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3214595163
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3895534454
Short name T384
Test name
Test status
Simulation time 5949799279 ps
CPU time 17.49 seconds
Started Apr 23 01:08:42 PM PDT 24
Finished Apr 23 01:09:00 PM PDT 24
Peak memory 210184 kb
Host smart-3916b193-2899-47be-9ed8-6da56e92b5d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895534454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3895534454
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1833719343
Short name T426
Test name
Test status
Simulation time 2009739470 ps
CPU time 12.8 seconds
Started Apr 23 01:08:42 PM PDT 24
Finished Apr 23 01:08:56 PM PDT 24
Peak memory 218448 kb
Host smart-4c277243-cef8-410b-9976-abb2e5a29515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833719343 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1833719343
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.79683276
Short name T444
Test name
Test status
Simulation time 1115633315 ps
CPU time 10.63 seconds
Started Apr 23 01:08:45 PM PDT 24
Finished Apr 23 01:08:57 PM PDT 24
Peak memory 210128 kb
Host smart-97c4c3d2-1b9e-44b9-a9b3-ec52e6a6447f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79683276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.79683276
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4287186031
Short name T445
Test name
Test status
Simulation time 1186569375 ps
CPU time 4.22 seconds
Started Apr 23 01:08:37 PM PDT 24
Finished Apr 23 01:08:42 PM PDT 24
Peak memory 210056 kb
Host smart-3a1e8643-6a2a-47f8-baa3-a9a2a944e3ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287186031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4287186031
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.955635015
Short name T413
Test name
Test status
Simulation time 87223726 ps
CPU time 4.3 seconds
Started Apr 23 01:08:41 PM PDT 24
Finished Apr 23 01:08:46 PM PDT 24
Peak memory 210132 kb
Host smart-afd5b97d-e634-41cf-9ec5-5a448393a4bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955635015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
955635015
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3068409438
Short name T447
Test name
Test status
Simulation time 1191097189 ps
CPU time 16.38 seconds
Started Apr 23 01:08:38 PM PDT 24
Finished Apr 23 01:08:55 PM PDT 24
Peak memory 218536 kb
Host smart-eab0b224-322a-4398-a7d0-ca62058a6802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068409438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3068409438
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3921391976
Short name T451
Test name
Test status
Simulation time 8168881998 ps
CPU time 15.85 seconds
Started Apr 23 01:08:48 PM PDT 24
Finished Apr 23 01:09:04 PM PDT 24
Peak memory 210240 kb
Host smart-6a0d7251-462b-4d4f-8cf7-500fd21069ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921391976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3921391976
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2498185238
Short name T66
Test name
Test status
Simulation time 1285124572 ps
CPU time 14.51 seconds
Started Apr 23 01:08:46 PM PDT 24
Finished Apr 23 01:09:01 PM PDT 24
Peak memory 210172 kb
Host smart-97d28a30-dec0-4910-97b1-a9d622f723a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498185238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2498185238
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4029731379
Short name T454
Test name
Test status
Simulation time 1766784931 ps
CPU time 15.02 seconds
Started Apr 23 01:08:49 PM PDT 24
Finished Apr 23 01:09:05 PM PDT 24
Peak memory 213568 kb
Host smart-8d084ac3-f7b2-42eb-96b3-5be085f3b6c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029731379 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4029731379
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1768572749
Short name T109
Test name
Test status
Simulation time 297710083 ps
CPU time 4.15 seconds
Started Apr 23 01:08:47 PM PDT 24
Finished Apr 23 01:08:52 PM PDT 24
Peak memory 210180 kb
Host smart-fe3899f5-7ce5-4d13-994c-4cf222423293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768572749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1768572749
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1897026971
Short name T397
Test name
Test status
Simulation time 1793187676 ps
CPU time 8.4 seconds
Started Apr 23 01:08:46 PM PDT 24
Finished Apr 23 01:08:55 PM PDT 24
Peak memory 210124 kb
Host smart-5c30dbdb-7d86-4575-8f8e-8ee3d1b1962a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897026971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1897026971
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4244523849
Short name T382
Test name
Test status
Simulation time 1806861757 ps
CPU time 15.36 seconds
Started Apr 23 01:08:43 PM PDT 24
Finished Apr 23 01:08:59 PM PDT 24
Peak memory 210112 kb
Host smart-f448ec4a-c371-4e0b-ae75-387d29c710f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244523849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4244523849
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2732888910
Short name T96
Test name
Test status
Simulation time 6224345914 ps
CPU time 55.52 seconds
Started Apr 23 01:08:44 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 210308 kb
Host smart-df0c2452-0414-4eb1-8af4-41835ddb17c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732888910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2732888910
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3708925296
Short name T383
Test name
Test status
Simulation time 2725969037 ps
CPU time 16.84 seconds
Started Apr 23 01:08:44 PM PDT 24
Finished Apr 23 01:09:01 PM PDT 24
Peak memory 218484 kb
Host smart-160e125e-c0b6-441d-b30d-eb8ddeb91674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708925296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3708925296
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3702425128
Short name T124
Test name
Test status
Simulation time 2092794778 ps
CPU time 47.3 seconds
Started Apr 23 01:08:44 PM PDT 24
Finished Apr 23 01:09:32 PM PDT 24
Peak memory 211092 kb
Host smart-2b285ee1-5755-4c2c-ae1f-7fc8b0236fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702425128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3702425128
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2297973405
Short name T416
Test name
Test status
Simulation time 383799329 ps
CPU time 5.04 seconds
Started Apr 23 01:09:06 PM PDT 24
Finished Apr 23 01:09:12 PM PDT 24
Peak memory 218476 kb
Host smart-c7b77c16-72ef-4995-a345-da9d108a3e1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297973405 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2297973405
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4185450755
Short name T419
Test name
Test status
Simulation time 479367854 ps
CPU time 7.07 seconds
Started Apr 23 01:09:03 PM PDT 24
Finished Apr 23 01:09:11 PM PDT 24
Peak memory 210080 kb
Host smart-26c49edf-3996-4e00-87fe-48470e24a225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185450755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4185450755
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3682292833
Short name T85
Test name
Test status
Simulation time 6526103654 ps
CPU time 65.38 seconds
Started Apr 23 01:09:03 PM PDT 24
Finished Apr 23 01:10:09 PM PDT 24
Peak memory 210304 kb
Host smart-1fd8a16c-84af-4425-a8b5-a595e6e6351d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682292833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3682292833
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3722900618
Short name T457
Test name
Test status
Simulation time 1325453278 ps
CPU time 6.17 seconds
Started Apr 23 01:09:07 PM PDT 24
Finished Apr 23 01:09:14 PM PDT 24
Peak memory 210272 kb
Host smart-b2ed2359-2597-417f-ae94-6ae6629f1003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722900618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3722900618
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4113980302
Short name T392
Test name
Test status
Simulation time 88231429 ps
CPU time 6.69 seconds
Started Apr 23 01:09:04 PM PDT 24
Finished Apr 23 01:09:11 PM PDT 24
Peak memory 218492 kb
Host smart-1a70f0a3-92ff-4fe1-9507-605a7dbd57c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113980302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4113980302
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.954672399
Short name T132
Test name
Test status
Simulation time 745778638 ps
CPU time 71.51 seconds
Started Apr 23 01:09:04 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 210236 kb
Host smart-49d998ea-fcbd-4cca-aa52-ce176e3107ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954672399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.954672399
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.97376330
Short name T443
Test name
Test status
Simulation time 690064476 ps
CPU time 4.46 seconds
Started Apr 23 01:09:07 PM PDT 24
Finished Apr 23 01:09:12 PM PDT 24
Peak memory 212668 kb
Host smart-4e7c3294-357c-4c81-9366-3f895f02fc58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97376330 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.97376330
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.733095807
Short name T432
Test name
Test status
Simulation time 9559990667 ps
CPU time 14.52 seconds
Started Apr 23 01:09:09 PM PDT 24
Finished Apr 23 01:09:24 PM PDT 24
Peak memory 210248 kb
Host smart-4a8c9d14-e62e-4353-a465-d5ef4f729f69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733095807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.733095807
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4253335107
Short name T69
Test name
Test status
Simulation time 745681125 ps
CPU time 18.4 seconds
Started Apr 23 01:09:08 PM PDT 24
Finished Apr 23 01:09:27 PM PDT 24
Peak memory 210232 kb
Host smart-d1cf1a20-9423-48cb-9986-58f5f6f6c121
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253335107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4253335107
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.278966835
Short name T74
Test name
Test status
Simulation time 1211327174 ps
CPU time 11.52 seconds
Started Apr 23 01:09:09 PM PDT 24
Finished Apr 23 01:09:21 PM PDT 24
Peak memory 210232 kb
Host smart-e208e22a-5ec5-4a18-bbfd-afcca057c42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278966835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.278966835
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2967609211
Short name T415
Test name
Test status
Simulation time 1408905442 ps
CPU time 16.93 seconds
Started Apr 23 01:09:07 PM PDT 24
Finished Apr 23 01:09:25 PM PDT 24
Peak memory 218544 kb
Host smart-d115edd8-36d2-466d-886b-69d6b2437446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967609211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2967609211
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1540444628
Short name T462
Test name
Test status
Simulation time 3694480935 ps
CPU time 76.45 seconds
Started Apr 23 01:09:06 PM PDT 24
Finished Apr 23 01:10:24 PM PDT 24
Peak memory 211132 kb
Host smart-0126de1e-8127-49e0-af40-a6161fa618be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540444628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1540444628
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1356992512
Short name T378
Test name
Test status
Simulation time 3759677490 ps
CPU time 10.4 seconds
Started Apr 23 01:09:12 PM PDT 24
Finished Apr 23 01:09:23 PM PDT 24
Peak memory 218448 kb
Host smart-bd503d4b-c0b5-4343-b982-a4423115c6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356992512 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1356992512
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2769556683
Short name T83
Test name
Test status
Simulation time 5593784320 ps
CPU time 13.25 seconds
Started Apr 23 01:09:09 PM PDT 24
Finished Apr 23 01:09:23 PM PDT 24
Peak memory 210248 kb
Host smart-4648ff78-ee96-4ead-a3b6-54e03f7b9488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769556683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2769556683
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2601156506
Short name T71
Test name
Test status
Simulation time 1784502219 ps
CPU time 14.45 seconds
Started Apr 23 01:09:06 PM PDT 24
Finished Apr 23 01:09:22 PM PDT 24
Peak memory 210244 kb
Host smart-31658704-1363-453b-a14c-678fac3b521a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601156506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2601156506
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1128720783
Short name T452
Test name
Test status
Simulation time 3330188748 ps
CPU time 17.22 seconds
Started Apr 23 01:09:08 PM PDT 24
Finished Apr 23 01:09:26 PM PDT 24
Peak memory 218536 kb
Host smart-dc5d637f-5944-42a2-8aea-cd4193ecf2af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128720783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1128720783
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1316479824
Short name T55
Test name
Test status
Simulation time 2013988870 ps
CPU time 46.34 seconds
Started Apr 23 01:09:06 PM PDT 24
Finished Apr 23 01:09:53 PM PDT 24
Peak memory 210988 kb
Host smart-1277159d-8538-4296-b1cb-a5de3338168f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316479824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1316479824
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1208937008
Short name T427
Test name
Test status
Simulation time 1945709599 ps
CPU time 14.3 seconds
Started Apr 23 01:09:10 PM PDT 24
Finished Apr 23 01:09:25 PM PDT 24
Peak memory 218472 kb
Host smart-189d0842-9115-4481-aa84-6a5bbacfc155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208937008 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1208937008
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.882860317
Short name T439
Test name
Test status
Simulation time 175448149 ps
CPU time 4.12 seconds
Started Apr 23 01:09:16 PM PDT 24
Finished Apr 23 01:09:21 PM PDT 24
Peak memory 210204 kb
Host smart-4c799db4-d170-42d9-a0f7-d3fa720ab83e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882860317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.882860317
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2310661406
Short name T398
Test name
Test status
Simulation time 37587106361 ps
CPU time 82.1 seconds
Started Apr 23 01:09:09 PM PDT 24
Finished Apr 23 01:10:32 PM PDT 24
Peak memory 210256 kb
Host smart-8aa5ce28-6c0f-4561-9d77-0cc514a9a30f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310661406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2310661406
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.468999413
Short name T450
Test name
Test status
Simulation time 3413979941 ps
CPU time 13.91 seconds
Started Apr 23 01:09:14 PM PDT 24
Finished Apr 23 01:09:29 PM PDT 24
Peak memory 210308 kb
Host smart-18a70de8-e499-4866-9908-c50d8307804c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468999413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.468999413
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1165105617
Short name T453
Test name
Test status
Simulation time 3425690158 ps
CPU time 11.05 seconds
Started Apr 23 01:09:11 PM PDT 24
Finished Apr 23 01:09:22 PM PDT 24
Peak memory 218548 kb
Host smart-9436bd9e-a30a-498e-be6d-006c0e38a0f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165105617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1165105617
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3123671742
Short name T405
Test name
Test status
Simulation time 103148580 ps
CPU time 5.2 seconds
Started Apr 23 01:09:19 PM PDT 24
Finished Apr 23 01:09:25 PM PDT 24
Peak memory 218416 kb
Host smart-5c696f35-2476-493b-8389-faea84f36b66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123671742 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3123671742
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1502026939
Short name T448
Test name
Test status
Simulation time 347023871 ps
CPU time 4.2 seconds
Started Apr 23 01:09:13 PM PDT 24
Finished Apr 23 01:09:17 PM PDT 24
Peak memory 210088 kb
Host smart-02e59a68-00b1-42e3-9410-7d05979d7f3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502026939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1502026939
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2249696075
Short name T459
Test name
Test status
Simulation time 53226391695 ps
CPU time 104.32 seconds
Started Apr 23 01:09:11 PM PDT 24
Finished Apr 23 01:10:56 PM PDT 24
Peak memory 210344 kb
Host smart-79100280-0b09-42b8-ac66-2b2613614288
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249696075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2249696075
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1109258724
Short name T436
Test name
Test status
Simulation time 3446490386 ps
CPU time 6.94 seconds
Started Apr 23 01:09:19 PM PDT 24
Finished Apr 23 01:09:26 PM PDT 24
Peak memory 210268 kb
Host smart-7ca95789-b82c-4d5a-bf78-ce1390f12729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109258724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1109258724
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.420625350
Short name T386
Test name
Test status
Simulation time 861657183 ps
CPU time 14.61 seconds
Started Apr 23 01:09:19 PM PDT 24
Finished Apr 23 01:09:34 PM PDT 24
Peak memory 218488 kb
Host smart-069ab48a-36f1-487b-a712-2204931b24f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420625350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.420625350
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1829958574
Short name T403
Test name
Test status
Simulation time 424985558 ps
CPU time 6.19 seconds
Started Apr 23 01:09:15 PM PDT 24
Finished Apr 23 01:09:22 PM PDT 24
Peak memory 218424 kb
Host smart-d524a017-1f29-4c36-8503-fd471610b828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829958574 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1829958574
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3534249403
Short name T82
Test name
Test status
Simulation time 1538144036 ps
CPU time 13.35 seconds
Started Apr 23 01:09:12 PM PDT 24
Finished Apr 23 01:09:26 PM PDT 24
Peak memory 210232 kb
Host smart-7a8c49b5-5de0-4435-a794-433b8c3bdf43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534249403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3534249403
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.700700051
Short name T92
Test name
Test status
Simulation time 6664677024 ps
CPU time 29.68 seconds
Started Apr 23 01:09:10 PM PDT 24
Finished Apr 23 01:09:41 PM PDT 24
Peak memory 210348 kb
Host smart-280799cc-ece9-41bb-8f51-b7e488d22552
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700700051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.700700051
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2250867384
Short name T107
Test name
Test status
Simulation time 332591937 ps
CPU time 4.57 seconds
Started Apr 23 01:09:12 PM PDT 24
Finished Apr 23 01:09:17 PM PDT 24
Peak memory 210172 kb
Host smart-e1422b8a-40a9-4361-b9c0-5848ea8dfbc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250867384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2250867384
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1858450092
Short name T425
Test name
Test status
Simulation time 1657533651 ps
CPU time 16.63 seconds
Started Apr 23 01:09:19 PM PDT 24
Finished Apr 23 01:09:36 PM PDT 24
Peak memory 218380 kb
Host smart-e973fae1-5bb2-4d55-902f-d5237a8cc905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858450092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1858450092
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3934977538
Short name T54
Test name
Test status
Simulation time 1452172452 ps
CPU time 74.86 seconds
Started Apr 23 01:09:14 PM PDT 24
Finished Apr 23 01:10:30 PM PDT 24
Peak memory 211136 kb
Host smart-fdc7af7b-ece6-444a-9425-4aaabbb61a32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934977538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3934977538
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1260890408
Short name T433
Test name
Test status
Simulation time 946063830 ps
CPU time 10.24 seconds
Started Apr 23 01:09:14 PM PDT 24
Finished Apr 23 01:09:25 PM PDT 24
Peak memory 218464 kb
Host smart-9a141141-2aa6-463f-bbca-f1b92850063d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260890408 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1260890408
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.646703287
Short name T410
Test name
Test status
Simulation time 1696310530 ps
CPU time 14.32 seconds
Started Apr 23 01:09:18 PM PDT 24
Finished Apr 23 01:09:32 PM PDT 24
Peak memory 210128 kb
Host smart-1272c03e-c4f1-4097-b703-eb82ec437bba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646703287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.646703287
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.177518702
Short name T420
Test name
Test status
Simulation time 10971049332 ps
CPU time 48.03 seconds
Started Apr 23 01:09:16 PM PDT 24
Finished Apr 23 01:10:04 PM PDT 24
Peak memory 210324 kb
Host smart-ac3b199c-02fd-45a3-8aee-99775e4d5eef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177518702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.177518702
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.66315135
Short name T110
Test name
Test status
Simulation time 8006826772 ps
CPU time 16.44 seconds
Started Apr 23 01:09:13 PM PDT 24
Finished Apr 23 01:09:30 PM PDT 24
Peak memory 210268 kb
Host smart-2aeb122c-de99-42d3-84d2-cdda1f27b860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66315135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ct
rl_same_csr_outstanding.66315135
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3796945115
Short name T434
Test name
Test status
Simulation time 2727029706 ps
CPU time 12.55 seconds
Started Apr 23 01:09:14 PM PDT 24
Finished Apr 23 01:09:27 PM PDT 24
Peak memory 218580 kb
Host smart-facea9dd-e36a-40e3-b62e-76101df52ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796945115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3796945115
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3195860719
Short name T130
Test name
Test status
Simulation time 4138440343 ps
CPU time 47.77 seconds
Started Apr 23 01:09:16 PM PDT 24
Finished Apr 23 01:10:04 PM PDT 24
Peak memory 210796 kb
Host smart-49e94998-f15f-4a73-ba21-e88626ce08c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195860719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3195860719
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2033765423
Short name T400
Test name
Test status
Simulation time 8236968830 ps
CPU time 17.32 seconds
Started Apr 23 01:09:20 PM PDT 24
Finished Apr 23 01:09:38 PM PDT 24
Peak memory 218496 kb
Host smart-dd945b0e-3b8a-41b0-9547-ddae9ec77b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033765423 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2033765423
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1794588522
Short name T461
Test name
Test status
Simulation time 6457098220 ps
CPU time 14.18 seconds
Started Apr 23 01:09:21 PM PDT 24
Finished Apr 23 01:09:35 PM PDT 24
Peak memory 210216 kb
Host smart-ed0a92d9-a73a-4b01-a7d7-bfee116fc436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794588522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1794588522
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2264774778
Short name T401
Test name
Test status
Simulation time 9611049890 ps
CPU time 76.16 seconds
Started Apr 23 01:09:14 PM PDT 24
Finished Apr 23 01:10:31 PM PDT 24
Peak memory 210356 kb
Host smart-fef061f8-7d68-4ae4-98e7-14fc4bb9c419
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264774778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2264774778
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1762595508
Short name T431
Test name
Test status
Simulation time 168725281 ps
CPU time 4.38 seconds
Started Apr 23 01:09:20 PM PDT 24
Finished Apr 23 01:09:24 PM PDT 24
Peak memory 210200 kb
Host smart-3c8b0b92-348e-467b-87b9-7a7393e1d7df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762595508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1762595508
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.656919315
Short name T464
Test name
Test status
Simulation time 1239327362 ps
CPU time 12.11 seconds
Started Apr 23 01:09:15 PM PDT 24
Finished Apr 23 01:09:27 PM PDT 24
Peak memory 218492 kb
Host smart-9c392fdf-a05c-4f87-acef-c8c68dc6611d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656919315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.656919315
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1791974292
Short name T129
Test name
Test status
Simulation time 1244578600 ps
CPU time 72.95 seconds
Started Apr 23 01:09:16 PM PDT 24
Finished Apr 23 01:10:29 PM PDT 24
Peak memory 210240 kb
Host smart-23c4b88b-55c5-4a3c-97ff-02dd50e94359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791974292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1791974292
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2300351514
Short name T460
Test name
Test status
Simulation time 2690489568 ps
CPU time 7.93 seconds
Started Apr 23 01:09:30 PM PDT 24
Finished Apr 23 01:09:38 PM PDT 24
Peak memory 211556 kb
Host smart-6fb0adc3-d645-46ef-ad1d-573121d25d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300351514 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2300351514
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.110719566
Short name T417
Test name
Test status
Simulation time 1453118459 ps
CPU time 12.29 seconds
Started Apr 23 01:09:27 PM PDT 24
Finished Apr 23 01:09:39 PM PDT 24
Peak memory 210176 kb
Host smart-e680a12e-7848-4b04-84cd-fc40de427df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110719566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.110719566
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2178262258
Short name T435
Test name
Test status
Simulation time 10087523798 ps
CPU time 86.29 seconds
Started Apr 23 01:09:22 PM PDT 24
Finished Apr 23 01:10:49 PM PDT 24
Peak memory 210292 kb
Host smart-e2374a55-b906-480f-b09f-921710fd71a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178262258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2178262258
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3728968367
Short name T437
Test name
Test status
Simulation time 96045027 ps
CPU time 6.26 seconds
Started Apr 23 01:09:27 PM PDT 24
Finished Apr 23 01:09:33 PM PDT 24
Peak memory 210176 kb
Host smart-b429dcd4-22ff-4429-af28-50539e9c73d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728968367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3728968367
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3224831030
Short name T374
Test name
Test status
Simulation time 429138539 ps
CPU time 9.54 seconds
Started Apr 23 01:09:24 PM PDT 24
Finished Apr 23 01:09:34 PM PDT 24
Peak memory 213496 kb
Host smart-baac466a-442a-440d-a39d-4e3e6d48b369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224831030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3224831030
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1694621779
Short name T131
Test name
Test status
Simulation time 2158078416 ps
CPU time 72.88 seconds
Started Apr 23 01:09:25 PM PDT 24
Finished Apr 23 01:10:39 PM PDT 24
Peak memory 212064 kb
Host smart-12993500-7782-44d9-ac9e-fd5c78a7893e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694621779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1694621779
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.979314996
Short name T375
Test name
Test status
Simulation time 9736650386 ps
CPU time 12.27 seconds
Started Apr 23 01:09:29 PM PDT 24
Finished Apr 23 01:09:42 PM PDT 24
Peak memory 218556 kb
Host smart-4730e78c-ce23-4086-aaec-fd2df4143b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979314996 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.979314996
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.76624725
Short name T418
Test name
Test status
Simulation time 8609413998 ps
CPU time 14.07 seconds
Started Apr 23 01:09:30 PM PDT 24
Finished Apr 23 01:09:45 PM PDT 24
Peak memory 210204 kb
Host smart-71ff6bd5-1122-4fa6-80f5-7a812b50bdd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76624725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.76624725
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3341914428
Short name T95
Test name
Test status
Simulation time 32911543642 ps
CPU time 75.16 seconds
Started Apr 23 01:09:30 PM PDT 24
Finished Apr 23 01:10:45 PM PDT 24
Peak memory 210240 kb
Host smart-736d5ad3-3918-4ce3-bf6d-49699e7091ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341914428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3341914428
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2952286843
Short name T456
Test name
Test status
Simulation time 2121002836 ps
CPU time 18.16 seconds
Started Apr 23 01:09:30 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 210300 kb
Host smart-31f39b7b-7c54-4c89-b851-9c4c104e9dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952286843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2952286843
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4030222029
Short name T385
Test name
Test status
Simulation time 2404288635 ps
CPU time 10.72 seconds
Started Apr 23 01:09:28 PM PDT 24
Finished Apr 23 01:09:40 PM PDT 24
Peak memory 218532 kb
Host smart-31fdb7a9-37be-4c28-b8f9-b1c4a2d39c25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030222029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4030222029
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1955276730
Short name T125
Test name
Test status
Simulation time 229338276 ps
CPU time 36.96 seconds
Started Apr 23 01:09:28 PM PDT 24
Finished Apr 23 01:10:06 PM PDT 24
Peak memory 210192 kb
Host smart-91d9044c-be24-425e-9f51-069fcc9bcacd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955276730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1955276730
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1003324069
Short name T57
Test name
Test status
Simulation time 91745794 ps
CPU time 4.35 seconds
Started Apr 23 01:08:53 PM PDT 24
Finished Apr 23 01:08:58 PM PDT 24
Peak memory 210124 kb
Host smart-7c25e6f7-81d2-4964-988b-fb0ed396b9c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003324069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1003324069
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.765905127
Short name T394
Test name
Test status
Simulation time 15737363907 ps
CPU time 15.27 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:08 PM PDT 24
Peak memory 210192 kb
Host smart-074eceee-b97d-4953-a970-f678ec501e16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765905127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.765905127
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1998183604
Short name T89
Test name
Test status
Simulation time 5461701878 ps
CPU time 10.23 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:03 PM PDT 24
Peak memory 210244 kb
Host smart-6d3ee627-65f6-4907-83b7-6a3dfd7c82c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998183604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1998183604
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2278557840
Short name T411
Test name
Test status
Simulation time 2764575463 ps
CPU time 7.03 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:00 PM PDT 24
Peak memory 218488 kb
Host smart-6bcf1f96-163a-4423-b2a7-f8b4b79d382b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278557840 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2278557840
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2684699229
Short name T408
Test name
Test status
Simulation time 1168876578 ps
CPU time 11.53 seconds
Started Apr 23 01:08:56 PM PDT 24
Finished Apr 23 01:09:08 PM PDT 24
Peak memory 210160 kb
Host smart-02953697-dfc9-4274-8a59-ca858035b538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684699229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2684699229
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.668964635
Short name T402
Test name
Test status
Simulation time 1685513744 ps
CPU time 14.49 seconds
Started Apr 23 01:08:55 PM PDT 24
Finished Apr 23 01:09:11 PM PDT 24
Peak memory 210092 kb
Host smart-4a3a3b44-7078-4a13-a06e-399eae191c04
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668964635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.668964635
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3568961074
Short name T423
Test name
Test status
Simulation time 6496515233 ps
CPU time 13.59 seconds
Started Apr 23 01:08:47 PM PDT 24
Finished Apr 23 01:09:01 PM PDT 24
Peak memory 210140 kb
Host smart-b0cc1d69-12f4-4cc7-8c84-6f5eb42da28d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568961074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3568961074
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2554549597
Short name T88
Test name
Test status
Simulation time 567942990 ps
CPU time 26.89 seconds
Started Apr 23 01:08:46 PM PDT 24
Finished Apr 23 01:09:14 PM PDT 24
Peak memory 210264 kb
Host smart-50121877-0eef-4877-9103-4443ebbc3dfd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554549597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2554549597
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.997039631
Short name T440
Test name
Test status
Simulation time 4274459143 ps
CPU time 17.88 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:10 PM PDT 24
Peak memory 210352 kb
Host smart-c3dd82dc-b72c-44d6-97a1-c83998d8871b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997039631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.997039631
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3257241708
Short name T393
Test name
Test status
Simulation time 194414150 ps
CPU time 7.34 seconds
Started Apr 23 01:08:48 PM PDT 24
Finished Apr 23 01:08:56 PM PDT 24
Peak memory 218468 kb
Host smart-3d8edd78-c70d-4cf0-b58f-d105cb2bf7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257241708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3257241708
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2245287830
Short name T120
Test name
Test status
Simulation time 2321662072 ps
CPU time 48.79 seconds
Started Apr 23 01:08:48 PM PDT 24
Finished Apr 23 01:09:38 PM PDT 24
Peak memory 210816 kb
Host smart-8057ae10-59be-4933-a0cf-02683fb00f92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245287830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2245287830
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2937479921
Short name T446
Test name
Test status
Simulation time 333316500 ps
CPU time 4.21 seconds
Started Apr 23 01:08:50 PM PDT 24
Finished Apr 23 01:08:55 PM PDT 24
Peak memory 210124 kb
Host smart-888374f6-1ee8-4dfc-aa89-a78410596dea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937479921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2937479921
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4073873153
Short name T409
Test name
Test status
Simulation time 8435008155 ps
CPU time 17.46 seconds
Started Apr 23 01:08:51 PM PDT 24
Finished Apr 23 01:09:09 PM PDT 24
Peak memory 210272 kb
Host smart-51a87cc3-1cd7-4dab-9059-157df9f7e3a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073873153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4073873153
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.755030256
Short name T84
Test name
Test status
Simulation time 102176709 ps
CPU time 7.62 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:00 PM PDT 24
Peak memory 210148 kb
Host smart-780b569d-4497-4714-891b-5dea810f6b3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755030256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.755030256
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1031956199
Short name T391
Test name
Test status
Simulation time 1328198923 ps
CPU time 12.55 seconds
Started Apr 23 01:08:55 PM PDT 24
Finished Apr 23 01:09:09 PM PDT 24
Peak memory 212944 kb
Host smart-313c4a0f-4d1d-42ee-a3ae-19dd307a4e4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031956199 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1031956199
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3522948181
Short name T112
Test name
Test status
Simulation time 5691125688 ps
CPU time 9.15 seconds
Started Apr 23 01:08:55 PM PDT 24
Finished Apr 23 01:09:05 PM PDT 24
Peak memory 210224 kb
Host smart-1eca9767-866d-4e22-90d6-5aa887f1385c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522948181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3522948181
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3044342906
Short name T399
Test name
Test status
Simulation time 839070399 ps
CPU time 9.13 seconds
Started Apr 23 01:08:56 PM PDT 24
Finished Apr 23 01:09:06 PM PDT 24
Peak memory 210060 kb
Host smart-3278dffa-5ed2-411a-a45d-2f5141955245
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044342906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3044342906
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3505395812
Short name T458
Test name
Test status
Simulation time 1386508113 ps
CPU time 12.4 seconds
Started Apr 23 01:08:55 PM PDT 24
Finished Apr 23 01:09:08 PM PDT 24
Peak memory 210104 kb
Host smart-a47eace9-4c20-485c-82e3-c8b18e62769a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505395812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3505395812
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2705262658
Short name T119
Test name
Test status
Simulation time 1074971075 ps
CPU time 34.37 seconds
Started Apr 23 01:08:51 PM PDT 24
Finished Apr 23 01:09:26 PM PDT 24
Peak memory 210244 kb
Host smart-705b8250-725d-46be-b4ce-12f9ee5d014b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705262658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2705262658
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2550331299
Short name T72
Test name
Test status
Simulation time 3968637541 ps
CPU time 10.36 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:03 PM PDT 24
Peak memory 210300 kb
Host smart-8874efe2-9457-4563-a8f0-37028d0c4a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550331299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2550331299
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4084759879
Short name T428
Test name
Test status
Simulation time 1010525440 ps
CPU time 9.66 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:02 PM PDT 24
Peak memory 218520 kb
Host smart-49e475aa-ec0b-4e80-ad8b-cb7dc0432a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084759879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4084759879
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2474340561
Short name T56
Test name
Test status
Simulation time 1010905461 ps
CPU time 71.63 seconds
Started Apr 23 01:08:50 PM PDT 24
Finished Apr 23 01:10:03 PM PDT 24
Peak memory 218412 kb
Host smart-b70cc56b-90c5-4a08-b0e9-9bd13450258d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474340561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2474340561
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4081296297
Short name T90
Test name
Test status
Simulation time 1902919672 ps
CPU time 14.91 seconds
Started Apr 23 01:08:55 PM PDT 24
Finished Apr 23 01:09:11 PM PDT 24
Peak memory 210192 kb
Host smart-d23ffa6c-1358-4390-833f-1e617987e624
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081296297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4081296297
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3620337034
Short name T429
Test name
Test status
Simulation time 362674185 ps
CPU time 4.68 seconds
Started Apr 23 01:08:59 PM PDT 24
Finished Apr 23 01:09:05 PM PDT 24
Peak memory 210204 kb
Host smart-e4ebc8c2-7c89-4866-a71a-f8fe0f1e761b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620337034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3620337034
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.283266436
Short name T86
Test name
Test status
Simulation time 424177908 ps
CPU time 8.71 seconds
Started Apr 23 01:08:54 PM PDT 24
Finished Apr 23 01:09:03 PM PDT 24
Peak memory 210116 kb
Host smart-7eb17664-7de8-4dc1-8642-191537c554fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283266436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.283266436
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.845843357
Short name T377
Test name
Test status
Simulation time 7302610937 ps
CPU time 15.77 seconds
Started Apr 23 01:08:54 PM PDT 24
Finished Apr 23 01:09:11 PM PDT 24
Peak memory 218544 kb
Host smart-20af0423-d017-4ab2-b9f4-581188e289db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845843357 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.845843357
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1153095206
Short name T449
Test name
Test status
Simulation time 333601518 ps
CPU time 4.26 seconds
Started Apr 23 01:08:56 PM PDT 24
Finished Apr 23 01:09:01 PM PDT 24
Peak memory 210196 kb
Host smart-4229a79b-0738-4a59-a282-97c05a4ba747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153095206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1153095206
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1826124762
Short name T421
Test name
Test status
Simulation time 2458385276 ps
CPU time 16.09 seconds
Started Apr 23 01:08:56 PM PDT 24
Finished Apr 23 01:09:13 PM PDT 24
Peak memory 210164 kb
Host smart-b77cfe01-0342-406d-b728-19a9c32c5504
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826124762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1826124762
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4050623653
Short name T422
Test name
Test status
Simulation time 1485540840 ps
CPU time 13.16 seconds
Started Apr 23 01:08:57 PM PDT 24
Finished Apr 23 01:09:11 PM PDT 24
Peak memory 210092 kb
Host smart-654884e5-a770-4599-b830-9fcb269c442a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050623653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4050623653
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3320784467
Short name T68
Test name
Test status
Simulation time 9038768377 ps
CPU time 32.49 seconds
Started Apr 23 01:08:52 PM PDT 24
Finished Apr 23 01:09:25 PM PDT 24
Peak memory 210300 kb
Host smart-dbc412e6-9417-41f3-9bb5-50a19a0fa70d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320784467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3320784467
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2985660618
Short name T424
Test name
Test status
Simulation time 3420573532 ps
CPU time 13.92 seconds
Started Apr 23 01:08:59 PM PDT 24
Finished Apr 23 01:09:15 PM PDT 24
Peak memory 210364 kb
Host smart-00e23803-2f17-4081-815c-a4a1cc2ce0c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985660618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2985660618
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3959564176
Short name T396
Test name
Test status
Simulation time 1144604157 ps
CPU time 15.34 seconds
Started Apr 23 01:08:50 PM PDT 24
Finished Apr 23 01:09:06 PM PDT 24
Peak memory 218432 kb
Host smart-edf0ac4c-a6c5-452c-a382-2fc5d90add2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959564176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3959564176
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1163304607
Short name T455
Test name
Test status
Simulation time 9184377617 ps
CPU time 79.02 seconds
Started Apr 23 01:08:56 PM PDT 24
Finished Apr 23 01:10:16 PM PDT 24
Peak memory 218520 kb
Host smart-860449a8-8f25-4839-846d-b0d0c4995161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163304607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1163304607
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2197392586
Short name T430
Test name
Test status
Simulation time 15341980317 ps
CPU time 15.39 seconds
Started Apr 23 01:08:56 PM PDT 24
Finished Apr 23 01:09:13 PM PDT 24
Peak memory 218532 kb
Host smart-396812b3-4c7f-4183-8c9f-1a1dd38835c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197392586 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2197392586
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1950841362
Short name T381
Test name
Test status
Simulation time 4640192714 ps
CPU time 10.68 seconds
Started Apr 23 01:09:00 PM PDT 24
Finished Apr 23 01:09:12 PM PDT 24
Peak memory 210300 kb
Host smart-d75de5a6-949e-4c30-9353-8ea27f80b47b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950841362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1950841362
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3225885333
Short name T118
Test name
Test status
Simulation time 8303852430 ps
CPU time 30.14 seconds
Started Apr 23 01:08:57 PM PDT 24
Finished Apr 23 01:09:28 PM PDT 24
Peak memory 210348 kb
Host smart-69bbe244-f9db-40a8-903b-bde05e8f07b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225885333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3225885333
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2999847518
Short name T73
Test name
Test status
Simulation time 763721748 ps
CPU time 10.57 seconds
Started Apr 23 01:09:00 PM PDT 24
Finished Apr 23 01:09:12 PM PDT 24
Peak memory 210300 kb
Host smart-a96fa653-0150-488f-b934-e7d264cba919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999847518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2999847518
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3004034440
Short name T414
Test name
Test status
Simulation time 6447490951 ps
CPU time 14.04 seconds
Started Apr 23 01:08:59 PM PDT 24
Finished Apr 23 01:09:15 PM PDT 24
Peak memory 218552 kb
Host smart-e5a3cf31-5587-4403-bfe9-ef79fe3c69ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004034440 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3004034440
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.320360834
Short name T111
Test name
Test status
Simulation time 1256870670 ps
CPU time 6.33 seconds
Started Apr 23 01:09:01 PM PDT 24
Finished Apr 23 01:09:09 PM PDT 24
Peak memory 210116 kb
Host smart-9e9208e5-17b3-4bb0-a2ac-52f4f5783a52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320360834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.320360834
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3446572089
Short name T98
Test name
Test status
Simulation time 127043578482 ps
CPU time 77.11 seconds
Started Apr 23 01:08:59 PM PDT 24
Finished Apr 23 01:10:18 PM PDT 24
Peak memory 210468 kb
Host smart-040c6f38-7767-4a2b-b6fa-eaa3a129e7cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446572089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3446572089
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3420926334
Short name T441
Test name
Test status
Simulation time 7243057237 ps
CPU time 14.08 seconds
Started Apr 23 01:09:01 PM PDT 24
Finished Apr 23 01:09:16 PM PDT 24
Peak memory 210220 kb
Host smart-06e0b9b9-f605-4368-b6e5-aca43d5c660c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420926334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3420926334
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.878571619
Short name T404
Test name
Test status
Simulation time 1801934613 ps
CPU time 10.39 seconds
Started Apr 23 01:09:01 PM PDT 24
Finished Apr 23 01:09:13 PM PDT 24
Peak memory 218444 kb
Host smart-d6e1d17d-10df-4308-9399-687b5d65058e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878571619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.878571619
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1091927548
Short name T442
Test name
Test status
Simulation time 1659210015 ps
CPU time 44.35 seconds
Started Apr 23 01:09:00 PM PDT 24
Finished Apr 23 01:09:46 PM PDT 24
Peak memory 211016 kb
Host smart-3781b771-9f71-4bb7-9dfc-6757dc0520b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091927548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1091927548
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3353582829
Short name T376
Test name
Test status
Simulation time 342978806 ps
CPU time 4.63 seconds
Started Apr 23 01:08:58 PM PDT 24
Finished Apr 23 01:09:04 PM PDT 24
Peak memory 212452 kb
Host smart-472fd632-f452-4b31-a6cc-2c489394c322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353582829 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3353582829
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.225543358
Short name T412
Test name
Test status
Simulation time 89160401 ps
CPU time 4.08 seconds
Started Apr 23 01:08:59 PM PDT 24
Finished Apr 23 01:09:05 PM PDT 24
Peak memory 209924 kb
Host smart-aabc2ef1-ee6d-4d90-b327-27034533e132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225543358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.225543358
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.519492537
Short name T97
Test name
Test status
Simulation time 48548950883 ps
CPU time 66.61 seconds
Started Apr 23 01:09:00 PM PDT 24
Finished Apr 23 01:10:09 PM PDT 24
Peak memory 210352 kb
Host smart-b6bd5427-650d-4f50-a23b-4865d1f223a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519492537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.519492537
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3533096095
Short name T438
Test name
Test status
Simulation time 346391266 ps
CPU time 4.37 seconds
Started Apr 23 01:08:59 PM PDT 24
Finished Apr 23 01:09:05 PM PDT 24
Peak memory 210240 kb
Host smart-c66cf454-b0ee-427c-ae4a-6524565e3a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533096095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3533096095
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.828974947
Short name T390
Test name
Test status
Simulation time 1935626011 ps
CPU time 18.95 seconds
Started Apr 23 01:09:01 PM PDT 24
Finished Apr 23 01:09:21 PM PDT 24
Peak memory 218444 kb
Host smart-56b70cb0-7ff3-4e7c-b4d2-9e6e2e05f56f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828974947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.828974947
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3228796886
Short name T128
Test name
Test status
Simulation time 15697628117 ps
CPU time 77.48 seconds
Started Apr 23 01:08:58 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 210532 kb
Host smart-0f4238d1-3685-4207-a426-95a7cec2f583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228796886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3228796886
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3036926143
Short name T388
Test name
Test status
Simulation time 353630016 ps
CPU time 8.32 seconds
Started Apr 23 01:09:00 PM PDT 24
Finished Apr 23 01:09:10 PM PDT 24
Peak memory 218436 kb
Host smart-0a709645-615f-48d2-82cb-c0bca52ffb0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036926143 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3036926143
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3175697114
Short name T91
Test name
Test status
Simulation time 21408499037 ps
CPU time 10.45 seconds
Started Apr 23 01:08:59 PM PDT 24
Finished Apr 23 01:09:10 PM PDT 24
Peak memory 210192 kb
Host smart-d308899f-9780-47c4-9e54-32690f06770a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175697114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3175697114
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3422932198
Short name T117
Test name
Test status
Simulation time 388258738 ps
CPU time 18.77 seconds
Started Apr 23 01:09:00 PM PDT 24
Finished Apr 23 01:09:20 PM PDT 24
Peak memory 210324 kb
Host smart-40f24045-b04d-4fdb-92a5-6a79029a12b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422932198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3422932198
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.880723747
Short name T70
Test name
Test status
Simulation time 7008821453 ps
CPU time 11.95 seconds
Started Apr 23 01:09:00 PM PDT 24
Finished Apr 23 01:09:14 PM PDT 24
Peak memory 210260 kb
Host smart-64ea91de-9db8-4049-a0ae-98b5b2532e0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880723747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.880723747
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1168164529
Short name T407
Test name
Test status
Simulation time 10246233956 ps
CPU time 16.36 seconds
Started Apr 23 01:08:58 PM PDT 24
Finished Apr 23 01:09:15 PM PDT 24
Peak memory 218544 kb
Host smart-c43bff36-5bd9-497e-ac50-580c08d83547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168164529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1168164529
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2686693372
Short name T127
Test name
Test status
Simulation time 1580519230 ps
CPU time 38.21 seconds
Started Apr 23 01:08:58 PM PDT 24
Finished Apr 23 01:09:37 PM PDT 24
Peak memory 210208 kb
Host smart-82b251c5-c50a-4a01-a4d8-434e511afb17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686693372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2686693372
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2846279380
Short name T379
Test name
Test status
Simulation time 3051968095 ps
CPU time 14.01 seconds
Started Apr 23 01:09:03 PM PDT 24
Finished Apr 23 01:09:18 PM PDT 24
Peak memory 218512 kb
Host smart-5b945bbb-9dcc-4c5f-b2ce-237ee3909436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846279380 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2846279380
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.498585659
Short name T406
Test name
Test status
Simulation time 7736612108 ps
CPU time 15.33 seconds
Started Apr 23 01:09:05 PM PDT 24
Finished Apr 23 01:09:21 PM PDT 24
Peak memory 210284 kb
Host smart-e5066241-7df6-4023-bcc6-79850d947b2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498585659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.498585659
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2671340084
Short name T395
Test name
Test status
Simulation time 8270301763 ps
CPU time 74.44 seconds
Started Apr 23 01:09:01 PM PDT 24
Finished Apr 23 01:10:17 PM PDT 24
Peak memory 218384 kb
Host smart-fdb3b166-c0ff-4b1b-b45f-57ad18fe8c3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671340084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2671340084
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4124157239
Short name T65
Test name
Test status
Simulation time 951326492 ps
CPU time 10.39 seconds
Started Apr 23 01:09:03 PM PDT 24
Finished Apr 23 01:09:14 PM PDT 24
Peak memory 210184 kb
Host smart-a0016c3a-735e-4c69-98b6-c446ffcdbebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124157239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4124157239
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3333643478
Short name T380
Test name
Test status
Simulation time 1540268970 ps
CPU time 16.28 seconds
Started Apr 23 01:09:06 PM PDT 24
Finished Apr 23 01:09:23 PM PDT 24
Peak memory 218492 kb
Host smart-bff8b829-24f7-4217-9361-677171a9cd43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333643478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3333643478
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3744567461
Short name T122
Test name
Test status
Simulation time 6018350777 ps
CPU time 44.28 seconds
Started Apr 23 01:09:04 PM PDT 24
Finished Apr 23 01:09:49 PM PDT 24
Peak memory 211436 kb
Host smart-6cf02aec-6421-4fed-aa06-35fb60ef8752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744567461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3744567461
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1197971229
Short name T271
Test name
Test status
Simulation time 1436132365 ps
CPU time 12.91 seconds
Started Apr 23 02:12:27 PM PDT 24
Finished Apr 23 02:12:41 PM PDT 24
Peak memory 211448 kb
Host smart-9134c00d-d474-477e-84d4-f6c99ad5e43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197971229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1197971229
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.780979269
Short name T38
Test name
Test status
Simulation time 4750305404 ps
CPU time 82.59 seconds
Started Apr 23 02:12:28 PM PDT 24
Finished Apr 23 02:13:51 PM PDT 24
Peak memory 238032 kb
Host smart-a6d8669f-51fd-4f87-aec8-6c42f039ee48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780979269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.780979269
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1011142868
Short name T22
Test name
Test status
Simulation time 7082972864 ps
CPU time 13.63 seconds
Started Apr 23 02:12:27 PM PDT 24
Finished Apr 23 02:12:41 PM PDT 24
Peak memory 212652 kb
Host smart-e4627320-7150-490b-adb6-8c3250fe36ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011142868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1011142868
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3147623508
Short name T283
Test name
Test status
Simulation time 641780723 ps
CPU time 5.27 seconds
Started Apr 23 02:12:28 PM PDT 24
Finished Apr 23 02:12:34 PM PDT 24
Peak memory 211352 kb
Host smart-c838911f-77c0-4122-acd9-58b8065e4351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147623508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3147623508
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1608642454
Short name T31
Test name
Test status
Simulation time 1938861859 ps
CPU time 107.24 seconds
Started Apr 23 02:12:22 PM PDT 24
Finished Apr 23 02:14:10 PM PDT 24
Peak memory 235892 kb
Host smart-08a6d1d5-8c46-4fdc-887c-139e71ff2363
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608642454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1608642454
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1048596845
Short name T181
Test name
Test status
Simulation time 184313003 ps
CPU time 10.09 seconds
Started Apr 23 02:12:26 PM PDT 24
Finished Apr 23 02:12:37 PM PDT 24
Peak memory 212808 kb
Host smart-fc9552f9-406e-4592-b3a2-5707ea4ce48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048596845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1048596845
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2908598199
Short name T152
Test name
Test status
Simulation time 2919330174 ps
CPU time 17.27 seconds
Started Apr 23 02:12:25 PM PDT 24
Finished Apr 23 02:12:43 PM PDT 24
Peak memory 212888 kb
Host smart-8226869f-96bf-4026-8bfa-fb7f63238dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908598199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2908598199
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1543259197
Short name T174
Test name
Test status
Simulation time 988778289 ps
CPU time 7.43 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:12:38 PM PDT 24
Peak memory 211360 kb
Host smart-8eea6ce2-bb5d-4d11-a432-0678da27f957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543259197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1543259197
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.477711544
Short name T172
Test name
Test status
Simulation time 47550517403 ps
CPU time 252.9 seconds
Started Apr 23 02:12:31 PM PDT 24
Finished Apr 23 02:16:44 PM PDT 24
Peak memory 211924 kb
Host smart-f8eba5a7-2881-4943-9d43-04ba6935e58b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477711544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.477711544
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1415756120
Short name T214
Test name
Test status
Simulation time 27755296432 ps
CPU time 29.12 seconds
Started Apr 23 02:12:28 PM PDT 24
Finished Apr 23 02:12:57 PM PDT 24
Peak memory 212592 kb
Host smart-5bb4ef08-837d-463f-b6af-b6c0bba37bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415756120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1415756120
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3000426160
Short name T302
Test name
Test status
Simulation time 2687201896 ps
CPU time 9.53 seconds
Started Apr 23 02:12:27 PM PDT 24
Finished Apr 23 02:12:38 PM PDT 24
Peak memory 211416 kb
Host smart-e0291606-6baf-4fe7-a7d5-32b43acc7665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000426160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3000426160
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2943565467
Short name T29
Test name
Test status
Simulation time 2797344687 ps
CPU time 55.39 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:13:26 PM PDT 24
Peak memory 230608 kb
Host smart-c857679c-4767-4626-a140-9f87789c6991
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943565467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2943565467
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3932764438
Short name T364
Test name
Test status
Simulation time 4449617785 ps
CPU time 26.21 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:12:57 PM PDT 24
Peak memory 213324 kb
Host smart-e4459276-4427-4d1b-922f-12370cd4d53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932764438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3932764438
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1524706604
Short name T76
Test name
Test status
Simulation time 3155608439 ps
CPU time 19.75 seconds
Started Apr 23 02:12:25 PM PDT 24
Finished Apr 23 02:12:45 PM PDT 24
Peak memory 211508 kb
Host smart-ce38c410-ddec-481e-8f33-aebb0dbbb21f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524706604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1524706604
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1583296506
Short name T7
Test name
Test status
Simulation time 63584465134 ps
CPU time 214.77 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:16:13 PM PDT 24
Peak memory 237176 kb
Host smart-27d9dc34-8480-473b-964e-7ddf71c7a163
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583296506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1583296506
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2157636847
Short name T23
Test name
Test status
Simulation time 1286033264 ps
CPU time 17.63 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:12:56 PM PDT 24
Peak memory 211956 kb
Host smart-748b294d-d83a-45a6-9e90-24f514929c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157636847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2157636847
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2758313515
Short name T264
Test name
Test status
Simulation time 3625364086 ps
CPU time 15.43 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:12:53 PM PDT 24
Peak memory 211400 kb
Host smart-ac8db95c-82df-473d-a13c-2e8b5626c6ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758313515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2758313515
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1363090717
Short name T367
Test name
Test status
Simulation time 13536364376 ps
CPU time 31.91 seconds
Started Apr 23 02:12:36 PM PDT 24
Finished Apr 23 02:13:09 PM PDT 24
Peak memory 219604 kb
Host smart-fb488e4d-b609-47bb-a45e-7641120bcfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363090717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1363090717
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.778371319
Short name T359
Test name
Test status
Simulation time 7631608661 ps
CPU time 81.36 seconds
Started Apr 23 02:12:38 PM PDT 24
Finished Apr 23 02:14:00 PM PDT 24
Peak memory 219724 kb
Host smart-d904e352-904a-49c7-b392-cce15a66b9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778371319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.778371319
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2274587022
Short name T14
Test name
Test status
Simulation time 198069073658 ps
CPU time 3965.9 seconds
Started Apr 23 02:12:38 PM PDT 24
Finished Apr 23 03:18:45 PM PDT 24
Peak memory 247796 kb
Host smart-ab099d94-32b5-4da8-8771-9be5afc2d770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274587022 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2274587022
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3313191462
Short name T216
Test name
Test status
Simulation time 19929229761 ps
CPU time 15.72 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:12:55 PM PDT 24
Peak memory 211596 kb
Host smart-e9bf6111-c640-430e-ad42-a6c1dfd24222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313191462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3313191462
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1575341340
Short name T346
Test name
Test status
Simulation time 37612961030 ps
CPU time 98.8 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:14:19 PM PDT 24
Peak memory 219340 kb
Host smart-709070a1-f6e2-42d5-93dd-7b42e8278352
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575341340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1575341340
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2813214842
Short name T238
Test name
Test status
Simulation time 1810587448 ps
CPU time 15.31 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:12:54 PM PDT 24
Peak memory 211468 kb
Host smart-7377c006-1705-4be1-9b0b-a348d6ff287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813214842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2813214842
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.188891199
Short name T368
Test name
Test status
Simulation time 99096458 ps
CPU time 5.49 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:12:44 PM PDT 24
Peak memory 211372 kb
Host smart-c455f135-2f1e-4376-9f97-42de426dc24f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188891199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.188891199
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2037754166
Short name T331
Test name
Test status
Simulation time 11015488243 ps
CPU time 33.73 seconds
Started Apr 23 02:12:36 PM PDT 24
Finished Apr 23 02:13:11 PM PDT 24
Peak memory 219648 kb
Host smart-06870d93-af68-46be-9385-efee2f0c4a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037754166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2037754166
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1276170548
Short name T274
Test name
Test status
Simulation time 6195662750 ps
CPU time 66.17 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:13:45 PM PDT 24
Peak memory 219712 kb
Host smart-879bfbfa-9bee-4dfd-84cf-0555678ada14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276170548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1276170548
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2289824797
Short name T39
Test name
Test status
Simulation time 87365838 ps
CPU time 4.23 seconds
Started Apr 23 02:12:44 PM PDT 24
Finished Apr 23 02:12:49 PM PDT 24
Peak memory 211464 kb
Host smart-2ea7b315-f411-41d8-aa8b-844e4e3204cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289824797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2289824797
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1860738675
Short name T223
Test name
Test status
Simulation time 24549551918 ps
CPU time 269.97 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:17:10 PM PDT 24
Peak memory 212656 kb
Host smart-b72094ee-54bf-4b08-b766-f6990687c342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860738675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1860738675
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4098499482
Short name T327
Test name
Test status
Simulation time 578862197 ps
CPU time 13.67 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:12:53 PM PDT 24
Peak memory 211388 kb
Host smart-5a9a29c4-1f4d-4a36-84c7-35d2768ea68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098499482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4098499482
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.920866587
Short name T149
Test name
Test status
Simulation time 1834100326 ps
CPU time 13.46 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:12:53 PM PDT 24
Peak memory 211348 kb
Host smart-062ad440-c2d5-423b-87c2-8d6468adad6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920866587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.920866587
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3915487683
Short name T279
Test name
Test status
Simulation time 3305622355 ps
CPU time 28.82 seconds
Started Apr 23 02:12:34 PM PDT 24
Finished Apr 23 02:13:04 PM PDT 24
Peak memory 213328 kb
Host smart-25d876f0-97ba-4237-a533-7b223d5034c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915487683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3915487683
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2949188845
Short name T40
Test name
Test status
Simulation time 8343866961 ps
CPU time 55.04 seconds
Started Apr 23 02:12:40 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 216820 kb
Host smart-7de8c645-edc3-41b1-b919-1ce32be89897
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949188845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2949188845
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.21422959
Short name T208
Test name
Test status
Simulation time 1581522078 ps
CPU time 13.33 seconds
Started Apr 23 02:12:44 PM PDT 24
Finished Apr 23 02:12:58 PM PDT 24
Peak memory 211356 kb
Host smart-a23a2807-4198-4c62-832e-1d0f170f15e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21422959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.21422959
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2875781630
Short name T242
Test name
Test status
Simulation time 105311977787 ps
CPU time 238.76 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:16:37 PM PDT 24
Peak memory 241588 kb
Host smart-38ac3089-1bf8-47c3-8fab-d9052acdd42a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875781630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2875781630
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1139990707
Short name T101
Test name
Test status
Simulation time 15119971706 ps
CPU time 33.35 seconds
Started Apr 23 02:12:38 PM PDT 24
Finished Apr 23 02:13:13 PM PDT 24
Peak memory 212400 kb
Host smart-3cb60ca0-db32-438c-a2ef-fcb6476ae0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139990707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1139990707
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2128164291
Short name T116
Test name
Test status
Simulation time 5710202851 ps
CPU time 12.85 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:12:52 PM PDT 24
Peak memory 211400 kb
Host smart-ac88a316-c159-4af5-b549-176d68b9b988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128164291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2128164291
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.121220208
Short name T210
Test name
Test status
Simulation time 3666067420 ps
CPU time 16.79 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:12:57 PM PDT 24
Peak memory 219628 kb
Host smart-c1cb99d1-c2b3-4eec-b7bd-d271b96cd767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121220208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.121220208
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1023408463
Short name T352
Test name
Test status
Simulation time 3779942633 ps
CPU time 11.03 seconds
Started Apr 23 02:12:41 PM PDT 24
Finished Apr 23 02:12:52 PM PDT 24
Peak memory 212444 kb
Host smart-86bd6d6a-9018-4813-83af-f60d2ca4d8e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023408463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1023408463
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1655415080
Short name T206
Test name
Test status
Simulation time 501006420 ps
CPU time 7.69 seconds
Started Apr 23 02:12:42 PM PDT 24
Finished Apr 23 02:12:50 PM PDT 24
Peak memory 211484 kb
Host smart-c4661bd3-22f9-4ed7-ae15-4371f5d2fc74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655415080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1655415080
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.286686982
Short name T41
Test name
Test status
Simulation time 15753331479 ps
CPU time 230.22 seconds
Started Apr 23 02:12:41 PM PDT 24
Finished Apr 23 02:16:32 PM PDT 24
Peak memory 233904 kb
Host smart-07328f44-22b1-4d65-98b1-7e14e2f999e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286686982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.286686982
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.761013181
Short name T328
Test name
Test status
Simulation time 3476197842 ps
CPU time 28.48 seconds
Started Apr 23 02:12:42 PM PDT 24
Finished Apr 23 02:13:11 PM PDT 24
Peak memory 211948 kb
Host smart-b9991cb3-aed7-4e8c-bcc0-08deb9b0f980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761013181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.761013181
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.525450751
Short name T240
Test name
Test status
Simulation time 5360358965 ps
CPU time 12.63 seconds
Started Apr 23 02:12:42 PM PDT 24
Finished Apr 23 02:12:55 PM PDT 24
Peak memory 211448 kb
Host smart-e7f0205b-82ad-40a1-adbf-a72c633ff6e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525450751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.525450751
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2613587922
Short name T204
Test name
Test status
Simulation time 8046477214 ps
CPU time 33.49 seconds
Started Apr 23 02:12:45 PM PDT 24
Finished Apr 23 02:13:19 PM PDT 24
Peak memory 215068 kb
Host smart-8d37e397-8cd8-4a2d-8ca5-ce898ebc17da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613587922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2613587922
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3912620587
Short name T356
Test name
Test status
Simulation time 12102216632 ps
CPU time 32.98 seconds
Started Apr 23 02:12:43 PM PDT 24
Finished Apr 23 02:13:16 PM PDT 24
Peak memory 219032 kb
Host smart-3517d98a-04e4-4f73-bc8c-6d2439f935b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912620587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3912620587
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1954371111
Short name T287
Test name
Test status
Simulation time 197546410577 ps
CPU time 1124.02 seconds
Started Apr 23 02:12:43 PM PDT 24
Finished Apr 23 02:31:28 PM PDT 24
Peak memory 232448 kb
Host smart-d5c3e9f7-68e0-4b11-ae1e-99d8ff4dc030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954371111 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1954371111
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4201879716
Short name T167
Test name
Test status
Simulation time 2128941657 ps
CPU time 16.92 seconds
Started Apr 23 02:12:41 PM PDT 24
Finished Apr 23 02:12:59 PM PDT 24
Peak memory 211484 kb
Host smart-c628fcdc-35f1-4f04-9b4e-1deb1b8e91ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201879716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4201879716
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3832747147
Short name T207
Test name
Test status
Simulation time 39400845598 ps
CPU time 240.75 seconds
Started Apr 23 02:12:40 PM PDT 24
Finished Apr 23 02:16:41 PM PDT 24
Peak memory 230980 kb
Host smart-bb83bd0f-1cd2-4d2a-9268-cf44ca33eaae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832747147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3832747147
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3058822591
Short name T311
Test name
Test status
Simulation time 1870197203 ps
CPU time 15.23 seconds
Started Apr 23 02:12:43 PM PDT 24
Finished Apr 23 02:12:59 PM PDT 24
Peak memory 212020 kb
Host smart-c7c90a27-e6ac-49d0-a862-0711402b9837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058822591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3058822591
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.732076415
Short name T323
Test name
Test status
Simulation time 26330948593 ps
CPU time 17.27 seconds
Started Apr 23 02:12:41 PM PDT 24
Finished Apr 23 02:12:59 PM PDT 24
Peak memory 211356 kb
Host smart-e27076c7-5069-4553-b03d-f9af3a51d4a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732076415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.732076415
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1504239299
Short name T13
Test name
Test status
Simulation time 2109721013 ps
CPU time 21.67 seconds
Started Apr 23 02:12:43 PM PDT 24
Finished Apr 23 02:13:05 PM PDT 24
Peak memory 218932 kb
Host smart-2a1b5bb0-0e84-4346-861f-a6f547487bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504239299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1504239299
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2774193473
Short name T362
Test name
Test status
Simulation time 1920539028 ps
CPU time 24.89 seconds
Started Apr 23 02:12:42 PM PDT 24
Finished Apr 23 02:13:07 PM PDT 24
Peak memory 216568 kb
Host smart-9140af66-8397-4a80-a5f2-dd088881b51d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774193473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2774193473
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1296754821
Short name T161
Test name
Test status
Simulation time 1624049955 ps
CPU time 13.76 seconds
Started Apr 23 02:13:02 PM PDT 24
Finished Apr 23 02:13:16 PM PDT 24
Peak memory 211440 kb
Host smart-9cb5718c-06e7-470d-9933-af7184f7b474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296754821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1296754821
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1948032017
Short name T33
Test name
Test status
Simulation time 64559302773 ps
CPU time 193.45 seconds
Started Apr 23 02:12:48 PM PDT 24
Finished Apr 23 02:16:02 PM PDT 24
Peak memory 236596 kb
Host smart-5e0ce09f-ec05-4d63-aa37-11406b083620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948032017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1948032017
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2035658884
Short name T243
Test name
Test status
Simulation time 6493789549 ps
CPU time 19.26 seconds
Started Apr 23 02:12:43 PM PDT 24
Finished Apr 23 02:13:03 PM PDT 24
Peak memory 212580 kb
Host smart-f65b1351-80a5-4a1b-98b1-693dab8d6a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035658884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2035658884
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1461603754
Short name T175
Test name
Test status
Simulation time 117610648 ps
CPU time 5.48 seconds
Started Apr 23 02:13:01 PM PDT 24
Finished Apr 23 02:13:07 PM PDT 24
Peak memory 211276 kb
Host smart-477e13cd-b314-46c9-af9b-6dc27c8a9afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461603754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1461603754
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.198268830
Short name T102
Test name
Test status
Simulation time 29110378485 ps
CPU time 31.51 seconds
Started Apr 23 02:12:45 PM PDT 24
Finished Apr 23 02:13:17 PM PDT 24
Peak memory 219676 kb
Host smart-8683533c-e050-4f8f-b7a4-b8a61b682150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198268830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.198268830
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1565506366
Short name T199
Test name
Test status
Simulation time 4090864585 ps
CPU time 41.88 seconds
Started Apr 23 02:12:40 PM PDT 24
Finished Apr 23 02:13:22 PM PDT 24
Peak memory 219696 kb
Host smart-d1433149-fc4e-48b7-9cf8-78e2a0706a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565506366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1565506366
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.104470523
Short name T236
Test name
Test status
Simulation time 436867239 ps
CPU time 4.25 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:12:55 PM PDT 24
Peak memory 211500 kb
Host smart-e815d733-c204-4be4-b10b-3c956064ab53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104470523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.104470523
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3060445124
Short name T312
Test name
Test status
Simulation time 1755760066 ps
CPU time 119.01 seconds
Started Apr 23 02:12:44 PM PDT 24
Finished Apr 23 02:14:43 PM PDT 24
Peak memory 233252 kb
Host smart-fee08722-d59b-4081-8e2d-c3b38eb68b1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060445124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3060445124
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3412510167
Short name T157
Test name
Test status
Simulation time 17381893226 ps
CPU time 35.56 seconds
Started Apr 23 02:12:48 PM PDT 24
Finished Apr 23 02:13:24 PM PDT 24
Peak memory 212384 kb
Host smart-0df87961-9012-4e52-a916-5b8c92e66e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412510167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3412510167
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.468334925
Short name T104
Test name
Test status
Simulation time 1155633950 ps
CPU time 12.3 seconds
Started Apr 23 02:13:00 PM PDT 24
Finished Apr 23 02:13:13 PM PDT 24
Peak memory 211276 kb
Host smart-bc9cd515-c598-4842-ad8f-1dc58a2e2dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468334925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.468334925
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1015805190
Short name T187
Test name
Test status
Simulation time 14775420047 ps
CPU time 31.55 seconds
Started Apr 23 02:12:45 PM PDT 24
Finished Apr 23 02:13:17 PM PDT 24
Peak memory 219592 kb
Host smart-7b11d05d-0edf-407c-9c00-6038cffb7a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015805190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1015805190
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3767789288
Short name T237
Test name
Test status
Simulation time 240711242 ps
CPU time 14.63 seconds
Started Apr 23 02:13:01 PM PDT 24
Finished Apr 23 02:13:16 PM PDT 24
Peak memory 219540 kb
Host smart-88866fd2-93b5-4b75-8b9e-9485eae96b39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767789288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3767789288
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4144778139
Short name T278
Test name
Test status
Simulation time 8333085792 ps
CPU time 16.6 seconds
Started Apr 23 02:12:45 PM PDT 24
Finished Apr 23 02:13:02 PM PDT 24
Peak memory 211536 kb
Host smart-1242638a-a673-4354-a672-fd83b65828f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144778139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4144778139
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1436757465
Short name T252
Test name
Test status
Simulation time 32821669119 ps
CPU time 286.06 seconds
Started Apr 23 02:12:46 PM PDT 24
Finished Apr 23 02:17:33 PM PDT 24
Peak memory 235096 kb
Host smart-fbad738c-95fd-4af4-a46b-0ac3d2b09788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436757465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1436757465
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3570582828
Short name T265
Test name
Test status
Simulation time 7037660314 ps
CPU time 27.91 seconds
Started Apr 23 02:12:44 PM PDT 24
Finished Apr 23 02:13:12 PM PDT 24
Peak memory 212688 kb
Host smart-2751b3d1-2f49-4524-a855-cff55bba04f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570582828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3570582828
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.225847970
Short name T228
Test name
Test status
Simulation time 2824935988 ps
CPU time 12.75 seconds
Started Apr 23 02:12:45 PM PDT 24
Finished Apr 23 02:12:58 PM PDT 24
Peak memory 211316 kb
Host smart-6cd9aa20-8407-4bcb-9dd6-5e679b6a09c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225847970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.225847970
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1798615678
Short name T198
Test name
Test status
Simulation time 670486941 ps
CPU time 14.54 seconds
Started Apr 23 02:12:47 PM PDT 24
Finished Apr 23 02:13:02 PM PDT 24
Peak memory 213504 kb
Host smart-ea086600-f4e7-452d-9098-9f93399d8da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798615678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1798615678
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3852598011
Short name T348
Test name
Test status
Simulation time 4500950329 ps
CPU time 24.4 seconds
Started Apr 23 02:13:00 PM PDT 24
Finished Apr 23 02:13:25 PM PDT 24
Peak memory 219624 kb
Host smart-56df7bd1-0bba-4b65-9b3f-1cb0582207fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852598011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3852598011
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2200443942
Short name T273
Test name
Test status
Simulation time 89347343 ps
CPU time 4.15 seconds
Started Apr 23 02:13:02 PM PDT 24
Finished Apr 23 02:13:06 PM PDT 24
Peak memory 211440 kb
Host smart-391d6e98-975c-4ef9-91ce-f0dc96bd5d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200443942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2200443942
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2144142649
Short name T46
Test name
Test status
Simulation time 3268945595 ps
CPU time 77.72 seconds
Started Apr 23 02:13:00 PM PDT 24
Finished Apr 23 02:14:18 PM PDT 24
Peak memory 233936 kb
Host smart-d4b90e98-e85f-46bd-ab5a-d3f37b451159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144142649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2144142649
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.134688435
Short name T203
Test name
Test status
Simulation time 27370002509 ps
CPU time 29 seconds
Started Apr 23 02:12:51 PM PDT 24
Finished Apr 23 02:13:20 PM PDT 24
Peak memory 212248 kb
Host smart-e7c76d50-3ab7-43ef-8014-a7a9326ac9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134688435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.134688435
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.156389953
Short name T321
Test name
Test status
Simulation time 667441350 ps
CPU time 10.05 seconds
Started Apr 23 02:12:49 PM PDT 24
Finished Apr 23 02:13:00 PM PDT 24
Peak memory 211376 kb
Host smart-7924f169-a453-4be7-ada3-46f53704aa94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156389953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.156389953
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1892262818
Short name T171
Test name
Test status
Simulation time 32001186082 ps
CPU time 40.04 seconds
Started Apr 23 02:12:46 PM PDT 24
Finished Apr 23 02:13:26 PM PDT 24
Peak memory 219612 kb
Host smart-005695c8-f5fd-48d0-b9f6-dcfcbf266715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892262818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1892262818
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.762849467
Short name T361
Test name
Test status
Simulation time 3955520415 ps
CPU time 19.02 seconds
Started Apr 23 02:13:01 PM PDT 24
Finished Apr 23 02:13:21 PM PDT 24
Peak memory 213756 kb
Host smart-03828cf2-da1a-4a80-8275-151622ebc4d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762849467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.762849467
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1410698753
Short name T47
Test name
Test status
Simulation time 332414703570 ps
CPU time 2802.37 seconds
Started Apr 23 02:12:49 PM PDT 24
Finished Apr 23 02:59:32 PM PDT 24
Peak memory 246500 kb
Host smart-549f581c-c18b-491e-8c1d-6a1b4a5f06b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410698753 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1410698753
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2812773549
Short name T299
Test name
Test status
Simulation time 1255082431 ps
CPU time 11.06 seconds
Started Apr 23 02:12:26 PM PDT 24
Finished Apr 23 02:12:37 PM PDT 24
Peak memory 211468 kb
Host smart-41157562-9a26-4bad-bdbd-4a4edbe177d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812773549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2812773549
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3048885410
Short name T25
Test name
Test status
Simulation time 148325097070 ps
CPU time 321.73 seconds
Started Apr 23 02:12:28 PM PDT 24
Finished Apr 23 02:17:50 PM PDT 24
Peak memory 219812 kb
Host smart-e9d72f45-b55d-4622-a9cd-1806d84a0ca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048885410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3048885410
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.542647169
Short name T269
Test name
Test status
Simulation time 3972689855 ps
CPU time 30.81 seconds
Started Apr 23 02:12:29 PM PDT 24
Finished Apr 23 02:13:01 PM PDT 24
Peak memory 212204 kb
Host smart-6131f1e7-25e7-4c09-bc36-758b5ebe9860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542647169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.542647169
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1004679846
Short name T176
Test name
Test status
Simulation time 1584028070 ps
CPU time 10.39 seconds
Started Apr 23 02:12:31 PM PDT 24
Finished Apr 23 02:12:42 PM PDT 24
Peak memory 211376 kb
Host smart-b4b7e280-480e-480f-94df-1c6ca953cb85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004679846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1004679846
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.653371185
Short name T28
Test name
Test status
Simulation time 6105232414 ps
CPU time 61.42 seconds
Started Apr 23 02:12:27 PM PDT 24
Finished Apr 23 02:13:29 PM PDT 24
Peak memory 233992 kb
Host smart-974d133d-0f98-4dc8-9bed-32d5c317f3e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653371185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.653371185
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3929827541
Short name T81
Test name
Test status
Simulation time 183594343 ps
CPU time 10.41 seconds
Started Apr 23 02:12:24 PM PDT 24
Finished Apr 23 02:12:35 PM PDT 24
Peak memory 213640 kb
Host smart-c22c4842-9a99-429e-b812-0ff3dfaa43e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929827541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3929827541
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1466406742
Short name T45
Test name
Test status
Simulation time 30302188648 ps
CPU time 25.74 seconds
Started Apr 23 02:12:27 PM PDT 24
Finished Apr 23 02:12:54 PM PDT 24
Peak memory 219680 kb
Host smart-c26adcee-e59a-467a-b134-9aec3aaa5d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466406742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1466406742
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3821046920
Short name T61
Test name
Test status
Simulation time 6907959820 ps
CPU time 14.29 seconds
Started Apr 23 02:12:49 PM PDT 24
Finished Apr 23 02:13:04 PM PDT 24
Peak memory 211580 kb
Host smart-f7b36856-f6b3-4de9-a8ba-5f5e1e48bed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821046920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3821046920
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.892662273
Short name T42
Test name
Test status
Simulation time 6371392318 ps
CPU time 98.48 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:14:29 PM PDT 24
Peak memory 237004 kb
Host smart-fed97866-130b-4969-9274-91d61ae04f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892662273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.892662273
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2759623625
Short name T156
Test name
Test status
Simulation time 3899592618 ps
CPU time 31.11 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:13:21 PM PDT 24
Peak memory 212344 kb
Host smart-a91ccb8b-d45a-41f3-b5fa-52cd00725aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759623625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2759623625
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.339578900
Short name T282
Test name
Test status
Simulation time 8133025258 ps
CPU time 16.55 seconds
Started Apr 23 02:12:49 PM PDT 24
Finished Apr 23 02:13:06 PM PDT 24
Peak memory 211424 kb
Host smart-f3960a53-9e16-4256-aaac-5fcfd43727f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339578900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.339578900
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2407104770
Short name T160
Test name
Test status
Simulation time 14435525610 ps
CPU time 34.47 seconds
Started Apr 23 02:12:47 PM PDT 24
Finished Apr 23 02:13:21 PM PDT 24
Peak memory 214100 kb
Host smart-86a83dd5-7410-4f64-a19f-01a223822255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407104770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2407104770
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2471366081
Short name T234
Test name
Test status
Simulation time 210100152 ps
CPU time 13.57 seconds
Started Apr 23 02:12:48 PM PDT 24
Finished Apr 23 02:13:02 PM PDT 24
Peak memory 213460 kb
Host smart-87af5c6d-c545-452d-b9d4-ea7e312f76ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471366081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2471366081
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3677147018
Short name T158
Test name
Test status
Simulation time 165461198 ps
CPU time 4.2 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:12:55 PM PDT 24
Peak memory 211528 kb
Host smart-9ce1fd15-cd93-4dd4-94f1-c832d0190bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677147018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3677147018
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2788758598
Short name T370
Test name
Test status
Simulation time 2691444845 ps
CPU time 152.07 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:15:23 PM PDT 24
Peak memory 234364 kb
Host smart-b574a234-97e8-42e0-8b1c-2251104cef7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788758598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2788758598
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1728826443
Short name T180
Test name
Test status
Simulation time 8611751594 ps
CPU time 22.29 seconds
Started Apr 23 02:12:51 PM PDT 24
Finished Apr 23 02:13:14 PM PDT 24
Peak memory 212368 kb
Host smart-62961ded-8685-4ffb-bfc4-80e05c5cb22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728826443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1728826443
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3528253842
Short name T153
Test name
Test status
Simulation time 2275430574 ps
CPU time 8.86 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:13:00 PM PDT 24
Peak memory 211384 kb
Host smart-b3263504-0388-4ac7-ae94-c2c8a8b53c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528253842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3528253842
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.257890790
Short name T221
Test name
Test status
Simulation time 6012514071 ps
CPU time 26.34 seconds
Started Apr 23 02:13:00 PM PDT 24
Finished Apr 23 02:13:27 PM PDT 24
Peak memory 219564 kb
Host smart-3d527198-e7a2-4431-b68b-f28cdb3d01d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257890790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.257890790
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1647096000
Short name T247
Test name
Test status
Simulation time 568241544 ps
CPU time 26.3 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:13:17 PM PDT 24
Peak memory 214048 kb
Host smart-7abac094-07c1-4cad-bd87-d631d01785da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647096000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1647096000
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1087207940
Short name T205
Test name
Test status
Simulation time 495475521 ps
CPU time 7.36 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:12:58 PM PDT 24
Peak memory 211472 kb
Host smart-4e67ab43-9704-40ba-bc9b-96a89ba48760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087207940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1087207940
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3777751748
Short name T227
Test name
Test status
Simulation time 30784872450 ps
CPU time 149.98 seconds
Started Apr 23 02:12:49 PM PDT 24
Finished Apr 23 02:15:20 PM PDT 24
Peak memory 237072 kb
Host smart-187ff0cf-91dc-4625-8afa-7475c9c89db5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777751748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3777751748
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1936764465
Short name T195
Test name
Test status
Simulation time 4034351022 ps
CPU time 32.7 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:13:24 PM PDT 24
Peak memory 211980 kb
Host smart-05bd7a3b-64d5-4947-968d-6748e5675876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936764465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1936764465
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.605054219
Short name T304
Test name
Test status
Simulation time 436650339 ps
CPU time 5.43 seconds
Started Apr 23 02:13:01 PM PDT 24
Finished Apr 23 02:13:07 PM PDT 24
Peak memory 211276 kb
Host smart-fba29fa2-aefe-4741-b398-9ea5e0b1d0af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605054219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.605054219
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2035310284
Short name T293
Test name
Test status
Simulation time 4285862487 ps
CPU time 40.05 seconds
Started Apr 23 02:13:01 PM PDT 24
Finished Apr 23 02:13:42 PM PDT 24
Peak memory 213492 kb
Host smart-6e64dba7-724d-4382-a737-207ba6eba99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035310284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2035310284
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1832689269
Short name T263
Test name
Test status
Simulation time 34315027907 ps
CPU time 34.41 seconds
Started Apr 23 02:12:47 PM PDT 24
Finished Apr 23 02:13:22 PM PDT 24
Peak memory 219696 kb
Host smart-564d5eb8-eadd-4ef1-acab-2c1bdcc40f45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832689269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1832689269
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.501302334
Short name T59
Test name
Test status
Simulation time 8927551393 ps
CPU time 10.22 seconds
Started Apr 23 02:12:52 PM PDT 24
Finished Apr 23 02:13:03 PM PDT 24
Peak memory 211596 kb
Host smart-e92cbefc-3633-40a0-bdda-8ed98610acb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501302334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.501302334
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.322855541
Short name T220
Test name
Test status
Simulation time 97126795213 ps
CPU time 203.25 seconds
Started Apr 23 02:12:53 PM PDT 24
Finished Apr 23 02:16:17 PM PDT 24
Peak memory 224840 kb
Host smart-d945fb04-0e7c-4e06-98e0-ec58f3715520
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322855541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.322855541
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1937451000
Short name T260
Test name
Test status
Simulation time 3077801714 ps
CPU time 15.06 seconds
Started Apr 23 02:12:51 PM PDT 24
Finished Apr 23 02:13:07 PM PDT 24
Peak memory 212136 kb
Host smart-b23d89b6-c688-49ad-ad6c-143287c254b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937451000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1937451000
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3562540879
Short name T250
Test name
Test status
Simulation time 1536486966 ps
CPU time 14.34 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:13:05 PM PDT 24
Peak memory 211312 kb
Host smart-4d8ac0e6-6264-4a20-84c6-413b2e1033d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562540879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3562540879
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1024769470
Short name T258
Test name
Test status
Simulation time 178859399 ps
CPU time 10.93 seconds
Started Apr 23 02:12:53 PM PDT 24
Finished Apr 23 02:13:05 PM PDT 24
Peak memory 219544 kb
Host smart-26c58547-fd27-4361-9be9-879c5eafc946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024769470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1024769470
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2417990882
Short name T254
Test name
Test status
Simulation time 3452196037 ps
CPU time 37.08 seconds
Started Apr 23 02:12:51 PM PDT 24
Finished Apr 23 02:13:28 PM PDT 24
Peak memory 219640 kb
Host smart-46aeb279-385c-4ca5-b428-79e5f2e5f559
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417990882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2417990882
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2737420561
Short name T255
Test name
Test status
Simulation time 87980125 ps
CPU time 4.35 seconds
Started Apr 23 02:12:54 PM PDT 24
Finished Apr 23 02:12:58 PM PDT 24
Peak memory 211552 kb
Host smart-24bc5262-f024-4e5d-98dc-39a2be900f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737420561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2737420561
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4181516966
Short name T351
Test name
Test status
Simulation time 30841915610 ps
CPU time 271.09 seconds
Started Apr 23 02:12:55 PM PDT 24
Finished Apr 23 02:17:27 PM PDT 24
Peak memory 212796 kb
Host smart-b561b347-49fd-493d-876e-8f9b2d5d5b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181516966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4181516966
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1203015668
Short name T209
Test name
Test status
Simulation time 5883926585 ps
CPU time 19.18 seconds
Started Apr 23 02:12:54 PM PDT 24
Finished Apr 23 02:13:13 PM PDT 24
Peak memory 212512 kb
Host smart-9990b1b9-0733-45cd-81d3-bc11b8610759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203015668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1203015668
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1730555435
Short name T194
Test name
Test status
Simulation time 99300169 ps
CPU time 6.24 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:12:57 PM PDT 24
Peak memory 211316 kb
Host smart-d72d9c3f-a977-42ce-b959-39752a615b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730555435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1730555435
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.879402049
Short name T169
Test name
Test status
Simulation time 12874803630 ps
CPU time 30.34 seconds
Started Apr 23 02:12:50 PM PDT 24
Finished Apr 23 02:13:21 PM PDT 24
Peak memory 214128 kb
Host smart-312b0ed9-0c6e-4b0c-adba-67d6061a70f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879402049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.879402049
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3568636064
Short name T289
Test name
Test status
Simulation time 3686269521 ps
CPU time 38.9 seconds
Started Apr 23 02:12:53 PM PDT 24
Finished Apr 23 02:13:33 PM PDT 24
Peak memory 219616 kb
Host smart-b69302dc-8aa4-4a7d-8cd9-1ea3f75d8e1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568636064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3568636064
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.666686482
Short name T306
Test name
Test status
Simulation time 89290609 ps
CPU time 4.16 seconds
Started Apr 23 02:12:56 PM PDT 24
Finished Apr 23 02:13:01 PM PDT 24
Peak memory 211472 kb
Host smart-bf135f4c-5ba8-421c-8940-aa48f92e06a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666686482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.666686482
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3082029284
Short name T34
Test name
Test status
Simulation time 45439196413 ps
CPU time 124.33 seconds
Started Apr 23 02:12:54 PM PDT 24
Finished Apr 23 02:14:59 PM PDT 24
Peak memory 237280 kb
Host smart-bcb57d62-fad0-4541-a78e-01a2a344fda0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082029284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3082029284
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3177196881
Short name T224
Test name
Test status
Simulation time 14500341284 ps
CPU time 26.73 seconds
Started Apr 23 02:12:57 PM PDT 24
Finished Apr 23 02:13:24 PM PDT 24
Peak memory 212444 kb
Host smart-6a3d80a3-30b0-4d3d-b5d3-19bebfaa1833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177196881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3177196881
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3830073480
Short name T190
Test name
Test status
Simulation time 1577780907 ps
CPU time 7.8 seconds
Started Apr 23 02:12:53 PM PDT 24
Finished Apr 23 02:13:01 PM PDT 24
Peak memory 211360 kb
Host smart-626cb590-9dfb-4ec2-aed6-6a0319cb8622
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830073480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3830073480
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3744102606
Short name T373
Test name
Test status
Simulation time 3863992262 ps
CPU time 31.24 seconds
Started Apr 23 02:12:55 PM PDT 24
Finished Apr 23 02:13:26 PM PDT 24
Peak memory 213680 kb
Host smart-11ff77e5-d6fc-4524-8485-ff0c392fa35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744102606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3744102606
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2343950687
Short name T178
Test name
Test status
Simulation time 44643978103 ps
CPU time 87.52 seconds
Started Apr 23 02:12:53 PM PDT 24
Finished Apr 23 02:14:21 PM PDT 24
Peak memory 219676 kb
Host smart-e5a710cf-e04e-4a98-a9b6-66f228fa4703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343950687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2343950687
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2003290977
Short name T235
Test name
Test status
Simulation time 5015180567 ps
CPU time 11.08 seconds
Started Apr 23 02:12:59 PM PDT 24
Finished Apr 23 02:13:11 PM PDT 24
Peak memory 211564 kb
Host smart-f680ed4d-8a73-41b7-8ec5-1676b6cddcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003290977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2003290977
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1197450103
Short name T292
Test name
Test status
Simulation time 27663760825 ps
CPU time 141.71 seconds
Started Apr 23 02:12:57 PM PDT 24
Finished Apr 23 02:15:19 PM PDT 24
Peak memory 227372 kb
Host smart-c2649f62-abba-42e6-b7ca-3ed3a9c6543a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197450103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1197450103
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1108112189
Short name T340
Test name
Test status
Simulation time 7368656612 ps
CPU time 29.35 seconds
Started Apr 23 02:12:57 PM PDT 24
Finished Apr 23 02:13:27 PM PDT 24
Peak memory 212520 kb
Host smart-ab871426-8e79-4436-a0bb-8c7d8fd133c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108112189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1108112189
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3546167115
Short name T1
Test name
Test status
Simulation time 8178247285 ps
CPU time 16.62 seconds
Started Apr 23 02:12:57 PM PDT 24
Finished Apr 23 02:13:14 PM PDT 24
Peak memory 211372 kb
Host smart-94b187bd-c20a-4d6d-8845-7a38e3f48151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546167115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3546167115
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2068489567
Short name T189
Test name
Test status
Simulation time 7586627750 ps
CPU time 46.98 seconds
Started Apr 23 02:12:59 PM PDT 24
Finished Apr 23 02:13:46 PM PDT 24
Peak memory 217224 kb
Host smart-07ea7c2f-e361-4662-8425-83aab3ed2373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068489567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2068489567
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2707726110
Short name T2
Test name
Test status
Simulation time 3270753047 ps
CPU time 9.39 seconds
Started Apr 23 02:13:01 PM PDT 24
Finished Apr 23 02:13:11 PM PDT 24
Peak memory 211512 kb
Host smart-f3c646e7-7ac5-46ce-ab80-f38498282cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707726110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2707726110
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3041828336
Short name T100
Test name
Test status
Simulation time 86562194799 ps
CPU time 275.33 seconds
Started Apr 23 02:13:00 PM PDT 24
Finished Apr 23 02:17:36 PM PDT 24
Peak memory 237116 kb
Host smart-ec06ff16-973a-4591-a0b8-078b07afffdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041828336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3041828336
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3268248326
Short name T337
Test name
Test status
Simulation time 72127580539 ps
CPU time 30.22 seconds
Started Apr 23 02:13:00 PM PDT 24
Finished Apr 23 02:13:31 PM PDT 24
Peak memory 212728 kb
Host smart-fb4ef284-9900-4116-8528-11748892a553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268248326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3268248326
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.7091146
Short name T10
Test name
Test status
Simulation time 875518487 ps
CPU time 16.21 seconds
Started Apr 23 02:13:00 PM PDT 24
Finished Apr 23 02:13:16 PM PDT 24
Peak memory 213188 kb
Host smart-51a99189-870d-41f8-b3ca-8f53da54e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7091146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.7091146
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2095144552
Short name T213
Test name
Test status
Simulation time 3235982478 ps
CPU time 44.9 seconds
Started Apr 23 02:13:03 PM PDT 24
Finished Apr 23 02:13:48 PM PDT 24
Peak memory 213876 kb
Host smart-604702e8-81df-45ed-b152-60326e2a54a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095144552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2095144552
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1857029949
Short name T179
Test name
Test status
Simulation time 1572302668 ps
CPU time 13.42 seconds
Started Apr 23 02:13:04 PM PDT 24
Finished Apr 23 02:13:18 PM PDT 24
Peak memory 211456 kb
Host smart-8f2f56fa-710e-47d4-850f-98ce3cf7d8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857029949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1857029949
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4225589876
Short name T354
Test name
Test status
Simulation time 34755818406 ps
CPU time 175.15 seconds
Started Apr 23 02:13:03 PM PDT 24
Finished Apr 23 02:15:59 PM PDT 24
Peak memory 224980 kb
Host smart-62232bc7-3eca-4ac3-8004-3e5028c5c84d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225589876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4225589876
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2834896429
Short name T229
Test name
Test status
Simulation time 4434986602 ps
CPU time 22.97 seconds
Started Apr 23 02:13:08 PM PDT 24
Finished Apr 23 02:13:32 PM PDT 24
Peak memory 212252 kb
Host smart-a18d8974-3a6d-46c7-9269-600d5c5337c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834896429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2834896429
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4003251431
Short name T170
Test name
Test status
Simulation time 3099592167 ps
CPU time 9.85 seconds
Started Apr 23 02:13:04 PM PDT 24
Finished Apr 23 02:13:14 PM PDT 24
Peak memory 211408 kb
Host smart-675af274-9e04-4a63-868e-744fb8581355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003251431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4003251431
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3386936661
Short name T217
Test name
Test status
Simulation time 3744149895 ps
CPU time 30.42 seconds
Started Apr 23 02:13:05 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 213196 kb
Host smart-8d5b1aef-652a-46b7-867c-288e6d3e0242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386936661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3386936661
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.131988155
Short name T296
Test name
Test status
Simulation time 4387877553 ps
CPU time 36.4 seconds
Started Apr 23 02:13:04 PM PDT 24
Finished Apr 23 02:13:41 PM PDT 24
Peak memory 215324 kb
Host smart-4327c5ea-1e3f-43f6-b0b6-e570115f3bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131988155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.131988155
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.649623337
Short name T280
Test name
Test status
Simulation time 7878021494 ps
CPU time 15.61 seconds
Started Apr 23 02:13:06 PM PDT 24
Finished Apr 23 02:13:22 PM PDT 24
Peak memory 211560 kb
Host smart-25a49fc7-df4e-4a3e-a49f-8679996b6e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649623337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.649623337
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2373904700
Short name T24
Test name
Test status
Simulation time 8169665477 ps
CPU time 119.89 seconds
Started Apr 23 02:13:09 PM PDT 24
Finished Apr 23 02:15:10 PM PDT 24
Peak memory 238124 kb
Host smart-0daa2ea7-01b1-4c88-bd23-43ec34de8e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373904700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2373904700
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.940514321
Short name T163
Test name
Test status
Simulation time 3832293677 ps
CPU time 31 seconds
Started Apr 23 02:13:09 PM PDT 24
Finished Apr 23 02:13:40 PM PDT 24
Peak memory 211976 kb
Host smart-f2c487f8-0d54-4590-8715-5d00c3a7fd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940514321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.940514321
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2018282599
Short name T244
Test name
Test status
Simulation time 2188192777 ps
CPU time 17.39 seconds
Started Apr 23 02:13:06 PM PDT 24
Finished Apr 23 02:13:24 PM PDT 24
Peak memory 211420 kb
Host smart-db9fb9c2-35a3-4871-a0e5-69d8df92ec4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018282599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2018282599
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.610249324
Short name T79
Test name
Test status
Simulation time 1304510669 ps
CPU time 19.31 seconds
Started Apr 23 02:13:09 PM PDT 24
Finished Apr 23 02:13:29 PM PDT 24
Peak memory 219548 kb
Host smart-2d5b9f88-ac17-4264-a1b8-4717ca8efdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610249324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.610249324
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.502218340
Short name T78
Test name
Test status
Simulation time 3037766339 ps
CPU time 19.31 seconds
Started Apr 23 02:13:07 PM PDT 24
Finished Apr 23 02:13:27 PM PDT 24
Peak memory 212196 kb
Host smart-9f04c405-89ca-4470-a30f-87aebf1f6405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502218340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.502218340
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3806232663
Short name T288
Test name
Test status
Simulation time 6496292105 ps
CPU time 15.09 seconds
Started Apr 23 02:12:29 PM PDT 24
Finished Apr 23 02:12:45 PM PDT 24
Peak memory 211428 kb
Host smart-363cea86-0485-4e56-aebf-d3ac992e3c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806232663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3806232663
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.749499341
Short name T43
Test name
Test status
Simulation time 1538038993 ps
CPU time 90.82 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 236860 kb
Host smart-a49da09d-61a3-41d7-aa42-027fd6ce7c49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749499341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.749499341
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.460065835
Short name T184
Test name
Test status
Simulation time 1530840054 ps
CPU time 13.77 seconds
Started Apr 23 02:12:29 PM PDT 24
Finished Apr 23 02:12:43 PM PDT 24
Peak memory 211284 kb
Host smart-ecc8001b-9347-4f8f-893f-a6f9c0ac646b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460065835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.460065835
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.884262843
Short name T201
Test name
Test status
Simulation time 10656995773 ps
CPU time 32.1 seconds
Started Apr 23 02:12:26 PM PDT 24
Finished Apr 23 02:12:58 PM PDT 24
Peak memory 214372 kb
Host smart-de8791ff-362e-43d3-80f6-5d0327ea5bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884262843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.884262843
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1066521485
Short name T344
Test name
Test status
Simulation time 586420867 ps
CPU time 31.31 seconds
Started Apr 23 02:12:26 PM PDT 24
Finished Apr 23 02:12:58 PM PDT 24
Peak memory 217008 kb
Host smart-390f0731-8214-4ca3-8510-54f5e924f383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066521485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1066521485
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.586651769
Short name T358
Test name
Test status
Simulation time 95073315353 ps
CPU time 3631.96 seconds
Started Apr 23 02:12:28 PM PDT 24
Finished Apr 23 03:13:01 PM PDT 24
Peak memory 245764 kb
Host smart-fcfb35b7-2af2-40e5-bf79-1d13df9d0007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586651769 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.586651769
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1259193948
Short name T257
Test name
Test status
Simulation time 5926104804 ps
CPU time 13.41 seconds
Started Apr 23 02:13:11 PM PDT 24
Finished Apr 23 02:13:25 PM PDT 24
Peak memory 211544 kb
Host smart-87919b0b-10d7-42c8-b7f2-cc47138a4df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259193948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1259193948
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2733777406
Short name T286
Test name
Test status
Simulation time 107634984482 ps
CPU time 188 seconds
Started Apr 23 02:13:11 PM PDT 24
Finished Apr 23 02:16:20 PM PDT 24
Peak memory 225200 kb
Host smart-069c77be-7ecd-4bce-a545-ea60f74549b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733777406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2733777406
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4184526020
Short name T173
Test name
Test status
Simulation time 2232829975 ps
CPU time 22.72 seconds
Started Apr 23 02:13:11 PM PDT 24
Finished Apr 23 02:13:34 PM PDT 24
Peak memory 212016 kb
Host smart-51584af7-e859-4209-bb02-a35adea40465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184526020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4184526020
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3020717418
Short name T342
Test name
Test status
Simulation time 584945396 ps
CPU time 9.35 seconds
Started Apr 23 02:13:11 PM PDT 24
Finished Apr 23 02:13:21 PM PDT 24
Peak memory 211360 kb
Host smart-8dd412fc-01f1-4bdf-8d31-af82fcca52ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020717418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3020717418
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3596396394
Short name T298
Test name
Test status
Simulation time 4109438185 ps
CPU time 41.99 seconds
Started Apr 23 02:13:06 PM PDT 24
Finished Apr 23 02:13:49 PM PDT 24
Peak memory 219724 kb
Host smart-eb9c553d-8f45-4c9a-9cde-e11475425d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596396394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3596396394
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.801113539
Short name T164
Test name
Test status
Simulation time 15744183003 ps
CPU time 70.57 seconds
Started Apr 23 02:13:08 PM PDT 24
Finished Apr 23 02:14:20 PM PDT 24
Peak memory 219676 kb
Host smart-991c859b-da7d-480a-a51c-d1926df3375f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801113539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.801113539
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1535189010
Short name T303
Test name
Test status
Simulation time 37665185752 ps
CPU time 2115.9 seconds
Started Apr 23 02:13:12 PM PDT 24
Finished Apr 23 02:48:29 PM PDT 24
Peak memory 233724 kb
Host smart-5ffdd5ec-8d05-4945-803d-27e767024cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535189010 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1535189010
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2943440965
Short name T317
Test name
Test status
Simulation time 8103272089 ps
CPU time 15.76 seconds
Started Apr 23 02:13:12 PM PDT 24
Finished Apr 23 02:13:28 PM PDT 24
Peak memory 211468 kb
Host smart-00aab9f6-1a8a-4ac2-a32c-c8e5aa0fdcac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943440965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2943440965
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.885116650
Short name T159
Test name
Test status
Simulation time 29913400117 ps
CPU time 154.81 seconds
Started Apr 23 02:13:08 PM PDT 24
Finished Apr 23 02:15:44 PM PDT 24
Peak memory 231168 kb
Host smart-0d56aef2-a522-45c0-8894-eb387b818515
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885116650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.885116650
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2503857979
Short name T276
Test name
Test status
Simulation time 8203505453 ps
CPU time 32.96 seconds
Started Apr 23 02:13:10 PM PDT 24
Finished Apr 23 02:13:43 PM PDT 24
Peak memory 212536 kb
Host smart-3926df77-5107-4f97-8250-20d49eaf60eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503857979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2503857979
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1160498592
Short name T315
Test name
Test status
Simulation time 785822939 ps
CPU time 8.31 seconds
Started Apr 23 02:13:11 PM PDT 24
Finished Apr 23 02:13:20 PM PDT 24
Peak memory 211368 kb
Host smart-5f52361d-1e08-41ae-b399-980afc6e8887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160498592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1160498592
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.100081003
Short name T320
Test name
Test status
Simulation time 1984852161 ps
CPU time 21.73 seconds
Started Apr 23 02:13:11 PM PDT 24
Finished Apr 23 02:13:33 PM PDT 24
Peak memory 219604 kb
Host smart-a801871d-2b3b-42d0-951e-01dcda1e3fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100081003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.100081003
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3296638500
Short name T313
Test name
Test status
Simulation time 1885176454 ps
CPU time 23.25 seconds
Started Apr 23 02:13:12 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 213752 kb
Host smart-ec1f94e2-5e63-4c2f-a222-344c8cd91906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296638500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3296638500
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.82181324
Short name T347
Test name
Test status
Simulation time 19383620350 ps
CPU time 14.83 seconds
Started Apr 23 02:13:15 PM PDT 24
Finished Apr 23 02:13:30 PM PDT 24
Peak memory 211556 kb
Host smart-6200565e-4ad2-4e38-9029-c630981e9dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82181324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.82181324
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3776196524
Short name T268
Test name
Test status
Simulation time 22771178013 ps
CPU time 264.58 seconds
Started Apr 23 02:13:16 PM PDT 24
Finished Apr 23 02:17:41 PM PDT 24
Peak memory 238392 kb
Host smart-f585cbc4-bed7-453d-82b1-6c060bf70b7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776196524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3776196524
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.505377504
Short name T281
Test name
Test status
Simulation time 490915447 ps
CPU time 9.26 seconds
Started Apr 23 02:13:13 PM PDT 24
Finished Apr 23 02:13:22 PM PDT 24
Peak memory 211964 kb
Host smart-497bc59b-0096-48e7-bfd6-11731e837beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505377504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.505377504
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1657142309
Short name T310
Test name
Test status
Simulation time 9155448956 ps
CPU time 16.69 seconds
Started Apr 23 02:13:16 PM PDT 24
Finished Apr 23 02:13:33 PM PDT 24
Peak memory 211380 kb
Host smart-b596c376-28ad-42ae-8977-d47c30318e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657142309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1657142309
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1981378308
Short name T366
Test name
Test status
Simulation time 4406038542 ps
CPU time 11.58 seconds
Started Apr 23 02:13:14 PM PDT 24
Finished Apr 23 02:13:26 PM PDT 24
Peak memory 213496 kb
Host smart-8ccd4bc2-c367-4155-8cce-f279fe605ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981378308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1981378308
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3812126388
Short name T30
Test name
Test status
Simulation time 6805646305 ps
CPU time 13.54 seconds
Started Apr 23 02:13:20 PM PDT 24
Finished Apr 23 02:13:34 PM PDT 24
Peak memory 211584 kb
Host smart-a0bdef6c-9f4a-4cbf-b99b-11cde5c7e158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812126388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3812126388
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.152435885
Short name T215
Test name
Test status
Simulation time 13738172452 ps
CPU time 177.2 seconds
Started Apr 23 02:13:16 PM PDT 24
Finished Apr 23 02:16:14 PM PDT 24
Peak memory 234412 kb
Host smart-c193cfb4-61fe-490f-a8b5-11ca88bf8e75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152435885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.152435885
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3310125237
Short name T353
Test name
Test status
Simulation time 2880810955 ps
CPU time 25.95 seconds
Started Apr 23 02:13:17 PM PDT 24
Finished Apr 23 02:13:44 PM PDT 24
Peak memory 211540 kb
Host smart-783840b7-f0a2-4798-b9cd-f166a59e5c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310125237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3310125237
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.375494302
Short name T200
Test name
Test status
Simulation time 7760061983 ps
CPU time 16.59 seconds
Started Apr 23 02:13:17 PM PDT 24
Finished Apr 23 02:13:34 PM PDT 24
Peak memory 211360 kb
Host smart-8328aedc-9908-49ad-9e83-559e6fa5554e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375494302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.375494302
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.749998359
Short name T188
Test name
Test status
Simulation time 4545297829 ps
CPU time 13.93 seconds
Started Apr 23 02:13:17 PM PDT 24
Finished Apr 23 02:13:32 PM PDT 24
Peak memory 219652 kb
Host smart-28be59c6-0037-4257-b083-a7fc1dd60804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749998359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.749998359
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3733084585
Short name T3
Test name
Test status
Simulation time 10978153657 ps
CPU time 56.09 seconds
Started Apr 23 02:13:15 PM PDT 24
Finished Apr 23 02:14:11 PM PDT 24
Peak memory 219652 kb
Host smart-981fc742-ff96-4b7f-a685-f6bbb186b96c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733084585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3733084585
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2343068690
Short name T225
Test name
Test status
Simulation time 90196509 ps
CPU time 4.33 seconds
Started Apr 23 02:13:17 PM PDT 24
Finished Apr 23 02:13:22 PM PDT 24
Peak memory 211540 kb
Host smart-bd7795da-d9a4-4ec5-b733-571c77525994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343068690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2343068690
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1066616162
Short name T26
Test name
Test status
Simulation time 2891230565 ps
CPU time 149.57 seconds
Started Apr 23 02:13:18 PM PDT 24
Finished Apr 23 02:15:48 PM PDT 24
Peak memory 229040 kb
Host smart-e3bc175e-2f6a-4791-8d0e-a846b45800f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066616162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1066616162
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.644294162
Short name T144
Test name
Test status
Simulation time 13800790157 ps
CPU time 23.14 seconds
Started Apr 23 02:13:17 PM PDT 24
Finished Apr 23 02:13:41 PM PDT 24
Peak memory 214004 kb
Host smart-49d84bbd-d8d3-4db9-808c-51452f4ab6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644294162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.644294162
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2234212968
Short name T338
Test name
Test status
Simulation time 382276540 ps
CPU time 5.27 seconds
Started Apr 23 02:13:18 PM PDT 24
Finished Apr 23 02:13:24 PM PDT 24
Peak memory 211316 kb
Host smart-0182a7fa-3231-4572-888e-66ca90b98afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2234212968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2234212968
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1390685762
Short name T256
Test name
Test status
Simulation time 11431132189 ps
CPU time 21.77 seconds
Started Apr 23 02:13:18 PM PDT 24
Finished Apr 23 02:13:40 PM PDT 24
Peak memory 214104 kb
Host smart-3b67aa1e-d20a-4aa9-8d35-f9566e140dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390685762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1390685762
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2185111215
Short name T357
Test name
Test status
Simulation time 23117167403 ps
CPU time 96.26 seconds
Started Apr 23 02:13:19 PM PDT 24
Finished Apr 23 02:14:56 PM PDT 24
Peak memory 219708 kb
Host smart-cecc6719-9504-4477-a4e6-709000a4a811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185111215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2185111215
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2253511498
Short name T52
Test name
Test status
Simulation time 18792568077 ps
CPU time 4337.18 seconds
Started Apr 23 02:13:20 PM PDT 24
Finished Apr 23 03:25:37 PM PDT 24
Peak memory 228176 kb
Host smart-9b9b656f-f05a-47ff-98dc-d2d99786c022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253511498 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2253511498
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3438317450
Short name T140
Test name
Test status
Simulation time 1190124619 ps
CPU time 11.49 seconds
Started Apr 23 02:13:22 PM PDT 24
Finished Apr 23 02:13:34 PM PDT 24
Peak memory 211484 kb
Host smart-7b5d44e9-140b-489c-a96e-be2d623fa541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438317450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3438317450
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.18051483
Short name T301
Test name
Test status
Simulation time 44594324275 ps
CPU time 386 seconds
Started Apr 23 02:13:20 PM PDT 24
Finished Apr 23 02:19:47 PM PDT 24
Peak memory 235144 kb
Host smart-54274d8a-1bc7-4474-8e14-fc7fb365313f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18051483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_co
rrupt_sig_fatal_chk.18051483
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3051102350
Short name T341
Test name
Test status
Simulation time 692335882 ps
CPU time 9.35 seconds
Started Apr 23 02:13:25 PM PDT 24
Finished Apr 23 02:13:35 PM PDT 24
Peak memory 211472 kb
Host smart-0a996bc4-a38e-485b-8025-eca21a1cfcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051102350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3051102350
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.425327626
Short name T333
Test name
Test status
Simulation time 7724070569 ps
CPU time 16.32 seconds
Started Apr 23 02:13:22 PM PDT 24
Finished Apr 23 02:13:38 PM PDT 24
Peak memory 211412 kb
Host smart-9ec52984-7dc3-4077-90aa-e7141f5f08ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425327626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.425327626
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2821249323
Short name T355
Test name
Test status
Simulation time 4197859552 ps
CPU time 14.55 seconds
Started Apr 23 02:13:20 PM PDT 24
Finished Apr 23 02:13:35 PM PDT 24
Peak memory 219612 kb
Host smart-8499642b-c5b1-4913-bd55-73312dcb3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821249323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2821249323
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2546569828
Short name T241
Test name
Test status
Simulation time 7096118634 ps
CPU time 40.82 seconds
Started Apr 23 02:13:21 PM PDT 24
Finished Apr 23 02:14:03 PM PDT 24
Peak memory 213776 kb
Host smart-ac7fb0c0-8a9a-4cec-af1d-c0ed5b2c0082
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546569828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2546569828
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.987500899
Short name T58
Test name
Test status
Simulation time 4582561354 ps
CPU time 8.99 seconds
Started Apr 23 02:13:26 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 211584 kb
Host smart-2a09e39e-82a5-4f5b-8d60-435ccbea5117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987500899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.987500899
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.605794917
Short name T345
Test name
Test status
Simulation time 2891907815 ps
CPU time 96.27 seconds
Started Apr 23 02:13:21 PM PDT 24
Finished Apr 23 02:14:57 PM PDT 24
Peak memory 230004 kb
Host smart-d5ac64d7-5b3c-47df-a58e-2acf9a0df3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605794917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.605794917
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2801421606
Short name T17
Test name
Test status
Simulation time 738419158 ps
CPU time 10.39 seconds
Started Apr 23 02:13:25 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 215988 kb
Host smart-40f6546e-fcc5-46d2-8091-64ce3fd711ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801421606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2801421606
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2190876548
Short name T226
Test name
Test status
Simulation time 4300436225 ps
CPU time 17.42 seconds
Started Apr 23 02:13:22 PM PDT 24
Finished Apr 23 02:13:39 PM PDT 24
Peak memory 211332 kb
Host smart-c7eaeef7-3d5e-473e-b7d0-30166daa2c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190876548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2190876548
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.489282829
Short name T239
Test name
Test status
Simulation time 617239573 ps
CPU time 15.42 seconds
Started Apr 23 02:13:20 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 219440 kb
Host smart-01c5f640-12c7-49da-86e0-e8cddd41d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489282829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.489282829
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2889324275
Short name T275
Test name
Test status
Simulation time 123573099 ps
CPU time 5.99 seconds
Started Apr 23 02:13:21 PM PDT 24
Finished Apr 23 02:13:27 PM PDT 24
Peak memory 211480 kb
Host smart-e459bca4-1ab1-4ebf-9aef-b1fe713954f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889324275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2889324275
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2785304572
Short name T295
Test name
Test status
Simulation time 6260483105 ps
CPU time 10.69 seconds
Started Apr 23 02:13:28 PM PDT 24
Finished Apr 23 02:13:39 PM PDT 24
Peak memory 211552 kb
Host smart-c761e525-110f-41a6-8502-dea8b3b4a263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785304572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2785304572
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1539635063
Short name T349
Test name
Test status
Simulation time 3718179448 ps
CPU time 134.93 seconds
Started Apr 23 02:13:26 PM PDT 24
Finished Apr 23 02:15:41 PM PDT 24
Peak memory 230048 kb
Host smart-5d7d734d-962a-4c7a-9336-45cebd868a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539635063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1539635063
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1960292324
Short name T36
Test name
Test status
Simulation time 10280552524 ps
CPU time 24.13 seconds
Started Apr 23 02:13:24 PM PDT 24
Finished Apr 23 02:13:48 PM PDT 24
Peak memory 212728 kb
Host smart-f49ae199-2b70-4502-9c78-183ee67bce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960292324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1960292324
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.46698890
Short name T309
Test name
Test status
Simulation time 918284080 ps
CPU time 5.29 seconds
Started Apr 23 02:13:26 PM PDT 24
Finished Apr 23 02:13:32 PM PDT 24
Peak memory 211240 kb
Host smart-021df607-5a05-437a-a875-c54219bacd7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46698890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.46698890
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1629229132
Short name T297
Test name
Test status
Simulation time 1049552840 ps
CPU time 10.34 seconds
Started Apr 23 02:13:25 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 213132 kb
Host smart-5bcbd20b-487b-4e43-aebe-fc416684fe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629229132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1629229132
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2978185891
Short name T251
Test name
Test status
Simulation time 1505889013 ps
CPU time 20.6 seconds
Started Apr 23 02:13:24 PM PDT 24
Finished Apr 23 02:13:45 PM PDT 24
Peak memory 215608 kb
Host smart-2b575642-504b-49c1-9a3d-fb9baa5306fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978185891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2978185891
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3629926932
Short name T182
Test name
Test status
Simulation time 2236781293 ps
CPU time 8.08 seconds
Started Apr 23 02:13:27 PM PDT 24
Finished Apr 23 02:13:36 PM PDT 24
Peak memory 211620 kb
Host smart-9a0c5408-6023-4b71-a567-4791827d69cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629926932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3629926932
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3719729274
Short name T141
Test name
Test status
Simulation time 25679814815 ps
CPU time 339.48 seconds
Started Apr 23 02:13:26 PM PDT 24
Finished Apr 23 02:19:06 PM PDT 24
Peak memory 228796 kb
Host smart-91f28488-488e-446b-8804-064080025516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719729274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3719729274
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.258486029
Short name T363
Test name
Test status
Simulation time 3659819106 ps
CPU time 30.36 seconds
Started Apr 23 02:13:32 PM PDT 24
Finished Apr 23 02:14:03 PM PDT 24
Peak memory 212052 kb
Host smart-0c9517e5-f2e4-4848-b84e-4da8ed555f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258486029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.258486029
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1386881621
Short name T151
Test name
Test status
Simulation time 1572233273 ps
CPU time 15.08 seconds
Started Apr 23 02:13:28 PM PDT 24
Finished Apr 23 02:13:44 PM PDT 24
Peak memory 211316 kb
Host smart-640a1393-2be4-4c6a-9335-5c4a3cc34aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386881621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1386881621
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2802900685
Short name T142
Test name
Test status
Simulation time 2440016926 ps
CPU time 14.05 seconds
Started Apr 23 02:13:29 PM PDT 24
Finished Apr 23 02:13:44 PM PDT 24
Peak memory 219612 kb
Host smart-60bf1219-1645-4cb0-aaae-5bf9421f389c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802900685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2802900685
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1112295698
Short name T183
Test name
Test status
Simulation time 7384027249 ps
CPU time 18.28 seconds
Started Apr 23 02:13:29 PM PDT 24
Finished Apr 23 02:13:48 PM PDT 24
Peak memory 211368 kb
Host smart-bc8faeaf-2633-4783-bf77-ad63c8ebaf3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112295698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1112295698
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3512206133
Short name T308
Test name
Test status
Simulation time 7902821348 ps
CPU time 15.75 seconds
Started Apr 23 02:13:30 PM PDT 24
Finished Apr 23 02:13:46 PM PDT 24
Peak memory 211580 kb
Host smart-b85e31c0-c691-425c-ae98-b190497ec8b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512206133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3512206133
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.204206878
Short name T330
Test name
Test status
Simulation time 87161981110 ps
CPU time 191.11 seconds
Started Apr 23 02:13:29 PM PDT 24
Finished Apr 23 02:16:40 PM PDT 24
Peak memory 212804 kb
Host smart-95bc38c8-9353-49a7-aed1-b647d3fba911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204206878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.204206878
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4234715279
Short name T322
Test name
Test status
Simulation time 8351517107 ps
CPU time 16.79 seconds
Started Apr 23 02:13:31 PM PDT 24
Finished Apr 23 02:13:48 PM PDT 24
Peak memory 211344 kb
Host smart-b41145b1-9ffb-4ad0-a30b-de1ddeaaa317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234715279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4234715279
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3328994200
Short name T371
Test name
Test status
Simulation time 7904405908 ps
CPU time 21.82 seconds
Started Apr 23 02:13:30 PM PDT 24
Finished Apr 23 02:13:53 PM PDT 24
Peak memory 219580 kb
Host smart-724e842b-76af-42d6-96ce-7ed1ac93beb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328994200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3328994200
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.34349003
Short name T134
Test name
Test status
Simulation time 1628989783 ps
CPU time 19.93 seconds
Started Apr 23 02:13:29 PM PDT 24
Finished Apr 23 02:13:49 PM PDT 24
Peak memory 213592 kb
Host smart-972740a8-4c5d-4efb-a21a-6d250627c2d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.34349003
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1348457580
Short name T290
Test name
Test status
Simulation time 25599882625 ps
CPU time 1025.8 seconds
Started Apr 23 02:13:28 PM PDT 24
Finished Apr 23 02:30:35 PM PDT 24
Peak memory 236076 kb
Host smart-36e1c396-dd62-475b-8a1c-ddb43919ba5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348457580 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1348457580
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1438459986
Short name T332
Test name
Test status
Simulation time 9953593999 ps
CPU time 13.17 seconds
Started Apr 23 02:12:31 PM PDT 24
Finished Apr 23 02:12:44 PM PDT 24
Peak memory 211528 kb
Host smart-ac6f7fbd-e769-461d-8641-5156fc6847a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438459986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1438459986
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3812090931
Short name T19
Test name
Test status
Simulation time 19477520405 ps
CPU time 225.7 seconds
Started Apr 23 02:12:28 PM PDT 24
Finished Apr 23 02:16:14 PM PDT 24
Peak memory 238032 kb
Host smart-4025ce46-52c2-4030-baf2-b8da9f1314d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812090931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3812090931
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.990127538
Short name T165
Test name
Test status
Simulation time 2804258060 ps
CPU time 27 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:13:01 PM PDT 24
Peak memory 212080 kb
Host smart-292bd1d2-3c24-4c63-9c3e-673d66d8c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990127538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.990127538
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1183663611
Short name T334
Test name
Test status
Simulation time 4968561892 ps
CPU time 12.46 seconds
Started Apr 23 02:12:29 PM PDT 24
Finished Apr 23 02:12:43 PM PDT 24
Peak memory 211380 kb
Host smart-21191b2e-16a5-417f-9dbd-3116bb40a8a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183663611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1183663611
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1715232840
Short name T32
Test name
Test status
Simulation time 215666447 ps
CPU time 52.91 seconds
Started Apr 23 02:12:34 PM PDT 24
Finished Apr 23 02:13:28 PM PDT 24
Peak memory 230772 kb
Host smart-3bd65eb9-0258-418a-97a5-bad1c40a3b74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715232840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1715232840
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.219009848
Short name T80
Test name
Test status
Simulation time 10769603576 ps
CPU time 28.08 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:13:02 PM PDT 24
Peak memory 219652 kb
Host smart-22c5ac0d-740c-4fad-b1fb-0a2a27c386b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219009848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.219009848
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3620627726
Short name T212
Test name
Test status
Simulation time 11769932365 ps
CPU time 49.84 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:13:24 PM PDT 24
Peak memory 217524 kb
Host smart-8b5c27ac-dadf-49b3-acee-d5a326a74b5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620627726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3620627726
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.19166824
Short name T270
Test name
Test status
Simulation time 304887097 ps
CPU time 6.39 seconds
Started Apr 23 02:13:31 PM PDT 24
Finished Apr 23 02:13:38 PM PDT 24
Peak memory 211524 kb
Host smart-76432db4-ce90-4c24-a85f-e5daf2eb0fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19166824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.19166824
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.266512038
Short name T166
Test name
Test status
Simulation time 26081836005 ps
CPU time 258.52 seconds
Started Apr 23 02:13:30 PM PDT 24
Finished Apr 23 02:17:49 PM PDT 24
Peak memory 225292 kb
Host smart-3a0393bc-c705-4472-91c3-621c4c4f2f1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266512038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.266512038
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.72775942
Short name T147
Test name
Test status
Simulation time 3144239748 ps
CPU time 19.88 seconds
Started Apr 23 02:13:32 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 211556 kb
Host smart-c227664d-4427-4824-af35-b5b8ba213cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72775942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.72775942
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3291183003
Short name T63
Test name
Test status
Simulation time 6193152377 ps
CPU time 15.24 seconds
Started Apr 23 02:13:36 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 211356 kb
Host smart-5b0d64f6-252f-463f-be8c-58146a913446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291183003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3291183003
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2921679098
Short name T318
Test name
Test status
Simulation time 184441883 ps
CPU time 10.01 seconds
Started Apr 23 02:13:28 PM PDT 24
Finished Apr 23 02:13:39 PM PDT 24
Peak memory 219580 kb
Host smart-699b5515-71dd-4010-897d-5e10ff9c405e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921679098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2921679098
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.546624953
Short name T137
Test name
Test status
Simulation time 12206424431 ps
CPU time 57.35 seconds
Started Apr 23 02:13:36 PM PDT 24
Finished Apr 23 02:14:34 PM PDT 24
Peak memory 214576 kb
Host smart-c739ea7b-b84e-4c08-b900-59add56f085c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546624953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.546624953
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.831762128
Short name T15
Test name
Test status
Simulation time 45868862151 ps
CPU time 1639.33 seconds
Started Apr 23 02:13:31 PM PDT 24
Finished Apr 23 02:40:51 PM PDT 24
Peak memory 236052 kb
Host smart-63acb516-d3be-4e0d-884c-f74010c0b6cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831762128 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.831762128
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.556302862
Short name T222
Test name
Test status
Simulation time 1147289047 ps
CPU time 10.63 seconds
Started Apr 23 02:13:38 PM PDT 24
Finished Apr 23 02:13:49 PM PDT 24
Peak memory 211472 kb
Host smart-f5e3c506-5cb1-4f17-a764-4981f47aa024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556302862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.556302862
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3161760925
Short name T155
Test name
Test status
Simulation time 1589482233 ps
CPU time 75.14 seconds
Started Apr 23 02:13:35 PM PDT 24
Finished Apr 23 02:14:51 PM PDT 24
Peak memory 233464 kb
Host smart-5b6930a3-8f50-4b83-97de-e2a42de474a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161760925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3161760925
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2855898526
Short name T294
Test name
Test status
Simulation time 2243153525 ps
CPU time 22.99 seconds
Started Apr 23 02:13:28 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 211536 kb
Host smart-39816979-0750-4a92-9a83-e98a56ea056d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855898526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2855898526
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.999870566
Short name T253
Test name
Test status
Simulation time 1827106061 ps
CPU time 11.1 seconds
Started Apr 23 02:13:32 PM PDT 24
Finished Apr 23 02:13:44 PM PDT 24
Peak memory 211320 kb
Host smart-bca5b87b-3ee5-4c45-889b-20bb18335b94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999870566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.999870566
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2986941081
Short name T75
Test name
Test status
Simulation time 6333781974 ps
CPU time 32.13 seconds
Started Apr 23 02:13:30 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 219620 kb
Host smart-c2ae1cca-554b-4088-9808-7ad3ae0bdf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986941081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2986941081
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4169698474
Short name T372
Test name
Test status
Simulation time 2526863337 ps
CPU time 20.75 seconds
Started Apr 23 02:13:31 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 212216 kb
Host smart-cb7b17c8-b632-405d-99ab-3b4288f12bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169698474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4169698474
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.1331065082
Short name T105
Test name
Test status
Simulation time 189070481593 ps
CPU time 934.83 seconds
Started Apr 23 02:13:31 PM PDT 24
Finished Apr 23 02:29:06 PM PDT 24
Peak memory 236052 kb
Host smart-1d1aafc5-a491-4d16-90e7-989df7296476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331065082 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.1331065082
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2697280636
Short name T196
Test name
Test status
Simulation time 333563552 ps
CPU time 4.21 seconds
Started Apr 23 02:13:35 PM PDT 24
Finished Apr 23 02:13:39 PM PDT 24
Peak memory 211552 kb
Host smart-dbcc35c1-1235-4810-8194-79e77c8763da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697280636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2697280636
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3268240823
Short name T133
Test name
Test status
Simulation time 17267463048 ps
CPU time 104.81 seconds
Started Apr 23 02:13:31 PM PDT 24
Finished Apr 23 02:15:16 PM PDT 24
Peak memory 214868 kb
Host smart-bd3fbc8a-5bf8-4f52-8bf8-a67b1324c10d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268240823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3268240823
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.216632992
Short name T335
Test name
Test status
Simulation time 1207260603 ps
CPU time 13.4 seconds
Started Apr 23 02:13:33 PM PDT 24
Finished Apr 23 02:13:47 PM PDT 24
Peak memory 212188 kb
Host smart-141ef4df-ac87-49e5-aed1-84c08515483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216632992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.216632992
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2203476536
Short name T103
Test name
Test status
Simulation time 7538340882 ps
CPU time 15.95 seconds
Started Apr 23 02:13:35 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 211356 kb
Host smart-d1d81c3e-65d9-4f96-81cb-98563f7cb4df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203476536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2203476536
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2956063705
Short name T316
Test name
Test status
Simulation time 17507281954 ps
CPU time 35.62 seconds
Started Apr 23 02:13:31 PM PDT 24
Finished Apr 23 02:14:07 PM PDT 24
Peak memory 219648 kb
Host smart-bcbab989-79ab-4773-b0c3-10baf31d945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956063705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2956063705
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1468582680
Short name T261
Test name
Test status
Simulation time 34764252676 ps
CPU time 98.24 seconds
Started Apr 23 02:13:33 PM PDT 24
Finished Apr 23 02:15:12 PM PDT 24
Peak memory 219636 kb
Host smart-40d830ae-b637-4e47-95a1-112ee935392d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468582680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1468582680
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.561633266
Short name T369
Test name
Test status
Simulation time 5579395456 ps
CPU time 15.27 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 02:13:58 PM PDT 24
Peak memory 211528 kb
Host smart-4404ee1b-a7a4-4d6e-8de0-1664760a7c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561633266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.561633266
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3204579064
Short name T5
Test name
Test status
Simulation time 9012563148 ps
CPU time 98.04 seconds
Started Apr 23 02:13:35 PM PDT 24
Finished Apr 23 02:15:14 PM PDT 24
Peak memory 212620 kb
Host smart-0f4ac1bb-db6c-4093-b2e1-f64782ea4073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204579064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3204579064
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.476585441
Short name T18
Test name
Test status
Simulation time 490590559 ps
CPU time 9.39 seconds
Started Apr 23 02:13:34 PM PDT 24
Finished Apr 23 02:13:44 PM PDT 24
Peak memory 212120 kb
Host smart-0b811e77-096a-4168-a9f2-98db93440c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476585441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.476585441
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1302080941
Short name T267
Test name
Test status
Simulation time 4287382949 ps
CPU time 12.72 seconds
Started Apr 23 02:13:34 PM PDT 24
Finished Apr 23 02:13:47 PM PDT 24
Peak memory 211304 kb
Host smart-6013590c-8fab-482b-910a-0596b575e4fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302080941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1302080941
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1218758011
Short name T326
Test name
Test status
Simulation time 19688684832 ps
CPU time 37.69 seconds
Started Apr 23 02:13:33 PM PDT 24
Finished Apr 23 02:14:11 PM PDT 24
Peak memory 219584 kb
Host smart-0a7d81ae-654a-4a2b-853c-f9ba32dd7853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218758011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1218758011
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1484093659
Short name T232
Test name
Test status
Simulation time 5042886667 ps
CPU time 35.13 seconds
Started Apr 23 02:13:34 PM PDT 24
Finished Apr 23 02:14:10 PM PDT 24
Peak memory 213584 kb
Host smart-6410ba4b-0545-4547-bd82-d5dc12ba4da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484093659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1484093659
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1796214206
Short name T50
Test name
Test status
Simulation time 40792799304 ps
CPU time 3297.17 seconds
Started Apr 23 02:13:34 PM PDT 24
Finished Apr 23 03:08:32 PM PDT 24
Peak memory 236080 kb
Host smart-8bb55d19-fd10-44a9-8d14-a12e04cbe110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796214206 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1796214206
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.428695296
Short name T262
Test name
Test status
Simulation time 8111647727 ps
CPU time 15.19 seconds
Started Apr 23 02:13:37 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 211532 kb
Host smart-80956481-1302-414d-9122-4a5df8d253ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428695296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.428695296
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2591824042
Short name T202
Test name
Test status
Simulation time 2375354412 ps
CPU time 24.26 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 02:14:07 PM PDT 24
Peak memory 212044 kb
Host smart-b63584b2-9a6e-4491-a6d9-20878892a96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591824042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2591824042
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1304969232
Short name T185
Test name
Test status
Simulation time 1380173266 ps
CPU time 13.49 seconds
Started Apr 23 02:13:37 PM PDT 24
Finished Apr 23 02:13:51 PM PDT 24
Peak memory 211324 kb
Host smart-38aa480f-5e81-4d16-beb6-ec3dad12ad56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304969232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1304969232
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1458153809
Short name T138
Test name
Test status
Simulation time 11151526300 ps
CPU time 24.48 seconds
Started Apr 23 02:13:37 PM PDT 24
Finished Apr 23 02:14:01 PM PDT 24
Peak memory 213420 kb
Host smart-ed974705-4c50-4713-8e60-f80da16600b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458153809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1458153809
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3590601117
Short name T106
Test name
Test status
Simulation time 29445158968 ps
CPU time 76.31 seconds
Started Apr 23 02:13:37 PM PDT 24
Finished Apr 23 02:14:54 PM PDT 24
Peak memory 218048 kb
Host smart-f05223b3-ad36-42ec-b29a-1ec6a8f8f64a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590601117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3590601117
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3102160203
Short name T324
Test name
Test status
Simulation time 85721097 ps
CPU time 4.32 seconds
Started Apr 23 02:13:38 PM PDT 24
Finished Apr 23 02:13:43 PM PDT 24
Peak memory 211476 kb
Host smart-69218c88-916b-46d7-9868-0cb018acf687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102160203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3102160203
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3887351666
Short name T219
Test name
Test status
Simulation time 238178489419 ps
CPU time 254.94 seconds
Started Apr 23 02:13:43 PM PDT 24
Finished Apr 23 02:17:58 PM PDT 24
Peak memory 224936 kb
Host smart-7c4ada82-8d49-4849-9de1-1bcc34970a4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887351666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3887351666
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2170913513
Short name T143
Test name
Test status
Simulation time 3948565338 ps
CPU time 16.46 seconds
Started Apr 23 02:13:37 PM PDT 24
Finished Apr 23 02:13:53 PM PDT 24
Peak memory 211964 kb
Host smart-4821c738-1399-4cfd-a592-e193dfa2ed7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170913513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2170913513
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3256765331
Short name T150
Test name
Test status
Simulation time 1183576168 ps
CPU time 7.51 seconds
Started Apr 23 02:13:37 PM PDT 24
Finished Apr 23 02:13:45 PM PDT 24
Peak memory 211340 kb
Host smart-28ba91f4-1ad4-4ff5-a9f6-76da3c8cf6c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256765331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3256765331
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.682800569
Short name T64
Test name
Test status
Simulation time 2832161322 ps
CPU time 25.35 seconds
Started Apr 23 02:13:43 PM PDT 24
Finished Apr 23 02:14:09 PM PDT 24
Peak memory 212384 kb
Host smart-79a40ad4-01b6-4791-9a79-b02e3f5311d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682800569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.682800569
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2578502452
Short name T218
Test name
Test status
Simulation time 1887977787 ps
CPU time 26.05 seconds
Started Apr 23 02:13:35 PM PDT 24
Finished Apr 23 02:14:02 PM PDT 24
Peak memory 219592 kb
Host smart-36c1ff42-78ce-48c0-a3e8-1d4d4bf1a3b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578502452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2578502452
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1959672858
Short name T266
Test name
Test status
Simulation time 334316571 ps
CPU time 4.2 seconds
Started Apr 23 02:13:40 PM PDT 24
Finished Apr 23 02:13:45 PM PDT 24
Peak memory 211472 kb
Host smart-0d3d07ac-8f01-4fb2-8b70-74ccb5b38b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959672858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1959672858
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3816725172
Short name T139
Test name
Test status
Simulation time 5086260192 ps
CPU time 179.01 seconds
Started Apr 23 02:13:41 PM PDT 24
Finished Apr 23 02:16:41 PM PDT 24
Peak memory 232972 kb
Host smart-96ecaa13-5caf-4477-b7f9-93b81c8061a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816725172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3816725172
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2893222179
Short name T360
Test name
Test status
Simulation time 4243574587 ps
CPU time 16.22 seconds
Started Apr 23 02:13:38 PM PDT 24
Finished Apr 23 02:13:55 PM PDT 24
Peak memory 212196 kb
Host smart-f5d8c054-e656-46d3-8c88-451a59d123b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893222179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2893222179
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2644474691
Short name T277
Test name
Test status
Simulation time 4763271684 ps
CPU time 16.86 seconds
Started Apr 23 02:13:47 PM PDT 24
Finished Apr 23 02:14:04 PM PDT 24
Peak memory 211376 kb
Host smart-ebb292d5-f618-4acc-9862-f53912108f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644474691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2644474691
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1182848000
Short name T307
Test name
Test status
Simulation time 4060953112 ps
CPU time 33.31 seconds
Started Apr 23 02:13:40 PM PDT 24
Finished Apr 23 02:14:14 PM PDT 24
Peak memory 213608 kb
Host smart-d002a036-12ab-4881-9f0f-d3070a7b71cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182848000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1182848000
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1505497863
Short name T305
Test name
Test status
Simulation time 211580741 ps
CPU time 15.2 seconds
Started Apr 23 02:13:39 PM PDT 24
Finished Apr 23 02:13:54 PM PDT 24
Peak memory 213344 kb
Host smart-bac26dc0-9bf3-4639-9a43-55cc5fc6d3d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505497863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1505497863
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.582803065
Short name T53
Test name
Test status
Simulation time 15444148809 ps
CPU time 560.21 seconds
Started Apr 23 02:13:38 PM PDT 24
Finished Apr 23 02:22:59 PM PDT 24
Peak memory 223372 kb
Host smart-f35aadb8-f1db-4b30-b290-e188ff2bc91f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582803065 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.582803065
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2181290713
Short name T325
Test name
Test status
Simulation time 87458846 ps
CPU time 4.26 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 02:13:47 PM PDT 24
Peak memory 211448 kb
Host smart-5f20ad8d-4c79-4a86-bf7f-507ca374ee28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181290713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2181290713
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.24460686
Short name T284
Test name
Test status
Simulation time 79847469386 ps
CPU time 194.95 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 02:16:57 PM PDT 24
Peak memory 230992 kb
Host smart-52b27f15-7064-4e5a-a639-94f63ed405b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24460686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_co
rrupt_sig_fatal_chk.24460686
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3395848698
Short name T145
Test name
Test status
Simulation time 32877210972 ps
CPU time 27.56 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 02:14:10 PM PDT 24
Peak memory 211544 kb
Host smart-b2b50d48-39ce-4153-8b7f-a625ea790d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395848698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3395848698
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1812166974
Short name T191
Test name
Test status
Simulation time 878005402 ps
CPU time 10.42 seconds
Started Apr 23 02:13:43 PM PDT 24
Finished Apr 23 02:13:54 PM PDT 24
Peak memory 211308 kb
Host smart-badcb255-c2ff-4ee7-80ca-ff3069972d24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812166974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1812166974
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1740951353
Short name T135
Test name
Test status
Simulation time 1932463512 ps
CPU time 13.71 seconds
Started Apr 23 02:13:47 PM PDT 24
Finished Apr 23 02:14:01 PM PDT 24
Peak memory 213304 kb
Host smart-2a8256d1-a922-4238-9ee7-af4702e4872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740951353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1740951353
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2818781129
Short name T115
Test name
Test status
Simulation time 31780484673 ps
CPU time 37.68 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 02:14:21 PM PDT 24
Peak memory 216904 kb
Host smart-43dc5572-e6e9-47f5-8727-24a4adf1dd69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818781129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2818781129
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4112597861
Short name T339
Test name
Test status
Simulation time 1449704193 ps
CPU time 11.7 seconds
Started Apr 23 02:13:44 PM PDT 24
Finished Apr 23 02:13:57 PM PDT 24
Peak memory 211508 kb
Host smart-d7507478-623a-44b2-ac83-9d6b2dd636d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112597861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4112597861
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3069548026
Short name T365
Test name
Test status
Simulation time 58481650141 ps
CPU time 174.47 seconds
Started Apr 23 02:13:47 PM PDT 24
Finished Apr 23 02:16:42 PM PDT 24
Peak memory 238016 kb
Host smart-07b60791-5a88-48a0-ba12-16a8dd73f11b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069548026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3069548026
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1448544386
Short name T154
Test name
Test status
Simulation time 3615438257 ps
CPU time 29.85 seconds
Started Apr 23 02:13:41 PM PDT 24
Finished Apr 23 02:14:12 PM PDT 24
Peak memory 211896 kb
Host smart-029b9b8e-3b2a-40eb-bcb4-044450487b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448544386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1448544386
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.996215061
Short name T193
Test name
Test status
Simulation time 2223793540 ps
CPU time 16.75 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 02:13:59 PM PDT 24
Peak memory 211360 kb
Host smart-8691d3cb-73c6-4c48-b5a4-4a6d0e62deeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996215061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.996215061
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4250650597
Short name T136
Test name
Test status
Simulation time 941712980 ps
CPU time 16.23 seconds
Started Apr 23 02:13:41 PM PDT 24
Finished Apr 23 02:13:57 PM PDT 24
Peak memory 213692 kb
Host smart-29442335-761c-4ca7-b4bc-c582da160e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250650597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4250650597
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.697658967
Short name T245
Test name
Test status
Simulation time 22355059767 ps
CPU time 119.93 seconds
Started Apr 23 02:13:49 PM PDT 24
Finished Apr 23 02:15:50 PM PDT 24
Peak memory 219688 kb
Host smart-f9c5de3f-7168-4160-9458-eb0f90308b8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697658967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.697658967
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.446273683
Short name T51
Test name
Test status
Simulation time 107701764941 ps
CPU time 3214.67 seconds
Started Apr 23 02:13:42 PM PDT 24
Finished Apr 23 03:07:17 PM PDT 24
Peak memory 236136 kb
Host smart-6c42ab88-ffc3-49b0-b9e5-f191dd0847df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446273683 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.446273683
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3386853654
Short name T211
Test name
Test status
Simulation time 5111822344 ps
CPU time 11.87 seconds
Started Apr 23 02:13:46 PM PDT 24
Finished Apr 23 02:13:58 PM PDT 24
Peak memory 211588 kb
Host smart-f018e88c-668a-45b8-9c3d-28a7a7192918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386853654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3386853654
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2088245418
Short name T336
Test name
Test status
Simulation time 8142109604 ps
CPU time 32.37 seconds
Started Apr 23 02:13:44 PM PDT 24
Finished Apr 23 02:14:17 PM PDT 24
Peak memory 212384 kb
Host smart-bb7cde22-2bb7-46be-a0cc-70768d1d4122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088245418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2088245418
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.944975349
Short name T37
Test name
Test status
Simulation time 5879917380 ps
CPU time 11.1 seconds
Started Apr 23 02:13:49 PM PDT 24
Finished Apr 23 02:14:01 PM PDT 24
Peak memory 211388 kb
Host smart-c9f58b9b-a880-4d7a-a721-9f5a21b3c27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944975349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.944975349
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3683889167
Short name T291
Test name
Test status
Simulation time 4339157282 ps
CPU time 17.94 seconds
Started Apr 23 02:13:45 PM PDT 24
Finished Apr 23 02:14:04 PM PDT 24
Peak memory 213944 kb
Host smart-26d9b1b5-7ca2-47cc-874b-d3e7d295f0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683889167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3683889167
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.26451407
Short name T319
Test name
Test status
Simulation time 26059868519 ps
CPU time 34.4 seconds
Started Apr 23 02:13:45 PM PDT 24
Finished Apr 23 02:14:20 PM PDT 24
Peak memory 217028 kb
Host smart-fbfb74c5-e0f7-4f6b-b16e-af13892e874d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26451407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.rom_ctrl_stress_all.26451407
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.574807161
Short name T48
Test name
Test status
Simulation time 239415159924 ps
CPU time 1985.47 seconds
Started Apr 23 02:13:50 PM PDT 24
Finished Apr 23 02:46:56 PM PDT 24
Peak memory 245928 kb
Host smart-a7b1ba7e-ae62-404b-8958-f6c3bc2ba63b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574807161 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.574807161
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1072658439
Short name T60
Test name
Test status
Simulation time 168318747 ps
CPU time 4.15 seconds
Started Apr 23 02:12:29 PM PDT 24
Finished Apr 23 02:12:34 PM PDT 24
Peak memory 211524 kb
Host smart-0a97edeb-dfc9-4f72-b695-df0bf961a071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072658439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1072658439
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3127805906
Short name T259
Test name
Test status
Simulation time 55223879172 ps
CPU time 334.49 seconds
Started Apr 23 02:12:31 PM PDT 24
Finished Apr 23 02:18:06 PM PDT 24
Peak memory 213068 kb
Host smart-571728ba-9e42-4081-a8a6-420d28a8870c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127805906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3127805906
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.344273411
Short name T35
Test name
Test status
Simulation time 4152481213 ps
CPU time 30.68 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:13:04 PM PDT 24
Peak memory 212112 kb
Host smart-4917404a-7744-4591-831b-f31b128bfa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344273411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.344273411
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3741788501
Short name T146
Test name
Test status
Simulation time 4826385456 ps
CPU time 12.38 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:12:43 PM PDT 24
Peak memory 211472 kb
Host smart-4f5969c9-ec38-4b55-87f1-2e460dc9af5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741788501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3741788501
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1675812129
Short name T9
Test name
Test status
Simulation time 2799850252 ps
CPU time 25.2 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:12:56 PM PDT 24
Peak memory 213420 kb
Host smart-64563099-5cfc-4979-8c68-b95616e56cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675812129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1675812129
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1542380250
Short name T44
Test name
Test status
Simulation time 3170599196 ps
CPU time 18.73 seconds
Started Apr 23 02:12:30 PM PDT 24
Finished Apr 23 02:12:50 PM PDT 24
Peak memory 211372 kb
Host smart-ff236b98-c64c-455a-9435-862dc39d61cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542380250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1542380250
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1596215873
Short name T350
Test name
Test status
Simulation time 89941143 ps
CPU time 4.24 seconds
Started Apr 23 02:12:32 PM PDT 24
Finished Apr 23 02:12:36 PM PDT 24
Peak memory 211392 kb
Host smart-b3e7bb0d-a7e8-4b5f-b0a2-80aff7d9708d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596215873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1596215873
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4071766836
Short name T162
Test name
Test status
Simulation time 14409955873 ps
CPU time 154.75 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:15:09 PM PDT 24
Peak memory 214000 kb
Host smart-7e6f2fc3-56cd-487c-8c04-dee6f042a3da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071766836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4071766836
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.328933309
Short name T300
Test name
Test status
Simulation time 3843092408 ps
CPU time 30.68 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:13:04 PM PDT 24
Peak memory 211936 kb
Host smart-f5f5e5a3-610d-47d4-a482-d9420aba04bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328933309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.328933309
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2636820921
Short name T168
Test name
Test status
Simulation time 96843091 ps
CPU time 5.34 seconds
Started Apr 23 02:12:32 PM PDT 24
Finished Apr 23 02:12:37 PM PDT 24
Peak memory 211384 kb
Host smart-4db02ad2-83dc-48f8-92e9-8a4e12c7692e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636820921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2636820921
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1543769924
Short name T248
Test name
Test status
Simulation time 2403119715 ps
CPU time 24.77 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:12:59 PM PDT 24
Peak memory 213616 kb
Host smart-2c30f93f-d4d1-4b7a-8668-001d61e1cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543769924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1543769924
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1556793529
Short name T246
Test name
Test status
Simulation time 4654385147 ps
CPU time 16.72 seconds
Started Apr 23 02:12:28 PM PDT 24
Finished Apr 23 02:12:46 PM PDT 24
Peak memory 215608 kb
Host smart-7c7ac6e6-c1d6-4e04-8543-eccdfd7200a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556793529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1556793529
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2417510002
Short name T62
Test name
Test status
Simulation time 11264162536 ps
CPU time 15.05 seconds
Started Apr 23 02:12:38 PM PDT 24
Finished Apr 23 02:12:54 PM PDT 24
Peak memory 211420 kb
Host smart-916d9844-bb31-48cf-af6a-15c9c44c24d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417510002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2417510002
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3536058887
Short name T272
Test name
Test status
Simulation time 1537683731 ps
CPU time 81.29 seconds
Started Apr 23 02:12:38 PM PDT 24
Finished Apr 23 02:14:00 PM PDT 24
Peak memory 212636 kb
Host smart-ce7a84e3-8259-4f4b-866f-fb788503f15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536058887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3536058887
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1609478924
Short name T343
Test name
Test status
Simulation time 4092342662 ps
CPU time 32.49 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:13:11 PM PDT 24
Peak memory 212252 kb
Host smart-4f708086-d0b6-474f-a0ea-6786cc056fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609478924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1609478924
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1717176620
Short name T186
Test name
Test status
Simulation time 120883683 ps
CPU time 5.67 seconds
Started Apr 23 02:12:32 PM PDT 24
Finished Apr 23 02:12:38 PM PDT 24
Peak memory 211368 kb
Host smart-cd5629f3-9670-4bf1-98f6-520cf8919298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1717176620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1717176620
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.643086829
Short name T148
Test name
Test status
Simulation time 13919500113 ps
CPU time 35.46 seconds
Started Apr 23 02:12:38 PM PDT 24
Finished Apr 23 02:13:15 PM PDT 24
Peak memory 213884 kb
Host smart-5bc16869-fdbf-4bc9-9a96-5e44ac8a297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643086829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.643086829
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1226315343
Short name T177
Test name
Test status
Simulation time 467654663 ps
CPU time 8.74 seconds
Started Apr 23 02:12:38 PM PDT 24
Finished Apr 23 02:12:47 PM PDT 24
Peak memory 211780 kb
Host smart-0da96440-29e1-4536-8184-793251c1248f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226315343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1226315343
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.778527196
Short name T314
Test name
Test status
Simulation time 2060673379 ps
CPU time 10.29 seconds
Started Apr 23 02:12:34 PM PDT 24
Finished Apr 23 02:12:46 PM PDT 24
Peak memory 211520 kb
Host smart-229559a4-70cd-4f77-a559-fe5b277f7228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778527196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.778527196
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.509212391
Short name T329
Test name
Test status
Simulation time 37922426350 ps
CPU time 158.56 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:15:12 PM PDT 24
Peak memory 233584 kb
Host smart-4c6db159-6d24-43b1-b108-8846d9b3693c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509212391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.509212391
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.48187106
Short name T249
Test name
Test status
Simulation time 10752695191 ps
CPU time 25.52 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:13:00 PM PDT 24
Peak memory 212192 kb
Host smart-e66b83e3-25f8-4e44-8961-7dd300b2411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48187106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.48187106
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1388764195
Short name T113
Test name
Test status
Simulation time 4205927874 ps
CPU time 9.59 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:12:44 PM PDT 24
Peak memory 211332 kb
Host smart-c7c165c5-3841-4696-b251-26d7f5776637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388764195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1388764195
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2565963191
Short name T192
Test name
Test status
Simulation time 15027105905 ps
CPU time 39.68 seconds
Started Apr 23 02:12:32 PM PDT 24
Finished Apr 23 02:13:12 PM PDT 24
Peak memory 213964 kb
Host smart-11d8f45a-9c5b-483f-815e-b47533af9add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565963191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2565963191
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4072335122
Short name T230
Test name
Test status
Simulation time 9592816787 ps
CPU time 95.97 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:14:14 PM PDT 24
Peak memory 219544 kb
Host smart-3ec2b966-8e23-49a3-a656-a2b24836b998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072335122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4072335122
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1654772096
Short name T231
Test name
Test status
Simulation time 4338036988 ps
CPU time 13.26 seconds
Started Apr 23 02:12:39 PM PDT 24
Finished Apr 23 02:12:53 PM PDT 24
Peak memory 211580 kb
Host smart-b00756d2-9e4d-430a-8f1b-cace90997d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654772096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1654772096
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3096860849
Short name T197
Test name
Test status
Simulation time 285207530500 ps
CPU time 357.75 seconds
Started Apr 23 02:12:37 PM PDT 24
Finished Apr 23 02:18:36 PM PDT 24
Peak memory 241720 kb
Host smart-1955f1b3-a939-46ac-8282-8d4780fd09d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096860849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3096860849
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.799246967
Short name T114
Test name
Test status
Simulation time 1358471225 ps
CPU time 7.66 seconds
Started Apr 23 02:12:35 PM PDT 24
Finished Apr 23 02:12:43 PM PDT 24
Peak memory 211364 kb
Host smart-341a966a-5e8b-48e3-add0-55113e5e7562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799246967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.799246967
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1135456758
Short name T285
Test name
Test status
Simulation time 8340982454 ps
CPU time 16.06 seconds
Started Apr 23 02:12:34 PM PDT 24
Finished Apr 23 02:12:51 PM PDT 24
Peak memory 214516 kb
Host smart-1be04b97-12fa-42f0-8e55-7d3400da2f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135456758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1135456758
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.488802354
Short name T233
Test name
Test status
Simulation time 964265319 ps
CPU time 15.54 seconds
Started Apr 23 02:12:33 PM PDT 24
Finished Apr 23 02:12:50 PM PDT 24
Peak memory 212600 kb
Host smart-05fa7e4a-bdb4-4ec4-8c8e-45683099d855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488802354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.488802354
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3136707293
Short name T49
Test name
Test status
Simulation time 484619477645 ps
CPU time 5055.2 seconds
Started Apr 23 02:12:35 PM PDT 24
Finished Apr 23 03:36:52 PM PDT 24
Peak memory 261632 kb
Host smart-80856648-8ec8-4d41-bf20-5ffe3abd07fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136707293 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3136707293
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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