Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49849	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1038415

1

T1

15

T2

31

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	291104	1			T1	140		T2	389		T3	386
values[0x0]	391332	1			T6	56764		T28	45740		T29	72752
values[0x1]	405828	1			T6	59013		T28	47271		T29	74932

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1063072

1

T1

88

T2

215

T3

222

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4505	1			T6	630		T13	1		T11	4
valid_sources[0x01]	4229	1			T6	605		T11	7		T19	2
valid_sources[0x02]	4652	1			T6	601		T53	4		T28	507
valid_sources[0x03]	3842	1			T6	514		T13	1		T28	458
valid_sources[0x04]	4711	1			T6	609		T13	3		T28	465
valid_sources[0x05]	4129	1			T1	22		T6	616		T13	1
valid_sources[0x06]	4324	1			T3	16		T6	601		T13	1
valid_sources[0x07]	4472	1			T6	622		T13	6		T28	526
valid_sources[0x08]	3935	1			T6	535		T11	2		T28	523
valid_sources[0x09]	4198	1			T6	574		T13	2		T11	3
valid_sources[0x0a]	4084	1			T6	587		T13	1		T53	7
valid_sources[0x0b]	3968	1			T6	573		T13	1		T28	477
valid_sources[0x0c]	4146	1			T6	577		T13	1		T11	10
valid_sources[0x0d]	4113	1			T6	611		T13	4		T11	1
valid_sources[0x0e]	4044	1			T6	654		T19	10		T28	463
valid_sources[0x0f]	4164	1			T3	44		T6	658		T13	3
valid_sources[0x10]	4087	1			T6	577		T13	2		T11	13
valid_sources[0x11]	4337	1			T6	633		T13	3		T11	1
valid_sources[0x12]	4044	1			T6	605		T28	505		T105	3
valid_sources[0x13]	4211	1			T6	623		T11	10		T53	1
valid_sources[0x14]	4103	1			T6	607		T13	1		T28	458
valid_sources[0x15]	4480	1			T6	561		T12	6		T13	1
valid_sources[0x16]	4392	1			T3	4		T6	580		T13	5
valid_sources[0x17]	3985	1			T6	591		T13	1		T28	489
valid_sources[0x18]	4195	1			T6	644		T53	5		T28	488
valid_sources[0x19]	4187	1			T6	628		T13	3		T28	514
valid_sources[0x1a]	3962	1			T6	632		T13	3		T28	467
valid_sources[0x1b]	4440	1			T6	609		T13	3		T28	485
valid_sources[0x1c]	4500	1			T3	2		T6	615		T13	1
valid_sources[0x1d]	4565	1			T6	607		T13	3		T53	3
valid_sources[0x1e]	4525	1			T3	6		T6	646		T53	4
valid_sources[0x1f]	4070	1			T6	603		T13	2		T53	8
valid_sources[0x20]	4402	1			T6	588		T28	496		T105	1
valid_sources[0x21]	4400	1			T6	638		T13	2		T14	1
valid_sources[0x22]	4339	1			T6	570		T13	2		T19	25
valid_sources[0x23]	4855	1			T6	606		T13	1		T28	518
valid_sources[0x24]	4300	1			T6	625		T28	489		T106	4
valid_sources[0x25]	4763	1			T6	683		T13	4		T28	492
valid_sources[0x26]	4853	1			T6	599		T28	501		T105	2
valid_sources[0x27]	4738	1			T6	597		T28	488		T107	1
valid_sources[0x28]	3934	1			T6	588		T13	1		T28	447
valid_sources[0x29]	3988	1			T6	606		T13	2		T28	481
valid_sources[0x2a]	4236	1			T6	578		T28	492		T105	1
valid_sources[0x2b]	4446	1			T6	635		T28	507		T64	3
valid_sources[0x2c]	3959	1			T6	606		T28	496		T105	1
valid_sources[0x2d]	4312	1			T6	581		T13	1		T28	459
valid_sources[0x2e]	4037	1			T6	615		T13	3		T11	2
valid_sources[0x2f]	4108	1			T6	585		T12	7		T28	491
valid_sources[0x30]	4195	1			T6	605		T13	2		T28	478
valid_sources[0x31]	4147	1			T6	614		T13	6		T28	458
valid_sources[0x32]	4886	1			T6	590		T12	1		T13	3
valid_sources[0x33]	3949	1			T6	615		T13	3		T28	479
valid_sources[0x34]	4801	1			T6	585		T13	1		T11	6
valid_sources[0x35]	3909	1			T3	8		T6	604		T53	17
valid_sources[0x36]	4216	1			T6	629		T13	3		T19	8
valid_sources[0x37]	4699	1			T6	582		T10	5		T13	2
valid_sources[0x38]	4102	1			T6	619		T19	8		T53	1
valid_sources[0x39]	4494	1			T6	587		T28	468		T106	4
valid_sources[0x3a]	5433	1			T6	612		T14	1		T28	492
valid_sources[0x3b]	3888	1			T6	592		T28	475		T65	1
valid_sources[0x3c]	4070	1			T6	636		T13	1		T28	460
valid_sources[0x3d]	4860	1			T6	619		T13	2		T28	513
valid_sources[0x3e]	4031	1			T6	656		T13	1		T11	2
valid_sources[0x3f]	3969	1			T6	603		T13	1		T28	486
valid_sources[0x40]	4426	1			T6	620		T13	2		T28	514
valid_sources[0x41]	4318	1			T6	624		T12	3		T11	8
valid_sources[0x42]	3979	1			T6	604		T13	1		T28	469
valid_sources[0x43]	3941	1			T6	644		T10	10		T28	479
valid_sources[0x44]	4059	1			T6	628		T12	2		T19	13
valid_sources[0x45]	4119	1			T6	569		T11	1		T28	453
valid_sources[0x46]	4062	1			T2	43		T6	581		T91	3
valid_sources[0x47]	4081	1			T6	548		T13	2		T28	510
valid_sources[0x48]	3891	1			T6	591		T13	2		T28	437
valid_sources[0x49]	4295	1			T6	549		T10	1		T13	1
valid_sources[0x4a]	4082	1			T6	625		T28	497		T105	2
valid_sources[0x4b]	4247	1			T6	639		T28	458		T108	1
valid_sources[0x4c]	4071	1			T6	625		T13	2		T28	476
valid_sources[0x4d]	4142	1			T6	617		T13	3		T53	7
valid_sources[0x4e]	4128	1			T3	5		T6	612		T13	4
valid_sources[0x4f]	4850	1			T6	619		T28	476		T65	1
valid_sources[0x50]	4406	1			T6	606		T12	3		T11	4
valid_sources[0x51]	4971	1			T6	605		T13	2		T28	494
valid_sources[0x52]	4045	1			T6	555		T13	2		T28	511
valid_sources[0x53]	4615	1			T6	649		T13	2		T28	497
valid_sources[0x54]	4462	1			T3	24		T6	617		T13	3
valid_sources[0x55]	4731	1			T6	594		T11	8		T28	456
valid_sources[0x56]	4083	1			T6	576		T13	1		T53	1
valid_sources[0x57]	4291	1			T3	3		T6	622		T13	1
valid_sources[0x58]	4725	1			T3	2		T6	602		T13	2
valid_sources[0x59]	4891	1			T6	605		T28	478		T105	1
valid_sources[0x5a]	4030	1			T6	644		T13	2		T28	479
valid_sources[0x5b]	4551	1			T6	632		T13	2		T28	485
valid_sources[0x5c]	4207	1			T3	3		T6	599		T13	4
valid_sources[0x5d]	4803	1			T6	614		T12	8		T13	1
valid_sources[0x5e]	3937	1			T6	571		T13	1		T11	2
valid_sources[0x5f]	3973	1			T6	610		T13	2		T28	491
valid_sources[0x60]	4388	1			T6	596		T13	5		T28	480
valid_sources[0x61]	4034	1			T3	10		T6	598		T13	1
valid_sources[0x62]	3937	1			T3	2		T6	608		T13	2
valid_sources[0x63]	4664	1			T2	15		T3	6		T6	588
valid_sources[0x64]	4131	1			T6	637		T13	4		T53	4
valid_sources[0x65]	4547	1			T6	604		T28	492		T105	1
valid_sources[0x66]	4201	1			T6	602		T28	498		T62	3
valid_sources[0x67]	4328	1			T6	667		T13	1		T28	488
valid_sources[0x68]	4174	1			T6	575		T28	467		T105	3
valid_sources[0x69]	4421	1			T2	14		T6	622		T13	3
valid_sources[0x6a]	4271	1			T6	592		T10	1		T11	8
valid_sources[0x6b]	4016	1			T6	615		T13	3		T28	507
valid_sources[0x6c]	4136	1			T6	620		T10	4		T28	484
valid_sources[0x6d]	4059	1			T6	586		T12	4		T13	3
valid_sources[0x6e]	4215	1			T6	649		T13	1		T28	501
valid_sources[0x6f]	4297	1			T6	601		T13	1		T28	461
valid_sources[0x70]	4007	1			T3	2		T6	605		T11	10
valid_sources[0x71]	4259	1			T6	587		T28	477		T105	3
valid_sources[0x72]	4044	1			T6	596		T28	479		T63	10
valid_sources[0x73]	4709	1			T2	35		T6	600		T13	1
valid_sources[0x74]	3989	1			T6	646		T13	1		T28	474
valid_sources[0x75]	4297	1			T3	6		T6	619		T28	489
valid_sources[0x76]	4063	1			T6	636		T13	2		T28	489
valid_sources[0x77]	4053	1			T6	618		T53	4		T28	494
valid_sources[0x78]	4395	1			T6	614		T13	3		T28	485
valid_sources[0x79]	4087	1			T6	615		T11	12		T28	466
valid_sources[0x7a]	4331	1			T6	603		T28	474		T105	5
valid_sources[0x7b]	4167	1			T3	50		T6	586		T13	3
valid_sources[0x7c]	4131	1			T3	32		T6	601		T11	6
valid_sources[0x7d]	4118	1			T6	596		T13	1		T28	468
valid_sources[0x7e]	4077	1			T6	597		T28	484		T65	2
valid_sources[0x7f]	4500	1			T6	618		T28	502		T108	1
valid_sources[0x80]	4416	1			T6	605		T13	1		T28	471

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

262671

1

T1

15

T2

31

T3

36

values[0x0]

all_enables

biggest_size

387816

1

T6

56275

T28

45318

T29

72083

values[0x1]

all_enables

biggest_size

387928

1

T6

56431

T28

45058

T29

71703

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	82018	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

799101

1

T5

1

T6

115572

T8

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	222084	1			T4	20		T6	30883		T7	10
values[0x0]	304835	1			T5	5		T6	44273		T33	4
values[0x1]	354200	1			T5	1		T6	51718		T33	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37841	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

843278

1

T4

7

T5

1

T6

122002

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3316	1			T6	527		T91	1		T28	317
valid_sources[0x01]	2326	1			T6	24		T28	402		T17	1
valid_sources[0x02]	2885	1			T6	435		T10	1		T28	360
valid_sources[0x03]	3266	1			T6	337		T28	406		T109	16
valid_sources[0x04]	2578	1			T6	12		T28	422		T29	611
valid_sources[0x05]	3490	1			T4	1		T6	597		T91	1
valid_sources[0x06]	3173	1			T6	234		T12	1		T28	413
valid_sources[0x07]	3962	1			T6	1005		T28	385		T29	594
valid_sources[0x08]	3577	1			T6	479		T91	1		T28	470
valid_sources[0x09]	2979	1			T6	282		T91	1		T28	390
valid_sources[0x0a]	4373	1			T4	1		T6	628		T28	352
valid_sources[0x0b]	2672	1			T4	1		T6	51		T28	320
valid_sources[0x0c]	3455	1			T6	387		T28	350		T66	2
valid_sources[0x0d]	3402	1			T6	362		T28	390		T110	2
valid_sources[0x0e]	2829	1			T6	97		T28	367		T29	605
valid_sources[0x0f]	3258	1			T6	327		T15	32		T28	410
valid_sources[0x10]	3715	1			T6	184		T14	3		T91	1
valid_sources[0x11]	4937	1			T6	718		T28	376		T38	1
valid_sources[0x12]	2893	1			T6	247		T19	1		T91	1
valid_sources[0x13]	3077	1			T6	58		T28	406		T111	1
valid_sources[0x14]	3055	1			T6	304		T28	326		T23	1
valid_sources[0x15]	3395	1			T6	580		T8	17		T19	1
valid_sources[0x16]	3370	1			T6	70		T28	461		T27	1
valid_sources[0x17]	3154	1			T6	336		T28	321		T27	1
valid_sources[0x18]	3098	1			T6	543		T19	1		T28	369
valid_sources[0x19]	3267	1			T6	19		T28	391		T38	1
valid_sources[0x1a]	3567	1			T6	547		T10	1		T28	394
valid_sources[0x1b]	3724	1			T6	908		T28	394		T65	1
valid_sources[0x1c]	3264	1			T6	384		T10	1		T28	285
valid_sources[0x1d]	2899	1			T6	229		T28	401		T29	588
valid_sources[0x1e]	3145	1			T6	201		T28	329		T106	1
valid_sources[0x1f]	2677	1			T6	222		T28	396		T106	1
valid_sources[0x20]	2783	1			T6	10		T28	377		T25	9
valid_sources[0x21]	3272	1			T6	305		T33	1		T14	1
valid_sources[0x22]	3385	1			T6	455		T19	1		T28	297
valid_sources[0x23]	3479	1			T6	782		T91	2		T28	403
valid_sources[0x24]	2997	1			T4	1		T6	333		T28	414
valid_sources[0x25]	4020	1			T6	986		T28	259		T65	1
valid_sources[0x26]	3143	1			T4	1		T5	1		T6	176
valid_sources[0x27]	3478	1			T6	803		T28	351		T66	1
valid_sources[0x28]	4055	1			T6	686		T19	2		T28	327
valid_sources[0x29]	3677	1			T6	445		T91	1		T28	325
valid_sources[0x2a]	3787	1			T4	2		T6	433		T28	404
valid_sources[0x2b]	3176	1			T6	299		T10	2		T28	328
valid_sources[0x2c]	4023	1			T6	1101		T10	1		T28	383
valid_sources[0x2d]	3372	1			T6	644		T91	1		T28	418
valid_sources[0x2e]	3665	1			T6	760		T19	2		T28	378
valid_sources[0x2f]	3424	1			T6	509		T19	1		T28	346
valid_sources[0x30]	3890	1			T6	546		T14	1		T28	443
valid_sources[0x31]	3213	1			T6	381		T28	370		T29	606
valid_sources[0x32]	3624	1			T6	548		T26	2		T28	311
valid_sources[0x33]	4417	1			T6	85		T28	342		T67	4
valid_sources[0x34]	2964	1			T6	133		T28	417		T29	648
valid_sources[0x35]	3283	1			T6	632		T28	399		T110	1
valid_sources[0x36]	3549	1			T6	802		T28	450		T66	1
valid_sources[0x37]	3079	1			T6	115		T28	369		T64	1
valid_sources[0x38]	3174	1			T6	249		T28	465		T65	1
valid_sources[0x39]	3792	1			T4	3		T6	850		T14	1
valid_sources[0x3a]	3050	1			T6	234		T28	286		T27	2
valid_sources[0x3b]	3084	1			T6	413		T28	478		T112	1
valid_sources[0x3c]	3682	1			T6	558		T14	1		T28	266
valid_sources[0x3d]	3849	1			T6	584		T19	2		T28	488
valid_sources[0x3e]	3383	1			T6	459		T28	404		T113	1
valid_sources[0x3f]	3875	1			T6	392		T10	1		T28	448
valid_sources[0x40]	2745	1			T6	173		T19	1		T28	325
valid_sources[0x41]	2786	1			T6	214		T10	2		T33	1
valid_sources[0x42]	4146	1			T6	1569		T14	1		T28	358
valid_sources[0x43]	3445	1			T6	713		T28	315		T106	1
valid_sources[0x44]	3400	1			T6	263		T22	1		T28	425
valid_sources[0x45]	2943	1			T6	243		T28	428		T29	584
valid_sources[0x46]	3237	1			T6	709		T28	285		T110	7
valid_sources[0x47]	4085	1			T6	862		T28	451		T27	1
valid_sources[0x48]	4067	1			T6	894		T28	439		T29	598
valid_sources[0x49]	3362	1			T6	107		T19	1		T28	337
valid_sources[0x4a]	3232	1			T6	389		T28	349		T62	3
valid_sources[0x4b]	4184	1			T5	2		T6	1157		T28	359
valid_sources[0x4c]	2733	1			T6	375		T91	1		T28	331
valid_sources[0x4d]	3655	1			T6	394		T19	2		T91	1
valid_sources[0x4e]	2975	1			T6	80		T19	1		T28	363
valid_sources[0x4f]	3166	1			T6	212		T26	1		T28	414
valid_sources[0x50]	3748	1			T6	447		T19	1		T91	1
valid_sources[0x51]	2548	1			T6	120		T28	412		T32	1
valid_sources[0x52]	3260	1			T6	248		T28	358		T38	1
valid_sources[0x53]	3939	1			T6	760		T28	431		T29	615
valid_sources[0x54]	3269	1			T6	503		T28	348		T113	1
valid_sources[0x55]	3567	1			T6	501		T28	433		T112	1
valid_sources[0x56]	3451	1			T6	481		T91	1		T28	394
valid_sources[0x57]	4226	1			T6	906		T28	311		T27	1
valid_sources[0x58]	2974	1			T6	91		T10	1		T28	404
valid_sources[0x59]	4234	1			T6	730		T28	372		T66	5
valid_sources[0x5a]	3324	1			T6	446		T28	371		T29	609
valid_sources[0x5b]	3017	1			T4	1		T6	491		T28	417
valid_sources[0x5c]	3323	1			T6	259		T14	1		T28	461
valid_sources[0x5d]	3462	1			T4	1		T5	1		T6	776
valid_sources[0x5e]	3735	1			T6	416		T28	455		T64	1
valid_sources[0x5f]	2600	1			T6	58		T12	11		T28	326
valid_sources[0x60]	3551	1			T6	254		T26	1		T19	1
valid_sources[0x61]	3351	1			T6	986		T7	2		T28	350
valid_sources[0x62]	3506	1			T6	223		T26	1		T28	418
valid_sources[0x63]	3225	1			T6	222		T28	414		T38	1
valid_sources[0x64]	4066	1			T6	849		T28	369		T29	563
valid_sources[0x65]	3531	1			T6	507		T28	332		T29	567
valid_sources[0x66]	3193	1			T6	564		T28	413		T68	1
valid_sources[0x67]	3432	1			T6	642		T10	1		T28	326
valid_sources[0x68]	3312	1			T6	510		T28	402		T106	1
valid_sources[0x69]	3182	1			T4	1		T6	621		T28	392
valid_sources[0x6a]	3838	1			T6	797		T28	387		T64	1
valid_sources[0x6b]	2794	1			T6	173		T28	376		T112	1
valid_sources[0x6c]	3214	1			T6	526		T10	1		T28	285
valid_sources[0x6d]	3550	1			T6	514		T14	1		T19	2
valid_sources[0x6e]	2791	1			T6	21		T28	347		T29	654
valid_sources[0x6f]	3898	1			T6	774		T14	2		T28	382
valid_sources[0x70]	3238	1			T6	385		T28	374		T29	634
valid_sources[0x71]	3426	1			T6	413		T28	400		T29	568
valid_sources[0x72]	3229	1			T6	339		T28	408		T29	578
valid_sources[0x73]	3267	1			T6	533		T28	385		T29	650
valid_sources[0x74]	3072	1			T6	548		T28	419		T27	1
valid_sources[0x75]	3019	1			T6	19		T28	360		T37	28
valid_sources[0x76]	2651	1			T6	56		T28	383		T29	530
valid_sources[0x77]	3728	1			T6	636		T19	1		T28	347
valid_sources[0x78]	3964	1			T6	1154		T91	1		T28	355
valid_sources[0x79]	3640	1			T6	613		T91	1		T28	327
valid_sources[0x7a]	3511	1			T6	703		T28	491		T66	2
valid_sources[0x7b]	3473	1			T6	317		T26	1		T19	1
valid_sources[0x7c]	3959	1			T6	873		T19	1		T28	399
valid_sources[0x7d]	3807	1			T4	1		T6	900		T28	254
valid_sources[0x7e]	3110	1			T4	1		T6	225		T10	1
valid_sources[0x7f]	4213	1			T6	284		T28	433		T29	590
valid_sources[0x80]	3796	1			T6	510		T28	335		T110	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

202505

1

T6

28975

T8

11

T10

13

values[0x0]

all_enables

biggest_size

298155

1

T5

1

T6

43346

T33

1

values[0x1]

all_enables

biggest_size

298441

1

T6

43251

T28

33900

T49

1