Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1924490

1

T1

125

T2

358

T3

350

full_word

1214163

1

T1

15

T2

31

T3

36

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3138373	1			T1	140		T2	389		T3	386
auto[TlIntgErrCmd]	104	1			T44	11		T45	3		T46	3
auto[TlIntgErrData]	88	1			T44	5		T45	1		T46	6
auto[TlIntgErrBoth]	88	1			T44	4		T45	6		T46	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

506286

1

T1

140

T2

389

T3

386

auto[1]

2632367

1

T6

384881

T28

312135

T29

485448

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	217894	1			T1	125		T2	358		T3	350
auto[TlIntgErrNone]	partial	auto[1]	1706341	1			T6	250054		T28	203966		T29	314132
auto[TlIntgErrNone]	full_word	auto[0]	288272	1			T1	15		T2	31		T3	36
auto[TlIntgErrNone]	full_word	auto[1]	925866	1			T6	134827		T28	108169		T29	171316
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T44	3		T45	2		T46	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T44	8		T45	1		T46	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T93	2		T98	1		T99	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T98	1		T100	1		T101	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T44	3		T46	4		T93	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T44	2		T45	1		T46	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T102	2		T99	1		T103	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T94	1		T97	1		T98	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T44	3		T45	3		T93	5
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T44	1		T45	3		T46	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T100	1		T103	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T97	1		T98	2		T104	1