Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3789389

1

T3

253

T5

70

T6

73

full_word

2419108

1

T1

4

T3

19

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6208187	1			T1	4		T3	272		T4	2
auto[TlIntgErrCmd]	107	1			T58	12		T59	5		T60	5
auto[TlIntgErrData]	98	1			T58	4		T59	1		T60	6
auto[TlIntgErrBoth]	105	1			T58	4		T59	4		T60	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988027

1

T1

4

T3

272

T4

2

auto[1]

5220470

1

T11

129075

T18

128631

T19

509503

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	416911	1			T3	253		T5	70		T6	73
auto[TlIntgErrNone]	partial	auto[1]	3372207	1			T11	82923		T18	82751		T19	331283
auto[TlIntgErrNone]	full_word	auto[0]	570968	1			T1	4		T3	19		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	1848101	1			T11	46152		T18	45880		T19	178220
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T58	3		T59	1		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T58	7		T59	1		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T58	1		T59	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T58	1		T59	2		T126	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T58	3		T124	3		T128	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T58	1		T59	1		T60	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T60	1		T124	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T60	3		T124	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T58	1		T59	2		T60	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T58	3		T59	1		T60	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T60	1		T130	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T59	1		T125	1		T131	1