Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2133853

1

T1

45438

T2

57

T3

75

full_word

1370321

1

T1

27304

T2

3

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3503864	1			T1	72742		T2	60		T3	84
auto[TlIntgErrCmd]	101	1			T57	4		T58	8		T59	4
auto[TlIntgErrData]	98	1			T57	3		T58	3		T59	6
auto[TlIntgErrBoth]	111	1			T57	3		T58	9		T59	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

567434

1

T1

11532

T2

60

T3

84

auto[1]

2936740

1

T1

61210

T17

302352

T18

185937

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	242573	1			T1	5066		T2	57		T3	75
auto[TlIntgErrNone]	partial	auto[1]	1890990	1			T1	40372		T17	194400		T18	121568
auto[TlIntgErrNone]	full_word	auto[0]	324731	1			T1	6466		T2	3		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	1045570	1			T1	20838		T17	107952		T18	64369
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T57	2		T58	4		T111	4
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T57	2		T58	4		T59	4
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T112	1		T113	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T57	1		T59	4		T111	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T57	2		T58	2		T59	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T115	1		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T58	1		T116	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T58	2		T59	2		T111	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T57	2		T58	7		T59	8
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T118	1		T117	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T57	1		T119	1		T120	1