Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.98	100.00	98.28	97.33		100.00	79.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.98	100.00	98.28	97.33		100.00	79.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.46	96.97	93.15	97.88	100.00	98.69	98.03

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	94.22	91.60	85.14	99.07		95.29	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	438	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
208	1	1
254	1	1
309	1	1
410	8	8
411	8	8
413	8	8
414	8	8
416	8	8
417	8	8
421	1	1
423	1	1
426	1	1
427	1	1
428	1	1
429	1	1
434	1	1
438	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T14,T12
1	1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       414
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       414
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       421
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T32,T33
1	0	Not Covered

 LINE       423
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T14,T12
1	0	Covered	T5,T7,T8

 LINE       434
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T20,T34

 LINE       438
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T8,T14,T12
0	1	0	Covered	T5,T7,T8
1	0	0	Covered	T31,T32,T33

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	61	56	91.80
Total Bits	2882	2805	97.33
Total Bits 0->1	1441	1402	97.29
Total Bits 1->0	1441	1403	97.36

Ports	61	56	91.80
Port Bits	2882	2805	97.33
Port Bits 0->1	1441	1402	97.29
Port Bits 1->0	1441	1403	97.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T1,T17,T18	Yes	T1,T17,T18	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T1,*T17,*T18	Yes	T1,T17,T18	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T1,T17,T18	Yes	T1,T17,T18	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
kmac_data_i.error	No	Yes	T5,T7,T9	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T4,T5	Yes	T3,T8,T14	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T8,T14	Yes	T1,T2,T3	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	208	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	208	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	29	29	100.00	23	79.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	29	29	100.00	23	79.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	178863481	178687889	0	0
BusRomIndicesMatch_A	178852324	178682727	0	0
FpvSecCmFifoRptrCheck_A	178863481	0	0	0
FpvSecCmFifoWptrCheck_A	178863481	0	0	0
FpvSecCmRegWeOnehotCheck_A	178863481	80	0	0
KeymgrDataODataKnown_A	178863481	47790393	0	0
KeymgrDataODataKnown_AKnownEnable	178863481	178687889	0	0
KeymgrDataOValidKnown_A	178863481	178687889	0	0
KeymgrValidChk_A	178863481	0	0	318
KmacDataODataKnown_A	178863481	130767623	0	0
KmacDataODataKnown_AKnownEnable	178863481	178687889	0	0
KmacDataOValidKnown_A	178863481	178687889	0	0
PwrmgrDataChk_A	178863481	0	0	318
PwrmgrDataOKnown_A	178863481	178687889	0	0
RegsTlOAReadyKnown_A	178863481	178687889	0	0
RegsTlODDataKnown_A	178863481	6680571	0	0
RegsTlODDataKnown_AKnownEnable	178863481	178687889	0	0
RegsTlODValidKnown_A	178863481	178687889	0	0
RomTlOAReadyKnown_A	178863481	178687889	0	0
RomTlODDataKnown_A	178863481	10270668	0	0
RomTlODDataKnown_AKnownEnable	178863481	178687889	0	0
RomTlODValidKnown_A	178863481	178687889	0	0
StabilityChkKmac_A	178863481	130765213	0	0
StabilityChkkeymgr_A	178863481	47789215	0	0
TlAccessChk_A	178863481	130897496	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	178863481	80	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	178863481	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	178863481	475	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	178863481	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178852324	178682727	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293501	291387	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	80	0	0
T31	64769	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T35	0	20	0	0
T36	0	20	0	0
T37	37094	0	0	0
T38	200736	0	0	0
T39	238175	0	0	0
T40	422422	0	0	0
T41	253924	0	0	0
T42	140072	0	0	0
T43	54580	0	0	0
T44	82687	0	0	0
T45	87310	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	47790393	0	0
T1	106020	101872	0	0
T2	393346	1444	0	0
T3	124734	1405	0	0
T4	108614	1626	0	0
T5	404565	64	0	0
T6	78342	34	0	0
T7	245706	59	0	0
T8	293826	25454	0	0
T9	33013	134	0	0
T10	352964	1541	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	0	0	318

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	130767623	0	0
T1	106020	41283	0	0
T2	393346	391747	0	0
T3	124734	123090	0	0
T4	108614	106723	0	0
T5	404565	404113	0	0
T6	78342	78138	0	0
T7	245706	245412	0	0
T8	293826	264406	0	0
T9	33013	32681	0	0
T10	352964	351155	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	0	0	318

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	6680571	0	0
T1	106020	286137	0	0
T2	393346	89	0	0
T3	124734	32	0	0
T4	108614	32	0	0
T5	404565	2	0	0
T6	78342	7	0	0
T7	245706	1	0	0
T8	293826	26	0	0
T9	33013	1	0	0
T10	352964	32	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	10270668	0	0
T1	106020	72742	0	0
T2	393346	162	0	0
T3	124734	84	0	0
T4	108614	214	0	0
T5	404565	0	0	0
T6	78342	0	0	0
T7	245706	0	0	0
T8	293826	6	0	0
T9	33013	0	0	0
T10	352964	97	0	0
T13	0	232	0	0
T14	0	3	0	0
T15	0	258	0	0
T16	0	282	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	178687889	0	0
T1	106020	106011	0	0
T2	393346	393240	0	0
T3	124734	124600	0	0
T4	108614	108468	0	0
T5	404565	404377	0	0
T6	78342	78275	0	0
T7	245706	245553	0	0
T8	293826	291597	0	0
T9	33013	32891	0	0
T10	352964	352792	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	130765213	0	0
T1	106020	41277	0	0
T2	393346	391745	0	0
T3	124734	123088	0	0
T4	108614	106721	0	0
T5	404565	404111	0	0
T6	78342	78137	0	0
T7	245706	245410	0	0
T8	293826	264375	0	0
T9	33013	32679	0	0
T10	352964	351153	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	47789215	0	0
T1	106020	101872	0	0
T2	393346	1442	0	0
T3	124734	1403	0	0
T4	108614	1624	0	0
T5	404565	63	0	0
T6	78342	33	0	0
T7	245706	58	0	0
T8	293826	25442	0	0
T9	33013	133	0	0
T10	352964	1539	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	130897496	0	0
T1	106020	41390	0	0
T2	393346	391796	0	0
T3	124734	123195	0	0
T4	108614	106842	0	0
T5	404565	404313	0	0
T6	78342	78241	0	0
T7	245706	245494	0	0
T8	293826	266143	0	0
T9	33013	32757	0	0
T10	352964	351251	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	80	0	0
T31	64769	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T35	0	20	0	0
T36	0	20	0	0
T37	37094	0	0	0
T38	200736	0	0	0
T39	238175	0	0	0
T40	422422	0	0	0
T41	253924	0	0	0
T42	140072	0	0	0
T43	54580	0	0	0
T44	82687	0	0	0
T45	87310	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	475	0	0
T8	293826	5	0	0
T9	33013	0	0	0
T10	352964	0	0	0
T12	0	15	0	0
T13	87440	0	0	0
T14	839269	5	0	0
T15	31101	0	0	0
T16	42296	0	0	0
T20	69831	0	0	0
T28	0	10	0	0
T29	0	10	0	0
T30	0	11	0	0
T34	8471	0	0	0
T46	0	10	0	0
T47	0	10	0	0
T48	0	10	0	0
T49	0	21	0	0
T50	854630	0	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178863481	0	0	0