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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 96.97 93.01 97.88 100.00 98.69 98.03 98.37


Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T298 /workspace/coverage/default/14.rom_ctrl_stress_all.3886470095 May 02 12:52:34 PM PDT 24 May 02 12:53:50 PM PDT 24 24703961516 ps
T299 /workspace/coverage/default/13.rom_ctrl_stress_all.192451249 May 02 12:52:31 PM PDT 24 May 02 12:52:45 PM PDT 24 476522440 ps
T300 /workspace/coverage/default/40.rom_ctrl_smoke.3696744205 May 02 12:53:08 PM PDT 24 May 02 12:53:47 PM PDT 24 4079033248 ps
T301 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3247470239 May 02 12:52:18 PM PDT 24 May 02 12:52:51 PM PDT 24 12299072988 ps
T302 /workspace/coverage/default/45.rom_ctrl_stress_all.2909311245 May 02 12:53:15 PM PDT 24 May 02 12:53:58 PM PDT 24 23351202418 ps
T303 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1034563263 May 02 12:52:56 PM PDT 24 May 02 12:55:50 PM PDT 24 4124188510 ps
T304 /workspace/coverage/default/47.rom_ctrl_smoke.4070451817 May 02 12:53:21 PM PDT 24 May 02 12:54:01 PM PDT 24 13817022280 ps
T305 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1470039029 May 02 12:52:51 PM PDT 24 May 02 12:54:20 PM PDT 24 5265650800 ps
T306 /workspace/coverage/default/3.rom_ctrl_alert_test.529107370 May 02 12:52:12 PM PDT 24 May 02 12:52:32 PM PDT 24 5882859097 ps
T307 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2709352155 May 02 12:52:26 PM PDT 24 May 02 12:52:42 PM PDT 24 5458801922 ps
T308 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3237090355 May 02 12:52:13 PM PDT 24 May 02 12:52:34 PM PDT 24 5347020734 ps
T309 /workspace/coverage/default/6.rom_ctrl_smoke.3943483582 May 02 12:52:21 PM PDT 24 May 02 12:52:45 PM PDT 24 4387263452 ps
T310 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3305815721 May 02 12:53:14 PM PDT 24 May 02 12:55:17 PM PDT 24 42494782401 ps
T311 /workspace/coverage/default/19.rom_ctrl_stress_all.2200344316 May 02 12:52:41 PM PDT 24 May 02 12:53:52 PM PDT 24 29565219246 ps
T312 /workspace/coverage/default/28.rom_ctrl_stress_all.3063017645 May 02 12:52:53 PM PDT 24 May 02 12:53:14 PM PDT 24 2953819920 ps
T313 /workspace/coverage/default/25.rom_ctrl_stress_all.1505216897 May 02 12:52:45 PM PDT 24 May 02 12:53:13 PM PDT 24 1072010859 ps
T314 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.682304204 May 02 12:52:29 PM PDT 24 May 02 12:53:03 PM PDT 24 3685855952 ps
T315 /workspace/coverage/default/10.rom_ctrl_stress_all.3832880458 May 02 12:52:30 PM PDT 24 May 02 12:53:12 PM PDT 24 16399044749 ps
T316 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.142849521 May 02 12:52:49 PM PDT 24 May 02 12:53:18 PM PDT 24 2596404820 ps
T317 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4182828959 May 02 12:52:14 PM PDT 24 May 02 12:57:34 PM PDT 24 212592304877 ps
T318 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1862661895 May 02 12:53:08 PM PDT 24 May 02 12:53:18 PM PDT 24 97899987 ps
T319 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3185248395 May 02 12:52:26 PM PDT 24 May 02 12:52:43 PM PDT 24 1605991657 ps
T320 /workspace/coverage/default/41.rom_ctrl_stress_all.2127841665 May 02 12:53:10 PM PDT 24 May 02 12:54:24 PM PDT 24 6151839675 ps
T321 /workspace/coverage/default/46.rom_ctrl_smoke.3077579627 May 02 12:53:13 PM PDT 24 May 02 12:53:34 PM PDT 24 865381018 ps
T322 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3807751342 May 02 12:52:16 PM PDT 24 May 02 12:52:39 PM PDT 24 8589139474 ps
T323 /workspace/coverage/default/34.rom_ctrl_stress_all.1437210644 May 02 12:53:03 PM PDT 24 May 02 12:53:53 PM PDT 24 14867448188 ps
T324 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.554106316 May 02 12:52:56 PM PDT 24 May 02 12:53:25 PM PDT 24 2397446215 ps
T325 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.473678686 May 02 12:53:03 PM PDT 24 May 02 12:55:36 PM PDT 24 3098642311 ps
T326 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4053836917 May 02 12:52:59 PM PDT 24 May 02 12:55:25 PM PDT 24 3441041934 ps
T327 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.817219538 May 02 12:53:06 PM PDT 24 May 02 12:53:36 PM PDT 24 5867954665 ps
T328 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3658772829 May 02 12:53:17 PM PDT 24 May 02 12:57:39 PM PDT 24 112998369960 ps
T329 /workspace/coverage/default/2.rom_ctrl_stress_all.1170475880 May 02 12:52:18 PM PDT 24 May 02 12:53:16 PM PDT 24 12928342827 ps
T330 /workspace/coverage/default/13.rom_ctrl_smoke.2851052525 May 02 12:52:34 PM PDT 24 May 02 12:53:02 PM PDT 24 5816555149 ps
T331 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1329428768 May 02 12:52:14 PM PDT 24 May 02 12:52:45 PM PDT 24 9474986520 ps
T332 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.760624280 May 02 12:53:02 PM PDT 24 May 02 12:54:59 PM PDT 24 28005864827 ps
T55 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3863308695 May 02 12:52:45 PM PDT 24 May 02 01:18:15 PM PDT 24 38598706457 ps
T333 /workspace/coverage/default/6.rom_ctrl_stress_all.2093649967 May 02 12:52:24 PM PDT 24 May 02 12:53:54 PM PDT 24 8886591372 ps
T334 /workspace/coverage/default/16.rom_ctrl_alert_test.1123956940 May 02 12:52:42 PM PDT 24 May 02 12:52:57 PM PDT 24 1092439653 ps
T335 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3573692809 May 02 12:52:38 PM PDT 24 May 02 12:52:52 PM PDT 24 4126654877 ps
T336 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1594392033 May 02 12:53:08 PM PDT 24 May 02 12:54:53 PM PDT 24 58654022534 ps
T337 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3027001513 May 02 12:52:56 PM PDT 24 May 02 12:53:51 PM PDT 24 2828779273 ps
T338 /workspace/coverage/default/28.rom_ctrl_smoke.848689161 May 02 12:52:54 PM PDT 24 May 02 12:53:25 PM PDT 24 15499595101 ps
T339 /workspace/coverage/default/22.rom_ctrl_stress_all.2597905850 May 02 12:52:43 PM PDT 24 May 02 12:53:06 PM PDT 24 20589379319 ps
T340 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2360331530 May 02 12:52:32 PM PDT 24 May 02 12:53:03 PM PDT 24 3164078481 ps
T341 /workspace/coverage/default/48.rom_ctrl_smoke.1591915876 May 02 12:53:21 PM PDT 24 May 02 12:54:00 PM PDT 24 7363821687 ps
T342 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1308290052 May 02 12:52:25 PM PDT 24 May 02 12:52:37 PM PDT 24 2181535004 ps
T343 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3873121976 May 02 12:53:04 PM PDT 24 May 02 12:53:16 PM PDT 24 641198621 ps
T344 /workspace/coverage/default/41.rom_ctrl_alert_test.3869573810 May 02 12:53:10 PM PDT 24 May 02 12:53:25 PM PDT 24 3488025575 ps
T345 /workspace/coverage/default/23.rom_ctrl_stress_all.2223234164 May 02 12:52:54 PM PDT 24 May 02 12:53:55 PM PDT 24 4679602609 ps
T346 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.900293777 May 02 12:52:48 PM PDT 24 May 02 12:53:07 PM PDT 24 5622155354 ps
T347 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2839314333 May 02 12:52:12 PM PDT 24 May 02 12:55:59 PM PDT 24 18442415758 ps
T348 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.594307876 May 02 12:52:47 PM PDT 24 May 02 12:55:50 PM PDT 24 49972486930 ps
T349 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3865996916 May 02 12:52:47 PM PDT 24 May 02 12:53:09 PM PDT 24 7937104847 ps
T350 /workspace/coverage/default/44.rom_ctrl_smoke.1316989552 May 02 12:53:10 PM PDT 24 May 02 12:53:41 PM PDT 24 24821186071 ps
T351 /workspace/coverage/default/0.rom_ctrl_smoke.3685311537 May 02 12:52:13 PM PDT 24 May 02 12:52:46 PM PDT 24 3094407364 ps
T352 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3849364277 May 02 12:53:14 PM PDT 24 May 02 12:53:46 PM PDT 24 3024893156 ps
T353 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.393011479 May 02 12:52:30 PM PDT 24 May 02 12:56:31 PM PDT 24 15646179834 ps
T354 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3891760314 May 02 12:52:38 PM PDT 24 May 02 12:52:49 PM PDT 24 347877679 ps
T355 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4059867669 May 02 12:52:35 PM PDT 24 May 02 12:55:59 PM PDT 24 20723464161 ps
T356 /workspace/coverage/default/18.rom_ctrl_stress_all.1592789193 May 02 12:52:40 PM PDT 24 May 02 12:53:01 PM PDT 24 955660346 ps
T357 /workspace/coverage/default/43.rom_ctrl_alert_test.2225108647 May 02 12:53:08 PM PDT 24 May 02 12:53:18 PM PDT 24 519368321 ps
T358 /workspace/coverage/default/38.rom_ctrl_stress_all.846695584 May 02 12:53:03 PM PDT 24 May 02 12:54:55 PM PDT 24 49398419760 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3473610722 May 02 12:52:01 PM PDT 24 May 02 12:52:15 PM PDT 24 216429296 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1723892046 May 02 12:52:15 PM PDT 24 May 02 12:52:40 PM PDT 24 3200663566 ps
T63 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4036135856 May 02 12:51:57 PM PDT 24 May 02 12:52:17 PM PDT 24 3944596076 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1774733095 May 02 12:52:01 PM PDT 24 May 02 12:52:44 PM PDT 24 1144923842 ps
T69 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.546604521 May 02 12:52:01 PM PDT 24 May 02 12:52:18 PM PDT 24 2371895000 ps
T70 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4201209438 May 02 12:52:10 PM PDT 24 May 02 12:53:07 PM PDT 24 3361530158 ps
T106 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1651530711 May 02 12:52:08 PM PDT 24 May 02 12:52:31 PM PDT 24 7995878101 ps
T71 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3569926885 May 02 12:51:53 PM PDT 24 May 02 12:52:24 PM PDT 24 1175636243 ps
T72 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4189402005 May 02 12:52:00 PM PDT 24 May 02 12:52:09 PM PDT 24 334362863 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1799981819 May 02 12:52:08 PM PDT 24 May 02 12:52:22 PM PDT 24 90588945 ps
T68 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2546802251 May 02 12:52:01 PM PDT 24 May 02 12:52:12 PM PDT 24 199700103 ps
T359 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.73953304 May 02 12:51:53 PM PDT 24 May 02 12:52:14 PM PDT 24 13027983060 ps
T360 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3896178399 May 02 12:52:06 PM PDT 24 May 02 12:52:30 PM PDT 24 13848010040 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2900461509 May 02 12:52:09 PM PDT 24 May 02 12:52:28 PM PDT 24 3973317056 ps
T74 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1077298404 May 02 12:52:09 PM PDT 24 May 02 12:53:32 PM PDT 24 35917776904 ps
T75 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1220742076 May 02 12:52:07 PM PDT 24 May 02 12:52:30 PM PDT 24 25628774062 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2117344624 May 02 12:51:55 PM PDT 24 May 02 12:52:44 PM PDT 24 4809690832 ps
T77 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3304168831 May 02 12:52:06 PM PDT 24 May 02 12:53:28 PM PDT 24 16313140906 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.126308099 May 02 12:52:15 PM PDT 24 May 02 12:52:33 PM PDT 24 1242380987 ps
T361 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3344176739 May 02 12:52:08 PM PDT 24 May 02 12:52:21 PM PDT 24 846246472 ps
T58 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3218406377 May 02 12:52:07 PM PDT 24 May 02 12:52:51 PM PDT 24 192846935 ps
T362 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3207882381 May 02 12:52:00 PM PDT 24 May 02 12:52:24 PM PDT 24 13906909243 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2821357729 May 02 12:51:54 PM PDT 24 May 02 12:52:16 PM PDT 24 8868069083 ps
T364 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.357392110 May 02 12:52:08 PM PDT 24 May 02 12:52:24 PM PDT 24 678991603 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1107792778 May 02 12:52:09 PM PDT 24 May 02 12:52:26 PM PDT 24 5486376740 ps
T59 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3725914245 May 02 12:52:17 PM PDT 24 May 02 12:53:41 PM PDT 24 3588067806 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.905293428 May 02 12:52:01 PM PDT 24 May 02 12:52:26 PM PDT 24 384609257 ps
T116 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.53364108 May 02 12:52:17 PM PDT 24 May 02 12:52:59 PM PDT 24 164611905 ps
T117 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3076768719 May 02 12:51:58 PM PDT 24 May 02 12:53:14 PM PDT 24 421328942 ps
T108 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.822335425 May 02 12:52:03 PM PDT 24 May 02 12:52:23 PM PDT 24 1246604004 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.72379299 May 02 12:52:01 PM PDT 24 May 02 12:52:12 PM PDT 24 348326516 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2229851408 May 02 12:51:56 PM PDT 24 May 02 12:52:06 PM PDT 24 1369586467 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3636990103 May 02 12:51:56 PM PDT 24 May 02 12:52:11 PM PDT 24 756099728 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3120006435 May 02 12:52:07 PM PDT 24 May 02 12:52:23 PM PDT 24 675309483 ps
T109 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.858252949 May 02 12:52:07 PM PDT 24 May 02 12:52:23 PM PDT 24 811670456 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.876479680 May 02 12:51:56 PM PDT 24 May 02 12:52:15 PM PDT 24 8345857170 ps
T371 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3381165367 May 02 12:52:01 PM PDT 24 May 02 12:52:12 PM PDT 24 637605386 ps
T118 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1754152454 May 02 12:52:00 PM PDT 24 May 02 12:53:20 PM PDT 24 14581035938 ps
T372 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.786755041 May 02 12:52:02 PM PDT 24 May 02 12:52:15 PM PDT 24 406997443 ps
T124 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.825616256 May 02 12:52:07 PM PDT 24 May 02 12:53:01 PM PDT 24 2131149653 ps
T85 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2367743902 May 02 12:51:54 PM PDT 24 May 02 12:52:11 PM PDT 24 7637459627 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.145766475 May 02 12:52:08 PM PDT 24 May 02 12:52:30 PM PDT 24 3229217845 ps
T373 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4003221943 May 02 12:52:08 PM PDT 24 May 02 12:52:35 PM PDT 24 788070779 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.409412529 May 02 12:51:57 PM PDT 24 May 02 12:52:16 PM PDT 24 8345018522 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4104586619 May 02 12:51:52 PM PDT 24 May 02 12:52:12 PM PDT 24 10868872138 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2446446057 May 02 12:52:01 PM PDT 24 May 02 12:53:23 PM PDT 24 4265075010 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1877372395 May 02 12:52:11 PM PDT 24 May 02 12:52:26 PM PDT 24 937435302 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4091638091 May 02 12:51:52 PM PDT 24 May 02 12:52:03 PM PDT 24 610865454 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1715864406 May 02 12:52:06 PM PDT 24 May 02 12:52:24 PM PDT 24 988563989 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2698158805 May 02 12:51:53 PM PDT 24 May 02 12:52:01 PM PDT 24 309937251 ps
T122 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2169157530 May 02 12:51:59 PM PDT 24 May 02 12:53:14 PM PDT 24 1229446173 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3733618369 May 02 12:51:59 PM PDT 24 May 02 12:53:06 PM PDT 24 23048930559 ps
T378 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3351356904 May 02 12:52:17 PM PDT 24 May 02 12:52:37 PM PDT 24 1808020887 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3714627656 May 02 12:52:09 PM PDT 24 May 02 12:53:26 PM PDT 24 864053458 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.557255858 May 02 12:51:50 PM PDT 24 May 02 12:52:04 PM PDT 24 5584517070 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.419080034 May 02 12:51:54 PM PDT 24 May 02 12:52:02 PM PDT 24 175070976 ps
T381 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1607856556 May 02 12:52:08 PM PDT 24 May 02 12:52:59 PM PDT 24 911352013 ps
T382 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1452374970 May 02 12:52:17 PM PDT 24 May 02 12:52:33 PM PDT 24 758473534 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1295804973 May 02 12:52:08 PM PDT 24 May 02 12:52:27 PM PDT 24 2484685870 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.785417028 May 02 12:52:00 PM PDT 24 May 02 12:52:10 PM PDT 24 334322682 ps
T384 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4168043551 May 02 12:52:22 PM PDT 24 May 02 12:52:40 PM PDT 24 1736843033 ps
T385 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2966730939 May 02 12:52:09 PM PDT 24 May 02 12:52:25 PM PDT 24 744646536 ps
T386 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4013472738 May 02 12:52:06 PM PDT 24 May 02 12:52:27 PM PDT 24 1563417070 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3360576951 May 02 12:52:05 PM PDT 24 May 02 12:52:53 PM PDT 24 1309496061 ps
T115 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.64707891 May 02 12:51:59 PM PDT 24 May 02 12:52:54 PM PDT 24 20454279273 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1418656369 May 02 12:52:00 PM PDT 24 May 02 12:52:24 PM PDT 24 6875190373 ps
T389 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3653883105 May 02 12:52:07 PM PDT 24 May 02 12:52:31 PM PDT 24 1749528955 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1881721278 May 02 12:52:09 PM PDT 24 May 02 12:52:24 PM PDT 24 426295585 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3413083370 May 02 12:51:57 PM PDT 24 May 02 12:52:10 PM PDT 24 2656761539 ps
T125 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1635800744 May 02 12:51:57 PM PDT 24 May 02 12:53:15 PM PDT 24 5514462534 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2595682789 May 02 12:52:01 PM PDT 24 May 02 12:52:17 PM PDT 24 1031787206 ps
T392 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2817551746 May 02 12:52:06 PM PDT 24 May 02 12:52:29 PM PDT 24 6021040320 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3887872251 May 02 12:51:55 PM PDT 24 May 02 12:52:03 PM PDT 24 554503812 ps
T87 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.41367240 May 02 12:52:24 PM PDT 24 May 02 12:52:42 PM PDT 24 6924751048 ps
T394 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3908193231 May 02 12:51:59 PM PDT 24 May 02 12:52:23 PM PDT 24 2095842433 ps
T123 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3934593902 May 02 12:51:58 PM PDT 24 May 02 12:53:11 PM PDT 24 1308088848 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.884173849 May 02 12:51:54 PM PDT 24 May 02 12:52:05 PM PDT 24 205512056 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.301868035 May 02 12:51:54 PM PDT 24 May 02 12:52:13 PM PDT 24 3712950958 ps
T89 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2440952759 May 02 12:52:09 PM PDT 24 May 02 12:52:44 PM PDT 24 1076600131 ps
T397 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.828940351 May 02 12:52:07 PM PDT 24 May 02 12:52:19 PM PDT 24 223989488 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1078134022 May 02 12:52:02 PM PDT 24 May 02 12:53:52 PM PDT 24 53320221786 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2772871697 May 02 12:51:57 PM PDT 24 May 02 12:52:16 PM PDT 24 7004656101 ps
T400 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.799510970 May 02 12:51:59 PM PDT 24 May 02 12:52:53 PM PDT 24 2451137289 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.909935663 May 02 12:51:56 PM PDT 24 May 02 12:52:37 PM PDT 24 436419105 ps
T402 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1421553108 May 02 12:52:06 PM PDT 24 May 02 12:52:26 PM PDT 24 4833322875 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.374796495 May 02 12:51:54 PM PDT 24 May 02 12:52:12 PM PDT 24 1786472999 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1635615631 May 02 12:51:57 PM PDT 24 May 02 12:52:08 PM PDT 24 211613763 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3938970798 May 02 12:51:55 PM PDT 24 May 02 12:52:08 PM PDT 24 5863198504 ps
T90 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3054022191 May 02 12:51:50 PM PDT 24 May 02 12:52:07 PM PDT 24 6371376917 ps
T406 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3939546203 May 02 12:52:07 PM PDT 24 May 02 12:52:27 PM PDT 24 1302734010 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.784151577 May 02 12:51:55 PM PDT 24 May 02 12:52:03 PM PDT 24 692010902 ps
T95 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3235311076 May 02 12:52:00 PM PDT 24 May 02 12:53:16 PM PDT 24 7754999297 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.430387413 May 02 12:51:54 PM PDT 24 May 02 12:52:07 PM PDT 24 3388870020 ps
T408 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3088721403 May 02 12:52:02 PM PDT 24 May 02 12:52:21 PM PDT 24 5104211501 ps
T409 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3476752831 May 02 12:52:07 PM PDT 24 May 02 12:52:52 PM PDT 24 1574711640 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1301169296 May 02 12:52:07 PM PDT 24 May 02 12:52:22 PM PDT 24 344486357 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2401926525 May 02 12:51:56 PM PDT 24 May 02 12:52:14 PM PDT 24 7454703937 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2987539504 May 02 12:51:57 PM PDT 24 May 02 12:52:14 PM PDT 24 5752057554 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2995284902 May 02 12:52:01 PM PDT 24 May 02 12:52:14 PM PDT 24 472615323 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3833883760 May 02 12:52:00 PM PDT 24 May 02 12:52:09 PM PDT 24 86709602 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4122119404 May 02 12:51:54 PM PDT 24 May 02 12:52:13 PM PDT 24 3943252098 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3299128125 May 02 12:51:57 PM PDT 24 May 02 12:52:07 PM PDT 24 695502132 ps
T417 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1878012877 May 02 12:52:09 PM PDT 24 May 02 12:52:36 PM PDT 24 1438140982 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2259484119 May 02 12:51:54 PM PDT 24 May 02 12:52:17 PM PDT 24 3974660147 ps
T419 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1940355006 May 02 12:52:09 PM PDT 24 May 02 12:52:53 PM PDT 24 324618919 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2496971108 May 02 12:51:58 PM PDT 24 May 02 12:52:38 PM PDT 24 2655824549 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1565546865 May 02 12:52:10 PM PDT 24 May 02 12:52:57 PM PDT 24 729428013 ps
T422 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1383114053 May 02 12:52:18 PM PDT 24 May 02 12:52:30 PM PDT 24 334459203 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1821427869 May 02 12:52:02 PM PDT 24 May 02 12:52:17 PM PDT 24 1273983515 ps
T424 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2129654587 May 02 12:52:06 PM PDT 24 May 02 12:52:20 PM PDT 24 334512536 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.508222412 May 02 12:52:08 PM PDT 24 May 02 12:53:49 PM PDT 24 12093469463 ps
T426 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1041454940 May 02 12:52:00 PM PDT 24 May 02 12:52:17 PM PDT 24 2699551964 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3879993733 May 02 12:52:10 PM PDT 24 May 02 12:53:33 PM PDT 24 1338920937 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.687584302 May 02 12:51:54 PM PDT 24 May 02 12:52:09 PM PDT 24 3362125384 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1230974236 May 02 12:51:54 PM PDT 24 May 02 12:52:14 PM PDT 24 2126958411 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3269259535 May 02 12:52:01 PM PDT 24 May 02 12:52:12 PM PDT 24 515979776 ps
T431 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3053745047 May 02 12:52:08 PM PDT 24 May 02 12:52:28 PM PDT 24 5521435578 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2296785846 May 02 12:52:00 PM PDT 24 May 02 12:52:17 PM PDT 24 909379066 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.378926877 May 02 12:52:00 PM PDT 24 May 02 12:52:16 PM PDT 24 416478067 ps
T120 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3683894384 May 02 12:51:51 PM PDT 24 May 02 12:53:09 PM PDT 24 1422573873 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1947069415 May 02 12:51:57 PM PDT 24 May 02 12:52:11 PM PDT 24 441478194 ps
T435 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1520441414 May 02 12:52:11 PM PDT 24 May 02 12:52:29 PM PDT 24 12953189371 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1642982200 May 02 12:52:01 PM PDT 24 May 02 12:52:22 PM PDT 24 3335250196 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.406862639 May 02 12:52:07 PM PDT 24 May 02 12:52:31 PM PDT 24 2200604299 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2942853336 May 02 12:51:55 PM PDT 24 May 02 12:52:09 PM PDT 24 978474196 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1120460455 May 02 12:52:09 PM PDT 24 May 02 12:52:55 PM PDT 24 11804060788 ps
T440 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.190054074 May 02 12:51:54 PM PDT 24 May 02 12:52:13 PM PDT 24 7063152426 ps
T441 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.289307952 May 02 12:52:11 PM PDT 24 May 02 12:52:34 PM PDT 24 22154432120 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1141925694 May 02 12:52:08 PM PDT 24 May 02 12:52:20 PM PDT 24 89209094 ps
T443 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4220984020 May 02 12:52:01 PM PDT 24 May 02 12:53:16 PM PDT 24 34953365453 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1414814931 May 02 12:51:57 PM PDT 24 May 02 12:52:18 PM PDT 24 2132195581 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2234279927 May 02 12:51:53 PM PDT 24 May 02 12:52:12 PM PDT 24 4058328002 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1218065986 May 02 12:52:07 PM PDT 24 May 02 12:52:18 PM PDT 24 178712756 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.786390508 May 02 12:52:00 PM PDT 24 May 02 12:52:21 PM PDT 24 7797413743 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4159127697 May 02 12:51:54 PM PDT 24 May 02 12:52:17 PM PDT 24 382194722 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3073682231 May 02 12:51:54 PM PDT 24 May 02 12:52:07 PM PDT 24 12370147669 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1977342010 May 02 12:51:56 PM PDT 24 May 02 12:52:13 PM PDT 24 6591699048 ps
T450 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3694631002 May 02 12:52:00 PM PDT 24 May 02 12:52:18 PM PDT 24 5222225032 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.989180518 May 02 12:51:52 PM PDT 24 May 02 12:52:10 PM PDT 24 7747669065 ps
T452 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3919198310 May 02 12:52:05 PM PDT 24 May 02 12:52:19 PM PDT 24 437566421 ps
T453 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3463096867 May 02 12:52:00 PM PDT 24 May 02 12:52:18 PM PDT 24 4962376147 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3749464342 May 02 12:51:53 PM PDT 24 May 02 12:53:04 PM PDT 24 8260546239 ps
T455 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.696828232 May 02 12:52:08 PM PDT 24 May 02 12:52:27 PM PDT 24 2298560911 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1708665806 May 02 12:51:52 PM PDT 24 May 02 12:52:12 PM PDT 24 1591240913 ps

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2989736330
Short name T7
Test name
Test status
Simulation time 61422047949 ps
CPU time 638.3 seconds
Started May 02 12:52:18 PM PDT 24
Finished May 02 01:03:03 PM PDT 24
Peak memory 236072 kb
Host smart-79cd9560-0b8c-4c5f-9d90-a46189ce7fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989736330 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2989736330
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2667832750
Short name T1
Test name
Test status
Simulation time 125296686390 ps
CPU time 375.16 seconds
Started May 02 12:52:29 PM PDT 24
Finished May 02 12:58:47 PM PDT 24
Peak memory 234488 kb
Host smart-62ce06f4-c9e0-4f4a-a221-d02241e8b940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667832750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2667832750
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3743615810
Short name T23
Test name
Test status
Simulation time 525894884574 ps
CPU time 819.78 seconds
Started May 02 12:52:44 PM PDT 24
Finished May 02 01:06:29 PM PDT 24
Peak memory 238072 kb
Host smart-37a816d4-6c97-4764-8b59-ab5a49321642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743615810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3743615810
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3076768719
Short name T117
Test name
Test status
Simulation time 421328942 ps
CPU time 71.7 seconds
Started May 02 12:51:58 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 218652 kb
Host smart-6953d604-71f1-4e39-b6a2-beae4fb68e46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076768719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3076768719
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3318481269
Short name T13
Test name
Test status
Simulation time 21334202889 ps
CPU time 53.87 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:52 PM PDT 24
Peak memory 219624 kb
Host smart-b17352fc-bc4f-4981-b0e2-35c900778d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318481269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3318481269
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4092054259
Short name T31
Test name
Test status
Simulation time 747741754 ps
CPU time 99.47 seconds
Started May 02 12:52:14 PM PDT 24
Finished May 02 12:54:01 PM PDT 24
Peak memory 236972 kb
Host smart-bdd43614-ff56-4ca4-ba5b-16d09f1329d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092054259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4092054259
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4201209438
Short name T70
Test name
Test status
Simulation time 3361530158 ps
CPU time 49.34 seconds
Started May 02 12:52:10 PM PDT 24
Finished May 02 12:53:07 PM PDT 24
Peak memory 210548 kb
Host smart-1813b9c3-c242-481e-9c8a-e0a29f01c515
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201209438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4201209438
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2083124730
Short name T4
Test name
Test status
Simulation time 90773243 ps
CPU time 4.31 seconds
Started May 02 12:52:36 PM PDT 24
Finished May 02 12:52:43 PM PDT 24
Peak memory 211392 kb
Host smart-208b220f-60a6-42e8-940a-c002f812d820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083124730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2083124730
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3683894384
Short name T120
Test name
Test status
Simulation time 1422573873 ps
CPU time 73.83 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:53:09 PM PDT 24
Peak memory 210484 kb
Host smart-512344b4-491a-4d44-bf85-286af8698fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683894384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3683894384
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1303260379
Short name T40
Test name
Test status
Simulation time 47457726416 ps
CPU time 26.49 seconds
Started May 02 12:52:33 PM PDT 24
Finished May 02 12:53:02 PM PDT 24
Peak memory 212428 kb
Host smart-562bae74-728e-4e5c-ad16-6be557839031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303260379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1303260379
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1483753777
Short name T2
Test name
Test status
Simulation time 1184860303 ps
CPU time 9.22 seconds
Started May 02 12:52:57 PM PDT 24
Finished May 02 12:53:11 PM PDT 24
Peak memory 212020 kb
Host smart-6fb6cdad-2953-4b58-a54e-c7f3de5a8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483753777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1483753777
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1307430029
Short name T26
Test name
Test status
Simulation time 7213507392 ps
CPU time 20.59 seconds
Started May 02 12:52:36 PM PDT 24
Finished May 02 12:53:00 PM PDT 24
Peak memory 211480 kb
Host smart-f806db16-b6c7-4b85-ade3-602a93232152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307430029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1307430029
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2859361736
Short name T60
Test name
Test status
Simulation time 378777257 ps
CPU time 21.74 seconds
Started May 02 12:52:38 PM PDT 24
Finished May 02 12:53:03 PM PDT 24
Peak memory 214700 kb
Host smart-9b38dfab-29ab-4d51-9b1d-f9cb9bee8b5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859361736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2859361736
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.825616256
Short name T124
Test name
Test status
Simulation time 2131149653 ps
CPU time 46.79 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:53:01 PM PDT 24
Peak memory 211216 kb
Host smart-c04d1202-9c64-4e0f-b040-746b68ef751d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825616256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.825616256
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.64707891
Short name T115
Test name
Test status
Simulation time 20454279273 ps
CPU time 48.71 seconds
Started May 02 12:51:59 PM PDT 24
Finished May 02 12:52:54 PM PDT 24
Peak memory 210624 kb
Host smart-a4dbccb4-0436-4223-9642-034f18183972
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64707891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pass
thru_mem_tl_intg_err.64707891
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1220742076
Short name T75
Test name
Test status
Simulation time 25628774062 ps
CPU time 15.52 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 210596 kb
Host smart-78de0137-8d75-4420-8e89-547758a94df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220742076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1220742076
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1238435472
Short name T97
Test name
Test status
Simulation time 1314397424 ps
CPU time 13.39 seconds
Started May 02 12:53:07 PM PDT 24
Finished May 02 12:53:26 PM PDT 24
Peak memory 211380 kb
Host smart-68ef5d6b-457b-4343-a4fa-b5ab7dac4c6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238435472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1238435472
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3572959111
Short name T230
Test name
Test status
Simulation time 20779894587 ps
CPU time 242.87 seconds
Started May 02 12:52:15 PM PDT 24
Finished May 02 12:56:25 PM PDT 24
Peak memory 213092 kb
Host smart-b3a809fd-efda-4095-913f-9cd8623d9bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572959111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3572959111
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3054022191
Short name T90
Test name
Test status
Simulation time 6371376917 ps
CPU time 13.26 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:52:07 PM PDT 24
Peak memory 210588 kb
Host smart-278b825a-6701-4023-a86c-2a6d16d95179
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054022191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3054022191
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2942853336
Short name T438
Test name
Test status
Simulation time 978474196 ps
CPU time 10.42 seconds
Started May 02 12:51:55 PM PDT 24
Finished May 02 12:52:09 PM PDT 24
Peak memory 210512 kb
Host smart-e6130f8b-770a-4e78-902c-5af1a99e6557
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942853336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2942853336
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2821357729
Short name T363
Test name
Test status
Simulation time 8868069083 ps
CPU time 18.3 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:16 PM PDT 24
Peak memory 210560 kb
Host smart-69e82865-b487-47f2-b41f-ae95fe65a102
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821357729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2821357729
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.73953304
Short name T359
Test name
Test status
Simulation time 13027983060 ps
CPU time 16.6 seconds
Started May 02 12:51:53 PM PDT 24
Finished May 02 12:52:14 PM PDT 24
Peak memory 218800 kb
Host smart-de08252d-86c2-49a8-9408-cdf605bd702f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73953304 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.73953304
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2401926525
Short name T411
Test name
Test status
Simulation time 7454703937 ps
CPU time 14.68 seconds
Started May 02 12:51:56 PM PDT 24
Finished May 02 12:52:14 PM PDT 24
Peak memory 210612 kb
Host smart-5f2a329a-6fa0-426f-99bd-847cab616515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401926525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2401926525
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.989180518
Short name T451
Test name
Test status
Simulation time 7747669065 ps
CPU time 13.79 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:10 PM PDT 24
Peak memory 210412 kb
Host smart-483e68cc-018b-4de5-8aae-38dbfac492e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989180518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.989180518
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1977342010
Short name T449
Test name
Test status
Simulation time 6591699048 ps
CPU time 13.64 seconds
Started May 02 12:51:56 PM PDT 24
Finished May 02 12:52:13 PM PDT 24
Peak memory 210476 kb
Host smart-61fce03d-2533-4570-b236-8c5fb1d0f1fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977342010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1977342010
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.905293428
Short name T365
Test name
Test status
Simulation time 384609257 ps
CPU time 18.52 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:26 PM PDT 24
Peak memory 210428 kb
Host smart-ab8734b8-1408-4494-8612-a065082e5cc0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905293428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.905293428
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3073682231
Short name T448
Test name
Test status
Simulation time 12370147669 ps
CPU time 8.91 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:07 PM PDT 24
Peak memory 210596 kb
Host smart-660c91cf-0598-431a-9d62-03042389382b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073682231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3073682231
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1708665806
Short name T456
Test name
Test status
Simulation time 1591240913 ps
CPU time 16.08 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 218760 kb
Host smart-2c8804c4-91cf-4cd2-a11c-629401dd2beb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708665806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1708665806
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4122119404
Short name T415
Test name
Test status
Simulation time 3943252098 ps
CPU time 15.06 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:13 PM PDT 24
Peak memory 210484 kb
Host smart-a0112212-8316-44e5-90af-6e83f9c57edd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122119404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4122119404
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1414814931
Short name T444
Test name
Test status
Simulation time 2132195581 ps
CPU time 15.99 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:18 PM PDT 24
Peak memory 210456 kb
Host smart-76b66031-f5e6-4fdf-95b4-f8a93663170e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414814931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1414814931
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4091638091
Short name T375
Test name
Test status
Simulation time 610865454 ps
CPU time 7.21 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:03 PM PDT 24
Peak memory 210468 kb
Host smart-55a9d97e-b240-4bc8-89ef-bc9c8deb5ea3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091638091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4091638091
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.374796495
Short name T403
Test name
Test status
Simulation time 1786472999 ps
CPU time 14.92 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 218668 kb
Host smart-271ccce1-29a0-44ff-8d89-bc1d983140c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374796495 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.374796495
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.784151577
Short name T91
Test name
Test status
Simulation time 692010902 ps
CPU time 4.13 seconds
Started May 02 12:51:55 PM PDT 24
Finished May 02 12:52:03 PM PDT 24
Peak memory 210444 kb
Host smart-1b530513-e36b-4a53-add7-d240f34e40a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784151577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.784151577
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.430387413
Short name T407
Test name
Test status
Simulation time 3388870020 ps
CPU time 8.99 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:07 PM PDT 24
Peak memory 210360 kb
Host smart-b59c0a84-1fe7-419b-9b5d-a778d5eac6e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430387413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.430387413
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.419080034
Short name T380
Test name
Test status
Simulation time 175070976 ps
CPU time 4.14 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:02 PM PDT 24
Peak memory 210320 kb
Host smart-d742d5d8-6041-4d98-a5c1-735db45798ce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419080034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
419080034
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3569926885
Short name T71
Test name
Test status
Simulation time 1175636243 ps
CPU time 27.2 seconds
Started May 02 12:51:53 PM PDT 24
Finished May 02 12:52:24 PM PDT 24
Peak memory 210540 kb
Host smart-5adb95a7-d7c1-478f-88b3-9b13ee57e807
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569926885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3569926885
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1230974236
Short name T429
Test name
Test status
Simulation time 2126958411 ps
CPU time 16.85 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:14 PM PDT 24
Peak memory 210460 kb
Host smart-d5ec0995-19e1-43d2-8baa-da874ee4a324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230974236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1230974236
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3636990103
Short name T368
Test name
Test status
Simulation time 756099728 ps
CPU time 10.61 seconds
Started May 02 12:51:56 PM PDT 24
Finished May 02 12:52:11 PM PDT 24
Peak memory 218660 kb
Host smart-f6e15710-e5c9-4d49-b337-5cb2b96d1e55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636990103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3636990103
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.828940351
Short name T397
Test name
Test status
Simulation time 223989488 ps
CPU time 5.16 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:19 PM PDT 24
Peak memory 218708 kb
Host smart-7aae8324-4df1-4089-b44f-676d01a13cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828940351 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.828940351
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1821427869
Short name T423
Test name
Test status
Simulation time 1273983515 ps
CPU time 8.21 seconds
Started May 02 12:52:02 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 210364 kb
Host smart-1e3b3915-d727-4f57-938d-25a81101995f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821427869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1821427869
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4220984020
Short name T443
Test name
Test status
Simulation time 34953365453 ps
CPU time 69.17 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:53:16 PM PDT 24
Peak memory 210600 kb
Host smart-289c9e64-2b67-4b0d-8ae2-d33d7d4f218a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220984020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4220984020
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1041454940
Short name T426
Test name
Test status
Simulation time 2699551964 ps
CPU time 11.37 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 210596 kb
Host smart-bc4b0712-59ae-44e0-9ff6-f3be58e08df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041454940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1041454940
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.378926877
Short name T433
Test name
Test status
Simulation time 416478067 ps
CPU time 9.8 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:16 PM PDT 24
Peak memory 218724 kb
Host smart-3406f1e6-8a8b-4b1a-b9c2-41c191fd68bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378926877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.378926877
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1754152454
Short name T118
Test name
Test status
Simulation time 14581035938 ps
CPU time 74.29 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:53:20 PM PDT 24
Peak memory 218740 kb
Host smart-60800817-aea0-4214-81ad-0a90134267e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754152454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1754152454
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4013472738
Short name T386
Test name
Test status
Simulation time 1563417070 ps
CPU time 14.38 seconds
Started May 02 12:52:06 PM PDT 24
Finished May 02 12:52:27 PM PDT 24
Peak memory 214816 kb
Host smart-f294c313-4358-4baf-9ded-37721bcddcc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013472738 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4013472738
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2496971108
Short name T420
Test name
Test status
Simulation time 2655824549 ps
CPU time 35.03 seconds
Started May 02 12:51:58 PM PDT 24
Finished May 02 12:52:38 PM PDT 24
Peak memory 210560 kb
Host smart-66f9407d-3fd5-40e8-9a68-0a559dd1e4ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496971108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2496971108
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2772871697
Short name T399
Test name
Test status
Simulation time 7004656101 ps
CPU time 14.42 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:16 PM PDT 24
Peak memory 210576 kb
Host smart-8cff850a-337a-4ea5-9199-549736db81d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772871697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2772871697
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1947069415
Short name T434
Test name
Test status
Simulation time 441478194 ps
CPU time 8.72 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:11 PM PDT 24
Peak memory 218780 kb
Host smart-7b719d18-33a5-473a-9cd7-fc5dc76678e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947069415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1947069415
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.799510970
Short name T400
Test name
Test status
Simulation time 2451137289 ps
CPU time 48.19 seconds
Started May 02 12:51:59 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 212260 kb
Host smart-57e640a6-ae88-4048-8a37-f18f9a2252c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799510970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.799510970
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4168043551
Short name T384
Test name
Test status
Simulation time 1736843033 ps
CPU time 13.9 seconds
Started May 02 12:52:22 PM PDT 24
Finished May 02 12:52:40 PM PDT 24
Peak memory 218628 kb
Host smart-c108cc21-1536-4b94-a49b-2e075e77eb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168043551 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4168043551
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2129654587
Short name T424
Test name
Test status
Simulation time 334512536 ps
CPU time 6.4 seconds
Started May 02 12:52:06 PM PDT 24
Finished May 02 12:52:20 PM PDT 24
Peak memory 210456 kb
Host smart-30b63ec2-9198-422c-95a8-8f7bcbfd33b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129654587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2129654587
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4003221943
Short name T373
Test name
Test status
Simulation time 788070779 ps
CPU time 18.85 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:35 PM PDT 24
Peak memory 210556 kb
Host smart-9d8d0020-3da3-4a00-b022-c5706cb16b9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003221943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4003221943
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2966730939
Short name T385
Test name
Test status
Simulation time 744646536 ps
CPU time 8.64 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:25 PM PDT 24
Peak memory 210428 kb
Host smart-4f6b6414-c99b-4316-8214-43e1a8c898ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966730939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2966730939
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1418656369
Short name T388
Test name
Test status
Simulation time 6875190373 ps
CPU time 18.06 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:24 PM PDT 24
Peak memory 218836 kb
Host smart-0e35db1d-8937-430c-af76-9e5544fb5f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418656369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1418656369
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1565546865
Short name T421
Test name
Test status
Simulation time 729428013 ps
CPU time 38.57 seconds
Started May 02 12:52:10 PM PDT 24
Finished May 02 12:52:57 PM PDT 24
Peak memory 212372 kb
Host smart-7f4b67d7-a3be-45d3-807c-e18d03329371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565546865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1565546865
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3053745047
Short name T431
Test name
Test status
Simulation time 5521435578 ps
CPU time 12.01 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:28 PM PDT 24
Peak memory 213524 kb
Host smart-5f6b5840-4db4-407d-ba8a-83ed0202188d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053745047 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3053745047
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1520441414
Short name T435
Test name
Test status
Simulation time 12953189371 ps
CPU time 9.62 seconds
Started May 02 12:52:11 PM PDT 24
Finished May 02 12:52:29 PM PDT 24
Peak memory 210652 kb
Host smart-c7f0b823-1bd1-4795-ae7e-02eab582aee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520441414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1520441414
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1878012877
Short name T417
Test name
Test status
Simulation time 1438140982 ps
CPU time 18.85 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:36 PM PDT 24
Peak memory 210516 kb
Host smart-ac901024-fd3e-48c9-a6d4-a1aefd6f4d71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878012877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1878012877
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1799981819
Short name T73
Test name
Test status
Simulation time 90588945 ps
CPU time 5.94 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:22 PM PDT 24
Peak memory 210488 kb
Host smart-48ee75ce-1e18-4cc6-90ab-4c217edd8640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799981819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1799981819
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1881721278
Short name T390
Test name
Test status
Simulation time 426295585 ps
CPU time 7.18 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:24 PM PDT 24
Peak memory 218748 kb
Host smart-80df0ade-274b-440f-a9de-d3326766f6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881721278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1881721278
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.53364108
Short name T116
Test name
Test status
Simulation time 164611905 ps
CPU time 36.23 seconds
Started May 02 12:52:17 PM PDT 24
Finished May 02 12:52:59 PM PDT 24
Peak memory 211344 kb
Host smart-f15f3cd7-db01-44a6-a2c0-49617459aedc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53364108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.53364108
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3919198310
Short name T452
Test name
Test status
Simulation time 437566421 ps
CPU time 7.22 seconds
Started May 02 12:52:05 PM PDT 24
Finished May 02 12:52:19 PM PDT 24
Peak memory 218728 kb
Host smart-6f3ea39a-3ff2-4ee8-9589-e8a8adacb910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919198310 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3919198310
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.41367240
Short name T87
Test name
Test status
Simulation time 6924751048 ps
CPU time 14.09 seconds
Started May 02 12:52:24 PM PDT 24
Finished May 02 12:52:42 PM PDT 24
Peak memory 210540 kb
Host smart-39e4b4bc-ff48-4b9b-aceb-6f52015004ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41367240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.41367240
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.858252949
Short name T109
Test name
Test status
Simulation time 811670456 ps
CPU time 9.5 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:23 PM PDT 24
Peak memory 210560 kb
Host smart-7038c412-f0b8-4699-852d-5b94c41fb5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858252949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.858252949
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2817551746
Short name T392
Test name
Test status
Simulation time 6021040320 ps
CPU time 16.71 seconds
Started May 02 12:52:06 PM PDT 24
Finished May 02 12:52:29 PM PDT 24
Peak memory 218784 kb
Host smart-d3def81b-ca79-4837-ba84-3457dad26f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817551746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2817551746
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3218406377
Short name T58
Test name
Test status
Simulation time 192846935 ps
CPU time 37.13 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:51 PM PDT 24
Peak memory 210456 kb
Host smart-a69d99d3-50e8-442e-9d2f-c105bf6c77b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218406377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3218406377
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1715864406
Short name T376
Test name
Test status
Simulation time 988563989 ps
CPU time 11.01 seconds
Started May 02 12:52:06 PM PDT 24
Finished May 02 12:52:24 PM PDT 24
Peak memory 218688 kb
Host smart-12246849-1436-4354-85cd-63e3fb9d603b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715864406 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1715864406
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1877372395
Short name T92
Test name
Test status
Simulation time 937435302 ps
CPU time 7.33 seconds
Started May 02 12:52:11 PM PDT 24
Finished May 02 12:52:26 PM PDT 24
Peak memory 210440 kb
Host smart-a6e0d65b-e7e9-4458-937a-a52be2d8dc19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877372395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1877372395
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.508222412
Short name T425
Test name
Test status
Simulation time 12093469463 ps
CPU time 94.67 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:53:49 PM PDT 24
Peak memory 210572 kb
Host smart-6cfe937b-1af7-458d-a90f-435f89cc2270
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508222412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.508222412
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1452374970
Short name T382
Test name
Test status
Simulation time 758473534 ps
CPU time 8.59 seconds
Started May 02 12:52:17 PM PDT 24
Finished May 02 12:52:33 PM PDT 24
Peak memory 210424 kb
Host smart-7a5dac8c-2c70-4074-b216-a189fc7a6e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452374970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1452374970
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3939546203
Short name T406
Test name
Test status
Simulation time 1302734010 ps
CPU time 13.43 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:27 PM PDT 24
Peak memory 218664 kb
Host smart-8abed4e2-4a9a-4852-ae20-ea8100b38db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939546203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3939546203
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1295804973
Short name T383
Test name
Test status
Simulation time 2484685870 ps
CPU time 12.2 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:27 PM PDT 24
Peak memory 218644 kb
Host smart-bdf878c0-3c66-446f-99eb-8011b490c558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295804973 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1295804973
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1107792778
Short name T84
Test name
Test status
Simulation time 5486376740 ps
CPU time 10.05 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:26 PM PDT 24
Peak memory 210536 kb
Host smart-2ca452fd-4225-46f3-af42-6d42a9901880
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107792778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1107792778
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1077298404
Short name T74
Test name
Test status
Simulation time 35917776904 ps
CPU time 74.8 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:53:32 PM PDT 24
Peak memory 210640 kb
Host smart-ae7a548f-e23c-4826-8acf-ec5a76687d66
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077298404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1077298404
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.145766475
Short name T110
Test name
Test status
Simulation time 3229217845 ps
CPU time 14.16 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 210544 kb
Host smart-215de12e-e89b-474c-896d-f0e0c234a655
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145766475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.145766475
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1607856556
Short name T381
Test name
Test status
Simulation time 911352013 ps
CPU time 38.52 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:59 PM PDT 24
Peak memory 210432 kb
Host smart-a3944582-aa6c-41eb-9da1-c6bba9b5cedc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607856556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1607856556
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3896178399
Short name T360
Test name
Test status
Simulation time 13848010040 ps
CPU time 16.94 seconds
Started May 02 12:52:06 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 218804 kb
Host smart-0d97aa93-82b1-4616-98a9-eb346b0b1354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896178399 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3896178399
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1141925694
Short name T442
Test name
Test status
Simulation time 89209094 ps
CPU time 4.14 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:20 PM PDT 24
Peak memory 210448 kb
Host smart-caa9fd03-14e8-45f0-85de-8452bd304d50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141925694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1141925694
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2440952759
Short name T89
Test name
Test status
Simulation time 1076600131 ps
CPU time 27.05 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:44 PM PDT 24
Peak memory 218680 kb
Host smart-24d6dddd-95f2-4315-89c7-71da250efb9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440952759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2440952759
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2900461509
Short name T107
Test name
Test status
Simulation time 3973317056 ps
CPU time 11.86 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:28 PM PDT 24
Peak memory 210544 kb
Host smart-e7c0da3a-68da-464f-805a-a4230bb5af1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900461509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2900461509
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.696828232
Short name T455
Test name
Test status
Simulation time 2298560911 ps
CPU time 12.81 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:27 PM PDT 24
Peak memory 218664 kb
Host smart-ed18d4c9-2bed-4e78-bac0-8620fb30590e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696828232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.696828232
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3879993733
Short name T427
Test name
Test status
Simulation time 1338920937 ps
CPU time 74.83 seconds
Started May 02 12:52:10 PM PDT 24
Finished May 02 12:53:33 PM PDT 24
Peak memory 211284 kb
Host smart-69117ecf-a652-4ff4-926e-05805b61fe86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879993733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3879993733
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1301169296
Short name T410
Test name
Test status
Simulation time 344486357 ps
CPU time 6.93 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:22 PM PDT 24
Peak memory 213832 kb
Host smart-77ac68b6-3dc7-4111-b7d7-c2f956cfa61c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301169296 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1301169296
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1383114053
Short name T422
Test name
Test status
Simulation time 334459203 ps
CPU time 5.29 seconds
Started May 02 12:52:18 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 210388 kb
Host smart-9f46bae8-9a42-44af-b3c8-2d7e4339a90f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383114053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1383114053
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3476752831
Short name T409
Test name
Test status
Simulation time 1574711640 ps
CPU time 37.31 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:52 PM PDT 24
Peak memory 210472 kb
Host smart-583eae6a-0f2b-4bf6-a5f2-7249597d32e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476752831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3476752831
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1651530711
Short name T106
Test name
Test status
Simulation time 7995878101 ps
CPU time 15.72 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:31 PM PDT 24
Peak memory 210576 kb
Host smart-fc6c4ffe-5253-47be-93ba-8893581c3185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651530711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1651530711
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3351356904
Short name T378
Test name
Test status
Simulation time 1808020887 ps
CPU time 13.34 seconds
Started May 02 12:52:17 PM PDT 24
Finished May 02 12:52:37 PM PDT 24
Peak memory 218676 kb
Host smart-39e152c6-ca1f-4e83-863d-9885ccf2e5f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351356904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3351356904
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3725914245
Short name T59
Test name
Test status
Simulation time 3588067806 ps
CPU time 77.27 seconds
Started May 02 12:52:17 PM PDT 24
Finished May 02 12:53:41 PM PDT 24
Peak memory 211444 kb
Host smart-1003bfed-dc10-4244-8d45-f003ccc2ff61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725914245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3725914245
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.289307952
Short name T441
Test name
Test status
Simulation time 22154432120 ps
CPU time 14.69 seconds
Started May 02 12:52:11 PM PDT 24
Finished May 02 12:52:34 PM PDT 24
Peak memory 213080 kb
Host smart-c0ca693a-20c7-4cfb-99a5-a0e97121b201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289307952 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.289307952
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3344176739
Short name T361
Test name
Test status
Simulation time 846246472 ps
CPU time 6.8 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:21 PM PDT 24
Peak memory 210432 kb
Host smart-a35d2849-438b-4084-88c7-315641a093b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344176739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3344176739
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1120460455
Short name T439
Test name
Test status
Simulation time 11804060788 ps
CPU time 38.36 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:55 PM PDT 24
Peak memory 210608 kb
Host smart-e9cdc9d3-7369-407a-8e4c-0e6e86751b21
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120460455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1120460455
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.126308099
Short name T78
Test name
Test status
Simulation time 1242380987 ps
CPU time 11.7 seconds
Started May 02 12:52:15 PM PDT 24
Finished May 02 12:52:33 PM PDT 24
Peak memory 210468 kb
Host smart-28cbda8f-5c4e-4320-b4a5-19b9b9ca1d0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126308099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.126308099
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3653883105
Short name T389
Test name
Test status
Simulation time 1749528955 ps
CPU time 16.79 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:31 PM PDT 24
Peak memory 218688 kb
Host smart-babfcd48-4e8a-46f3-aaf1-63458a79f47f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653883105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3653883105
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1940355006
Short name T419
Test name
Test status
Simulation time 324618919 ps
CPU time 36.45 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 210480 kb
Host smart-4f62d5be-4e36-4ce5-be4a-68a3ba0ebf13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940355006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1940355006
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1635615631
Short name T404
Test name
Test status
Simulation time 211613763 ps
CPU time 5.59 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:08 PM PDT 24
Peak memory 210400 kb
Host smart-e69dca9e-07b0-4e3c-8500-0b2a62bbd1d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635615631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1635615631
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2234279927
Short name T445
Test name
Test status
Simulation time 4058328002 ps
CPU time 15.18 seconds
Started May 02 12:51:53 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 210496 kb
Host smart-f6841041-3201-4261-a163-37cc046835d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234279927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2234279927
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.884173849
Short name T395
Test name
Test status
Simulation time 205512056 ps
CPU time 7.45 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:05 PM PDT 24
Peak memory 210444 kb
Host smart-0c325f1a-c704-44fe-aa15-32a35bab5470
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884173849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.884173849
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2987539504
Short name T412
Test name
Test status
Simulation time 5752057554 ps
CPU time 12.45 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:14 PM PDT 24
Peak memory 213428 kb
Host smart-cd81c2e2-efb9-407e-aaa6-b531cde1753c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987539504 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2987539504
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.72379299
Short name T366
Test name
Test status
Simulation time 348326516 ps
CPU time 4.24 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 210408 kb
Host smart-120376b1-5097-4c07-acd6-dd4511c3384b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72379299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.72379299
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3413083370
Short name T391
Test name
Test status
Simulation time 2656761539 ps
CPU time 8.09 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:10 PM PDT 24
Peak memory 210360 kb
Host smart-a74c1d50-4785-4285-8257-f3f80b0e11d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413083370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3413083370
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3381165367
Short name T371
Test name
Test status
Simulation time 637605386 ps
CPU time 4.1 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 210380 kb
Host smart-6acb4cf6-54c7-4b6e-a019-5c5b0afcef24
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381165367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3381165367
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2117344624
Short name T76
Test name
Test status
Simulation time 4809690832 ps
CPU time 44.72 seconds
Started May 02 12:51:55 PM PDT 24
Finished May 02 12:52:44 PM PDT 24
Peak memory 210604 kb
Host smart-c3780757-f924-4165-95a2-2fcc672f08aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117344624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2117344624
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2698158805
Short name T377
Test name
Test status
Simulation time 309937251 ps
CPU time 4.2 seconds
Started May 02 12:51:53 PM PDT 24
Finished May 02 12:52:01 PM PDT 24
Peak memory 210344 kb
Host smart-6bbc35df-7915-4308-b318-f154c613c379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698158805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2698158805
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4104586619
Short name T374
Test name
Test status
Simulation time 10868872138 ps
CPU time 15.22 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 218832 kb
Host smart-8bc9a1fc-09ec-4739-8efb-66bc71ed6758
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104586619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4104586619
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1774733095
Short name T57
Test name
Test status
Simulation time 1144923842 ps
CPU time 36.84 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:44 PM PDT 24
Peak memory 210444 kb
Host smart-2fd7221e-ce6e-49a4-8448-4335bbf9a1de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774733095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1774733095
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.409412529
Short name T86
Test name
Test status
Simulation time 8345018522 ps
CPU time 15.48 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:16 PM PDT 24
Peak memory 210608 kb
Host smart-d76443dc-cc03-46af-bfbc-47bc611c6e6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409412529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.409412529
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.190054074
Short name T440
Test name
Test status
Simulation time 7063152426 ps
CPU time 15.08 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:13 PM PDT 24
Peak memory 210544 kb
Host smart-f11ef4d4-924a-4e2b-8608-0dddb3e85fb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190054074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.190054074
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2367743902
Short name T85
Test name
Test status
Simulation time 7637459627 ps
CPU time 13.51 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:11 PM PDT 24
Peak memory 210588 kb
Host smart-c82e7ded-9ab1-463e-8730-6a83ff80f5b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367743902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2367743902
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1642982200
Short name T436
Test name
Test status
Simulation time 3335250196 ps
CPU time 14.33 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:22 PM PDT 24
Peak memory 218660 kb
Host smart-48603f2a-7c5f-437d-a6c1-8267caa701ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642982200 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1642982200
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.301868035
Short name T396
Test name
Test status
Simulation time 3712950958 ps
CPU time 15.47 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:13 PM PDT 24
Peak memory 210516 kb
Host smart-bade8669-1674-4302-9f06-bb16c3d4c9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301868035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.301868035
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.876479680
Short name T370
Test name
Test status
Simulation time 8345857170 ps
CPU time 15.52 seconds
Started May 02 12:51:56 PM PDT 24
Finished May 02 12:52:15 PM PDT 24
Peak memory 210480 kb
Host smart-194b87ba-e5e5-44c9-a13a-28104c551986
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876479680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.876479680
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3938970798
Short name T405
Test name
Test status
Simulation time 5863198504 ps
CPU time 9.05 seconds
Started May 02 12:51:55 PM PDT 24
Finished May 02 12:52:08 PM PDT 24
Peak memory 210460 kb
Host smart-2b8b1b59-7a3f-4a18-9262-390828a2911e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938970798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3938970798
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4159127697
Short name T447
Test name
Test status
Simulation time 382194722 ps
CPU time 18.8 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 210436 kb
Host smart-b34349c4-37b8-4199-a328-c57100506651
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159127697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4159127697
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.557255858
Short name T379
Test name
Test status
Simulation time 5584517070 ps
CPU time 9.87 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:52:04 PM PDT 24
Peak memory 210572 kb
Host smart-6f857465-67bd-4464-8773-a8bfe108c680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557255858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.557255858
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2259484119
Short name T418
Test name
Test status
Simulation time 3974660147 ps
CPU time 18.71 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 218708 kb
Host smart-8551919a-c32b-4a2a-bb15-650bd15e1bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259484119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2259484119
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1635800744
Short name T125
Test name
Test status
Simulation time 5514462534 ps
CPU time 74.04 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:53:15 PM PDT 24
Peak memory 211776 kb
Host smart-330c6a31-d628-4d5c-b814-c120bd059fad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635800744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1635800744
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.785417028
Short name T96
Test name
Test status
Simulation time 334322682 ps
CPU time 4.09 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:10 PM PDT 24
Peak memory 210452 kb
Host smart-380e37b5-8ed1-4bc9-aeba-006a2e521c44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785417028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.785417028
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3299128125
Short name T416
Test name
Test status
Simulation time 695502132 ps
CPU time 5.28 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:07 PM PDT 24
Peak memory 210460 kb
Host smart-87a70f19-a73a-4bef-b06d-6e7d11a067a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299128125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3299128125
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3473610722
Short name T62
Test name
Test status
Simulation time 216429296 ps
CPU time 7.15 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:15 PM PDT 24
Peak memory 210444 kb
Host smart-9ad0d007-0c5a-4a73-8922-73c2f893d355
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473610722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3473610722
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2546802251
Short name T68
Test name
Test status
Simulation time 199700103 ps
CPU time 4.97 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 218680 kb
Host smart-7285f859-c23a-4f23-888d-d5df5f45c6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546802251 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2546802251
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4036135856
Short name T63
Test name
Test status
Simulation time 3944596076 ps
CPU time 14.98 seconds
Started May 02 12:51:57 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 210552 kb
Host smart-a086e2b8-bb19-4c51-b163-87d82c9d8cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036135856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4036135856
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3887872251
Short name T393
Test name
Test status
Simulation time 554503812 ps
CPU time 4.06 seconds
Started May 02 12:51:55 PM PDT 24
Finished May 02 12:52:03 PM PDT 24
Peak memory 210328 kb
Host smart-88e96429-6c13-4577-8ac2-2cd678b772d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887872251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3887872251
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2229851408
Short name T367
Test name
Test status
Simulation time 1369586467 ps
CPU time 6.25 seconds
Started May 02 12:51:56 PM PDT 24
Finished May 02 12:52:06 PM PDT 24
Peak memory 210412 kb
Host smart-242090c0-af5b-4847-a53d-3cfb3fa04bbd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229851408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2229851408
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3749464342
Short name T454
Test name
Test status
Simulation time 8260546239 ps
CPU time 66.57 seconds
Started May 02 12:51:53 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 210604 kb
Host smart-528a5520-3e7b-48fd-ba31-55f80cd790d0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749464342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3749464342
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3833883760
Short name T414
Test name
Test status
Simulation time 86709602 ps
CPU time 4.23 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:09 PM PDT 24
Peak memory 210456 kb
Host smart-31c702b6-0eee-49d9-9821-5c3bbb09d172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833883760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3833883760
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.687584302
Short name T428
Test name
Test status
Simulation time 3362125384 ps
CPU time 11.91 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:09 PM PDT 24
Peak memory 218724 kb
Host smart-72220e37-df3a-461a-a23b-fd9c32244485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687584302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.687584302
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.909935663
Short name T401
Test name
Test status
Simulation time 436419105 ps
CPU time 37.23 seconds
Started May 02 12:51:56 PM PDT 24
Finished May 02 12:52:37 PM PDT 24
Peak memory 212300 kb
Host smart-66c172fc-4dd0-41bd-9463-edb18560c246
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909935663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.909935663
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3694631002
Short name T450
Test name
Test status
Simulation time 5222225032 ps
CPU time 12.45 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:18 PM PDT 24
Peak memory 218812 kb
Host smart-d49c7011-c8ee-4202-8d38-c9b22282ec33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694631002 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3694631002
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.786390508
Short name T88
Test name
Test status
Simulation time 7797413743 ps
CPU time 15.77 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:21 PM PDT 24
Peak memory 210552 kb
Host smart-53a1cb41-2c5f-4978-9541-411416abd78f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786390508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.786390508
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3733618369
Short name T93
Test name
Test status
Simulation time 23048930559 ps
CPU time 62.26 seconds
Started May 02 12:51:59 PM PDT 24
Finished May 02 12:53:06 PM PDT 24
Peak memory 210628 kb
Host smart-86bd2f93-594f-45db-a130-baa7c213bd4b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733618369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3733618369
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2296785846
Short name T432
Test name
Test status
Simulation time 909379066 ps
CPU time 11.47 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 210496 kb
Host smart-b4cf26ab-202e-48d3-9489-251f199a1ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296785846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2296785846
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3908193231
Short name T394
Test name
Test status
Simulation time 2095842433 ps
CPU time 18.4 seconds
Started May 02 12:51:59 PM PDT 24
Finished May 02 12:52:23 PM PDT 24
Peak memory 218684 kb
Host smart-d737eeb6-a7b0-4461-a1cf-92a1e8992751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908193231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3908193231
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3360576951
Short name T387
Test name
Test status
Simulation time 1309496061 ps
CPU time 41.1 seconds
Started May 02 12:52:05 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 210488 kb
Host smart-4c867079-e7e9-42d7-86a5-5184b91838c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360576951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3360576951
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.357392110
Short name T364
Test name
Test status
Simulation time 678991603 ps
CPU time 8.76 seconds
Started May 02 12:52:08 PM PDT 24
Finished May 02 12:52:24 PM PDT 24
Peak memory 218740 kb
Host smart-22e63927-dd00-487d-b228-bfdc849f5181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357392110 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.357392110
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3120006435
Short name T369
Test name
Test status
Simulation time 675309483 ps
CPU time 8.14 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:23 PM PDT 24
Peak memory 210528 kb
Host smart-bd814330-9e53-4110-acb6-27421421360b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120006435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3120006435
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3304168831
Short name T77
Test name
Test status
Simulation time 16313140906 ps
CPU time 75.94 seconds
Started May 02 12:52:06 PM PDT 24
Finished May 02 12:53:28 PM PDT 24
Peak memory 210620 kb
Host smart-86f4ff41-6aa6-49be-afe1-77a2e123cf73
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304168831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3304168831
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1218065986
Short name T446
Test name
Test status
Simulation time 178712756 ps
CPU time 4.27 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:18 PM PDT 24
Peak memory 210444 kb
Host smart-1833184a-a8b1-47f8-bb80-c30fd695b547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218065986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1218065986
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1723892046
Short name T56
Test name
Test status
Simulation time 3200663566 ps
CPU time 17.9 seconds
Started May 02 12:52:15 PM PDT 24
Finished May 02 12:52:40 PM PDT 24
Peak memory 218832 kb
Host smart-16ec59c4-1807-4d1f-8e93-31a3d4f09340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723892046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1723892046
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3934593902
Short name T123
Test name
Test status
Simulation time 1308088848 ps
CPU time 67.84 seconds
Started May 02 12:51:58 PM PDT 24
Finished May 02 12:53:11 PM PDT 24
Peak memory 211632 kb
Host smart-de774e5d-9e1e-4dea-8ae8-fec0aac18a82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934593902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3934593902
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3463096867
Short name T453
Test name
Test status
Simulation time 4962376147 ps
CPU time 11.96 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:18 PM PDT 24
Peak memory 212348 kb
Host smart-aea1cd52-7f79-4964-8665-13e22ba88f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463096867 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3463096867
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.546604521
Short name T69
Test name
Test status
Simulation time 2371895000 ps
CPU time 11.49 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:18 PM PDT 24
Peak memory 210544 kb
Host smart-edc747a9-ba1a-4f92-9a34-f95f80241f3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546604521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.546604521
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.822335425
Short name T108
Test name
Test status
Simulation time 1246604004 ps
CPU time 12.89 seconds
Started May 02 12:52:03 PM PDT 24
Finished May 02 12:52:23 PM PDT 24
Peak memory 210500 kb
Host smart-b29614dd-7c5d-480b-8ab9-7d78103afe59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822335425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.822335425
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3207882381
Short name T362
Test name
Test status
Simulation time 13906909243 ps
CPU time 18.42 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:24 PM PDT 24
Peak memory 218852 kb
Host smart-e0cff7ae-1689-4c32-b7b0-0f7d60ba054b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207882381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3207882381
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3714627656
Short name T119
Test name
Test status
Simulation time 864053458 ps
CPU time 69.09 seconds
Started May 02 12:52:09 PM PDT 24
Finished May 02 12:53:26 PM PDT 24
Peak memory 210456 kb
Host smart-7c0227c5-569c-4a4c-b549-8a633e6b4356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714627656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3714627656
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.406862639
Short name T437
Test name
Test status
Simulation time 2200604299 ps
CPU time 16.74 seconds
Started May 02 12:52:07 PM PDT 24
Finished May 02 12:52:31 PM PDT 24
Peak memory 218776 kb
Host smart-9eb85cc5-c105-448a-929a-527df8cb4fac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406862639 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.406862639
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2595682789
Short name T94
Test name
Test status
Simulation time 1031787206 ps
CPU time 10.5 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 210408 kb
Host smart-14c5c2c8-db9f-4d1d-9d8e-285a1a868a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595682789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2595682789
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1078134022
Short name T398
Test name
Test status
Simulation time 53320221786 ps
CPU time 104.13 seconds
Started May 02 12:52:02 PM PDT 24
Finished May 02 12:53:52 PM PDT 24
Peak memory 210592 kb
Host smart-6c9ee963-591c-462e-ad7c-4b87a0d49118
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078134022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1078134022
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2995284902
Short name T413
Test name
Test status
Simulation time 472615323 ps
CPU time 7.06 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:14 PM PDT 24
Peak memory 210348 kb
Host smart-997cbc05-2a78-4c9e-b42a-69cec8f03f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995284902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2995284902
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1421553108
Short name T402
Test name
Test status
Simulation time 4833322875 ps
CPU time 13.73 seconds
Started May 02 12:52:06 PM PDT 24
Finished May 02 12:52:26 PM PDT 24
Peak memory 218848 kb
Host smart-15d12e6d-e956-4245-a99f-6247ab79eda6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421553108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1421553108
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2169157530
Short name T122
Test name
Test status
Simulation time 1229446173 ps
CPU time 68.77 seconds
Started May 02 12:51:59 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 211648 kb
Host smart-67edafe1-c23f-4d66-875c-51380eba1121
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169157530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2169157530
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.786755041
Short name T372
Test name
Test status
Simulation time 406997443 ps
CPU time 7.36 seconds
Started May 02 12:52:02 PM PDT 24
Finished May 02 12:52:15 PM PDT 24
Peak memory 218692 kb
Host smart-959496f0-e342-4279-819b-ec379a3509c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786755041 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.786755041
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4189402005
Short name T72
Test name
Test status
Simulation time 334362863 ps
CPU time 4.21 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:52:09 PM PDT 24
Peak memory 210492 kb
Host smart-c5ad728c-c853-45aa-87e9-7b672dc32f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189402005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4189402005
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3235311076
Short name T95
Test name
Test status
Simulation time 7754999297 ps
CPU time 70.85 seconds
Started May 02 12:52:00 PM PDT 24
Finished May 02 12:53:16 PM PDT 24
Peak memory 210596 kb
Host smart-0fc45ed9-bfce-4446-b67e-a6f94956a835
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235311076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3235311076
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3269259535
Short name T430
Test name
Test status
Simulation time 515979776 ps
CPU time 5.03 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 210532 kb
Host smart-9853d93e-b584-49cc-b4ad-eff5ca3a70ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269259535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3269259535
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3088721403
Short name T408
Test name
Test status
Simulation time 5104211501 ps
CPU time 13.12 seconds
Started May 02 12:52:02 PM PDT 24
Finished May 02 12:52:21 PM PDT 24
Peak memory 218812 kb
Host smart-b5da691f-ec93-4538-a30f-b788c8143be0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088721403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3088721403
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2446446057
Short name T121
Test name
Test status
Simulation time 4265075010 ps
CPU time 75.88 seconds
Started May 02 12:52:01 PM PDT 24
Finished May 02 12:53:23 PM PDT 24
Peak memory 212192 kb
Host smart-b6ea876e-4b49-4a15-bf52-e237f3b9a96d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446446057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2446446057
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1142491702
Short name T66
Test name
Test status
Simulation time 1189012256 ps
CPU time 11.88 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:52:32 PM PDT 24
Peak memory 211412 kb
Host smart-70570533-de2e-4c5c-81c9-46762129483c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142491702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1142491702
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1697255000
Short name T282
Test name
Test status
Simulation time 3015620029 ps
CPU time 51.55 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:53:11 PM PDT 24
Peak memory 228048 kb
Host smart-7a07ed86-9941-4cfc-ad8b-a94c45e4dcd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697255000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1697255000
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3247470239
Short name T301
Test name
Test status
Simulation time 12299072988 ps
CPU time 26.72 seconds
Started May 02 12:52:18 PM PDT 24
Finished May 02 12:52:51 PM PDT 24
Peak memory 212340 kb
Host smart-b141435c-5a65-4d47-8e78-31cbada86c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247470239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3247470239
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3664149317
Short name T260
Test name
Test status
Simulation time 94206188 ps
CPU time 5.41 seconds
Started May 02 12:52:17 PM PDT 24
Finished May 02 12:52:29 PM PDT 24
Peak memory 211348 kb
Host smart-68a7a00c-3d73-4e84-a0c1-8070deee0887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664149317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3664149317
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1811272475
Short name T35
Test name
Test status
Simulation time 10484949006 ps
CPU time 103.63 seconds
Started May 02 12:52:14 PM PDT 24
Finished May 02 12:54:05 PM PDT 24
Peak memory 234412 kb
Host smart-771fb687-66c9-469a-961e-d943aef277b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811272475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1811272475
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3685311537
Short name T351
Test name
Test status
Simulation time 3094407364 ps
CPU time 25.16 seconds
Started May 02 12:52:13 PM PDT 24
Finished May 02 12:52:46 PM PDT 24
Peak memory 213792 kb
Host smart-2206d2d5-deb6-4d97-8de7-8c86d88963ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685311537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3685311537
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1240175484
Short name T177
Test name
Test status
Simulation time 12449576811 ps
CPU time 19.59 seconds
Started May 02 12:52:16 PM PDT 24
Finished May 02 12:52:43 PM PDT 24
Peak memory 211992 kb
Host smart-862343fd-d850-4332-bf22-49f6d7f24b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240175484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1240175484
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.627553209
Short name T147
Test name
Test status
Simulation time 85556326 ps
CPU time 4.05 seconds
Started May 02 12:52:21 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 211344 kb
Host smart-2a505320-1c30-462c-accb-66e53e01e1c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627553209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.627553209
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2839314333
Short name T347
Test name
Test status
Simulation time 18442415758 ps
CPU time 219.15 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:55:59 PM PDT 24
Peak memory 225292 kb
Host smart-0a92b3a7-6a9a-4ece-a881-1f8edf278416
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839314333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2839314333
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2749198107
Short name T155
Test name
Test status
Simulation time 3508156209 ps
CPU time 28.57 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:52:48 PM PDT 24
Peak memory 212112 kb
Host smart-58942118-d4f8-4a54-b91b-d08d68d725b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749198107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2749198107
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3807751342
Short name T322
Test name
Test status
Simulation time 8589139474 ps
CPU time 16.07 seconds
Started May 02 12:52:16 PM PDT 24
Finished May 02 12:52:39 PM PDT 24
Peak memory 211352 kb
Host smart-32b14b53-26aa-4944-9e09-9b0a6925ba4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807751342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3807751342
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.21399789
Short name T82
Test name
Test status
Simulation time 10431607281 ps
CPU time 34.79 seconds
Started May 02 12:52:15 PM PDT 24
Finished May 02 12:52:57 PM PDT 24
Peak memory 213924 kb
Host smart-6671a9e4-1ead-448d-945b-147b20f2149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21399789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.21399789
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4064773765
Short name T175
Test name
Test status
Simulation time 7032111767 ps
CPU time 29.3 seconds
Started May 02 12:52:23 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 219564 kb
Host smart-f413d7bb-c202-4700-afb1-e03fde87e392
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064773765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4064773765
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2200320512
Short name T228
Test name
Test status
Simulation time 1934143058 ps
CPU time 115.94 seconds
Started May 02 12:52:32 PM PDT 24
Finished May 02 12:54:31 PM PDT 24
Peak memory 233092 kb
Host smart-524a2cda-42f0-4a07-ad1a-c56ed4aac5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200320512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2200320512
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3602974045
Short name T178
Test name
Test status
Simulation time 2269076127 ps
CPU time 24.08 seconds
Started May 02 12:52:30 PM PDT 24
Finished May 02 12:52:57 PM PDT 24
Peak memory 212128 kb
Host smart-d202e2da-2a7d-4d03-b0c5-78f6cbcdaf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602974045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3602974045
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3199659158
Short name T256
Test name
Test status
Simulation time 1642493517 ps
CPU time 11.89 seconds
Started May 02 12:52:29 PM PDT 24
Finished May 02 12:52:44 PM PDT 24
Peak memory 211336 kb
Host smart-0e6385d8-3ba8-40c9-b4fa-503aacf338da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199659158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3199659158
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.227406823
Short name T200
Test name
Test status
Simulation time 11423278542 ps
CPU time 26.35 seconds
Started May 02 12:52:28 PM PDT 24
Finished May 02 12:52:57 PM PDT 24
Peak memory 214492 kb
Host smart-de9e9888-f7b7-4863-86bf-3e474fd4d006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227406823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.227406823
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3832880458
Short name T315
Test name
Test status
Simulation time 16399044749 ps
CPU time 38.5 seconds
Started May 02 12:52:30 PM PDT 24
Finished May 02 12:53:12 PM PDT 24
Peak memory 219592 kb
Host smart-47b8e1c3-3fec-4990-9648-5ffe1b0bb191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832880458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3832880458
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2958850027
Short name T141
Test name
Test status
Simulation time 1379298765 ps
CPU time 5.65 seconds
Started May 02 12:52:38 PM PDT 24
Finished May 02 12:52:46 PM PDT 24
Peak memory 211368 kb
Host smart-5cc2525c-e42b-4df2-a191-d03a5f7046a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958850027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2958850027
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1049048291
Short name T30
Test name
Test status
Simulation time 94733149669 ps
CPU time 281.34 seconds
Started May 02 12:52:34 PM PDT 24
Finished May 02 12:57:18 PM PDT 24
Peak memory 238080 kb
Host smart-eef37e98-02fe-4326-83a3-07dfcbc0f2f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049048291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1049048291
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1704235297
Short name T295
Test name
Test status
Simulation time 1186246585 ps
CPU time 9.45 seconds
Started May 02 12:52:38 PM PDT 24
Finished May 02 12:52:50 PM PDT 24
Peak memory 212132 kb
Host smart-9bd2a0de-62d1-4935-84eb-88f8ad509b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704235297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1704235297
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.595223056
Short name T179
Test name
Test status
Simulation time 5578489641 ps
CPU time 11.35 seconds
Started May 02 12:52:33 PM PDT 24
Finished May 02 12:52:47 PM PDT 24
Peak memory 211424 kb
Host smart-c08a3801-3937-414b-9894-78b3469e8e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595223056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.595223056
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.816584420
Short name T83
Test name
Test status
Simulation time 5824805435 ps
CPU time 30.02 seconds
Started May 02 12:52:27 PM PDT 24
Finished May 02 12:52:59 PM PDT 24
Peak memory 213648 kb
Host smart-3f58b0b3-4aa1-457d-ac84-9b7b16e08586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816584420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.816584420
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2786958639
Short name T294
Test name
Test status
Simulation time 44804773010 ps
CPU time 39.42 seconds
Started May 02 12:52:29 PM PDT 24
Finished May 02 12:53:11 PM PDT 24
Peak memory 216808 kb
Host smart-7033767c-2313-4aac-bc11-1b79607d0963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786958639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2786958639
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3352646996
Short name T248
Test name
Test status
Simulation time 993820638 ps
CPU time 6 seconds
Started May 02 12:52:28 PM PDT 24
Finished May 02 12:52:36 PM PDT 24
Peak memory 211408 kb
Host smart-3e83d442-a284-4dbd-a4f5-4da5297369c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352646996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3352646996
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.547317806
Short name T133
Test name
Test status
Simulation time 3369830809 ps
CPU time 101.71 seconds
Started May 02 12:52:35 PM PDT 24
Finished May 02 12:54:19 PM PDT 24
Peak memory 225480 kb
Host smart-c37d2cb9-5943-4914-8370-123a8dbc76a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547317806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.547317806
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2991372126
Short name T38
Test name
Test status
Simulation time 959081799 ps
CPU time 10.69 seconds
Started May 02 12:52:33 PM PDT 24
Finished May 02 12:52:47 PM PDT 24
Peak memory 211340 kb
Host smart-df6dd375-73ce-48ae-b6f1-f60326dc31e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991372126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2991372126
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3138969726
Short name T180
Test name
Test status
Simulation time 11651366749 ps
CPU time 30.16 seconds
Started May 02 12:52:30 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 219660 kb
Host smart-c1923b04-49f5-4dad-ab5e-26cfb129a3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138969726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3138969726
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2009647987
Short name T205
Test name
Test status
Simulation time 2189172105 ps
CPU time 16.75 seconds
Started May 02 12:52:33 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 213868 kb
Host smart-598489b8-8da1-4482-9718-c81efeb336cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009647987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2009647987
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.59057767
Short name T287
Test name
Test status
Simulation time 6033873623 ps
CPU time 12.91 seconds
Started May 02 12:52:35 PM PDT 24
Finished May 02 12:52:50 PM PDT 24
Peak memory 211448 kb
Host smart-aaa3522f-b7dc-4520-ace7-f2149405a227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59057767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.59057767
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.393011479
Short name T353
Test name
Test status
Simulation time 15646179834 ps
CPU time 238.34 seconds
Started May 02 12:52:30 PM PDT 24
Finished May 02 12:56:31 PM PDT 24
Peak memory 230472 kb
Host smart-b277c812-74d4-48dd-9031-e80caf9e0a43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393011479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.393011479
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1117781467
Short name T148
Test name
Test status
Simulation time 16346302116 ps
CPU time 19.84 seconds
Started May 02 12:52:33 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 212452 kb
Host smart-2257aa70-d275-45a3-9864-424b55be3d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117781467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1117781467
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2069212923
Short name T201
Test name
Test status
Simulation time 192430411 ps
CPU time 5.3 seconds
Started May 02 12:52:34 PM PDT 24
Finished May 02 12:52:42 PM PDT 24
Peak memory 210548 kb
Host smart-ba463662-a49a-4006-b483-8edde5ebe295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2069212923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2069212923
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2851052525
Short name T330
Test name
Test status
Simulation time 5816555149 ps
CPU time 25.12 seconds
Started May 02 12:52:34 PM PDT 24
Finished May 02 12:53:02 PM PDT 24
Peak memory 219412 kb
Host smart-e7bc2f0e-1fd5-4b8f-980d-425eac5266df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851052525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2851052525
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.192451249
Short name T299
Test name
Test status
Simulation time 476522440 ps
CPU time 11.5 seconds
Started May 02 12:52:31 PM PDT 24
Finished May 02 12:52:45 PM PDT 24
Peak memory 214948 kb
Host smart-3e844227-a1d3-41f3-9dd7-f7e53d983bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192451249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.192451249
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.692905055
Short name T293
Test name
Test status
Simulation time 370581932 ps
CPU time 7.35 seconds
Started May 02 12:52:27 PM PDT 24
Finished May 02 12:52:37 PM PDT 24
Peak memory 211412 kb
Host smart-21ee5c07-ed00-4878-9baa-f2808d5736e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692905055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.692905055
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4034040474
Short name T14
Test name
Test status
Simulation time 213683129776 ps
CPU time 495.92 seconds
Started May 02 12:52:32 PM PDT 24
Finished May 02 01:00:51 PM PDT 24
Peak memory 229276 kb
Host smart-03aac794-8bc9-42a6-bf8f-c710792a5bf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034040474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4034040474
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.484056206
Short name T100
Test name
Test status
Simulation time 620262212 ps
CPU time 9.63 seconds
Started May 02 12:52:28 PM PDT 24
Finished May 02 12:52:41 PM PDT 24
Peak memory 211308 kb
Host smart-31d7eb00-95a1-4182-94ac-37bfb6db5387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484056206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.484056206
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3991818785
Short name T103
Test name
Test status
Simulation time 15180790424 ps
CPU time 32.21 seconds
Started May 02 12:52:32 PM PDT 24
Finished May 02 12:53:07 PM PDT 24
Peak memory 219652 kb
Host smart-3d5ea00c-a66c-48ca-b2d8-a247cab24a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991818785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3991818785
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3886470095
Short name T298
Test name
Test status
Simulation time 24703961516 ps
CPU time 73.26 seconds
Started May 02 12:52:34 PM PDT 24
Finished May 02 12:53:50 PM PDT 24
Peak memory 218760 kb
Host smart-70585522-72b9-4558-bfba-922b79c852dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886470095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3886470095
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1606159347
Short name T54
Test name
Test status
Simulation time 97266087314 ps
CPU time 6522.62 seconds
Started May 02 12:52:33 PM PDT 24
Finished May 02 02:41:19 PM PDT 24
Peak memory 236108 kb
Host smart-714ae7e6-9867-4640-af82-1781db9555a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606159347 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1606159347
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1528210546
Short name T206
Test name
Test status
Simulation time 88325105 ps
CPU time 4.35 seconds
Started May 02 12:52:28 PM PDT 24
Finished May 02 12:52:35 PM PDT 24
Peak memory 211352 kb
Host smart-3bd48d0b-47f3-464c-8a9a-689ea1ab1294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528210546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1528210546
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4059867669
Short name T355
Test name
Test status
Simulation time 20723464161 ps
CPU time 201.73 seconds
Started May 02 12:52:35 PM PDT 24
Finished May 02 12:55:59 PM PDT 24
Peak memory 241300 kb
Host smart-bc0fbfee-f076-4313-93ff-57403513f6ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059867669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4059867669
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.682304204
Short name T314
Test name
Test status
Simulation time 3685855952 ps
CPU time 31.09 seconds
Started May 02 12:52:29 PM PDT 24
Finished May 02 12:53:03 PM PDT 24
Peak memory 211932 kb
Host smart-2ea261ba-b154-4492-ab06-409eedc0e0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682304204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.682304204
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4144245940
Short name T6
Test name
Test status
Simulation time 111148161 ps
CPU time 5.83 seconds
Started May 02 12:52:34 PM PDT 24
Finished May 02 12:52:43 PM PDT 24
Peak memory 211360 kb
Host smart-5c48768e-6e2b-4463-b9e3-ad685f708bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144245940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4144245940
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2675873946
Short name T162
Test name
Test status
Simulation time 7326770616 ps
CPU time 19.48 seconds
Started May 02 12:52:29 PM PDT 24
Finished May 02 12:52:51 PM PDT 24
Peak memory 214276 kb
Host smart-8a31354c-446a-4d23-bede-dbb5d8fa02b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675873946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2675873946
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.567233639
Short name T258
Test name
Test status
Simulation time 804790922 ps
CPU time 13.79 seconds
Started May 02 12:52:29 PM PDT 24
Finished May 02 12:52:45 PM PDT 24
Peak memory 212488 kb
Host smart-c36f951b-dc40-4d8f-a13d-9ca2babc47be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567233639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.567233639
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1123956940
Short name T334
Test name
Test status
Simulation time 1092439653 ps
CPU time 10.56 seconds
Started May 02 12:52:42 PM PDT 24
Finished May 02 12:52:57 PM PDT 24
Peak memory 211308 kb
Host smart-04f61c4b-d959-405d-a4db-50708a533c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123956940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1123956940
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3014407963
Short name T237
Test name
Test status
Simulation time 16929547316 ps
CPU time 73.06 seconds
Started May 02 12:52:39 PM PDT 24
Finished May 02 12:53:54 PM PDT 24
Peak memory 241620 kb
Host smart-0a737a54-ca03-47ae-9a34-754d4d04e4e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014407963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3014407963
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3891760314
Short name T354
Test name
Test status
Simulation time 347877679 ps
CPU time 9.3 seconds
Started May 02 12:52:38 PM PDT 24
Finished May 02 12:52:49 PM PDT 24
Peak memory 211944 kb
Host smart-630c9c43-3a32-41c1-a668-2e314cfd7c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891760314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3891760314
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3465704099
Short name T202
Test name
Test status
Simulation time 2051513671 ps
CPU time 17.63 seconds
Started May 02 12:52:43 PM PDT 24
Finished May 02 12:53:05 PM PDT 24
Peak memory 211344 kb
Host smart-a189b739-4c13-4f4e-920b-60ecd6fac84c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465704099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3465704099
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2953963343
Short name T135
Test name
Test status
Simulation time 3986090186 ps
CPU time 31.24 seconds
Started May 02 12:52:35 PM PDT 24
Finished May 02 12:53:09 PM PDT 24
Peak memory 213388 kb
Host smart-43614d3e-4f2c-41d7-8e1e-aeb900b0c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953963343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2953963343
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1494320873
Short name T292
Test name
Test status
Simulation time 11374142400 ps
CPU time 54.41 seconds
Started May 02 12:52:38 PM PDT 24
Finished May 02 12:53:35 PM PDT 24
Peak memory 219576 kb
Host smart-1cb2214f-353d-4611-b5c1-b1c7544a1c3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494320873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1494320873
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.69274291
Short name T203
Test name
Test status
Simulation time 1493414835 ps
CPU time 12.79 seconds
Started May 02 12:52:37 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 211440 kb
Host smart-ecd15891-e342-482c-9784-13cbd8d46055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69274291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.69274291
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4240034633
Short name T46
Test name
Test status
Simulation time 24218859231 ps
CPU time 261.14 seconds
Started May 02 12:52:37 PM PDT 24
Finished May 02 12:57:01 PM PDT 24
Peak memory 228348 kb
Host smart-66e8d410-e904-4e43-9959-6bc24bd95757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240034633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4240034633
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1061514547
Short name T185
Test name
Test status
Simulation time 3373306935 ps
CPU time 20.46 seconds
Started May 02 12:52:35 PM PDT 24
Finished May 02 12:52:59 PM PDT 24
Peak memory 211552 kb
Host smart-3d911ec4-9dd2-4234-abb8-b5069157681a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061514547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1061514547
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.477091226
Short name T263
Test name
Test status
Simulation time 6413685657 ps
CPU time 13.51 seconds
Started May 02 12:52:40 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 211400 kb
Host smart-c15f5966-4957-4f45-a497-f265c169df6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477091226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.477091226
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.307653783
Short name T186
Test name
Test status
Simulation time 1490983857 ps
CPU time 10.16 seconds
Started May 02 12:52:41 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 219608 kb
Host smart-0d87050a-2d61-4dd7-a2f1-54cd29ae7ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307653783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.307653783
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.163631023
Short name T296
Test name
Test status
Simulation time 2510904423 ps
CPU time 12.17 seconds
Started May 02 12:52:43 PM PDT 24
Finished May 02 12:53:00 PM PDT 24
Peak memory 211472 kb
Host smart-ee707206-43c2-4c8f-aaa8-9585ebd6312a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163631023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.163631023
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2253203570
Short name T113
Test name
Test status
Simulation time 7201201438 ps
CPU time 13.92 seconds
Started May 02 12:52:40 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 211428 kb
Host smart-faf00c1b-50d7-407e-887d-7fc0e3249a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253203570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2253203570
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2371971012
Short name T12
Test name
Test status
Simulation time 9733957848 ps
CPU time 25.53 seconds
Started May 02 12:52:38 PM PDT 24
Finished May 02 12:53:06 PM PDT 24
Peak memory 219536 kb
Host smart-b89cbf38-6ddf-4c57-a221-7ee88741ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371971012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2371971012
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1592789193
Short name T356
Test name
Test status
Simulation time 955660346 ps
CPU time 18.33 seconds
Started May 02 12:52:40 PM PDT 24
Finished May 02 12:53:01 PM PDT 24
Peak memory 214044 kb
Host smart-4a788ae2-9853-4e4b-ab41-e761561ca810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592789193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1592789193
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3610181402
Short name T156
Test name
Test status
Simulation time 257525522 ps
CPU time 6.06 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 211388 kb
Host smart-b2524bcb-84d1-4fe0-b2e9-f7b5992bbb0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610181402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3610181402
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2957375416
Short name T242
Test name
Test status
Simulation time 80397655059 ps
CPU time 214.12 seconds
Started May 02 12:52:36 PM PDT 24
Finished May 02 12:56:13 PM PDT 24
Peak memory 238328 kb
Host smart-c32d244e-1a48-4ab4-a94e-24a13268f578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957375416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2957375416
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1926900112
Short name T165
Test name
Test status
Simulation time 660562800 ps
CPU time 14.04 seconds
Started May 02 12:52:36 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 211456 kb
Host smart-25c09059-b8da-4fd3-bc88-4d07c057bd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926900112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1926900112
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3573692809
Short name T335
Test name
Test status
Simulation time 4126654877 ps
CPU time 10.78 seconds
Started May 02 12:52:38 PM PDT 24
Finished May 02 12:52:52 PM PDT 24
Peak memory 211444 kb
Host smart-01260d69-52d0-4afb-9f1e-d6cc97531e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573692809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3573692809
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2848821770
Short name T268
Test name
Test status
Simulation time 37276372688 ps
CPU time 30.31 seconds
Started May 02 12:52:41 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 214100 kb
Host smart-a237b3cd-5376-4d3c-b7bd-dc14dc0407f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848821770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2848821770
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2200344316
Short name T311
Test name
Test status
Simulation time 29565219246 ps
CPU time 68.35 seconds
Started May 02 12:52:41 PM PDT 24
Finished May 02 12:53:52 PM PDT 24
Peak memory 216440 kb
Host smart-3b67ba0a-f6c9-4b28-ad88-b39a60a6eb05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200344316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2200344316
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3188264093
Short name T64
Test name
Test status
Simulation time 8333615755 ps
CPU time 16.74 seconds
Started May 02 12:52:13 PM PDT 24
Finished May 02 12:52:37 PM PDT 24
Peak memory 211428 kb
Host smart-6e979d03-2b1c-4d1c-a505-4539388b124a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188264093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3188264093
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4029740234
Short name T279
Test name
Test status
Simulation time 692203287 ps
CPU time 9.52 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 212032 kb
Host smart-576a8278-dffa-4c31-9089-a1169a9575fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029740234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4029740234
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3237090355
Short name T308
Test name
Test status
Simulation time 5347020734 ps
CPU time 12.9 seconds
Started May 02 12:52:13 PM PDT 24
Finished May 02 12:52:34 PM PDT 24
Peak memory 211400 kb
Host smart-886292bc-9cf3-4d7e-be57-309a88278ee4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237090355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3237090355
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3740948975
Short name T36
Test name
Test status
Simulation time 847083638 ps
CPU time 98.49 seconds
Started May 02 12:52:14 PM PDT 24
Finished May 02 12:54:00 PM PDT 24
Peak memory 233032 kb
Host smart-0c432d26-af57-4c95-89e8-e89b698c5cd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740948975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3740948975
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1316700016
Short name T15
Test name
Test status
Simulation time 673308374 ps
CPU time 15.29 seconds
Started May 02 12:52:18 PM PDT 24
Finished May 02 12:52:40 PM PDT 24
Peak memory 213348 kb
Host smart-a7a11be3-9fb4-41c8-9b12-c999656ca591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316700016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1316700016
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1170475880
Short name T329
Test name
Test status
Simulation time 12928342827 ps
CPU time 52.38 seconds
Started May 02 12:52:18 PM PDT 24
Finished May 02 12:53:16 PM PDT 24
Peak memory 219544 kb
Host smart-6fbcee29-8a46-42fd-9809-0af14fb72a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170475880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1170475880
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2564119644
Short name T269
Test name
Test status
Simulation time 5221764775 ps
CPU time 16.79 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:53:08 PM PDT 24
Peak memory 211480 kb
Host smart-84cc19ad-7ef2-4738-a489-87cdab548732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564119644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2564119644
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.660305184
Short name T274
Test name
Test status
Simulation time 39031907718 ps
CPU time 352.81 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:58:43 PM PDT 24
Peak memory 238064 kb
Host smart-87dc7811-d0e3-4a26-8955-e39a890c999d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660305184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.660305184
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.535863143
Short name T209
Test name
Test status
Simulation time 666468982 ps
CPU time 9.73 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:53:00 PM PDT 24
Peak memory 211952 kb
Host smart-19c7a07e-e1c1-452a-9f52-07be40c95f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535863143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.535863143
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.900293777
Short name T346
Test name
Test status
Simulation time 5622155354 ps
CPU time 14 seconds
Started May 02 12:52:48 PM PDT 24
Finished May 02 12:53:07 PM PDT 24
Peak memory 211420 kb
Host smart-a05abde9-b58a-4446-b907-c71b1a458388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900293777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.900293777
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4236959728
Short name T281
Test name
Test status
Simulation time 3373527312 ps
CPU time 28.64 seconds
Started May 02 12:52:44 PM PDT 24
Finished May 02 12:53:17 PM PDT 24
Peak memory 219672 kb
Host smart-61f18fed-c4dc-4493-a15d-bcd5c4c79dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236959728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4236959728
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.814934514
Short name T158
Test name
Test status
Simulation time 273403065 ps
CPU time 15.67 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:53:07 PM PDT 24
Peak memory 213404 kb
Host smart-f9e62fcd-56dd-4751-ad4b-e65ccf6f068f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814934514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.814934514
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1773031194
Short name T160
Test name
Test status
Simulation time 1534378757 ps
CPU time 13.21 seconds
Started May 02 12:52:47 PM PDT 24
Finished May 02 12:53:05 PM PDT 24
Peak memory 211392 kb
Host smart-9b6d3df7-d82e-4c1e-96e3-142453d7fe3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773031194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1773031194
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.594307876
Short name T348
Test name
Test status
Simulation time 49972486930 ps
CPU time 178.45 seconds
Started May 02 12:52:47 PM PDT 24
Finished May 02 12:55:50 PM PDT 24
Peak memory 219836 kb
Host smart-e134b905-b6bf-446d-a04d-c72340ce972d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594307876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.594307876
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1538000087
Short name T140
Test name
Test status
Simulation time 5804211987 ps
CPU time 21.26 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:53:13 PM PDT 24
Peak memory 212552 kb
Host smart-ce136a62-0cc4-4216-83a6-1c26140ed8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538000087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1538000087
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.552494246
Short name T265
Test name
Test status
Simulation time 1225282158 ps
CPU time 12.77 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 211408 kb
Host smart-9e1edf28-61bf-4201-a1bb-202342b3b304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552494246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.552494246
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2419133921
Short name T227
Test name
Test status
Simulation time 952676915 ps
CPU time 9.88 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:53:01 PM PDT 24
Peak memory 213612 kb
Host smart-88c1c5ef-b626-4792-846e-5833a4858fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419133921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2419133921
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3669435451
Short name T61
Test name
Test status
Simulation time 27876192038 ps
CPU time 78 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:54:08 PM PDT 24
Peak memory 219576 kb
Host smart-6cefbdbb-9954-4831-8a84-579409d7462f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669435451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3669435451
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.100566801
Short name T18
Test name
Test status
Simulation time 1269194541 ps
CPU time 11.8 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:53:03 PM PDT 24
Peak memory 211372 kb
Host smart-b86478f7-2476-414f-a646-246b4572759a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100566801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.100566801
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.490739177
Short name T208
Test name
Test status
Simulation time 44657095072 ps
CPU time 132.97 seconds
Started May 02 12:52:43 PM PDT 24
Finished May 02 12:55:01 PM PDT 24
Peak memory 232596 kb
Host smart-c4b237da-574c-4cea-8781-f6f3a7e929fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490739177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.490739177
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.142849521
Short name T316
Test name
Test status
Simulation time 2596404820 ps
CPU time 24.18 seconds
Started May 02 12:52:49 PM PDT 24
Finished May 02 12:53:18 PM PDT 24
Peak memory 212688 kb
Host smart-15355bc6-ee49-4e56-8f76-eed32490a7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142849521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.142849521
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2413986180
Short name T17
Test name
Test status
Simulation time 97655411 ps
CPU time 5.3 seconds
Started May 02 12:52:47 PM PDT 24
Finished May 02 12:52:57 PM PDT 24
Peak memory 211380 kb
Host smart-2f60a194-7bcc-46a8-9dca-3e2e3f511cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413986180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2413986180
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1564489277
Short name T127
Test name
Test status
Simulation time 2704082349 ps
CPU time 25.68 seconds
Started May 02 12:52:44 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 213388 kb
Host smart-f0d102eb-0d03-4f3d-8416-46bc918d88c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564489277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1564489277
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2597905850
Short name T339
Test name
Test status
Simulation time 20589379319 ps
CPU time 18.21 seconds
Started May 02 12:52:43 PM PDT 24
Finished May 02 12:53:06 PM PDT 24
Peak memory 211400 kb
Host smart-c67baf58-0f84-4fd1-99ef-e5426de61457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597905850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2597905850
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3236305291
Short name T278
Test name
Test status
Simulation time 1316672912 ps
CPU time 12.11 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:53:03 PM PDT 24
Peak memory 211392 kb
Host smart-589a6634-283b-4e57-82d6-2f4905972a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236305291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3236305291
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3031845641
Short name T192
Test name
Test status
Simulation time 23806388879 ps
CPU time 209.56 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:56:21 PM PDT 24
Peak memory 225648 kb
Host smart-34e0fa4e-fd80-4dca-8bf1-b5a9c412beeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031845641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3031845641
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.568812397
Short name T27
Test name
Test status
Simulation time 28491479849 ps
CPU time 33.49 seconds
Started May 02 12:52:47 PM PDT 24
Finished May 02 12:53:25 PM PDT 24
Peak memory 219612 kb
Host smart-83248f45-f54f-4688-917c-3e92638658a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568812397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.568812397
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3675952389
Short name T149
Test name
Test status
Simulation time 1733271959 ps
CPU time 14.48 seconds
Started May 02 12:52:43 PM PDT 24
Finished May 02 12:53:02 PM PDT 24
Peak memory 211324 kb
Host smart-1df2ef6a-1aa8-47c3-a078-42baf0d77a25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675952389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3675952389
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.506574894
Short name T81
Test name
Test status
Simulation time 6562048155 ps
CPU time 33.22 seconds
Started May 02 12:52:50 PM PDT 24
Finished May 02 12:53:28 PM PDT 24
Peak memory 214008 kb
Host smart-87b71390-abd2-4239-9c46-be852c50b37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506574894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.506574894
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2223234164
Short name T345
Test name
Test status
Simulation time 4679602609 ps
CPU time 56.32 seconds
Started May 02 12:52:54 PM PDT 24
Finished May 02 12:53:55 PM PDT 24
Peak memory 213652 kb
Host smart-76d685e9-d784-456a-9c52-79eae6537f06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223234164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2223234164
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.983667272
Short name T67
Test name
Test status
Simulation time 33865441962 ps
CPU time 14.75 seconds
Started May 02 12:52:44 PM PDT 24
Finished May 02 12:53:03 PM PDT 24
Peak memory 211404 kb
Host smart-32a28126-b6f7-4e3f-ba6a-7dd80f2a84a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983667272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.983667272
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4110784056
Short name T264
Test name
Test status
Simulation time 26551860276 ps
CPU time 249.66 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:57:01 PM PDT 24
Peak memory 212572 kb
Host smart-401c6997-5bc1-4d57-918a-7c9b5dea90b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110784056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4110784056
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.309441289
Short name T276
Test name
Test status
Simulation time 175894242 ps
CPU time 9.53 seconds
Started May 02 12:52:49 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 212188 kb
Host smart-a2c81760-3b29-4f4e-9d68-bed85decfc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309441289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.309441289
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3865996916
Short name T349
Test name
Test status
Simulation time 7937104847 ps
CPU time 16.32 seconds
Started May 02 12:52:47 PM PDT 24
Finished May 02 12:53:09 PM PDT 24
Peak memory 211388 kb
Host smart-d8d29915-14ff-412f-b704-06d838df8674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865996916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3865996916
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1521130600
Short name T151
Test name
Test status
Simulation time 42319563003 ps
CPU time 25.19 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:53:15 PM PDT 24
Peak memory 219660 kb
Host smart-146af34a-7461-4383-aa98-1a37ae6055b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521130600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1521130600
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4215341224
Short name T142
Test name
Test status
Simulation time 3225190573 ps
CPU time 14.77 seconds
Started May 02 12:52:44 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 211320 kb
Host smart-1123419f-1e4d-4f79-9c6b-50a7a4d9d9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215341224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4215341224
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3863308695
Short name T55
Test name
Test status
Simulation time 38598706457 ps
CPU time 1525.06 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 01:18:15 PM PDT 24
Peak memory 236292 kb
Host smart-489ebe24-c9ac-432f-9e63-3c5c4b57714b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863308695 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3863308695
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1682138679
Short name T215
Test name
Test status
Simulation time 2016772053 ps
CPU time 16.26 seconds
Started May 02 12:52:49 PM PDT 24
Finished May 02 12:53:10 PM PDT 24
Peak memory 211416 kb
Host smart-dca2f830-eb99-446c-8bec-756ab4ba5a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682138679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1682138679
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.917737193
Short name T47
Test name
Test status
Simulation time 21344119435 ps
CPU time 206.71 seconds
Started May 02 12:52:47 PM PDT 24
Finished May 02 12:56:19 PM PDT 24
Peak memory 224888 kb
Host smart-8d86e282-50f4-4fcb-aa21-971b9e17027d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917737193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.917737193
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2879151798
Short name T196
Test name
Test status
Simulation time 8911402500 ps
CPU time 22.12 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:53:13 PM PDT 24
Peak memory 212568 kb
Host smart-ce34dff6-9c8a-432f-b4d1-9da4b381140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879151798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2879151798
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1133744750
Short name T220
Test name
Test status
Simulation time 3591549477 ps
CPU time 10.41 seconds
Started May 02 12:52:44 PM PDT 24
Finished May 02 12:53:00 PM PDT 24
Peak memory 211296 kb
Host smart-17651682-0ffe-4a3e-a339-165794ddcf7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1133744750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1133744750
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3377991666
Short name T197
Test name
Test status
Simulation time 7577085473 ps
CPU time 36.57 seconds
Started May 02 12:52:46 PM PDT 24
Finished May 02 12:53:28 PM PDT 24
Peak memory 219624 kb
Host smart-e41486c3-80cc-432a-9d9a-495f3c721d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377991666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3377991666
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1505216897
Short name T313
Test name
Test status
Simulation time 1072010859 ps
CPU time 23.09 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:53:13 PM PDT 24
Peak memory 214308 kb
Host smart-e35f7ac0-6e45-45e8-aada-8f5fd7eb8d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505216897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1505216897
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1227022269
Short name T284
Test name
Test status
Simulation time 1523985090 ps
CPU time 13.26 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:11 PM PDT 24
Peak memory 211416 kb
Host smart-97b2c25f-a332-4b27-a74c-e64cea7a28ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227022269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1227022269
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3749139839
Short name T101
Test name
Test status
Simulation time 5454073982 ps
CPU time 74.62 seconds
Started May 02 12:52:50 PM PDT 24
Finished May 02 12:54:09 PM PDT 24
Peak memory 229464 kb
Host smart-9905a3e8-224f-4857-86d7-14fc848e4287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749139839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3749139839
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2948431640
Short name T187
Test name
Test status
Simulation time 17190060643 ps
CPU time 29.58 seconds
Started May 02 12:52:52 PM PDT 24
Finished May 02 12:53:26 PM PDT 24
Peak memory 212760 kb
Host smart-eff7c4cd-bc60-493e-94fc-b68dc2f8724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948431640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2948431640
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3050367074
Short name T99
Test name
Test status
Simulation time 357628582 ps
CPU time 7.8 seconds
Started May 02 12:52:43 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 211356 kb
Host smart-66b7945d-abb2-455f-a061-72849993a6e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050367074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3050367074
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2222605096
Short name T225
Test name
Test status
Simulation time 1844968447 ps
CPU time 24.15 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 214024 kb
Host smart-750c545a-2f66-4651-85d4-1317d1e4c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222605096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2222605096
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2931111070
Short name T286
Test name
Test status
Simulation time 75983337876 ps
CPU time 93.9 seconds
Started May 02 12:52:45 PM PDT 24
Finished May 02 12:54:23 PM PDT 24
Peak memory 217084 kb
Host smart-47dd043c-def1-4109-940a-66ce5d0a5aef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931111070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2931111070
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.95390291
Short name T37
Test name
Test status
Simulation time 89081320 ps
CPU time 4.15 seconds
Started May 02 12:52:51 PM PDT 24
Finished May 02 12:53:00 PM PDT 24
Peak memory 211372 kb
Host smart-7b18b930-1442-4b45-9077-3101e469a754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95390291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.95390291
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.728319001
Short name T191
Test name
Test status
Simulation time 91098649685 ps
CPU time 265.74 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:57:27 PM PDT 24
Peak memory 232960 kb
Host smart-1f7788fe-8e1e-4924-b912-1901dc5e4407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728319001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.728319001
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.554106316
Short name T324
Test name
Test status
Simulation time 2397446215 ps
CPU time 23.78 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:25 PM PDT 24
Peak memory 212200 kb
Host smart-880d6d20-80aa-41ee-bdd7-031d1530bc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554106316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.554106316
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1072509848
Short name T195
Test name
Test status
Simulation time 1706503837 ps
CPU time 10.31 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:09 PM PDT 24
Peak memory 211380 kb
Host smart-5a194825-438a-44cf-93e5-45e96211129c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072509848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1072509848
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3908227890
Short name T11
Test name
Test status
Simulation time 979738838 ps
CPU time 16.14 seconds
Started May 02 12:52:54 PM PDT 24
Finished May 02 12:53:16 PM PDT 24
Peak memory 213508 kb
Host smart-062e24bf-a41f-4303-b25f-05d5f107e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908227890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3908227890
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1893273898
Short name T240
Test name
Test status
Simulation time 11541958942 ps
CPU time 21.9 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:23 PM PDT 24
Peak memory 211312 kb
Host smart-f3e0c560-0287-47ca-966d-7bdd65ab9374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893273898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1893273898
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3713441621
Short name T168
Test name
Test status
Simulation time 1322021724 ps
CPU time 11.95 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:10 PM PDT 24
Peak memory 211428 kb
Host smart-c1c106f7-0183-4fc1-a8c3-706ca48a5bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713441621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3713441621
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4276669697
Short name T199
Test name
Test status
Simulation time 177860688770 ps
CPU time 362.28 seconds
Started May 02 12:52:52 PM PDT 24
Finished May 02 12:58:58 PM PDT 24
Peak memory 224916 kb
Host smart-bb2cbdab-b3c6-4c7a-b1d1-cd3600bf24bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276669697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4276669697
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2024079937
Short name T176
Test name
Test status
Simulation time 192130701 ps
CPU time 5.67 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 211348 kb
Host smart-a85a689f-0e55-4ef1-8576-2d6b70433cf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024079937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2024079937
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.848689161
Short name T338
Test name
Test status
Simulation time 15499595101 ps
CPU time 25.69 seconds
Started May 02 12:52:54 PM PDT 24
Finished May 02 12:53:25 PM PDT 24
Peak memory 219568 kb
Host smart-ea9572d2-ff7a-41ab-9ead-51f21d206408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848689161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.848689161
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3063017645
Short name T312
Test name
Test status
Simulation time 2953819920 ps
CPU time 16.31 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 211256 kb
Host smart-95940d4a-48c7-47af-b136-58e191b72d33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063017645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3063017645
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2866988698
Short name T153
Test name
Test status
Simulation time 2799142560 ps
CPU time 9.18 seconds
Started May 02 12:52:55 PM PDT 24
Finished May 02 12:53:10 PM PDT 24
Peak memory 211480 kb
Host smart-a1238356-889f-4405-bc03-2b266ce5884f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866988698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2866988698
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.160223436
Short name T24
Test name
Test status
Simulation time 56114340388 ps
CPU time 356.78 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:58:58 PM PDT 24
Peak memory 236992 kb
Host smart-fa146497-78b1-427c-9840-70ba7b1857ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160223436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.160223436
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3730882686
Short name T105
Test name
Test status
Simulation time 4032014347 ps
CPU time 32.42 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:31 PM PDT 24
Peak memory 212152 kb
Host smart-8c057459-9b34-4262-9f36-a747a29efd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730882686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3730882686
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.448790046
Short name T181
Test name
Test status
Simulation time 3164125041 ps
CPU time 14.1 seconds
Started May 02 12:52:55 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 211300 kb
Host smart-7b1b1b11-326c-46c9-b4d0-337204141603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448790046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.448790046
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2185154708
Short name T233
Test name
Test status
Simulation time 186535432 ps
CPU time 10.04 seconds
Started May 02 12:52:55 PM PDT 24
Finished May 02 12:53:11 PM PDT 24
Peak memory 213012 kb
Host smart-9f912432-860a-4e72-9aaf-5a7d1c7b414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185154708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2185154708
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3501990181
Short name T98
Test name
Test status
Simulation time 380355846 ps
CPU time 20.2 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:18 PM PDT 24
Peak memory 215200 kb
Host smart-88ff58c7-2257-4046-a483-3125d21e7443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501990181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3501990181
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.529107370
Short name T306
Test name
Test status
Simulation time 5882859097 ps
CPU time 12.29 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:52:32 PM PDT 24
Peak memory 211468 kb
Host smart-0419d155-7c72-4098-b75e-df7e83e1c0ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529107370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.529107370
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4182828959
Short name T317
Test name
Test status
Simulation time 212592304877 ps
CPU time 312.86 seconds
Started May 02 12:52:14 PM PDT 24
Finished May 02 12:57:34 PM PDT 24
Peak memory 244136 kb
Host smart-cc3a4b61-3472-4237-8124-4b56d82707dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182828959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4182828959
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2735799958
Short name T139
Test name
Test status
Simulation time 4455921994 ps
CPU time 35.48 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 212272 kb
Host smart-2a0d8c8e-a52f-43d5-a51f-be301871fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735799958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2735799958
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1308290052
Short name T342
Test name
Test status
Simulation time 2181535004 ps
CPU time 9.13 seconds
Started May 02 12:52:25 PM PDT 24
Finished May 02 12:52:37 PM PDT 24
Peak memory 211380 kb
Host smart-18da841d-6898-45ef-9a17-5221731edcaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308290052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1308290052
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3186581039
Short name T33
Test name
Test status
Simulation time 4544800908 ps
CPU time 104.84 seconds
Started May 02 12:52:14 PM PDT 24
Finished May 02 12:54:06 PM PDT 24
Peak memory 234356 kb
Host smart-b361537a-4d87-40bc-8212-167ee313c444
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186581039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3186581039
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3923464915
Short name T43
Test name
Test status
Simulation time 54076188536 ps
CPU time 31.39 seconds
Started May 02 12:52:18 PM PDT 24
Finished May 02 12:52:55 PM PDT 24
Peak memory 219640 kb
Host smart-238d6c50-f692-471b-a40d-3e693579cf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923464915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3923464915
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1939418706
Short name T277
Test name
Test status
Simulation time 991360941 ps
CPU time 25.04 seconds
Started May 02 12:52:13 PM PDT 24
Finished May 02 12:52:46 PM PDT 24
Peak memory 215640 kb
Host smart-7d5a6b2f-87ea-4e49-b3b3-b55af7ef6e97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939418706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1939418706
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1720187621
Short name T241
Test name
Test status
Simulation time 827680168 ps
CPU time 9.39 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:10 PM PDT 24
Peak memory 211408 kb
Host smart-44ae419b-fb2e-477b-9352-0bf7f26c106f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720187621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1720187621
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1470039029
Short name T305
Test name
Test status
Simulation time 5265650800 ps
CPU time 84.41 seconds
Started May 02 12:52:51 PM PDT 24
Finished May 02 12:54:20 PM PDT 24
Peak memory 220640 kb
Host smart-9d1ab986-c7fc-49b9-9860-78bbe2c75ca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470039029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1470039029
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.980632314
Short name T173
Test name
Test status
Simulation time 2710753494 ps
CPU time 25.44 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:27 PM PDT 24
Peak memory 211944 kb
Host smart-c474a9a7-1c17-4d83-8e7d-c5ec4a1c4410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980632314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.980632314
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2214225490
Short name T45
Test name
Test status
Simulation time 188797317 ps
CPU time 5.26 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 211348 kb
Host smart-0060f7f2-0f1d-4443-b5f6-cd562023ac46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214225490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2214225490
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2477710007
Short name T137
Test name
Test status
Simulation time 2243898715 ps
CPU time 16.91 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:18 PM PDT 24
Peak memory 219616 kb
Host smart-711a4c2c-52ce-42fa-b702-e3b750101715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477710007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2477710007
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2320167955
Short name T224
Test name
Test status
Simulation time 3185804237 ps
CPU time 37.22 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:39 PM PDT 24
Peak memory 219528 kb
Host smart-1d0f8583-debe-4918-9267-00d1ce047d90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320167955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2320167955
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1325927461
Short name T283
Test name
Test status
Simulation time 346003601 ps
CPU time 6.64 seconds
Started May 02 12:52:55 PM PDT 24
Finished May 02 12:53:07 PM PDT 24
Peak memory 211412 kb
Host smart-aae54cec-9f96-4187-80d7-6c5200cc0a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325927461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1325927461
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1034563263
Short name T303
Test name
Test status
Simulation time 4124188510 ps
CPU time 168.95 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:55:50 PM PDT 24
Peak memory 231248 kb
Host smart-1def5642-8561-42a9-990f-5ae38e0ff8a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034563263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1034563263
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3564920365
Short name T221
Test name
Test status
Simulation time 1835306455 ps
CPU time 20.61 seconds
Started May 02 12:52:52 PM PDT 24
Finished May 02 12:53:17 PM PDT 24
Peak memory 212044 kb
Host smart-621d8bbe-4958-4179-a371-91725b6da952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564920365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3564920365
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3875154453
Short name T150
Test name
Test status
Simulation time 193992036 ps
CPU time 5.76 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:04 PM PDT 24
Peak memory 211352 kb
Host smart-78466ddb-a098-457a-b700-4c61b8adefa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875154453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3875154453
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2248268344
Short name T171
Test name
Test status
Simulation time 356947612 ps
CPU time 12.94 seconds
Started May 02 12:52:55 PM PDT 24
Finished May 02 12:53:13 PM PDT 24
Peak memory 212792 kb
Host smart-38f4c561-2b25-427f-9c57-7fde41e98a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248268344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2248268344
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2953373115
Short name T271
Test name
Test status
Simulation time 35335930405 ps
CPU time 78.2 seconds
Started May 02 12:52:54 PM PDT 24
Finished May 02 12:54:18 PM PDT 24
Peak memory 219620 kb
Host smart-70d60d06-1946-4386-88f0-06963f665289
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953373115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2953373115
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1275023583
Short name T157
Test name
Test status
Simulation time 10271774807 ps
CPU time 15.88 seconds
Started May 02 12:53:02 PM PDT 24
Finished May 02 12:53:22 PM PDT 24
Peak memory 211500 kb
Host smart-65573d7c-2063-493a-87b6-3f21c6c142e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275023583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1275023583
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3027001513
Short name T337
Test name
Test status
Simulation time 2828779273 ps
CPU time 49.84 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:51 PM PDT 24
Peak memory 228180 kb
Host smart-1d91ed3e-cd3f-4260-9d55-7179cabe75e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027001513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3027001513
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2164269373
Short name T226
Test name
Test status
Simulation time 11107850959 ps
CPU time 31.36 seconds
Started May 02 12:52:56 PM PDT 24
Finished May 02 12:53:32 PM PDT 24
Peak memory 212412 kb
Host smart-3ff5514b-3394-4836-9017-10e5ef073424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164269373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2164269373
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2040874327
Short name T194
Test name
Test status
Simulation time 1637582231 ps
CPU time 8.62 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:07 PM PDT 24
Peak memory 211304 kb
Host smart-ced67e15-b4b8-46bf-88fb-09ec59224ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040874327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2040874327
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3042112717
Short name T261
Test name
Test status
Simulation time 3833132092 ps
CPU time 27.66 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:26 PM PDT 24
Peak memory 213216 kb
Host smart-4bab35c0-0793-4825-b993-30325a1934c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042112717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3042112717
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3626956470
Short name T169
Test name
Test status
Simulation time 15731884340 ps
CPU time 63.91 seconds
Started May 02 12:52:54 PM PDT 24
Finished May 02 12:54:03 PM PDT 24
Peak memory 219600 kb
Host smart-9e4452c5-f10a-4d22-b28f-a704ed7714c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626956470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3626956470
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1419802468
Short name T52
Test name
Test status
Simulation time 21731802922 ps
CPU time 1268.78 seconds
Started May 02 12:52:54 PM PDT 24
Finished May 02 01:14:08 PM PDT 24
Peak memory 235584 kb
Host smart-2b371fec-0e75-4a4d-8117-07dccae1af62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419802468 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1419802468
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.812461343
Short name T267
Test name
Test status
Simulation time 1399232336 ps
CPU time 12.35 seconds
Started May 02 12:53:00 PM PDT 24
Finished May 02 12:53:17 PM PDT 24
Peak memory 211336 kb
Host smart-d9356492-8a20-4afa-93ff-32202ef056d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812461343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.812461343
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.211601164
Short name T244
Test name
Test status
Simulation time 85248062000 ps
CPU time 450.16 seconds
Started May 02 12:52:55 PM PDT 24
Finished May 02 01:00:31 PM PDT 24
Peak memory 237000 kb
Host smart-64c28128-379d-448b-a41f-2bae1fdba540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211601164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.211601164
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4233956681
Short name T245
Test name
Test status
Simulation time 4318237528 ps
CPU time 32.06 seconds
Started May 02 12:52:52 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 214576 kb
Host smart-83805089-044f-4a77-8eb0-a53af130ac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233956681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4233956681
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.307802872
Short name T112
Test name
Test status
Simulation time 15955035017 ps
CPU time 16.91 seconds
Started May 02 12:52:53 PM PDT 24
Finished May 02 12:53:15 PM PDT 24
Peak memory 211408 kb
Host smart-56430b32-3301-42ca-9152-1487261f217e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307802872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.307802872
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2349142077
Short name T249
Test name
Test status
Simulation time 15507441587 ps
CPU time 33.84 seconds
Started May 02 12:52:54 PM PDT 24
Finished May 02 12:53:33 PM PDT 24
Peak memory 219620 kb
Host smart-d77414b1-8a52-4722-b89d-f0e1278be2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349142077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2349142077
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2845617289
Short name T9
Test name
Test status
Simulation time 13097420018 ps
CPU time 8.78 seconds
Started May 02 12:53:00 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 211504 kb
Host smart-ec84c840-33c9-44a2-96dc-fddb9fb64811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845617289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2845617289
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1079127278
Short name T257
Test name
Test status
Simulation time 24190688764 ps
CPU time 186.28 seconds
Started May 02 12:53:04 PM PDT 24
Finished May 02 12:56:15 PM PDT 24
Peak memory 233612 kb
Host smart-b63dcd32-cc00-40ba-9353-52e6c41b98b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079127278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1079127278
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3342750971
Short name T253
Test name
Test status
Simulation time 4932240226 ps
CPU time 30.33 seconds
Started May 02 12:53:03 PM PDT 24
Finished May 02 12:53:38 PM PDT 24
Peak memory 212232 kb
Host smart-a9fb6908-e409-45ed-a484-e0f8a60de1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342750971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3342750971
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3590231551
Short name T266
Test name
Test status
Simulation time 1970521666 ps
CPU time 15.94 seconds
Started May 02 12:53:02 PM PDT 24
Finished May 02 12:53:23 PM PDT 24
Peak memory 211284 kb
Host smart-8614910f-ceb4-4aca-8493-59835105198e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590231551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3590231551
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3369606897
Short name T130
Test name
Test status
Simulation time 740148008 ps
CPU time 9.97 seconds
Started May 02 12:53:05 PM PDT 24
Finished May 02 12:53:20 PM PDT 24
Peak memory 219604 kb
Host smart-fbf67f1e-e4ed-4cda-bd6e-9d4c588bdc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369606897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3369606897
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1437210644
Short name T323
Test name
Test status
Simulation time 14867448188 ps
CPU time 45.51 seconds
Started May 02 12:53:03 PM PDT 24
Finished May 02 12:53:53 PM PDT 24
Peak memory 215300 kb
Host smart-4b226f34-7869-4cbd-acf7-e702f94bcc91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437210644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1437210644
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1462480295
Short name T184
Test name
Test status
Simulation time 34721082001 ps
CPU time 16.92 seconds
Started May 02 12:53:02 PM PDT 24
Finished May 02 12:53:23 PM PDT 24
Peak memory 211456 kb
Host smart-d4d65e3d-a10f-4fe1-b7b9-4504e02cb07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462480295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1462480295
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2489745841
Short name T48
Test name
Test status
Simulation time 27176218088 ps
CPU time 209.36 seconds
Started May 02 12:53:04 PM PDT 24
Finished May 02 12:56:38 PM PDT 24
Peak memory 212272 kb
Host smart-6f359d25-880a-49cb-9602-ea0fa4805c96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489745841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2489745841
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.817219538
Short name T327
Test name
Test status
Simulation time 5867954665 ps
CPU time 25.99 seconds
Started May 02 12:53:06 PM PDT 24
Finished May 02 12:53:36 PM PDT 24
Peak memory 212724 kb
Host smart-9b949f34-b220-4366-8e26-5b1210b643fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817219538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.817219538
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3345370812
Short name T189
Test name
Test status
Simulation time 2150246814 ps
CPU time 15.51 seconds
Started May 02 12:53:06 PM PDT 24
Finished May 02 12:53:26 PM PDT 24
Peak memory 211260 kb
Host smart-6323c0de-ee11-40d8-be4c-36983e938d30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345370812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3345370812
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1796520612
Short name T190
Test name
Test status
Simulation time 2145537397 ps
CPU time 21.28 seconds
Started May 02 12:53:03 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 219612 kb
Host smart-438dc785-ccc2-488f-915a-64c03f8c45ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796520612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1796520612
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3740839368
Short name T289
Test name
Test status
Simulation time 1376516349 ps
CPU time 34.09 seconds
Started May 02 12:53:12 PM PDT 24
Finished May 02 12:53:51 PM PDT 24
Peak memory 216232 kb
Host smart-a06aca30-c6cb-48d8-8143-67b5a3e77312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740839368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3740839368
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1042855225
Short name T10
Test name
Test status
Simulation time 260483053 ps
CPU time 5.04 seconds
Started May 02 12:53:01 PM PDT 24
Finished May 02 12:53:11 PM PDT 24
Peak memory 211392 kb
Host smart-238b217c-2e9c-4b2b-8086-e82e25c0cb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042855225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1042855225
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3111680681
Short name T198
Test name
Test status
Simulation time 98234123096 ps
CPU time 211.52 seconds
Started May 02 12:52:58 PM PDT 24
Finished May 02 12:56:35 PM PDT 24
Peak memory 212760 kb
Host smart-514abd25-71da-4d88-974a-beb3441d6d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111680681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3111680681
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1384164082
Short name T22
Test name
Test status
Simulation time 694141699 ps
CPU time 9.28 seconds
Started May 02 12:52:59 PM PDT 24
Finished May 02 12:53:13 PM PDT 24
Peak memory 212204 kb
Host smart-09e224a2-f2ee-469c-b2d3-87d10ccc27a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384164082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1384164082
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1229505730
Short name T126
Test name
Test status
Simulation time 95097167 ps
CPU time 5.29 seconds
Started May 02 12:52:59 PM PDT 24
Finished May 02 12:53:09 PM PDT 24
Peak memory 211332 kb
Host smart-a322f15e-4513-489a-b443-46a31c399642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229505730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1229505730
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2045245460
Short name T161
Test name
Test status
Simulation time 2603505109 ps
CPU time 26.45 seconds
Started May 02 12:53:02 PM PDT 24
Finished May 02 12:53:33 PM PDT 24
Peak memory 219620 kb
Host smart-506aadfd-a028-4ce8-ad64-949de5f232af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045245460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2045245460
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1502655685
Short name T143
Test name
Test status
Simulation time 1583020940 ps
CPU time 9.38 seconds
Started May 02 12:53:02 PM PDT 24
Finished May 02 12:53:16 PM PDT 24
Peak memory 211168 kb
Host smart-887d2c3e-4aa4-4d68-99c4-4901b8720739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502655685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1502655685
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1704206065
Short name T204
Test name
Test status
Simulation time 89067636 ps
CPU time 4.32 seconds
Started May 02 12:53:03 PM PDT 24
Finished May 02 12:53:12 PM PDT 24
Peak memory 211444 kb
Host smart-d76e32e2-791f-424c-acf5-6b0bbfdb3cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704206065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1704206065
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.760624280
Short name T332
Test name
Test status
Simulation time 28005864827 ps
CPU time 111.57 seconds
Started May 02 12:53:02 PM PDT 24
Finished May 02 12:54:59 PM PDT 24
Peak memory 212616 kb
Host smart-5a2666c0-03ce-4298-986e-1923677f1d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760624280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.760624280
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2281637976
Short name T250
Test name
Test status
Simulation time 4828214653 ps
CPU time 23.22 seconds
Started May 02 12:53:00 PM PDT 24
Finished May 02 12:53:28 PM PDT 24
Peak memory 212312 kb
Host smart-6e5badde-b9a7-41e6-958d-13ffaedaaa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281637976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2281637976
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3583077793
Short name T146
Test name
Test status
Simulation time 1960114612 ps
CPU time 10.8 seconds
Started May 02 12:53:03 PM PDT 24
Finished May 02 12:53:19 PM PDT 24
Peak memory 211336 kb
Host smart-914550eb-9f6c-40c0-8d3d-24c0ae910077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583077793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3583077793
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3639440718
Short name T239
Test name
Test status
Simulation time 9232767691 ps
CPU time 23.43 seconds
Started May 02 12:53:01 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 214736 kb
Host smart-13a06dc3-5228-4c89-9fa0-1721dd3e5a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639440718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3639440718
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1546608136
Short name T111
Test name
Test status
Simulation time 805208692 ps
CPU time 22.12 seconds
Started May 02 12:53:06 PM PDT 24
Finished May 02 12:53:32 PM PDT 24
Peak memory 216272 kb
Host smart-450aaf73-b1b5-4d8b-b12c-4bb1ae2ae530
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546608136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1546608136
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1235206740
Short name T51
Test name
Test status
Simulation time 30717732712 ps
CPU time 1392.78 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 01:16:28 PM PDT 24
Peak memory 236020 kb
Host smart-8bdaf8d1-1d7c-4aeb-9600-39934aba1192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235206740 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1235206740
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2925614094
Short name T174
Test name
Test status
Simulation time 89118907 ps
CPU time 4.47 seconds
Started May 02 12:52:59 PM PDT 24
Finished May 02 12:53:09 PM PDT 24
Peak memory 211344 kb
Host smart-ee112b1a-2fe5-47d3-8633-d0697253092c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925614094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2925614094
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4053836917
Short name T326
Test name
Test status
Simulation time 3441041934 ps
CPU time 140.09 seconds
Started May 02 12:52:59 PM PDT 24
Finished May 02 12:55:25 PM PDT 24
Peak memory 211676 kb
Host smart-1b735ad7-8b27-41a6-a573-1ad16c5fdf88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053836917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4053836917
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3667263928
Short name T5
Test name
Test status
Simulation time 856084322 ps
CPU time 15.43 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:53:30 PM PDT 24
Peak memory 212016 kb
Host smart-73e0ac95-3bed-4a92-8ecb-6acdd01e2c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667263928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3667263928
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1295811717
Short name T275
Test name
Test status
Simulation time 3463388316 ps
CPU time 15.23 seconds
Started May 02 12:53:02 PM PDT 24
Finished May 02 12:53:22 PM PDT 24
Peak memory 211368 kb
Host smart-6a9ee6f7-58a9-4b80-b05c-6ae5be88650c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295811717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1295811717
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2006759644
Short name T290
Test name
Test status
Simulation time 17823873531 ps
CPU time 38.1 seconds
Started May 02 12:53:12 PM PDT 24
Finished May 02 12:53:55 PM PDT 24
Peak memory 219572 kb
Host smart-534b0def-4960-4d21-bb11-72e4afb9b6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006759644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2006759644
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.846695584
Short name T358
Test name
Test status
Simulation time 49398419760 ps
CPU time 107.09 seconds
Started May 02 12:53:03 PM PDT 24
Finished May 02 12:54:55 PM PDT 24
Peak memory 219584 kb
Host smart-430d043b-b318-49bc-9486-d1ca5113f516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846695584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.846695584
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1263976904
Short name T207
Test name
Test status
Simulation time 1219902387 ps
CPU time 11.14 seconds
Started May 02 12:53:01 PM PDT 24
Finished May 02 12:53:17 PM PDT 24
Peak memory 211436 kb
Host smart-32ed05b7-84c7-43d0-81d9-0e6f63af9ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263976904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1263976904
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.473678686
Short name T325
Test name
Test status
Simulation time 3098642311 ps
CPU time 147.84 seconds
Started May 02 12:53:03 PM PDT 24
Finished May 02 12:55:36 PM PDT 24
Peak memory 228996 kb
Host smart-7827d670-8c95-41d9-885b-195be9b4bfe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473678686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.473678686
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1001705130
Short name T218
Test name
Test status
Simulation time 49107692260 ps
CPU time 29.89 seconds
Started May 02 12:53:01 PM PDT 24
Finished May 02 12:53:36 PM PDT 24
Peak memory 212232 kb
Host smart-7a758f27-d072-4f2b-8350-15fb6e96d5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001705130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1001705130
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3873121976
Short name T343
Test name
Test status
Simulation time 641198621 ps
CPU time 7.63 seconds
Started May 02 12:53:04 PM PDT 24
Finished May 02 12:53:16 PM PDT 24
Peak memory 211404 kb
Host smart-a1d3a4f3-8ec3-4119-b5ad-55a73c508852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873121976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3873121976
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2466332447
Short name T79
Test name
Test status
Simulation time 32281358600 ps
CPU time 37.68 seconds
Started May 02 12:53:06 PM PDT 24
Finished May 02 12:53:48 PM PDT 24
Peak memory 213940 kb
Host smart-fd76442f-b783-4a3c-95ea-7056d8be8b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466332447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2466332447
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.64352262
Short name T145
Test name
Test status
Simulation time 4709630789 ps
CPU time 47.44 seconds
Started May 02 12:53:04 PM PDT 24
Finished May 02 12:53:56 PM PDT 24
Peak memory 219652 kb
Host smart-6c66c134-b3a0-47f6-8965-d11f02b48d5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64352262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.64352262
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1223512991
Short name T288
Test name
Test status
Simulation time 3558672926 ps
CPU time 15.3 seconds
Started May 02 12:52:18 PM PDT 24
Finished May 02 12:52:40 PM PDT 24
Peak memory 211420 kb
Host smart-1991261d-6c3d-4d64-b134-34b21d9d916d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223512991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1223512991
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2148103546
Short name T34
Test name
Test status
Simulation time 3200371712 ps
CPU time 53.53 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:53:14 PM PDT 24
Peak memory 211624 kb
Host smart-938c8653-290d-4e0f-b847-8ffdf03066cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148103546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2148103546
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.543587769
Short name T234
Test name
Test status
Simulation time 10026864994 ps
CPU time 23.39 seconds
Started May 02 12:52:12 PM PDT 24
Finished May 02 12:52:44 PM PDT 24
Peak memory 212468 kb
Host smart-4edab50f-1f8f-4765-8cbb-e97ab21e9428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543587769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.543587769
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3346090781
Short name T114
Test name
Test status
Simulation time 4400034417 ps
CPU time 11.86 seconds
Started May 02 12:52:16 PM PDT 24
Finished May 02 12:52:35 PM PDT 24
Peak memory 211408 kb
Host smart-9bbe4ca0-ba15-4eee-9853-766f33bd31d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346090781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3346090781
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3126995710
Short name T32
Test name
Test status
Simulation time 3289976725 ps
CPU time 102.35 seconds
Started May 02 12:52:13 PM PDT 24
Finished May 02 12:54:03 PM PDT 24
Peak memory 234160 kb
Host smart-a425068c-401b-4c56-a2ab-838155aef7c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126995710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3126995710
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3022679791
Short name T252
Test name
Test status
Simulation time 3209644407 ps
CPU time 31.47 seconds
Started May 02 12:52:13 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 213160 kb
Host smart-3c56cf13-53ae-4f5d-ae68-5fd978c519ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022679791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3022679791
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2786098334
Short name T229
Test name
Test status
Simulation time 81783690638 ps
CPU time 117.59 seconds
Started May 02 12:52:16 PM PDT 24
Finished May 02 12:54:21 PM PDT 24
Peak memory 216840 kb
Host smart-122ddff4-e0ed-4039-af7b-5feb3414ff06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786098334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2786098334
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2144754539
Short name T212
Test name
Test status
Simulation time 2133981180 ps
CPU time 16.48 seconds
Started May 02 12:53:09 PM PDT 24
Finished May 02 12:53:31 PM PDT 24
Peak memory 211408 kb
Host smart-96782450-07bb-4380-b6ac-7598894bc912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144754539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2144754539
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1594392033
Short name T336
Test name
Test status
Simulation time 58654022534 ps
CPU time 99.87 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:54:53 PM PDT 24
Peak memory 227712 kb
Host smart-64731a92-d01d-4172-b57a-dbfab25e5e4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594392033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1594392033
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3151026907
Short name T285
Test name
Test status
Simulation time 175531583 ps
CPU time 9.59 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:53:25 PM PDT 24
Peak memory 211900 kb
Host smart-502afa2b-7a06-46a8-ad72-230a6a9f5d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151026907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3151026907
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3072829000
Short name T216
Test name
Test status
Simulation time 95897338 ps
CPU time 5.57 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:53:21 PM PDT 24
Peak memory 211292 kb
Host smart-bb849d94-118d-4cfc-b992-b83f42f4ad5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072829000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3072829000
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3696744205
Short name T300
Test name
Test status
Simulation time 4079033248 ps
CPU time 34.46 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:53:47 PM PDT 24
Peak memory 213592 kb
Host smart-ecf62fbf-d31a-4039-a406-f3fe037a9748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696744205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3696744205
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3733614604
Short name T213
Test name
Test status
Simulation time 241894910 ps
CPU time 9.22 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:53:22 PM PDT 24
Peak memory 211372 kb
Host smart-787b0392-0533-44a8-b481-d9b093f74154
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733614604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3733614604
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3869573810
Short name T344
Test name
Test status
Simulation time 3488025575 ps
CPU time 10.14 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:53:25 PM PDT 24
Peak memory 211480 kb
Host smart-6ce95c8d-88a3-4b37-9732-7bad9a5be40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869573810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3869573810
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1249960086
Short name T270
Test name
Test status
Simulation time 17866668635 ps
CPU time 262.29 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:57:38 PM PDT 24
Peak memory 233544 kb
Host smart-d7a8aec0-1dbf-4052-8c32-7fd7868bed3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249960086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1249960086
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.665329423
Short name T29
Test name
Test status
Simulation time 926666550 ps
CPU time 15.56 seconds
Started May 02 12:53:09 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 212096 kb
Host smart-803210ba-5728-4415-a21a-95c711da5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665329423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.665329423
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.233381166
Short name T80
Test name
Test status
Simulation time 3777033021 ps
CPU time 38.01 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:53:53 PM PDT 24
Peak memory 219664 kb
Host smart-04839666-1175-4481-ab9b-29dc5f39f0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233381166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.233381166
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2127841665
Short name T320
Test name
Test status
Simulation time 6151839675 ps
CPU time 68.71 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:54:24 PM PDT 24
Peak memory 218904 kb
Host smart-2b6b0a1a-ba0f-4d17-b1de-97168f979744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127841665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2127841665
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4117536298
Short name T193
Test name
Test status
Simulation time 960847636 ps
CPU time 9.77 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 211320 kb
Host smart-3d8781a9-8819-4ad5-8517-6c1eaa404e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117536298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4117536298
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2363099803
Short name T50
Test name
Test status
Simulation time 5938666052 ps
CPU time 59.88 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:54:13 PM PDT 24
Peak memory 213696 kb
Host smart-c9a43f65-ef4f-420e-8931-98d2e361f1aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363099803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2363099803
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3700441492
Short name T28
Test name
Test status
Simulation time 10854289200 ps
CPU time 24.39 seconds
Started May 02 12:53:09 PM PDT 24
Finished May 02 12:53:38 PM PDT 24
Peak memory 219692 kb
Host smart-0e5e5424-7aeb-4b4a-8163-32150c2029ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700441492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3700441492
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1862661895
Short name T318
Test name
Test status
Simulation time 97899987 ps
CPU time 5.76 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:53:18 PM PDT 24
Peak memory 211368 kb
Host smart-d5995d0c-fc66-46ec-9b6f-448779ff099f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862661895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1862661895
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.629987764
Short name T131
Test name
Test status
Simulation time 361831819 ps
CPU time 10.08 seconds
Started May 02 12:53:09 PM PDT 24
Finished May 02 12:53:24 PM PDT 24
Peak memory 219592 kb
Host smart-6ceca73b-5436-40b6-93a4-9564f120e484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629987764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.629987764
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3479702363
Short name T210
Test name
Test status
Simulation time 16261291828 ps
CPU time 34.52 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:53:48 PM PDT 24
Peak memory 219600 kb
Host smart-9aa66f1c-30b9-44ce-98e3-74aeff5b4021
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479702363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3479702363
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1906144252
Short name T19
Test name
Test status
Simulation time 6998607952 ps
CPU time 256.58 seconds
Started May 02 12:53:06 PM PDT 24
Finished May 02 12:57:27 PM PDT 24
Peak memory 227872 kb
Host smart-345f2352-dd9d-42b2-8d16-5b47b4523160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906144252 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1906144252
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2225108647
Short name T357
Test name
Test status
Simulation time 519368321 ps
CPU time 5.01 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:53:18 PM PDT 24
Peak memory 211396 kb
Host smart-f89fa931-011b-4172-8c26-a658dba78aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225108647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2225108647
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.299968083
Short name T297
Test name
Test status
Simulation time 9089205943 ps
CPU time 108.25 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:55:01 PM PDT 24
Peak memory 238048 kb
Host smart-4be0523b-78ee-49a0-b066-b51a21917301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299968083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.299968083
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4022171567
Short name T247
Test name
Test status
Simulation time 1332089586 ps
CPU time 11.89 seconds
Started May 02 12:53:08 PM PDT 24
Finished May 02 12:53:25 PM PDT 24
Peak memory 212112 kb
Host smart-44f4f555-d641-40b5-9558-c210b937e914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022171567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4022171567
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2492152850
Short name T154
Test name
Test status
Simulation time 1712172792 ps
CPU time 14.73 seconds
Started May 02 12:53:09 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 211372 kb
Host smart-db6cc943-5aa7-4f0e-9d30-cc19f8380251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492152850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2492152850
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2236222796
Short name T16
Test name
Test status
Simulation time 8280426985 ps
CPU time 21.08 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:53:37 PM PDT 24
Peak memory 214208 kb
Host smart-058fea31-4427-46bc-aceb-810c137af9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236222796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2236222796
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2035738053
Short name T188
Test name
Test status
Simulation time 6794997974 ps
CPU time 71.23 seconds
Started May 02 12:53:06 PM PDT 24
Finished May 02 12:54:22 PM PDT 24
Peak memory 214644 kb
Host smart-9715bff4-a531-4555-9862-b73ca6f7e5dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035738053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2035738053
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3810088552
Short name T291
Test name
Test status
Simulation time 4456563156 ps
CPU time 7.81 seconds
Started May 02 12:53:13 PM PDT 24
Finished May 02 12:53:27 PM PDT 24
Peak memory 211480 kb
Host smart-e7326dcc-8ad2-4c2f-8b99-8b5bda3eb3ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810088552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3810088552
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3305815721
Short name T310
Test name
Test status
Simulation time 42494782401 ps
CPU time 117.49 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:55:17 PM PDT 24
Peak memory 212588 kb
Host smart-7d814b80-fbed-4acf-b300-867a9323291a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305815721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3305815721
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3849364277
Short name T352
Test name
Test status
Simulation time 3024893156 ps
CPU time 26.39 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:53:46 PM PDT 24
Peak memory 211388 kb
Host smart-5cf4aa4e-cab7-46d7-8596-736028a6b6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849364277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3849364277
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.804505788
Short name T262
Test name
Test status
Simulation time 570761451 ps
CPU time 5.32 seconds
Started May 02 12:53:07 PM PDT 24
Finished May 02 12:53:17 PM PDT 24
Peak memory 211312 kb
Host smart-6c9165b0-5fda-4c29-b169-ef93116fff84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804505788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.804505788
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1316989552
Short name T350
Test name
Test status
Simulation time 24821186071 ps
CPU time 25.66 seconds
Started May 02 12:53:10 PM PDT 24
Finished May 02 12:53:41 PM PDT 24
Peak memory 219680 kb
Host smart-950a863f-9e8f-4104-a806-bea02d56b8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316989552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1316989552
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.621051201
Short name T211
Test name
Test status
Simulation time 48369340099 ps
CPU time 88.42 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:54:48 PM PDT 24
Peak memory 219520 kb
Host smart-91a93e10-5b72-4027-ba3a-152df58a5425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621051201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.621051201
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1408866223
Short name T134
Test name
Test status
Simulation time 905742168 ps
CPU time 10.19 seconds
Started May 02 12:53:13 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 211408 kb
Host smart-647948bf-6830-459c-bab2-ecf6a36dc31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408866223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1408866223
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1376481332
Short name T49
Test name
Test status
Simulation time 103444441443 ps
CPU time 210.84 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:56:50 PM PDT 24
Peak memory 230052 kb
Host smart-04c70e43-6141-4b63-adf8-845afc00ffe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376481332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1376481332
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1399539645
Short name T164
Test name
Test status
Simulation time 6608039337 ps
CPU time 16.25 seconds
Started May 02 12:53:15 PM PDT 24
Finished May 02 12:53:37 PM PDT 24
Peak memory 212692 kb
Host smart-cc57fc4d-5ad9-4759-aaba-79785385968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399539645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1399539645
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3350635995
Short name T42
Test name
Test status
Simulation time 100709330 ps
CPU time 5.95 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:53:25 PM PDT 24
Peak memory 211352 kb
Host smart-75f96cc8-c5bf-4487-864f-9a1e026a65f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350635995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3350635995
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2929103563
Short name T172
Test name
Test status
Simulation time 590127716 ps
CPU time 14.06 seconds
Started May 02 12:53:15 PM PDT 24
Finished May 02 12:53:34 PM PDT 24
Peak memory 213668 kb
Host smart-863d0e28-917e-475a-b56b-fe27494b32f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929103563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2929103563
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2909311245
Short name T302
Test name
Test status
Simulation time 23351202418 ps
CPU time 37.43 seconds
Started May 02 12:53:15 PM PDT 24
Finished May 02 12:53:58 PM PDT 24
Peak memory 214200 kb
Host smart-09872c08-39aa-448a-9403-9ec5b8c12e77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909311245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2909311245
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2667387580
Short name T20
Test name
Test status
Simulation time 214184276676 ps
CPU time 5284.51 seconds
Started May 02 12:53:15 PM PDT 24
Finished May 02 02:21:25 PM PDT 24
Peak memory 234936 kb
Host smart-30196516-1009-4245-bbe1-7f557495426e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667387580 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2667387580
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2762331570
Short name T3
Test name
Test status
Simulation time 2191601256 ps
CPU time 16.47 seconds
Started May 02 12:53:12 PM PDT 24
Finished May 02 12:53:34 PM PDT 24
Peak memory 211432 kb
Host smart-f4076ec8-f4b2-4c5f-a712-55815a5c62b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762331570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2762331570
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3767459949
Short name T251
Test name
Test status
Simulation time 27200060733 ps
CPU time 169.77 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:56:09 PM PDT 24
Peak memory 237028 kb
Host smart-1507e56b-ac42-47b2-adcf-a119e7cc317a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767459949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3767459949
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.389589593
Short name T272
Test name
Test status
Simulation time 21411744742 ps
CPU time 31.7 seconds
Started May 02 12:53:17 PM PDT 24
Finished May 02 12:53:53 PM PDT 24
Peak memory 212576 kb
Host smart-247409ca-c7d1-46e4-a01c-42ce460b424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389589593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.389589593
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1858619477
Short name T144
Test name
Test status
Simulation time 3957235781 ps
CPU time 16.14 seconds
Started May 02 12:53:16 PM PDT 24
Finished May 02 12:53:37 PM PDT 24
Peak memory 211440 kb
Host smart-d64cb0ae-cc6a-4f47-ab5d-3a13b8447da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858619477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1858619477
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3077579627
Short name T321
Test name
Test status
Simulation time 865381018 ps
CPU time 16.25 seconds
Started May 02 12:53:13 PM PDT 24
Finished May 02 12:53:34 PM PDT 24
Peak memory 219612 kb
Host smart-ab2265df-c16e-4bde-81d4-a2b291ab29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077579627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3077579627
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1026171593
Short name T243
Test name
Test status
Simulation time 204839180 ps
CPU time 6.07 seconds
Started May 02 12:53:12 PM PDT 24
Finished May 02 12:53:24 PM PDT 24
Peak memory 211416 kb
Host smart-2ee86b29-91ac-44ea-a294-5e104a99eab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026171593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1026171593
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2436152925
Short name T136
Test name
Test status
Simulation time 8096892392 ps
CPU time 16.07 seconds
Started May 02 12:53:16 PM PDT 24
Finished May 02 12:53:37 PM PDT 24
Peak memory 211504 kb
Host smart-8c2f7260-2c86-4133-930c-f72285b1be83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436152925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2436152925
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3658772829
Short name T328
Test name
Test status
Simulation time 112998369960 ps
CPU time 257.6 seconds
Started May 02 12:53:17 PM PDT 24
Finished May 02 12:57:39 PM PDT 24
Peak memory 237884 kb
Host smart-fe2d3561-3ab0-4207-8342-6003ceef69ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658772829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3658772829
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2601749175
Short name T21
Test name
Test status
Simulation time 2458725727 ps
CPU time 24.86 seconds
Started May 02 12:53:15 PM PDT 24
Finished May 02 12:53:45 PM PDT 24
Peak memory 211860 kb
Host smart-0f773f84-6615-47de-a502-0065a578a713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601749175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2601749175
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4099455848
Short name T280
Test name
Test status
Simulation time 610481544 ps
CPU time 7.58 seconds
Started May 02 12:53:13 PM PDT 24
Finished May 02 12:53:26 PM PDT 24
Peak memory 211316 kb
Host smart-b658241c-d973-4931-8bae-cc8d3efdd173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4099455848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4099455848
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4070451817
Short name T304
Test name
Test status
Simulation time 13817022280 ps
CPU time 36.75 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:54:01 PM PDT 24
Peak memory 214400 kb
Host smart-f11cfd88-7bb5-4f26-9bd6-e712e70abe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070451817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4070451817
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1544984143
Short name T39
Test name
Test status
Simulation time 6130408223 ps
CPU time 40.73 seconds
Started May 02 12:53:14 PM PDT 24
Finished May 02 12:54:01 PM PDT 24
Peak memory 216704 kb
Host smart-a1368aff-2891-4182-9bb8-cddddf7fc997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544984143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1544984143
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1470455179
Short name T53
Test name
Test status
Simulation time 282802711782 ps
CPU time 7613.14 seconds
Started May 02 12:53:16 PM PDT 24
Finished May 02 03:00:15 PM PDT 24
Peak memory 236124 kb
Host smart-48a45599-78f5-4a48-aead-022c9f92c4d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470455179 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1470455179
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1700522531
Short name T152
Test name
Test status
Simulation time 2086160201 ps
CPU time 16.53 seconds
Started May 02 12:53:19 PM PDT 24
Finished May 02 12:53:39 PM PDT 24
Peak memory 211416 kb
Host smart-d6981ddd-099c-472c-83f6-2da8f5a48f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700522531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1700522531
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3435248842
Short name T104
Test name
Test status
Simulation time 29055926045 ps
CPU time 261.24 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:57:45 PM PDT 24
Peak memory 242048 kb
Host smart-34706100-b18d-4064-88d0-55b00d7ad4d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435248842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3435248842
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.561779321
Short name T254
Test name
Test status
Simulation time 1381408545 ps
CPU time 9.33 seconds
Started May 02 12:53:23 PM PDT 24
Finished May 02 12:53:37 PM PDT 24
Peak memory 211972 kb
Host smart-0e19050c-626f-45fd-b9fd-07dbd4874c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561779321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.561779321
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3141425809
Short name T8
Test name
Test status
Simulation time 422904500 ps
CPU time 8.12 seconds
Started May 02 12:53:15 PM PDT 24
Finished May 02 12:53:29 PM PDT 24
Peak memory 211224 kb
Host smart-273ecdc2-8fcc-4e27-aaac-54a9a8d15198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141425809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3141425809
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1591915876
Short name T341
Test name
Test status
Simulation time 7363821687 ps
CPU time 35.26 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:54:00 PM PDT 24
Peak memory 219576 kb
Host smart-35620c41-97a3-42c0-a3a7-ff3853db862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591915876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1591915876
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3288294658
Short name T41
Test name
Test status
Simulation time 806288374 ps
CPU time 20.74 seconds
Started May 02 12:53:15 PM PDT 24
Finished May 02 12:53:41 PM PDT 24
Peak memory 215092 kb
Host smart-981303eb-ce83-4d73-8645-6ee79c17be89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288294658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3288294658
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1802195455
Short name T182
Test name
Test status
Simulation time 2337802359 ps
CPU time 11.02 seconds
Started May 02 12:53:24 PM PDT 24
Finished May 02 12:53:40 PM PDT 24
Peak memory 211432 kb
Host smart-7313d5a7-8f25-47e9-b6d9-593a648c57a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802195455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1802195455
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.802036059
Short name T231
Test name
Test status
Simulation time 1424077110 ps
CPU time 70.16 seconds
Started May 02 12:53:22 PM PDT 24
Finished May 02 12:54:38 PM PDT 24
Peak memory 220048 kb
Host smart-9b1e8d24-7573-4ac1-a67d-c609b99e8c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802036059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.802036059
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3283425767
Short name T246
Test name
Test status
Simulation time 3301649288 ps
CPU time 19.06 seconds
Started May 02 12:53:20 PM PDT 24
Finished May 02 12:53:43 PM PDT 24
Peak memory 211948 kb
Host smart-ed5021be-b212-47ef-a755-dc7887e0d44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283425767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3283425767
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1540721024
Short name T44
Test name
Test status
Simulation time 2371838516 ps
CPU time 15.82 seconds
Started May 02 12:53:21 PM PDT 24
Finished May 02 12:53:41 PM PDT 24
Peak memory 211368 kb
Host smart-66f6ee5a-6879-42fe-9b25-5ca72e709b2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540721024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1540721024
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1564569343
Short name T128
Test name
Test status
Simulation time 11562845877 ps
CPU time 26.56 seconds
Started May 02 12:53:24 PM PDT 24
Finished May 02 12:53:56 PM PDT 24
Peak memory 219660 kb
Host smart-52b2402c-3435-49b2-8d4c-89cc268700c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564569343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1564569343
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3298219061
Short name T232
Test name
Test status
Simulation time 3782306020 ps
CPU time 19.67 seconds
Started May 02 12:53:25 PM PDT 24
Finished May 02 12:53:49 PM PDT 24
Peak memory 211992 kb
Host smart-a2418085-0074-4074-aa67-69664246ba76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298219061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3298219061
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1486629529
Short name T65
Test name
Test status
Simulation time 1567834355 ps
CPU time 13.96 seconds
Started May 02 12:52:22 PM PDT 24
Finished May 02 12:52:40 PM PDT 24
Peak memory 211420 kb
Host smart-487c3e2b-c537-4fe0-ac7f-cf0f9da8a7e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486629529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1486629529
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2891901346
Short name T159
Test name
Test status
Simulation time 126868307431 ps
CPU time 162.61 seconds
Started May 02 12:52:13 PM PDT 24
Finished May 02 12:55:03 PM PDT 24
Peak memory 237948 kb
Host smart-b6e1b6c8-6bc9-4bdb-b3bc-b01346237663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891901346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2891901346
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1329428768
Short name T331
Test name
Test status
Simulation time 9474986520 ps
CPU time 23.82 seconds
Started May 02 12:52:14 PM PDT 24
Finished May 02 12:52:45 PM PDT 24
Peak memory 212296 kb
Host smart-8146a1bf-fcd0-4e38-bf68-6071d2dadb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329428768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1329428768
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.186501051
Short name T273
Test name
Test status
Simulation time 878438121 ps
CPU time 10.88 seconds
Started May 02 12:52:15 PM PDT 24
Finished May 02 12:52:33 PM PDT 24
Peak memory 211272 kb
Host smart-48a37b5e-6d61-4cf7-9f99-77d30ad78d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186501051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.186501051
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3564198229
Short name T163
Test name
Test status
Simulation time 10498857687 ps
CPU time 23.92 seconds
Started May 02 12:52:14 PM PDT 24
Finished May 02 12:52:45 PM PDT 24
Peak memory 214596 kb
Host smart-87c107eb-b733-43d8-aa71-c2832b8306f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564198229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3564198229
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1835509119
Short name T255
Test name
Test status
Simulation time 821646109 ps
CPU time 13.92 seconds
Started May 02 12:52:17 PM PDT 24
Finished May 02 12:52:37 PM PDT 24
Peak memory 212472 kb
Host smart-fbe958c0-de84-47c4-9433-17ffedb16412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835509119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1835509119
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1369504952
Short name T167
Test name
Test status
Simulation time 8481422941 ps
CPU time 16.39 seconds
Started May 02 12:52:27 PM PDT 24
Finished May 02 12:52:46 PM PDT 24
Peak memory 211104 kb
Host smart-b0eafac3-b61c-4348-a33d-cc2a26f5ce41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369504952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1369504952
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4192742586
Short name T219
Test name
Test status
Simulation time 689272015 ps
CPU time 12.52 seconds
Started May 02 12:52:26 PM PDT 24
Finished May 02 12:52:41 PM PDT 24
Peak memory 212124 kb
Host smart-8638c8f9-71fc-480b-816d-d18d32a1f12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192742586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4192742586
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3185248395
Short name T319
Test name
Test status
Simulation time 1605991657 ps
CPU time 14.25 seconds
Started May 02 12:52:26 PM PDT 24
Finished May 02 12:52:43 PM PDT 24
Peak memory 211360 kb
Host smart-a59e6fb9-b4d3-4193-bbf8-1b98b6362372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185248395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3185248395
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3943483582
Short name T309
Test name
Test status
Simulation time 4387263452 ps
CPU time 19.09 seconds
Started May 02 12:52:21 PM PDT 24
Finished May 02 12:52:45 PM PDT 24
Peak memory 219628 kb
Host smart-d555838b-45ce-4f89-b301-9b1b38139e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943483582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3943483582
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2093649967
Short name T333
Test name
Test status
Simulation time 8886591372 ps
CPU time 86.74 seconds
Started May 02 12:52:24 PM PDT 24
Finished May 02 12:53:54 PM PDT 24
Peak memory 214820 kb
Host smart-41674c1c-3961-4622-8c7e-f33da8bbe9b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093649967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2093649967
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3735052012
Short name T132
Test name
Test status
Simulation time 4105459705 ps
CPU time 10.26 seconds
Started May 02 12:52:24 PM PDT 24
Finished May 02 12:52:38 PM PDT 24
Peak memory 211504 kb
Host smart-f693051d-f3cf-43bf-9fbb-72c922b28ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735052012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3735052012
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1005062950
Short name T236
Test name
Test status
Simulation time 4390616808 ps
CPU time 65.93 seconds
Started May 02 12:52:21 PM PDT 24
Finished May 02 12:53:32 PM PDT 24
Peak memory 234448 kb
Host smart-fe41085e-bf7a-4561-925d-c604c8a73608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005062950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1005062950
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1611714291
Short name T183
Test name
Test status
Simulation time 13048701545 ps
CPU time 28.58 seconds
Started May 02 12:52:21 PM PDT 24
Finished May 02 12:52:54 PM PDT 24
Peak memory 212340 kb
Host smart-d91968a3-7315-47f7-ab6a-168ca1e0120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611714291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1611714291
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3552045209
Short name T217
Test name
Test status
Simulation time 4631359116 ps
CPU time 12.38 seconds
Started May 02 12:52:23 PM PDT 24
Finished May 02 12:52:39 PM PDT 24
Peak memory 211420 kb
Host smart-55aef74e-987e-4361-b62a-2a1a80a5ad8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552045209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3552045209
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2263282808
Short name T129
Test name
Test status
Simulation time 1851736170 ps
CPU time 20.89 seconds
Started May 02 12:52:31 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 219552 kb
Host smart-d6afe4a8-7160-46b0-bf6e-688d677acf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263282808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2263282808
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.312059654
Short name T166
Test name
Test status
Simulation time 753221780 ps
CPU time 19.01 seconds
Started May 02 12:52:20 PM PDT 24
Finished May 02 12:52:44 PM PDT 24
Peak memory 213480 kb
Host smart-0cabd1cb-915e-4227-af73-3c1d2b27b6ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312059654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.312059654
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1858573816
Short name T170
Test name
Test status
Simulation time 1241103068 ps
CPU time 10.41 seconds
Started May 02 12:52:23 PM PDT 24
Finished May 02 12:52:38 PM PDT 24
Peak memory 211376 kb
Host smart-d23720de-9148-4cba-8245-5cb6fe968cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858573816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1858573816
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2526985768
Short name T259
Test name
Test status
Simulation time 36189651778 ps
CPU time 353.35 seconds
Started May 02 12:52:30 PM PDT 24
Finished May 02 12:58:26 PM PDT 24
Peak memory 235108 kb
Host smart-303d9d2e-4887-4b31-999c-72dc128640ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526985768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2526985768
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4047390354
Short name T222
Test name
Test status
Simulation time 1475952208 ps
CPU time 17.87 seconds
Started May 02 12:52:27 PM PDT 24
Finished May 02 12:52:48 PM PDT 24
Peak memory 211748 kb
Host smart-cdd870bc-be2a-4522-913e-89f287208015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047390354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4047390354
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2709352155
Short name T307
Test name
Test status
Simulation time 5458801922 ps
CPU time 13.88 seconds
Started May 02 12:52:26 PM PDT 24
Finished May 02 12:52:42 PM PDT 24
Peak memory 211332 kb
Host smart-473a51bb-e298-4266-8cb6-a5b7cd68861f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709352155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2709352155
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4185391285
Short name T223
Test name
Test status
Simulation time 13095264087 ps
CPU time 30.14 seconds
Started May 02 12:52:21 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 213916 kb
Host smart-8a06a38b-b8ec-45d0-b3d7-0f705d1d6961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185391285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4185391285
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1769642419
Short name T102
Test name
Test status
Simulation time 8980781255 ps
CPU time 23.13 seconds
Started May 02 12:52:22 PM PDT 24
Finished May 02 12:52:50 PM PDT 24
Peak memory 213728 kb
Host smart-26615b83-ee13-40fd-b85b-e6e2c568a297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769642419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1769642419
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2804795317
Short name T214
Test name
Test status
Simulation time 8004888337 ps
CPU time 15.6 seconds
Started May 02 12:52:21 PM PDT 24
Finished May 02 12:52:42 PM PDT 24
Peak memory 211472 kb
Host smart-6e4b053c-3fed-4997-a60f-c4868802ee27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804795317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2804795317
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4253372545
Short name T138
Test name
Test status
Simulation time 188166800521 ps
CPU time 488.72 seconds
Started May 02 12:52:23 PM PDT 24
Finished May 02 01:00:36 PM PDT 24
Peak memory 230760 kb
Host smart-0e14b218-c2ce-4591-a004-5c6d0dd5e613
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253372545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4253372545
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2360331530
Short name T340
Test name
Test status
Simulation time 3164078481 ps
CPU time 28 seconds
Started May 02 12:52:32 PM PDT 24
Finished May 02 12:53:03 PM PDT 24
Peak memory 212132 kb
Host smart-8fa96e2e-1289-4b7f-961e-5867a1c96e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360331530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2360331530
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3890312083
Short name T25
Test name
Test status
Simulation time 4632796004 ps
CPU time 12.72 seconds
Started May 02 12:52:20 PM PDT 24
Finished May 02 12:52:38 PM PDT 24
Peak memory 211432 kb
Host smart-ded89df6-1f47-4382-8397-ef364e73b4fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890312083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3890312083
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1828569263
Short name T238
Test name
Test status
Simulation time 10294681795 ps
CPU time 27.58 seconds
Started May 02 12:52:31 PM PDT 24
Finished May 02 12:53:02 PM PDT 24
Peak memory 219628 kb
Host smart-04a735e6-dcf5-40f1-8d19-6c08e19a53ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828569263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1828569263
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3923232026
Short name T235
Test name
Test status
Simulation time 54078053871 ps
CPU time 54.42 seconds
Started May 02 12:52:24 PM PDT 24
Finished May 02 12:53:22 PM PDT 24
Peak memory 219604 kb
Host smart-3075d1d1-67f0-4620-a6b2-d43450483fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923232026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3923232026
Directory /workspace/9.rom_ctrl_stress_all/latest
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