Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3660358

1

T1

283

T4

158894

T7

73

full_word

2335890

1

T1

31

T4

101032

T7

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5995958	1			T1	314		T4	259926		T7	79
auto[TlIntgErrCmd]	107	1			T46	3		T47	4		T48	3
auto[TlIntgErrData]	97	1			T46	4		T47	4		T48	15
auto[TlIntgErrBoth]	86	1			T46	3		T47	2		T48	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

945898

1

T1

314

T4

39969

T7

79

auto[1]

5050350

1

T4

219957

T20

85248

T21

202386

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	394467	1			T1	283		T4	16105		T7	73
auto[TlIntgErrNone]	partial	auto[1]	3265625	1			T4	142789		T20	54206		T21	130188
auto[TlIntgErrNone]	full_word	auto[0]	551294	1			T1	31		T4	23864		T7	6
auto[TlIntgErrNone]	full_word	auto[1]	1784572	1			T4	77168		T20	31042		T21	72198
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T46	1		T47	2		T48	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T46	2		T47	1		T48	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T111	1		T117	2		T115	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T47	1		T116	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T46	2		T47	3		T48	6
auto[TlIntgErrData]	partial	auto[1]	36	1			T46	2		T47	1		T48	7
auto[TlIntgErrData]	full_word	auto[0]	1	1			T119	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T48	2		T115	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T46	3		T47	1		T112	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T47	1		T48	2		T112	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T113	1		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T114	1		T117	1		T121	1