Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2756247

1

T1

253673

T2

269883

T5

58

full_word

1753038

1

T1

166621

T2

169096

T5

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4508975	1			T1	420294		T2	438979		T5	63
auto[TlIntgErrCmd]	101	1			T49	7		T50	2		T51	5
auto[TlIntgErrData]	100	1			T49	6		T50	10		T51	3
auto[TlIntgErrBoth]	109	1			T49	7		T50	8		T51	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

713935

1

T1

64725

T2

67438

T5

63

auto[1]

3795350

1

T1

355569

T2

371541

T14

282367

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	299599	1			T1	25461		T2	27823		T5	58
auto[TlIntgErrNone]	partial	auto[1]	2456363	1			T1	228212		T2	242060		T14	181651
auto[TlIntgErrNone]	full_word	auto[0]	414195	1			T1	39264		T2	39615		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	1338818	1			T1	127357		T2	129481		T14	100716
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T49	4		T50	1		T51	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T49	3		T50	1		T51	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T51	1		T122	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T117	1		T124	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T50	4		T51	1		T115	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T49	5		T50	5		T115	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T49	1		T119	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T50	1		T51	2		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T49	3		T50	4		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T49	3		T50	3		T51	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T50	1		T122	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T49	1		T121	1		T125	1