Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4028301

1

T5

128

T6

94039

T9

62

full_word

2569091

1

T5

12

T6

60405

T8

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6597092	1			T5	140		T6	154444		T8	2
auto[TlIntgErrCmd]	103	1			T56	8		T57	2		T58	8
auto[TlIntgErrData]	101	1			T56	5		T57	4		T58	9
auto[TlIntgErrBoth]	96	1			T56	7		T57	4		T58	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041433

1

T5

140

T6

24452

T8

2

auto[1]

5555959

1

T6

129992

T11

219440

T19

127210

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	434823	1			T5	128		T6	10099		T9	62
auto[TlIntgErrNone]	partial	auto[1]	3593199	1			T6	83940		T11	139226		T19	84432
auto[TlIntgErrNone]	full_word	auto[0]	606486	1			T5	12		T6	14353		T8	2
auto[TlIntgErrNone]	full_word	auto[1]	1962584	1			T6	46052		T11	80214		T19	42778
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T56	2		T57	1		T58	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T56	6		T57	1		T58	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T114	1		T113	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T111	1		T114	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T56	3		T57	1		T58	5
auto[TlIntgErrData]	partial	auto[1]	52	1			T56	2		T57	3		T58	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T118	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1			T58	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T56	2		T57	2		T58	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T56	5		T57	1		T58	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T57	1		T119	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T120	1		T121	1		T116	1