Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2327993

1

T2

149

T5

53

T6

140

full_word

1494410

1

T2

14

T5

4

T6

15

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3822113	1			T2	163		T5	57		T6	155
auto[TlIntgErrCmd]	102	1			T48	5		T49	6		T50	2
auto[TlIntgErrData]	93	1			T48	4		T49	8		T50	7
auto[TlIntgErrBoth]	95	1			T48	11		T49	6		T50	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

617781

1

T2

163

T5

57

T6

155

auto[1]

3204622

1

T9

213889

T17

410386

T18

190585

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	263116	1			T2	149		T5	53		T6	140
auto[TlIntgErrNone]	partial	auto[1]	2064608	1			T9	137788		T17	263608		T18	124134
auto[TlIntgErrNone]	full_word	auto[0]	354536	1			T2	14		T5	4		T6	15
auto[TlIntgErrNone]	full_word	auto[1]	1139853	1			T9	76101		T17	146778		T18	66451
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T48	3		T49	2		T96	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T48	2		T49	4		T50	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T97	1		T98	1		T99	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T100	2		T101	1		T102	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T48	1		T49	3		T50	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T48	3		T49	4		T50	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T49	1		T50	1		T103	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T48	3		T50	5		T96	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T48	8		T49	5		T50	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T49	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T50	2		T104	1		T97	1