Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1158334

1

T1

12

T3

3

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	323478	1			T1	103		T3	3		T4	3
values[0x0]	437384	1			T14	17459		T15	20639		T16	33778
values[0x1]	453458	1			T14	18139		T15	21591		T16	34336

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1185840

1

T1

61

T3

3

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5168	1			T5	6		T14	153		T15	230
valid_sources[0x01]	5929	1			T14	214		T15	223		T68	2
valid_sources[0x02]	4115	1			T14	179		T15	220		T68	1
valid_sources[0x03]	3937	1			T14	186		T45	1		T15	212
valid_sources[0x04]	4128	1			T14	182		T15	232		T100	2
valid_sources[0x05]	4091	1			T14	150		T45	2		T15	210
valid_sources[0x06]	5175	1			T14	174		T15	200		T100	2
valid_sources[0x07]	4904	1			T7	10		T11	9		T14	168
valid_sources[0x08]	4401	1			T14	205		T15	224		T64	1
valid_sources[0x09]	4755	1			T14	184		T12	1		T15	232
valid_sources[0x0a]	4582	1			T14	152		T45	1		T15	241
valid_sources[0x0b]	4614	1			T13	2		T14	211		T15	220
valid_sources[0x0c]	4246	1			T14	170		T15	226		T100	6
valid_sources[0x0d]	4543	1			T14	172		T15	250		T64	1
valid_sources[0x0e]	4696	1			T14	202		T15	219		T64	2
valid_sources[0x0f]	4951	1			T14	202		T15	234		T116	1
valid_sources[0x10]	5647	1			T7	27		T14	203		T15	198
valid_sources[0x11]	4363	1			T14	204		T12	3		T15	218
valid_sources[0x12]	4418	1			T13	3		T14	200		T15	230
valid_sources[0x13]	4245	1			T14	183		T12	4		T15	198
valid_sources[0x14]	3901	1			T14	161		T15	210		T66	3
valid_sources[0x15]	3918	1			T5	3		T13	1		T14	166
valid_sources[0x16]	4001	1			T5	3		T14	167		T15	228
valid_sources[0x17]	3958	1			T7	18		T13	1		T14	173
valid_sources[0x18]	5113	1			T9	52		T14	156		T15	194
valid_sources[0x19]	4581	1			T5	10		T14	192		T15	217
valid_sources[0x1a]	4520	1			T14	201		T15	210		T116	1
valid_sources[0x1b]	7580	1			T14	178		T15	230		T64	2
valid_sources[0x1c]	5443	1			T14	190		T45	1		T15	237
valid_sources[0x1d]	4316	1			T14	201		T46	20		T15	253
valid_sources[0x1e]	4283	1			T13	2		T14	183		T12	1
valid_sources[0x1f]	5493	1			T14	206		T15	231		T100	3
valid_sources[0x20]	5474	1			T14	196		T15	228		T99	15
valid_sources[0x21]	4672	1			T14	230		T15	218		T100	1
valid_sources[0x22]	4432	1			T13	1		T14	179		T15	231
valid_sources[0x23]	5554	1			T14	167		T15	216		T64	2
valid_sources[0x24]	4512	1			T14	229		T12	3		T15	202
valid_sources[0x25]	5406	1			T14	167		T15	213		T100	1
valid_sources[0x26]	5040	1			T14	194		T15	204		T117	1
valid_sources[0x27]	5442	1			T14	181		T12	2		T15	238
valid_sources[0x28]	4111	1			T4	1		T14	128		T15	222
valid_sources[0x29]	6052	1			T14	179		T15	208		T100	2
valid_sources[0x2a]	4585	1			T14	171		T15	203		T64	2
valid_sources[0x2b]	4134	1			T3	3		T14	184		T15	217
valid_sources[0x2c]	4540	1			T14	157		T15	211		T118	5
valid_sources[0x2d]	4656	1			T14	190		T15	223		T118	4
valid_sources[0x2e]	4811	1			T14	217		T15	221		T100	1
valid_sources[0x2f]	4909	1			T14	159		T46	2		T15	242
valid_sources[0x30]	4707	1			T14	190		T45	1		T15	230
valid_sources[0x31]	4421	1			T14	198		T15	222		T100	1
valid_sources[0x32]	4160	1			T14	178		T12	1		T15	213
valid_sources[0x33]	5685	1			T14	193		T12	4		T46	1
valid_sources[0x34]	4564	1			T14	184		T12	1		T15	188
valid_sources[0x35]	4785	1			T14	223		T12	3		T15	263
valid_sources[0x36]	4577	1			T14	186		T15	239		T118	4
valid_sources[0x37]	3878	1			T11	5		T14	177		T12	2
valid_sources[0x38]	4323	1			T14	159		T15	235		T119	3
valid_sources[0x39]	4507	1			T14	203		T45	2		T15	225
valid_sources[0x3a]	4535	1			T14	180		T15	225		T100	3
valid_sources[0x3b]	5877	1			T11	9		T14	191		T46	9
valid_sources[0x3c]	3994	1			T14	187		T15	236		T27	6
valid_sources[0x3d]	4852	1			T14	161		T15	220		T64	1
valid_sources[0x3e]	4440	1			T14	187		T15	227		T118	3
valid_sources[0x3f]	4301	1			T13	1		T14	155		T15	232
valid_sources[0x40]	4558	1			T14	217		T15	226		T64	1
valid_sources[0x41]	6628	1			T14	195		T15	208		T64	1
valid_sources[0x42]	5829	1			T14	179		T15	245		T100	1
valid_sources[0x43]	5720	1			T14	194		T15	213		T64	1
valid_sources[0x44]	5160	1			T14	191		T15	238		T67	1
valid_sources[0x45]	4350	1			T11	5		T14	193		T45	2
valid_sources[0x46]	4351	1			T14	186		T45	2		T15	243
valid_sources[0x47]	4909	1			T1	10		T13	3		T14	225
valid_sources[0x48]	5274	1			T14	210		T15	223		T116	1
valid_sources[0x49]	4637	1			T11	15		T14	189		T15	222
valid_sources[0x4a]	4556	1			T7	1		T14	177		T12	1
valid_sources[0x4b]	5270	1			T14	180		T15	238		T100	1
valid_sources[0x4c]	4908	1			T14	214		T15	210		T64	1
valid_sources[0x4d]	5849	1			T1	23		T14	199		T45	2
valid_sources[0x4e]	4451	1			T14	184		T15	226		T120	5
valid_sources[0x4f]	5530	1			T14	171		T45	2		T15	235
valid_sources[0x50]	4902	1			T14	208		T15	214		T121	1
valid_sources[0x51]	4861	1			T13	1		T14	189		T15	220
valid_sources[0x52]	4398	1			T13	1		T14	190		T15	211
valid_sources[0x53]	4715	1			T14	213		T15	225		T116	1
valid_sources[0x54]	5617	1			T14	175		T15	210		T64	3
valid_sources[0x55]	4619	1			T14	204		T15	209		T118	4
valid_sources[0x56]	6054	1			T5	1		T14	209		T15	224
valid_sources[0x57]	4830	1			T14	163		T12	2		T15	212
valid_sources[0x58]	4985	1			T14	180		T15	225		T64	1
valid_sources[0x59]	4913	1			T14	170		T15	242		T64	1
valid_sources[0x5a]	4943	1			T14	216		T45	1		T15	225
valid_sources[0x5b]	4378	1			T14	196		T15	247		T115	1
valid_sources[0x5c]	4638	1			T13	1		T14	199		T15	229
valid_sources[0x5d]	4123	1			T14	161		T12	1		T15	226
valid_sources[0x5e]	4506	1			T14	190		T15	230		T68	1
valid_sources[0x5f]	4637	1			T14	175		T45	3		T15	213
valid_sources[0x60]	4241	1			T14	170		T15	233		T116	3
valid_sources[0x61]	4570	1			T13	3		T14	201		T15	199
valid_sources[0x62]	4399	1			T5	1		T13	3		T14	185
valid_sources[0x63]	4004	1			T14	196		T15	246		T64	1
valid_sources[0x64]	4556	1			T14	182		T15	242		T100	2
valid_sources[0x65]	5627	1			T14	166		T15	243		T117	2
valid_sources[0x66]	4977	1			T14	191		T45	3		T15	226
valid_sources[0x67]	3925	1			T13	2		T14	185		T12	2
valid_sources[0x68]	6092	1			T14	219		T15	243		T64	1
valid_sources[0x69]	4560	1			T13	1		T14	152		T15	189
valid_sources[0x6a]	5271	1			T14	218		T15	200		T64	1
valid_sources[0x6b]	5008	1			T14	218		T12	2		T15	204
valid_sources[0x6c]	4434	1			T14	222		T15	231		T67	1
valid_sources[0x6d]	4757	1			T14	196		T15	249		T121	1
valid_sources[0x6e]	4614	1			T14	180		T15	219		T100	2
valid_sources[0x6f]	7038	1			T5	1		T13	3		T14	179
valid_sources[0x70]	4223	1			T11	6		T14	194		T15	229
valid_sources[0x71]	4784	1			T5	1		T14	204		T45	3
valid_sources[0x72]	5160	1			T14	209		T15	225		T66	2
valid_sources[0x73]	4108	1			T7	3		T14	228		T15	223
valid_sources[0x74]	4038	1			T14	172		T45	4		T15	201
valid_sources[0x75]	4132	1			T14	181		T15	239		T100	1
valid_sources[0x76]	4909	1			T5	1		T11	14		T14	195
valid_sources[0x77]	3923	1			T5	8		T13	1		T14	156
valid_sources[0x78]	5318	1			T5	3		T11	1		T14	167
valid_sources[0x79]	4031	1			T14	146		T15	215		T100	3
valid_sources[0x7a]	4352	1			T11	2		T14	230		T15	252
valid_sources[0x7b]	4576	1			T5	6		T14	166		T15	210
valid_sources[0x7c]	4353	1			T14	163		T45	2		T15	198
valid_sources[0x7d]	4411	1			T11	10		T14	176		T15	255
valid_sources[0x7e]	4695	1			T14	184		T12	2		T15	251
valid_sources[0x7f]	4464	1			T5	2		T9	34		T14	220
valid_sources[0x80]	4122	1			T14	188		T15	268		T64	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

291330

1

T1

12

T3

3

T4

3

values[0x0]

all_enables

biggest_size

433389

1

T14

17300

T15

20422

T16

33518

values[0x1]

all_enables

biggest_size

433615

1

T14

17334

T15

20632

T16

32958

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

897766

1

T2

5

T3

7

T4

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	249536	1			T3	16		T4	34		T5	32
values[0x0]	341942	1			T2	6		T10	5		T31	7
values[0x1]	396449	1			T2	5		T10	5		T31	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41482	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

946445

1

T2

6

T3

8

T4

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3395	1			T14	153		T45	1		T16	280
valid_sources[0x01]	4238	1			T14	191		T15	271		T47	1
valid_sources[0x02]	4006	1			T14	152		T46	1		T15	120
valid_sources[0x03]	3744	1			T10	10		T11	1		T14	178
valid_sources[0x04]	3342	1			T11	2		T14	157		T12	2
valid_sources[0x05]	3454	1			T14	138		T15	540		T114	1
valid_sources[0x06]	4052	1			T4	1		T14	138		T15	452
valid_sources[0x07]	4548	1			T14	154		T15	249		T115	1
valid_sources[0x08]	4030	1			T14	162		T45	1		T122	2
valid_sources[0x09]	3822	1			T2	11		T14	181		T15	11
valid_sources[0x0a]	3656	1			T14	136		T15	437		T65	1
valid_sources[0x0b]	3765	1			T14	138		T45	1		T123	1
valid_sources[0x0c]	3280	1			T14	172		T12	1		T15	3
valid_sources[0x0d]	3490	1			T4	1		T13	2		T11	1
valid_sources[0x0e]	4123	1			T14	153		T15	103		T16	336
valid_sources[0x0f]	3316	1			T14	139		T12	3		T45	1
valid_sources[0x10]	4905	1			T11	1		T14	174		T15	120
valid_sources[0x11]	3556	1			T7	1		T14	136		T15	140
valid_sources[0x12]	4527	1			T14	143		T15	550		T16	308
valid_sources[0x13]	4540	1			T11	1		T14	160		T15	645
valid_sources[0x14]	3751	1			T7	1		T14	150		T15	64
valid_sources[0x15]	4841	1			T4	1		T14	140		T45	1
valid_sources[0x16]	4723	1			T7	1		T11	1		T14	162
valid_sources[0x17]	3740	1			T13	1		T11	1		T14	134
valid_sources[0x18]	3802	1			T14	139		T15	207		T124	1
valid_sources[0x19]	3538	1			T4	1		T14	137		T15	185
valid_sources[0x1a]	3940	1			T14	191		T12	3		T45	1
valid_sources[0x1b]	4047	1			T11	2		T14	125		T15	4
valid_sources[0x1c]	3924	1			T14	134		T12	2		T15	350
valid_sources[0x1d]	4074	1			T31	1		T14	140		T15	615
valid_sources[0x1e]	4156	1			T14	152		T15	388		T16	277
valid_sources[0x1f]	3775	1			T11	1		T14	147		T15	4
valid_sources[0x20]	3737	1			T3	6		T14	130		T15	3
valid_sources[0x21]	4420	1			T14	134		T45	1		T15	79
valid_sources[0x22]	4836	1			T4	1		T14	135		T15	243
valid_sources[0x23]	3648	1			T14	164		T15	319		T16	271
valid_sources[0x24]	4071	1			T5	16		T14	146		T15	529
valid_sources[0x25]	3613	1			T11	1		T14	137		T15	215
valid_sources[0x26]	3972	1			T11	1		T14	142		T15	6
valid_sources[0x27]	3647	1			T4	1		T14	162		T15	402
valid_sources[0x28]	4277	1			T11	1		T14	143		T15	483
valid_sources[0x29]	4697	1			T14	168		T15	205		T125	6
valid_sources[0x2a]	3889	1			T14	169		T15	152		T122	2
valid_sources[0x2b]	3071	1			T7	1		T14	151		T126	1
valid_sources[0x2c]	4634	1			T14	143		T15	375		T124	3
valid_sources[0x2d]	4092	1			T14	119		T15	292		T28	1
valid_sources[0x2e]	4172	1			T14	141		T28	3		T124	1
valid_sources[0x2f]	4388	1			T7	1		T14	140		T15	203
valid_sources[0x30]	3870	1			T5	7		T11	1		T14	147
valid_sources[0x31]	2993	1			T14	179		T12	2		T15	17
valid_sources[0x32]	3594	1			T14	141		T46	2		T15	5
valid_sources[0x33]	3048	1			T14	166		T15	126		T114	1
valid_sources[0x34]	4238	1			T14	155		T15	12		T53	12
valid_sources[0x35]	3076	1			T14	165		T15	4		T28	1
valid_sources[0x36]	3848	1			T14	161		T15	106		T16	332
valid_sources[0x37]	4289	1			T14	163		T45	1		T15	479
valid_sources[0x38]	4225	1			T14	169		T12	7		T45	1
valid_sources[0x39]	4234	1			T14	172		T15	694		T115	1
valid_sources[0x3a]	3182	1			T14	177		T15	88		T67	64
valid_sources[0x3b]	2744	1			T14	145		T15	18		T16	295
valid_sources[0x3c]	3281	1			T7	1		T11	1		T14	116
valid_sources[0x3d]	3484	1			T11	1		T14	184		T15	1
valid_sources[0x3e]	3944	1			T14	155		T15	123		T47	1
valid_sources[0x3f]	4705	1			T14	147		T12	2		T15	507
valid_sources[0x40]	3754	1			T11	1		T14	138		T15	374
valid_sources[0x41]	4128	1			T7	1		T11	1		T14	173
valid_sources[0x42]	3126	1			T14	147		T15	296		T16	357
valid_sources[0x43]	3899	1			T14	121		T15	209		T16	297
valid_sources[0x44]	4083	1			T13	1		T14	139		T12	3
valid_sources[0x45]	3533	1			T6	10		T11	1		T14	154
valid_sources[0x46]	4112	1			T14	171		T15	92		T65	1
valid_sources[0x47]	5055	1			T14	164		T16	315		T37	660
valid_sources[0x48]	3118	1			T5	4		T14	144		T46	1
valid_sources[0x49]	4056	1			T14	156		T43	1		T15	194
valid_sources[0x4a]	3946	1			T4	1		T13	1		T14	142
valid_sources[0x4b]	4394	1			T14	133		T46	2		T15	611
valid_sources[0x4c]	4148	1			T11	2		T14	147		T15	538
valid_sources[0x4d]	3993	1			T11	1		T14	164		T12	2
valid_sources[0x4e]	4791	1			T14	121		T15	379		T65	1
valid_sources[0x4f]	3895	1			T11	1		T14	129		T15	337
valid_sources[0x50]	3594	1			T13	2		T14	115		T15	92
valid_sources[0x51]	3575	1			T11	1		T14	150		T15	108
valid_sources[0x52]	3203	1			T31	3		T14	168		T46	4
valid_sources[0x53]	3909	1			T7	1		T8	1		T14	150
valid_sources[0x54]	5092	1			T14	151		T15	96		T117	1
valid_sources[0x55]	3418	1			T14	138		T45	1		T46	3
valid_sources[0x56]	4158	1			T13	1		T14	127		T15	130
valid_sources[0x57]	4803	1			T4	1		T7	1		T14	150
valid_sources[0x58]	4188	1			T14	167		T15	3		T117	1
valid_sources[0x59]	3664	1			T14	164		T15	251		T65	1
valid_sources[0x5a]	4108	1			T13	1		T14	135		T15	25
valid_sources[0x5b]	3308	1			T14	163		T15	337		T16	288
valid_sources[0x5c]	3435	1			T4	1		T14	142		T24	1
valid_sources[0x5d]	3693	1			T14	176		T15	134		T127	1
valid_sources[0x5e]	4054	1			T14	169		T15	68		T65	1
valid_sources[0x5f]	4169	1			T14	144		T15	156		T28	1
valid_sources[0x60]	4528	1			T7	2		T14	153		T15	108
valid_sources[0x61]	4906	1			T11	1		T14	175		T15	187
valid_sources[0x62]	3696	1			T14	165		T15	51		T28	2
valid_sources[0x63]	4619	1			T5	2		T11	2		T14	144
valid_sources[0x64]	4357	1			T7	1		T14	145		T15	5
valid_sources[0x65]	4124	1			T14	163		T15	571		T28	1
valid_sources[0x66]	3750	1			T14	129		T15	1		T128	1
valid_sources[0x67]	4404	1			T7	1		T14	148		T45	1
valid_sources[0x68]	3866	1			T11	1		T14	153		T15	276
valid_sources[0x69]	3480	1			T4	2		T14	158		T15	154
valid_sources[0x6a]	4256	1			T14	167		T15	161		T28	1
valid_sources[0x6b]	3561	1			T14	175		T15	2		T47	1
valid_sources[0x6c]	3476	1			T14	122		T15	165		T129	1
valid_sources[0x6d]	3099	1			T14	152		T15	2		T16	268
valid_sources[0x6e]	3487	1			T4	1		T7	1		T11	1
valid_sources[0x6f]	4385	1			T14	180		T15	300		T115	1
valid_sources[0x70]	4200	1			T14	128		T15	1		T65	1
valid_sources[0x71]	3887	1			T14	158		T123	5		T16	403
valid_sources[0x72]	2782	1			T11	1		T14	179		T12	1
valid_sources[0x73]	3409	1			T14	148		T12	1		T15	98
valid_sources[0x74]	4089	1			T11	1		T14	147		T15	341
valid_sources[0x75]	3665	1			T11	1		T14	138		T15	5
valid_sources[0x76]	3636	1			T14	160		T15	200		T64	32
valid_sources[0x77]	4264	1			T4	1		T31	1		T14	121
valid_sources[0x78]	4338	1			T14	112		T15	391		T128	3
valid_sources[0x79]	4080	1			T14	136		T15	185		T47	1
valid_sources[0x7a]	4485	1			T14	159		T15	365		T16	329
valid_sources[0x7b]	4006	1			T14	154		T15	431		T117	1
valid_sources[0x7c]	3362	1			T31	1		T14	136		T130	1
valid_sources[0x7d]	4070	1			T14	141		T15	359		T16	310
valid_sources[0x7e]	3585	1			T11	2		T14	140		T15	108
valid_sources[0x7f]	3816	1			T14	131		T15	249		T68	7
valid_sources[0x80]	3728	1			T14	194		T15	6		T124	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

227713

1

T3

7

T4

18

T5

14

values[0x0]

all_enables

biggest_size

334713

1

T2

5

T10

2

T31

3

values[0x1]

all_enables

biggest_size

335340

1

T10

1

T31

1

T14

13099