Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2126882

1

T1

91

T5

65

T7

67

full_word

1352227

1

T1

12

T3

2

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3478839	1			T1	103		T3	2		T4	2
auto[TlIntgErrCmd]	83	1			T48	2		T49	4		T50	5
auto[TlIntgErrData]	101	1			T48	4		T49	4		T50	8
auto[TlIntgErrBoth]	86	1			T48	4		T49	2		T50	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559612

1

T1

103

T3

2

T4

2

auto[1]

2919497

1

T14

114358

T15

139616

T16

216325

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	239943	1			T1	91		T5	65		T7	67
auto[TlIntgErrNone]	partial	auto[1]	1886699	1			T14	73394		T15	90712		T16	137698
auto[TlIntgErrNone]	full_word	auto[0]	319551	1			T1	12		T3	2		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	1032646	1			T14	40964		T15	48904		T16	78627
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T48	1		T49	1		T103	2
auto[TlIntgErrCmd]	partial	auto[1]	35	1			T48	1		T49	3		T50	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T111	1		T112	2		T107	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T50	2		T110	1		T104	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T48	2		T49	2		T50	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T48	2		T49	2		T50	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T50	1		T103	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T111	1		T104	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	24	1			T48	1		T50	2		T103	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T48	2		T49	2		T50	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T105	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T48	1		T111	1		T105	1