Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2627075

1

T1

288

T2

84

T5

176

full_word

1667341

1

T1

15

T2

11

T4

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4294136	1			T1	303		T2	95		T4	6
auto[TlIntgErrCmd]	85	1			T58	5		T59	4		T60	2
auto[TlIntgErrData]	101	1			T58	2		T59	1		T60	4
auto[TlIntgErrBoth]	94	1			T58	3		T59	5		T60	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

685094

1

T1

303

T2

95

T4

6

auto[1]

3609322

1

T11

290115

T17

206056

T18

138023

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	290683	1			T1	288		T2	84		T5	176
auto[TlIntgErrNone]	partial	auto[1]	2336134	1			T11	184763		T17	134891		T18	89104
auto[TlIntgErrNone]	full_word	auto[0]	394285	1			T1	15		T2	11		T4	6
auto[TlIntgErrNone]	full_word	auto[1]	1273034	1			T11	105352		T17	71165		T18	48919
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T58	1		T59	1		T60	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T58	4		T59	3		T60	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T107	1		T117	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T112	1		T118	1		T109	2
auto[TlIntgErrData]	partial	auto[0]	48	1			T58	1		T59	1		T107	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T58	1		T60	3		T107	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T60	1		T107	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T107	1		T109	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T59	3		T60	1		T107	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T58	3		T59	2		T60	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T108	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T107	1		T119	1		T120	1