Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

721807

1

T3

6

T4

10

T5

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	208426	1			T3	6		T4	212		T5	169
values[0x0]	272038	1			T17	37309		T18	23898		T19	19503
values[0x1]	283381	1			T17	39644		T18	24496		T19	20461

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

743020

1

T3

6

T4

119

T5

91

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2908	1			T6	1		T17	331		T126	4
valid_sources[0x01]	3014	1			T8	2		T13	1		T15	11
valid_sources[0x02]	2869	1			T11	7		T17	312		T127	2
valid_sources[0x03]	2887	1			T17	381		T51	1		T126	1
valid_sources[0x04]	2913	1			T6	2		T13	1		T15	1
valid_sources[0x05]	2964	1			T4	12		T11	2		T17	368
valid_sources[0x06]	2925	1			T13	1		T17	434		T128	1
valid_sources[0x07]	2897	1			T13	1		T11	1		T17	391
valid_sources[0x08]	2914	1			T17	405		T127	1		T29	1
valid_sources[0x09]	3093	1			T13	2		T17	400		T51	1
valid_sources[0x0a]	3171	1			T13	2		T17	481		T128	1
valid_sources[0x0b]	2983	1			T17	424		T18	249		T19	209
valid_sources[0x0c]	2929	1			T17	439		T51	1		T18	224
valid_sources[0x0d]	3050	1			T13	1		T17	316		T51	1
valid_sources[0x0e]	2998	1			T6	8		T14	86		T13	1
valid_sources[0x0f]	2957	1			T11	4		T17	354		T51	1
valid_sources[0x10]	2971	1			T17	485		T51	1		T18	228
valid_sources[0x11]	2962	1			T15	27		T17	427		T127	2
valid_sources[0x12]	3094	1			T17	435		T51	2		T128	1
valid_sources[0x13]	3036	1			T13	2		T16	3		T17	381
valid_sources[0x14]	2860	1			T13	1		T17	367		T51	1
valid_sources[0x15]	3054	1			T13	2		T11	1		T17	455
valid_sources[0x16]	3125	1			T17	426		T51	1		T18	263
valid_sources[0x17]	2689	1			T5	2		T13	1		T17	362
valid_sources[0x18]	3045	1			T5	5		T13	1		T17	428
valid_sources[0x19]	2996	1			T13	1		T17	399		T127	1
valid_sources[0x1a]	3024	1			T17	397		T128	1		T129	1
valid_sources[0x1b]	3071	1			T17	398		T56	2		T127	1
valid_sources[0x1c]	2887	1			T13	2		T17	399		T128	2
valid_sources[0x1d]	3104	1			T17	512		T127	1		T130	1
valid_sources[0x1e]	2976	1			T17	368		T51	1		T131	12
valid_sources[0x1f]	2689	1			T17	396		T127	1		T129	1
valid_sources[0x20]	2909	1			T8	5		T17	379		T51	1
valid_sources[0x21]	2969	1			T13	2		T17	418		T51	1
valid_sources[0x22]	2944	1			T6	2		T17	374		T126	23
valid_sources[0x23]	2873	1			T13	2		T17	349		T127	1
valid_sources[0x24]	2758	1			T8	10		T11	4		T12	4
valid_sources[0x25]	3026	1			T6	4		T13	2		T15	34
valid_sources[0x26]	2953	1			T13	1		T17	378		T50	8
valid_sources[0x27]	3005	1			T17	375		T129	1		T18	235
valid_sources[0x28]	3235	1			T5	1		T6	1		T14	42
valid_sources[0x29]	3115	1			T13	5		T17	438		T51	1
valid_sources[0x2a]	3110	1			T17	398		T50	18		T51	1
valid_sources[0x2b]	2930	1			T11	1		T17	386		T51	2
valid_sources[0x2c]	3119	1			T17	325		T50	21		T56	1
valid_sources[0x2d]	2975	1			T13	1		T11	2		T17	371
valid_sources[0x2e]	3067	1			T11	6		T17	377		T18	254
valid_sources[0x2f]	3051	1			T17	422		T56	2		T126	7
valid_sources[0x30]	3095	1			T17	403		T51	1		T126	6
valid_sources[0x31]	2865	1			T13	1		T15	4		T17	462
valid_sources[0x32]	3116	1			T13	4		T11	1		T17	431
valid_sources[0x33]	3193	1			T13	1		T17	506		T51	2
valid_sources[0x34]	3011	1			T13	3		T11	10		T24	3
valid_sources[0x35]	2969	1			T17	467		T129	2		T18	257
valid_sources[0x36]	2995	1			T5	6		T6	3		T17	417
valid_sources[0x37]	2972	1			T6	1		T13	1		T17	411
valid_sources[0x38]	2918	1			T17	380		T56	1		T128	1
valid_sources[0x39]	3010	1			T13	1		T17	504		T127	1
valid_sources[0x3a]	3099	1			T14	17		T17	402		T51	1
valid_sources[0x3b]	2922	1			T13	2		T17	381		T128	2
valid_sources[0x3c]	2944	1			T17	420		T128	1		T18	225
valid_sources[0x3d]	3052	1			T13	1		T17	398		T51	2
valid_sources[0x3e]	2995	1			T17	363		T126	1		T128	1
valid_sources[0x3f]	2826	1			T5	2		T6	3		T11	16
valid_sources[0x40]	3200	1			T17	440		T56	1		T128	1
valid_sources[0x41]	2960	1			T4	18		T8	4		T17	420
valid_sources[0x42]	2734	1			T6	1		T13	1		T17	357
valid_sources[0x43]	2990	1			T5	26		T17	384		T51	1
valid_sources[0x44]	2865	1			T17	412		T56	1		T127	1
valid_sources[0x45]	2869	1			T13	1		T17	363		T56	1
valid_sources[0x46]	2932	1			T13	1		T17	321		T51	1
valid_sources[0x47]	2886	1			T17	397		T18	263		T19	155
valid_sources[0x48]	2797	1			T5	4		T13	3		T17	323
valid_sources[0x49]	2931	1			T17	326		T51	1		T128	1
valid_sources[0x4a]	2891	1			T17	373		T131	18		T128	1
valid_sources[0x4b]	2751	1			T17	348		T51	2		T127	1
valid_sources[0x4c]	2811	1			T13	2		T17	363		T51	1
valid_sources[0x4d]	2915	1			T13	4		T17	437		T127	1
valid_sources[0x4e]	2968	1			T17	458		T127	1		T18	208
valid_sources[0x4f]	3000	1			T17	335		T51	1		T56	1
valid_sources[0x50]	2833	1			T17	428		T126	2		T18	224
valid_sources[0x51]	3089	1			T13	2		T15	2		T11	3
valid_sources[0x52]	3169	1			T6	1		T17	347		T128	3
valid_sources[0x53]	2982	1			T5	1		T6	4		T8	3
valid_sources[0x54]	2907	1			T17	402		T51	1		T76	2
valid_sources[0x55]	2872	1			T17	364		T51	2		T128	2
valid_sources[0x56]	3136	1			T11	2		T17	378		T18	312
valid_sources[0x57]	2988	1			T13	1		T11	4		T17	427
valid_sources[0x58]	2752	1			T4	14		T8	8		T13	1
valid_sources[0x59]	2963	1			T6	4		T11	6		T17	456
valid_sources[0x5a]	2880	1			T5	1		T13	1		T17	374
valid_sources[0x5b]	3228	1			T13	1		T17	403		T51	2
valid_sources[0x5c]	2984	1			T5	4		T11	2		T17	427
valid_sources[0x5d]	2892	1			T8	2		T13	2		T17	412
valid_sources[0x5e]	3173	1			T8	5		T13	1		T17	346
valid_sources[0x5f]	2929	1			T5	8		T13	5		T17	461
valid_sources[0x60]	2912	1			T5	3		T6	3		T17	379
valid_sources[0x61]	3191	1			T4	90		T6	1		T13	2
valid_sources[0x62]	2905	1			T8	1		T13	1		T17	382
valid_sources[0x63]	2986	1			T17	339		T128	1		T129	1
valid_sources[0x64]	3009	1			T13	2		T17	374		T131	3
valid_sources[0x65]	2924	1			T4	16		T17	412		T56	2
valid_sources[0x66]	2843	1			T17	375		T49	10		T129	2
valid_sources[0x67]	2918	1			T5	1		T12	1		T17	406
valid_sources[0x68]	2944	1			T13	1		T17	420		T51	1
valid_sources[0x69]	3159	1			T17	369		T127	2		T129	2
valid_sources[0x6a]	2700	1			T6	3		T13	1		T17	400
valid_sources[0x6b]	2995	1			T15	3		T12	6		T17	407
valid_sources[0x6c]	2961	1			T13	4		T11	1		T17	364
valid_sources[0x6d]	2974	1			T17	439		T56	1		T18	303
valid_sources[0x6e]	2846	1			T6	1		T14	12		T13	1
valid_sources[0x6f]	2916	1			T17	437		T51	2		T127	1
valid_sources[0x70]	2785	1			T17	402		T128	1		T130	3
valid_sources[0x71]	3143	1			T4	35		T6	1		T13	2
valid_sources[0x72]	2694	1			T13	4		T17	314		T127	2
valid_sources[0x73]	3071	1			T17	404		T51	1		T56	1
valid_sources[0x74]	3165	1			T17	429		T127	2		T128	1
valid_sources[0x75]	2949	1			T6	5		T15	35		T17	425
valid_sources[0x76]	3053	1			T11	3		T17	430		T130	2
valid_sources[0x77]	3048	1			T6	1		T17	454		T51	1
valid_sources[0x78]	2928	1			T4	3		T6	2		T17	394
valid_sources[0x79]	3017	1			T5	10		T13	5		T15	7
valid_sources[0x7a]	3033	1			T11	1		T17	414		T76	3
valid_sources[0x7b]	2840	1			T6	1		T17	407		T51	1
valid_sources[0x7c]	3127	1			T13	1		T17	401		T51	1
valid_sources[0x7d]	3071	1			T17	426		T51	1		T18	219
valid_sources[0x7e]	3172	1			T17	398		T50	8		T129	1
valid_sources[0x7f]	3108	1			T6	1		T17	398		T50	3
valid_sources[0x80]	2835	1			T14	11		T11	1		T17	404

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

181089

1

T3

6

T4

10

T5

10

values[0x0]

all_enables

biggest_size

269641

1

T17

36962

T18

23726

T19

19324

values[0x1]

all_enables

biggest_size

271077

1

T17

37929

T18

23481

T19

19593

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

565240

1

T1

17

T2

1

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	159650	1			T1	39		T2	1		T3	18
values[0x0]	215584	1			T34	7		T35	10		T36	3
values[0x1]	249364	1			T34	7		T35	7		T36	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596049

1

T1

23

T2

1

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2368	1			T17	354		T127	1		T18	198
valid_sources[0x01]	2635	1			T24	3		T17	302		T18	165
valid_sources[0x02]	2381	1			T20	4		T17	373		T76	1
valid_sources[0x03]	2569	1			T3	1		T17	341		T18	190
valid_sources[0x04]	3168	1			T12	1		T17	287		T56	5
valid_sources[0x05]	2344	1			T17	328		T18	201		T19	97
valid_sources[0x06]	2653	1			T3	2		T17	318		T76	1
valid_sources[0x07]	3092	1			T17	348		T54	1		T126	1
valid_sources[0x08]	2351	1			T17	310		T18	274		T19	140
valid_sources[0x09]	2096	1			T24	1		T17	367		T52	1
valid_sources[0x0a]	2650	1			T65	1		T17	363		T127	1
valid_sources[0x0b]	2378	1			T17	304		T126	1		T64	1
valid_sources[0x0c]	2592	1			T17	365		T76	1		T18	225
valid_sources[0x0d]	2066	1			T17	342		T18	191		T19	116
valid_sources[0x0e]	2760	1			T17	348		T126	1		T18	178
valid_sources[0x0f]	2171	1			T1	1		T12	1		T17	351
valid_sources[0x10]	2256	1			T17	316		T18	232		T19	179
valid_sources[0x11]	2181	1			T1	1		T35	5		T17	307
valid_sources[0x12]	2487	1			T17	322		T18	233		T19	195
valid_sources[0x13]	2288	1			T17	260		T18	201		T19	195
valid_sources[0x14]	2163	1			T12	3		T17	353		T126	2
valid_sources[0x15]	2421	1			T17	338		T126	1		T18	212
valid_sources[0x16]	2340	1			T17	341		T126	1		T18	220
valid_sources[0x17]	2514	1			T17	316		T18	179		T19	195
valid_sources[0x18]	2657	1			T17	322		T40	4		T18	213
valid_sources[0x19]	2382	1			T20	2		T17	357		T18	265
valid_sources[0x1a]	2207	1			T20	1		T17	364		T40	3
valid_sources[0x1b]	2035	1			T17	330		T18	211		T19	151
valid_sources[0x1c]	2288	1			T3	1		T17	357		T127	1
valid_sources[0x1d]	3352	1			T1	1		T17	334		T64	4
valid_sources[0x1e]	2450	1			T1	2		T17	285		T56	6
valid_sources[0x1f]	2040	1			T17	328		T52	1		T18	171
valid_sources[0x20]	2332	1			T17	341		T18	197		T19	159
valid_sources[0x21]	2142	1			T17	295		T18	182		T19	196
valid_sources[0x22]	2319	1			T17	342		T39	1		T18	207
valid_sources[0x23]	2995	1			T17	385		T126	3		T18	187
valid_sources[0x24]	1919	1			T17	308		T18	216		T19	177
valid_sources[0x25]	2712	1			T17	343		T126	1		T18	217
valid_sources[0x26]	2710	1			T1	1		T3	1		T17	324
valid_sources[0x27]	2500	1			T12	1		T17	330		T50	1
valid_sources[0x28]	2110	1			T17	337		T126	1		T18	248
valid_sources[0x29]	2524	1			T17	337		T50	1		T126	3
valid_sources[0x2a]	2551	1			T17	324		T132	1		T18	168
valid_sources[0x2b]	1889	1			T17	328		T76	1		T126	1
valid_sources[0x2c]	2479	1			T17	310		T18	202		T77	1
valid_sources[0x2d]	2497	1			T36	1		T17	340		T18	186
valid_sources[0x2e]	2306	1			T12	1		T17	313		T18	180
valid_sources[0x2f]	2647	1			T6	32		T36	3		T17	324
valid_sources[0x30]	2553	1			T17	332		T126	1		T18	177
valid_sources[0x31]	2353	1			T17	330		T40	4		T18	227
valid_sources[0x32]	2133	1			T3	1		T7	1		T24	3
valid_sources[0x33]	2051	1			T7	2		T17	283		T76	1
valid_sources[0x34]	2424	1			T17	351		T18	230		T19	168
valid_sources[0x35]	2800	1			T1	1		T17	341		T54	1
valid_sources[0x36]	1986	1			T17	351		T126	1		T18	174
valid_sources[0x37]	2774	1			T24	1		T17	372		T53	1
valid_sources[0x38]	2273	1			T7	1		T20	1		T17	324
valid_sources[0x39]	2084	1			T17	399		T18	193		T19	164
valid_sources[0x3a]	2588	1			T1	1		T17	335		T127	1
valid_sources[0x3b]	2713	1			T34	14		T17	320		T52	1
valid_sources[0x3c]	2378	1			T12	1		T17	320		T126	1
valid_sources[0x3d]	2636	1			T1	1		T17	354		T39	2
valid_sources[0x3e]	2617	1			T17	305		T52	2		T18	170
valid_sources[0x3f]	2234	1			T17	289		T126	1		T18	229
valid_sources[0x40]	2172	1			T17	299		T18	174		T19	152
valid_sources[0x41]	2577	1			T17	302		T18	171		T19	185
valid_sources[0x42]	2734	1			T17	336		T50	1		T126	2
valid_sources[0x43]	2129	1			T24	1		T17	340		T18	209
valid_sources[0x44]	2180	1			T17	310		T50	1		T76	1
valid_sources[0x45]	2081	1			T1	1		T24	1		T17	327
valid_sources[0x46]	2441	1			T3	1		T17	336		T50	1
valid_sources[0x47]	2770	1			T1	1		T24	1		T17	337
valid_sources[0x48]	2958	1			T17	318		T127	1		T18	242
valid_sources[0x49]	2460	1			T17	295		T18	212		T19	155
valid_sources[0x4a]	2364	1			T17	292		T127	4		T18	220
valid_sources[0x4b]	2395	1			T20	1		T17	315		T50	1
valid_sources[0x4c]	2347	1			T17	325		T50	1		T18	254
valid_sources[0x4d]	2129	1			T1	1		T24	2		T17	347
valid_sources[0x4e]	2023	1			T24	1		T17	340		T126	2
valid_sources[0x4f]	2275	1			T17	301		T126	1		T18	166
valid_sources[0x50]	2765	1			T12	1		T17	301		T39	1
valid_sources[0x51]	1976	1			T1	1		T17	326		T18	211
valid_sources[0x52]	2357	1			T17	338		T40	2		T18	235
valid_sources[0x53]	2735	1			T3	1		T17	336		T18	225
valid_sources[0x54]	2445	1			T12	3		T17	300		T18	190
valid_sources[0x55]	2295	1			T1	2		T17	326		T18	152
valid_sources[0x56]	2190	1			T1	1		T17	337		T127	1
valid_sources[0x57]	2547	1			T24	1		T17	364		T32	7
valid_sources[0x58]	2123	1			T17	325		T18	176		T19	190
valid_sources[0x59]	2381	1			T3	1		T17	381		T39	1
valid_sources[0x5a]	2838	1			T17	330		T18	228		T19	178
valid_sources[0x5b]	2379	1			T17	345		T64	1		T18	178
valid_sources[0x5c]	2898	1			T17	339		T126	1		T39	1
valid_sources[0x5d]	2095	1			T1	1		T17	289		T39	1
valid_sources[0x5e]	2359	1			T1	1		T7	1		T17	328
valid_sources[0x5f]	2788	1			T17	316		T126	1		T18	245
valid_sources[0x60]	2575	1			T17	307		T127	1		T18	198
valid_sources[0x61]	2835	1			T17	322		T50	3		T18	237
valid_sources[0x62]	3031	1			T17	331		T76	1		T39	1
valid_sources[0x63]	2413	1			T17	351		T129	64		T18	196
valid_sources[0x64]	2226	1			T7	1		T24	1		T17	294
valid_sources[0x65]	2945	1			T17	324		T18	170		T19	193
valid_sources[0x66]	2362	1			T17	338		T50	2		T18	195
valid_sources[0x67]	2260	1			T17	312		T39	2		T18	282
valid_sources[0x68]	2689	1			T17	316		T50	2		T126	1
valid_sources[0x69]	2924	1			T17	337		T76	1		T18	205
valid_sources[0x6a]	2541	1			T12	1		T17	354		T18	207
valid_sources[0x6b]	1797	1			T3	1		T17	333		T127	1
valid_sources[0x6c]	1996	1			T8	32		T17	359		T41	28
valid_sources[0x6d]	2077	1			T1	1		T17	297		T18	229
valid_sources[0x6e]	2481	1			T1	1		T2	1		T17	316
valid_sources[0x6f]	2899	1			T35	1		T17	325		T49	4
valid_sources[0x70]	2571	1			T17	343		T18	177		T19	252
valid_sources[0x71]	2471	1			T1	1		T17	305		T18	212
valid_sources[0x72]	1874	1			T3	1		T17	305		T50	1
valid_sources[0x73]	1972	1			T17	355		T126	1		T39	2
valid_sources[0x74]	2200	1			T35	3		T17	302		T50	1
valid_sources[0x75]	2556	1			T1	1		T3	1		T17	333
valid_sources[0x76]	2912	1			T17	321		T18	240		T19	152
valid_sources[0x77]	2022	1			T24	1		T17	369		T127	1
valid_sources[0x78]	2276	1			T17	309		T126	1		T18	222
valid_sources[0x79]	2586	1			T17	360		T18	183		T19	140
valid_sources[0x7a]	2357	1			T12	5		T17	308		T18	277
valid_sources[0x7b]	1901	1			T17	362		T55	2		T18	180
valid_sources[0x7c]	2829	1			T17	333		T127	1		T18	255
valid_sources[0x7d]	1932	1			T17	339		T40	1		T18	203
valid_sources[0x7e]	2627	1			T17	374		T126	1		T39	1
valid_sources[0x7f]	2234	1			T7	1		T17	344		T18	201
valid_sources[0x80]	3062	1			T17	325		T52	1		T18	217

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

143365

1

T1

17

T2

1

T3

9

values[0x0]

all_enables

biggest_size

210702

1

T34

2

T35

6

T17

28882

values[0x1]

all_enables

biggest_size

211173

1

T34

2

T35

2

T17

28930