Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1323667

1

T4

202

T5

159

T6

75

full_word

842005

1

T3

4

T4

10

T5

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2165332	1			T3	4		T4	212		T5	169
auto[TlIntgErrCmd]	118	1			T57	4		T58	4		T59	8
auto[TlIntgErrData]	103	1			T58	7		T59	5		T112	3
auto[TlIntgErrBoth]	119	1			T57	6		T58	9		T59	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

354143

1

T3

4

T4

212

T5

169

auto[1]

1811529

1

T17

255607

T18

155305

T19

126178

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155465	1			T4	202		T5	159		T6	75
auto[TlIntgErrNone]	partial	auto[1]	1167896	1			T17	166050		T18	99448		T19	80264
auto[TlIntgErrNone]	full_word	auto[0]	198519	1			T3	4		T4	10		T5	10
auto[TlIntgErrNone]	full_word	auto[1]	643452	1			T17	89557		T18	55857		T19	45914
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T58	2		T59	7		T112	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T57	3		T58	2		T59	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T112	1		T121	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T57	1		T123	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T58	2		T59	3		T112	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T58	4		T59	2		T112	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T112	1		T123	2		T116	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T58	1		T123	2		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T57	5		T58	3		T59	4
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T57	1		T58	5		T59	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T59	1		T124	2		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T58	1		T120	1		T125	1