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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 96.97 93.44 97.88 100.00 98.69 98.03 99.07


Total test records in report: 464
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T296 /workspace/coverage/default/7.rom_ctrl_stress_all.3383852449 May 21 12:33:04 PM PDT 24 May 21 12:33:48 PM PDT 24 16846759190 ps
T297 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.716800738 May 21 12:33:03 PM PDT 24 May 21 12:33:26 PM PDT 24 995932491 ps
T298 /workspace/coverage/default/9.rom_ctrl_smoke.3514942414 May 21 12:32:48 PM PDT 24 May 21 12:33:29 PM PDT 24 13725291562 ps
T299 /workspace/coverage/default/15.rom_ctrl_stress_all.2102984362 May 21 12:32:57 PM PDT 24 May 21 12:34:02 PM PDT 24 19018955842 ps
T300 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2408315057 May 21 12:32:55 PM PDT 24 May 21 12:34:51 PM PDT 24 9377437878 ps
T301 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4291598532 May 21 12:33:19 PM PDT 24 May 21 12:34:16 PM PDT 24 4076775237 ps
T302 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2750207475 May 21 12:32:50 PM PDT 24 May 21 12:33:09 PM PDT 24 175613023 ps
T303 /workspace/coverage/default/32.rom_ctrl_stress_all.2028845823 May 21 12:33:22 PM PDT 24 May 21 12:34:43 PM PDT 24 8954954497 ps
T304 /workspace/coverage/default/33.rom_ctrl_alert_test.4224000387 May 21 12:33:03 PM PDT 24 May 21 12:33:30 PM PDT 24 424485931 ps
T305 /workspace/coverage/default/47.rom_ctrl_smoke.160074695 May 21 12:33:23 PM PDT 24 May 21 12:34:14 PM PDT 24 7585071943 ps
T306 /workspace/coverage/default/38.rom_ctrl_alert_test.1479012326 May 21 12:33:20 PM PDT 24 May 21 12:33:54 PM PDT 24 523854060 ps
T307 /workspace/coverage/default/26.rom_ctrl_stress_all.1434239910 May 21 12:33:23 PM PDT 24 May 21 12:35:17 PM PDT 24 95034161774 ps
T308 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1741103872 May 21 12:33:24 PM PDT 24 May 21 12:34:18 PM PDT 24 12305964156 ps
T309 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3834494045 May 21 12:32:53 PM PDT 24 May 21 12:33:13 PM PDT 24 1725931998 ps
T310 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2597177717 May 21 12:33:08 PM PDT 24 May 21 12:38:43 PM PDT 24 67300171898 ps
T311 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1158547998 May 21 12:33:10 PM PDT 24 May 21 12:33:41 PM PDT 24 6025780166 ps
T312 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3173882232 May 21 12:32:48 PM PDT 24 May 21 12:38:53 PM PDT 24 37246148143 ps
T313 /workspace/coverage/default/20.rom_ctrl_smoke.2451697234 May 21 12:32:54 PM PDT 24 May 21 12:33:40 PM PDT 24 3797205820 ps
T314 /workspace/coverage/default/27.rom_ctrl_alert_test.2279782380 May 21 12:33:10 PM PDT 24 May 21 12:33:31 PM PDT 24 1035918304 ps
T315 /workspace/coverage/default/49.rom_ctrl_smoke.4240096393 May 21 12:33:26 PM PDT 24 May 21 12:34:14 PM PDT 24 2986191970 ps
T316 /workspace/coverage/default/1.rom_ctrl_stress_all.1769453293 May 21 12:33:07 PM PDT 24 May 21 12:33:38 PM PDT 24 278390634 ps
T317 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2818380900 May 21 12:33:20 PM PDT 24 May 21 12:33:59 PM PDT 24 1028655215 ps
T318 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2482442347 May 21 12:33:08 PM PDT 24 May 21 12:35:31 PM PDT 24 14413666522 ps
T319 /workspace/coverage/default/47.rom_ctrl_alert_test.4284529759 May 21 12:33:21 PM PDT 24 May 21 12:33:56 PM PDT 24 1151741233 ps
T320 /workspace/coverage/default/13.rom_ctrl_stress_all.3833614306 May 21 12:32:54 PM PDT 24 May 21 12:33:23 PM PDT 24 549871754 ps
T321 /workspace/coverage/default/3.rom_ctrl_alert_test.2121163817 May 21 12:33:18 PM PDT 24 May 21 12:33:53 PM PDT 24 853719167 ps
T322 /workspace/coverage/default/33.rom_ctrl_smoke.345795484 May 21 12:33:08 PM PDT 24 May 21 12:33:55 PM PDT 24 4108716224 ps
T323 /workspace/coverage/default/42.rom_ctrl_alert_test.4017225177 May 21 12:33:19 PM PDT 24 May 21 12:33:55 PM PDT 24 1056877485 ps
T324 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2805642006 May 21 12:32:44 PM PDT 24 May 21 12:33:11 PM PDT 24 4021575671 ps
T98 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2015714191 May 21 12:33:29 PM PDT 24 May 21 12:34:04 PM PDT 24 100104439 ps
T325 /workspace/coverage/default/43.rom_ctrl_alert_test.2239912493 May 21 12:33:27 PM PDT 24 May 21 12:34:00 PM PDT 24 85734841 ps
T326 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1455366440 May 21 12:33:21 PM PDT 24 May 21 12:34:04 PM PDT 24 6066475758 ps
T327 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2239177138 May 21 12:33:02 PM PDT 24 May 21 12:33:34 PM PDT 24 3443515854 ps
T328 /workspace/coverage/default/30.rom_ctrl_alert_test.1237107347 May 21 12:33:09 PM PDT 24 May 21 12:33:35 PM PDT 24 1659409522 ps
T329 /workspace/coverage/default/40.rom_ctrl_alert_test.1339123586 May 21 12:33:21 PM PDT 24 May 21 12:34:03 PM PDT 24 8157076204 ps
T330 /workspace/coverage/default/22.rom_ctrl_stress_all.251273527 May 21 12:32:56 PM PDT 24 May 21 12:33:25 PM PDT 24 8011956417 ps
T331 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2397133304 May 21 12:33:00 PM PDT 24 May 21 12:34:10 PM PDT 24 4000068777 ps
T332 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.112373581 May 21 12:32:59 PM PDT 24 May 21 12:33:20 PM PDT 24 371764502 ps
T333 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3890024277 May 21 12:33:10 PM PDT 24 May 21 12:33:37 PM PDT 24 831676220 ps
T334 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4248778717 May 21 12:33:18 PM PDT 24 May 21 01:15:40 PM PDT 24 273203150254 ps
T335 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1115283589 May 21 12:33:20 PM PDT 24 May 21 12:36:36 PM PDT 24 5625551957 ps
T336 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2533124805 May 21 12:32:48 PM PDT 24 May 21 12:43:01 PM PDT 24 16383784168 ps
T337 /workspace/coverage/default/5.rom_ctrl_stress_all.652353785 May 21 12:32:59 PM PDT 24 May 21 12:33:22 PM PDT 24 795533749 ps
T338 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2122282955 May 21 12:33:05 PM PDT 24 May 21 12:33:30 PM PDT 24 3795685220 ps
T339 /workspace/coverage/default/18.rom_ctrl_alert_test.1607159617 May 21 12:33:17 PM PDT 24 May 21 12:33:51 PM PDT 24 5228309172 ps
T340 /workspace/coverage/default/39.rom_ctrl_smoke.591780772 May 21 12:33:23 PM PDT 24 May 21 12:34:02 PM PDT 24 201270941 ps
T341 /workspace/coverage/default/45.rom_ctrl_alert_test.180307956 May 21 12:33:17 PM PDT 24 May 21 12:33:45 PM PDT 24 829997183 ps
T342 /workspace/coverage/default/46.rom_ctrl_stress_all.1715019750 May 21 12:33:28 PM PDT 24 May 21 12:35:19 PM PDT 24 18152156747 ps
T343 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1974917621 May 21 12:33:17 PM PDT 24 May 21 12:33:46 PM PDT 24 836454470 ps
T344 /workspace/coverage/default/29.rom_ctrl_stress_all.1336333207 May 21 12:33:17 PM PDT 24 May 21 12:34:16 PM PDT 24 2749306365 ps
T345 /workspace/coverage/default/5.rom_ctrl_alert_test.2654541608 May 21 12:32:40 PM PDT 24 May 21 12:32:54 PM PDT 24 1315253647 ps
T346 /workspace/coverage/default/14.rom_ctrl_stress_all.3294995690 May 21 12:33:15 PM PDT 24 May 21 12:34:33 PM PDT 24 68304081570 ps
T347 /workspace/coverage/default/6.rom_ctrl_smoke.3427639862 May 21 12:32:57 PM PDT 24 May 21 12:33:34 PM PDT 24 5235599788 ps
T348 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1704404668 May 21 12:33:28 PM PDT 24 May 21 12:37:25 PM PDT 24 68006807127 ps
T349 /workspace/coverage/default/15.rom_ctrl_alert_test.2001695652 May 21 12:33:01 PM PDT 24 May 21 12:33:23 PM PDT 24 903751568 ps
T350 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3404180966 May 21 12:33:20 PM PDT 24 May 21 12:35:56 PM PDT 24 2151786293 ps
T351 /workspace/coverage/default/27.rom_ctrl_stress_all.3669212970 May 21 12:33:23 PM PDT 24 May 21 12:34:23 PM PDT 24 4173583661 ps
T352 /workspace/coverage/default/23.rom_ctrl_stress_all.360079819 May 21 12:32:59 PM PDT 24 May 21 12:34:04 PM PDT 24 25233834881 ps
T353 /workspace/coverage/default/16.rom_ctrl_alert_test.3585595936 May 21 12:33:06 PM PDT 24 May 21 12:33:25 PM PDT 24 164917498 ps
T354 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3025409751 May 21 12:33:08 PM PDT 24 May 21 12:33:39 PM PDT 24 7959440479 ps
T355 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.19514155 May 21 12:33:03 PM PDT 24 May 21 12:33:27 PM PDT 24 623648157 ps
T356 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2499286327 May 21 12:33:00 PM PDT 24 May 21 12:33:24 PM PDT 24 5283514293 ps
T357 /workspace/coverage/default/3.rom_ctrl_stress_all.2141891326 May 21 12:32:47 PM PDT 24 May 21 12:33:33 PM PDT 24 3731726952 ps
T358 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3281679434 May 21 12:33:09 PM PDT 24 May 21 12:36:12 PM PDT 24 9315272088 ps
T359 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3693245580 May 21 12:33:14 PM PDT 24 May 21 12:33:38 PM PDT 24 202572054 ps
T360 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.656146230 May 21 12:32:49 PM PDT 24 May 21 12:33:14 PM PDT 24 1745761993 ps
T361 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3796402857 May 21 12:33:19 PM PDT 24 May 21 12:35:57 PM PDT 24 7192174898 ps
T362 /workspace/coverage/default/11.rom_ctrl_smoke.3572058441 May 21 12:32:45 PM PDT 24 May 21 12:33:34 PM PDT 24 5402487526 ps
T363 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3909986167 May 21 12:33:08 PM PDT 24 May 21 12:41:29 PM PDT 24 540917376628 ps
T55 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3976131114 May 21 12:32:49 PM PDT 24 May 21 12:33:05 PM PDT 24 158237673 ps
T56 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4289644919 May 21 12:32:13 PM PDT 24 May 21 12:32:19 PM PDT 24 88899339 ps
T57 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.453037329 May 21 12:32:40 PM PDT 24 May 21 12:32:54 PM PDT 24 353400806 ps
T364 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.260978724 May 21 12:33:05 PM PDT 24 May 21 12:33:27 PM PDT 24 88953681 ps
T62 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.340076401 May 21 12:32:36 PM PDT 24 May 21 12:33:05 PM PDT 24 863029752 ps
T365 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.768000836 May 21 12:32:36 PM PDT 24 May 21 12:32:58 PM PDT 24 7527739961 ps
T94 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.331021536 May 21 12:32:39 PM PDT 24 May 21 12:32:56 PM PDT 24 2352599676 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4102466694 May 21 12:32:16 PM PDT 24 May 21 12:32:23 PM PDT 24 87740669 ps
T64 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.325325065 May 21 12:32:38 PM PDT 24 May 21 12:34:18 PM PDT 24 74158067991 ps
T366 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1414439151 May 21 12:32:41 PM PDT 24 May 21 12:32:57 PM PDT 24 1299069284 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1312509927 May 21 12:32:27 PM PDT 24 May 21 12:32:35 PM PDT 24 2209324081 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.831825957 May 21 12:32:23 PM PDT 24 May 21 12:32:31 PM PDT 24 1496088256 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1536479728 May 21 12:32:35 PM PDT 24 May 21 12:32:54 PM PDT 24 1886099510 ps
T99 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3668525869 May 21 12:32:33 PM PDT 24 May 21 12:32:44 PM PDT 24 382823656 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3509821522 May 21 12:32:23 PM PDT 24 May 21 12:32:34 PM PDT 24 3577206345 ps
T66 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3137077451 May 21 12:32:35 PM PDT 24 May 21 12:32:49 PM PDT 24 2781450225 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3491132277 May 21 12:32:16 PM PDT 24 May 21 12:32:25 PM PDT 24 574053464 ps
T52 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3996906252 May 21 12:32:52 PM PDT 24 May 21 12:33:42 PM PDT 24 2141792799 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2441165293 May 21 12:32:48 PM PDT 24 May 21 12:33:03 PM PDT 24 520411899 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3120106968 May 21 12:32:35 PM PDT 24 May 21 12:32:43 PM PDT 24 922118537 ps
T372 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3874241071 May 21 12:32:40 PM PDT 24 May 21 12:32:53 PM PDT 24 374662928 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.706602250 May 21 12:32:38 PM PDT 24 May 21 12:32:50 PM PDT 24 176210333 ps
T67 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2331328446 May 21 12:32:22 PM PDT 24 May 21 12:32:31 PM PDT 24 482574293 ps
T53 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4217646635 May 21 12:32:36 PM PDT 24 May 21 12:33:52 PM PDT 24 661917420 ps
T68 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1602902247 May 21 12:32:37 PM PDT 24 May 21 12:32:48 PM PDT 24 839942029 ps
T69 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3652414487 May 21 12:32:39 PM PDT 24 May 21 12:32:58 PM PDT 24 1770174231 ps
T374 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2981275647 May 21 12:32:42 PM PDT 24 May 21 12:33:05 PM PDT 24 3745202916 ps
T70 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1192083717 May 21 12:32:27 PM PDT 24 May 21 12:32:43 PM PDT 24 1962628099 ps
T375 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2610180481 May 21 12:32:56 PM PDT 24 May 21 12:33:12 PM PDT 24 408636364 ps
T96 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3214236518 May 21 12:32:48 PM PDT 24 May 21 12:33:07 PM PDT 24 3458709374 ps
T376 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.293420835 May 21 12:32:46 PM PDT 24 May 21 12:33:09 PM PDT 24 5594959750 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1899050907 May 21 12:32:42 PM PDT 24 May 21 12:33:08 PM PDT 24 381241554 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.770896595 May 21 12:32:42 PM PDT 24 May 21 12:33:01 PM PDT 24 2377808675 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2834201498 May 21 12:32:27 PM PDT 24 May 21 12:33:47 PM PDT 24 33494458827 ps
T54 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3221110097 May 21 12:32:44 PM PDT 24 May 21 12:33:31 PM PDT 24 4203070072 ps
T108 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3057194950 May 21 12:32:25 PM PDT 24 May 21 12:33:33 PM PDT 24 977032099 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1050178022 May 21 12:32:36 PM PDT 24 May 21 12:32:48 PM PDT 24 208903381 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2650893541 May 21 12:32:48 PM PDT 24 May 21 12:33:08 PM PDT 24 147613746 ps
T76 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4088969839 May 21 12:32:37 PM PDT 24 May 21 12:33:18 PM PDT 24 6748947163 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.632074424 May 21 12:32:39 PM PDT 24 May 21 12:33:21 PM PDT 24 542496764 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3944007073 May 21 12:33:13 PM PDT 24 May 21 12:34:24 PM PDT 24 21737262307 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4045861972 May 21 12:32:35 PM PDT 24 May 21 12:32:46 PM PDT 24 346701895 ps
T383 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1898956765 May 21 12:33:08 PM PDT 24 May 21 12:33:37 PM PDT 24 6524599296 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.30105843 May 21 12:32:34 PM PDT 24 May 21 12:33:18 PM PDT 24 962075596 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1934563666 May 21 12:32:24 PM PDT 24 May 21 12:33:45 PM PDT 24 23500451767 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3943896290 May 21 12:32:46 PM PDT 24 May 21 12:33:09 PM PDT 24 7282773040 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1100678955 May 21 12:32:35 PM PDT 24 May 21 12:32:44 PM PDT 24 168597597 ps
T386 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2872215848 May 21 12:32:36 PM PDT 24 May 21 12:32:56 PM PDT 24 8165041322 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2818045350 May 21 12:32:52 PM PDT 24 May 21 12:33:15 PM PDT 24 1337881300 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.604093258 May 21 12:32:25 PM PDT 24 May 21 12:33:48 PM PDT 24 2383180814 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1391762801 May 21 12:32:33 PM PDT 24 May 21 12:32:44 PM PDT 24 497204239 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2232509502 May 21 12:32:34 PM PDT 24 May 21 12:32:43 PM PDT 24 85578511 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1274997637 May 21 12:32:13 PM PDT 24 May 21 12:32:28 PM PDT 24 1621272172 ps
T77 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3752553383 May 21 12:32:24 PM PDT 24 May 21 12:32:53 PM PDT 24 545831908 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1354202078 May 21 12:32:23 PM PDT 24 May 21 12:32:44 PM PDT 24 9613968656 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2739855074 May 21 12:32:45 PM PDT 24 May 21 12:33:00 PM PDT 24 1032942579 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3985854040 May 21 12:32:42 PM PDT 24 May 21 12:33:02 PM PDT 24 1384283025 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3433867738 May 21 12:32:29 PM PDT 24 May 21 12:32:41 PM PDT 24 1160961954 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.469947512 May 21 12:32:31 PM PDT 24 May 21 12:32:55 PM PDT 24 3763741773 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2489128650 May 21 12:32:27 PM PDT 24 May 21 12:32:43 PM PDT 24 1817101457 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2188742628 May 21 12:32:29 PM PDT 24 May 21 12:32:40 PM PDT 24 3580955731 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1566101761 May 21 12:32:39 PM PDT 24 May 21 12:32:57 PM PDT 24 4682451073 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1030537494 May 21 12:32:14 PM PDT 24 May 21 12:32:26 PM PDT 24 763562664 ps
T101 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.969827533 May 21 12:32:45 PM PDT 24 May 21 12:33:38 PM PDT 24 4859625007 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.774187741 May 21 12:32:36 PM PDT 24 May 21 12:32:57 PM PDT 24 7488266416 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2822133476 May 21 12:32:47 PM PDT 24 May 21 12:33:07 PM PDT 24 7327575172 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3624983954 May 21 12:32:14 PM PDT 24 May 21 12:32:53 PM PDT 24 553459899 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3120124896 May 21 12:32:31 PM PDT 24 May 21 12:32:45 PM PDT 24 1321940652 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1607148143 May 21 12:32:20 PM PDT 24 May 21 12:32:31 PM PDT 24 3581894570 ps
T405 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2571549465 May 21 12:32:40 PM PDT 24 May 21 12:33:01 PM PDT 24 3329408040 ps
T110 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2864025390 May 21 12:32:22 PM PDT 24 May 21 12:33:43 PM PDT 24 8140853761 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.732639706 May 21 12:32:28 PM PDT 24 May 21 12:32:45 PM PDT 24 12740558527 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1763090952 May 21 12:32:34 PM PDT 24 May 21 12:34:03 PM PDT 24 14007005767 ps
T407 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1507398865 May 21 12:32:57 PM PDT 24 May 21 12:33:20 PM PDT 24 6582531792 ps
T408 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3034368154 May 21 12:32:40 PM PDT 24 May 21 12:32:55 PM PDT 24 549924789 ps
T409 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.747410929 May 21 12:32:13 PM PDT 24 May 21 12:32:32 PM PDT 24 10995059849 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2440826952 May 21 12:32:41 PM PDT 24 May 21 12:32:52 PM PDT 24 171838819 ps
T411 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.71767788 May 21 12:32:38 PM PDT 24 May 21 12:33:04 PM PDT 24 2124646422 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2137557985 May 21 12:32:42 PM PDT 24 May 21 12:33:30 PM PDT 24 2672076860 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.829489112 May 21 12:32:45 PM PDT 24 May 21 12:32:58 PM PDT 24 375003442 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.403979760 May 21 12:32:52 PM PDT 24 May 21 12:33:40 PM PDT 24 6490409976 ps
T111 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.570347206 May 21 12:32:42 PM PDT 24 May 21 12:33:34 PM PDT 24 1909090200 ps
T414 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3786607805 May 21 12:32:42 PM PDT 24 May 21 12:33:07 PM PDT 24 1323196877 ps
T415 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.587419281 May 21 12:32:41 PM PDT 24 May 21 12:32:56 PM PDT 24 2147489034 ps
T106 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.502101182 May 21 12:32:49 PM PDT 24 May 21 12:33:43 PM PDT 24 6529318045 ps
T416 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.833337787 May 21 12:32:37 PM PDT 24 May 21 12:32:48 PM PDT 24 362454832 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2701272404 May 21 12:32:25 PM PDT 24 May 21 12:32:41 PM PDT 24 6503463519 ps
T418 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2443141864 May 21 12:32:26 PM PDT 24 May 21 12:32:34 PM PDT 24 741871892 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3835072309 May 21 12:32:32 PM PDT 24 May 21 12:32:51 PM PDT 24 16747864569 ps
T420 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1137587590 May 21 12:33:04 PM PDT 24 May 21 12:33:30 PM PDT 24 3635153812 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3929158735 May 21 12:32:41 PM PDT 24 May 21 12:32:55 PM PDT 24 332857532 ps
T113 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.94043205 May 21 12:32:42 PM PDT 24 May 21 12:33:32 PM PDT 24 1306155399 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1330627306 May 21 12:32:42 PM PDT 24 May 21 12:33:36 PM PDT 24 11944525891 ps
T422 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1099942188 May 21 12:32:44 PM PDT 24 May 21 12:33:07 PM PDT 24 3915509629 ps
T423 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1883450958 May 21 12:32:44 PM PDT 24 May 21 12:33:07 PM PDT 24 7677836814 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2183859899 May 21 12:32:23 PM PDT 24 May 21 12:32:31 PM PDT 24 437858810 ps
T107 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3857032782 May 21 12:33:03 PM PDT 24 May 21 12:33:59 PM PDT 24 1640602140 ps
T80 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.257909057 May 21 12:32:59 PM PDT 24 May 21 12:33:25 PM PDT 24 7693195957 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.252983208 May 21 12:32:39 PM PDT 24 May 21 12:32:54 PM PDT 24 102259387 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3408320618 May 21 12:32:44 PM PDT 24 May 21 12:33:03 PM PDT 24 459879922 ps
T427 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1621389820 May 21 12:32:37 PM PDT 24 May 21 12:32:47 PM PDT 24 1181332347 ps
T428 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1293157333 May 21 12:32:35 PM PDT 24 May 21 12:33:18 PM PDT 24 428515017 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2278876926 May 21 12:33:10 PM PDT 24 May 21 12:33:34 PM PDT 24 923560457 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2964538816 May 21 12:33:09 PM PDT 24 May 21 12:33:42 PM PDT 24 31424580786 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.609686477 May 21 12:32:35 PM PDT 24 May 21 12:32:49 PM PDT 24 1624932884 ps
T432 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2420626958 May 21 12:32:21 PM PDT 24 May 21 12:32:41 PM PDT 24 366132395 ps
T82 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4028740561 May 21 12:32:43 PM PDT 24 May 21 12:34:01 PM PDT 24 8477417660 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3139245184 May 21 12:32:44 PM PDT 24 May 21 12:33:29 PM PDT 24 11762572668 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2154323666 May 21 12:32:22 PM PDT 24 May 21 12:32:42 PM PDT 24 1928138731 ps
T83 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3914306463 May 21 12:32:36 PM PDT 24 May 21 12:34:10 PM PDT 24 21111177774 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1823065811 May 21 12:32:28 PM PDT 24 May 21 12:32:46 PM PDT 24 10300283506 ps
T436 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2604150245 May 21 12:32:59 PM PDT 24 May 21 12:33:19 PM PDT 24 173094260 ps
T437 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1238341093 May 21 12:32:45 PM PDT 24 May 21 12:33:01 PM PDT 24 2309448272 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3197465080 May 21 12:32:21 PM PDT 24 May 21 12:32:28 PM PDT 24 172019044 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3192030484 May 21 12:32:38 PM PDT 24 May 21 12:32:50 PM PDT 24 191036090 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1564193135 May 21 12:32:11 PM PDT 24 May 21 12:32:27 PM PDT 24 7536227842 ps
T116 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2630487926 May 21 12:32:40 PM PDT 24 May 21 12:33:32 PM PDT 24 1677480393 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1463607511 May 21 12:32:55 PM PDT 24 May 21 12:33:49 PM PDT 24 28571265876 ps
T104 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2784681757 May 21 12:32:30 PM PDT 24 May 21 12:33:25 PM PDT 24 6493597644 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3468976857 May 21 12:32:39 PM PDT 24 May 21 12:32:53 PM PDT 24 1819670221 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3202516173 May 21 12:32:23 PM PDT 24 May 21 12:32:29 PM PDT 24 175383848 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3536962341 May 21 12:32:13 PM PDT 24 May 21 12:32:31 PM PDT 24 9700838981 ps
T445 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3043067958 May 21 12:32:47 PM PDT 24 May 21 12:33:01 PM PDT 24 1658564825 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3137129701 May 21 12:32:43 PM PDT 24 May 21 12:33:01 PM PDT 24 151974761 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3992732479 May 21 12:32:28 PM PDT 24 May 21 12:32:45 PM PDT 24 3951072412 ps
T102 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.89776328 May 21 12:32:39 PM PDT 24 May 21 12:33:50 PM PDT 24 8175721882 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3246214958 May 21 12:32:23 PM PDT 24 May 21 12:32:28 PM PDT 24 308934900 ps
T449 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1237975607 May 21 12:32:37 PM PDT 24 May 21 12:32:59 PM PDT 24 3173389956 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1176940299 May 21 12:32:23 PM PDT 24 May 21 12:32:38 PM PDT 24 1558932146 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1582553148 May 21 12:32:25 PM PDT 24 May 21 12:32:41 PM PDT 24 7356182612 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1038330627 May 21 12:32:22 PM PDT 24 May 21 12:32:38 PM PDT 24 3693743786 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.66654781 May 21 12:32:34 PM PDT 24 May 21 12:32:41 PM PDT 24 89175665 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2367231648 May 21 12:32:42 PM PDT 24 May 21 12:33:32 PM PDT 24 8906533602 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2707859412 May 21 12:32:22 PM PDT 24 May 21 12:32:37 PM PDT 24 6727474492 ps
T456 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4237286474 May 21 12:32:34 PM PDT 24 May 21 12:32:50 PM PDT 24 2258273106 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4088163356 May 21 12:32:42 PM PDT 24 May 21 12:33:02 PM PDT 24 5314737124 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3157569990 May 21 12:32:13 PM PDT 24 May 21 12:32:27 PM PDT 24 1472211807 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.659631570 May 21 12:32:29 PM PDT 24 May 21 12:33:20 PM PDT 24 5291797296 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3016943182 May 21 12:32:27 PM PDT 24 May 21 12:32:37 PM PDT 24 952862290 ps
T115 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2765836734 May 21 12:32:42 PM PDT 24 May 21 12:34:03 PM PDT 24 4352029148 ps
T460 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3935601459 May 21 12:32:37 PM PDT 24 May 21 12:33:54 PM PDT 24 2292749032 ps
T461 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1250888883 May 21 12:32:35 PM PDT 24 May 21 12:32:44 PM PDT 24 85562976 ps
T462 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1467282937 May 21 12:32:51 PM PDT 24 May 21 12:33:20 PM PDT 24 3369269957 ps
T463 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4196667398 May 21 12:32:37 PM PDT 24 May 21 12:32:55 PM PDT 24 3825626567 ps
T464 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.807737981 May 21 12:32:42 PM PDT 24 May 21 12:33:47 PM PDT 24 39045631861 ps

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3078069104
Short name T6
Test name
Test status
Simulation time 34997798648 ps
CPU time 4798.39 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 01:53:09 PM PDT 24
Peak memory 235864 kb
Host smart-96d4b493-786b-4674-93e4-314b9c8e2ff3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078069104 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3078069104
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1682747214
Short name T7
Test name
Test status
Simulation time 1910096645 ps
CPU time 113.71 seconds
Started May 21 12:32:58 PM PDT 24
Finished May 21 12:35:02 PM PDT 24
Peak memory 233656 kb
Host smart-42424734-ec97-4ff5-a7ed-c6f0992c7bf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682747214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1682747214
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3451029199
Short name T19
Test name
Test status
Simulation time 136095231009 ps
CPU time 348.9 seconds
Started May 21 12:33:05 PM PDT 24
Finished May 21 12:39:07 PM PDT 24
Peak memory 228056 kb
Host smart-b91a4134-75fc-4a02-947d-d47f5b887d6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451029199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3451029199
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4217646635
Short name T53
Test name
Test status
Simulation time 661917420 ps
CPU time 71.4 seconds
Started May 21 12:32:36 PM PDT 24
Finished May 21 12:33:52 PM PDT 24
Peak memory 213204 kb
Host smart-a6540f19-0f9e-4254-83f5-c80ee85a56af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217646635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4217646635
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3809498749
Short name T34
Test name
Test status
Simulation time 986051439 ps
CPU time 100.74 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 12:34:39 PM PDT 24
Peak memory 236380 kb
Host smart-bcdc10aa-c7ac-44ad-9c75-5e150e8ac521
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809498749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3809498749
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.325325065
Short name T64
Test name
Test status
Simulation time 74158067991 ps
CPU time 94.78 seconds
Started May 21 12:32:38 PM PDT 24
Finished May 21 12:34:18 PM PDT 24
Peak memory 211356 kb
Host smart-194e82ca-1ff1-4443-9caf-24da160c1088
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325325065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.325325065
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2521429912
Short name T118
Test name
Test status
Simulation time 188832684118 ps
CPU time 1764.22 seconds
Started May 21 12:33:25 PM PDT 24
Finished May 21 01:03:18 PM PDT 24
Peak memory 236108 kb
Host smart-00bd3a4e-ed62-425f-a9fe-b187265d75ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521429912 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2521429912
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.317443517
Short name T33
Test name
Test status
Simulation time 79504001136 ps
CPU time 2827.54 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 01:20:35 PM PDT 24
Peak memory 235820 kb
Host smart-f56ca81d-6650-4c47-9a33-b7a1688ae5c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317443517 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.317443517
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4074119245
Short name T3
Test name
Test status
Simulation time 3514067813 ps
CPU time 16.78 seconds
Started May 21 12:33:07 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 211584 kb
Host smart-fe409fe1-8362-49a7-9e93-61e6bb5bbc3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074119245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4074119245
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.294969967
Short name T22
Test name
Test status
Simulation time 995974551 ps
CPU time 16.32 seconds
Started May 21 12:33:14 PM PDT 24
Finished May 21 12:33:50 PM PDT 24
Peak memory 211808 kb
Host smart-25062f7a-8fc1-446e-9666-7d9dee611c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294969967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.294969967
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1380867218
Short name T14
Test name
Test status
Simulation time 36697031605 ps
CPU time 113 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:34:59 PM PDT 24
Peak memory 219232 kb
Host smart-bdfd9c4a-674a-4fec-8376-2ad5eeffe03d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380867218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1380867218
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1798054399
Short name T17
Test name
Test status
Simulation time 666275051 ps
CPU time 9.38 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:14 PM PDT 24
Peak memory 211904 kb
Host smart-4272191d-9f27-493a-8769-c74bddc1084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798054399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1798054399
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.502101182
Short name T106
Test name
Test status
Simulation time 6529318045 ps
CPU time 45.35 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 12:33:43 PM PDT 24
Peak memory 213480 kb
Host smart-fdad0aa9-0366-4d5e-a539-5c47265f3f92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502101182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.502101182
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.570347206
Short name T111
Test name
Test status
Simulation time 1909090200 ps
CPU time 45.13 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 212080 kb
Host smart-e9b028d8-a01a-41ab-8056-a311e2f8abcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570347206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.570347206
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.89776328
Short name T102
Test name
Test status
Simulation time 8175721882 ps
CPU time 64.35 seconds
Started May 21 12:32:39 PM PDT 24
Finished May 21 12:33:50 PM PDT 24
Peak memory 211360 kb
Host smart-00bb76b6-29a4-49a4-b366-252dc553839c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89776328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pas
sthru_mem_tl_intg_err.89776328
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4230109745
Short name T47
Test name
Test status
Simulation time 10023222558 ps
CPU time 111.67 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:35:20 PM PDT 24
Peak memory 212512 kb
Host smart-b8d348c6-4569-4616-a8c1-d2d17043ce63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230109745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4230109745
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3057194950
Short name T108
Test name
Test status
Simulation time 977032099 ps
CPU time 67.4 seconds
Started May 21 12:32:25 PM PDT 24
Finished May 21 12:33:33 PM PDT 24
Peak memory 211352 kb
Host smart-20ddc41c-ec2a-4ad6-addd-69418b0d093a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057194950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3057194950
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3765140625
Short name T84
Test name
Test status
Simulation time 219791646 ps
CPU time 7.35 seconds
Started May 21 12:33:16 PM PDT 24
Finished May 21 12:33:45 PM PDT 24
Peak memory 210952 kb
Host smart-f021a37b-0024-4ede-8d45-efdb8162d7c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765140625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3765140625
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.66654781
Short name T453
Test name
Test status
Simulation time 89175665 ps
CPU time 4.26 seconds
Started May 21 12:32:34 PM PDT 24
Finished May 21 12:32:41 PM PDT 24
Peak memory 211204 kb
Host smart-51a4c3a8-737f-4fa8-bd57-397972bf0001
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66654781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasi
ng.66654781
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2707859412
Short name T455
Test name
Test status
Simulation time 6727474492 ps
CPU time 14.19 seconds
Started May 21 12:32:22 PM PDT 24
Finished May 21 12:32:37 PM PDT 24
Peak memory 211256 kb
Host smart-e30a7f53-7d5c-492b-a321-0da27448dfd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707859412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2707859412
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3536962341
Short name T444
Test name
Test status
Simulation time 9700838981 ps
CPU time 17.17 seconds
Started May 21 12:32:13 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 211244 kb
Host smart-166d5081-00c1-43de-bc6e-9358f603cda9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536962341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3536962341
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2701272404
Short name T417
Test name
Test status
Simulation time 6503463519 ps
CPU time 14.17 seconds
Started May 21 12:32:25 PM PDT 24
Finished May 21 12:32:41 PM PDT 24
Peak memory 219508 kb
Host smart-6be702b7-75d9-4211-8514-a51fdc8b0c46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701272404 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2701272404
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3491132277
Short name T369
Test name
Test status
Simulation time 574053464 ps
CPU time 7.88 seconds
Started May 21 12:32:16 PM PDT 24
Finished May 21 12:32:25 PM PDT 24
Peak memory 211184 kb
Host smart-a5985f91-0bd0-49f5-a109-d0bfb90cd423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491132277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3491132277
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1607148143
Short name T404
Test name
Test status
Simulation time 3581894570 ps
CPU time 9.88 seconds
Started May 21 12:32:20 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 211100 kb
Host smart-d32d3d9f-762c-45ca-a532-85920a0d413f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607148143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1607148143
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3016943182
Short name T459
Test name
Test status
Simulation time 952862290 ps
CPU time 9.59 seconds
Started May 21 12:32:27 PM PDT 24
Finished May 21 12:32:37 PM PDT 24
Peak memory 211100 kb
Host smart-772e8206-ca0d-4a17-9f05-b897df60ca8d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016943182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3016943182
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2420626958
Short name T432
Test name
Test status
Simulation time 366132395 ps
CPU time 19.02 seconds
Started May 21 12:32:21 PM PDT 24
Finished May 21 12:32:41 PM PDT 24
Peak memory 211208 kb
Host smart-88d40517-db93-40d2-9c4b-cb6a36e4c25e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420626958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2420626958
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.469947512
Short name T395
Test name
Test status
Simulation time 3763741773 ps
CPU time 15.11 seconds
Started May 21 12:32:31 PM PDT 24
Finished May 21 12:32:55 PM PDT 24
Peak memory 211296 kb
Host smart-d0d83a02-1e81-40a3-b745-fcdaae103259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469947512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.469947512
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1030537494
Short name T399
Test name
Test status
Simulation time 763562664 ps
CPU time 10.8 seconds
Started May 21 12:32:14 PM PDT 24
Finished May 21 12:32:26 PM PDT 24
Peak memory 219412 kb
Host smart-d4008bfb-d5fd-4355-afa7-b1874f7d575a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030537494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1030537494
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3624983954
Short name T402
Test name
Test status
Simulation time 553459899 ps
CPU time 37.62 seconds
Started May 21 12:32:14 PM PDT 24
Finished May 21 12:32:53 PM PDT 24
Peak memory 211748 kb
Host smart-07d332ed-e9d5-4137-942b-7f770eb795ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624983954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3624983954
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3157569990
Short name T458
Test name
Test status
Simulation time 1472211807 ps
CPU time 11.93 seconds
Started May 21 12:32:13 PM PDT 24
Finished May 21 12:32:27 PM PDT 24
Peak memory 211164 kb
Host smart-ffa59798-7a31-4c81-8fac-f555dce11807
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157569990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3157569990
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4289644919
Short name T56
Test name
Test status
Simulation time 88899339 ps
CPU time 4.69 seconds
Started May 21 12:32:13 PM PDT 24
Finished May 21 12:32:19 PM PDT 24
Peak memory 211168 kb
Host smart-f2da2b6a-6c62-4227-83fe-7fa8356345df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289644919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4289644919
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4102466694
Short name T63
Test name
Test status
Simulation time 87740669 ps
CPU time 5.95 seconds
Started May 21 12:32:16 PM PDT 24
Finished May 21 12:32:23 PM PDT 24
Peak memory 211192 kb
Host smart-c88dea94-f714-44ed-b19e-893ecbd6567a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102466694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4102466694
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1536479728
Short name T368
Test name
Test status
Simulation time 1886099510 ps
CPU time 15.22 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:32:54 PM PDT 24
Peak memory 212676 kb
Host smart-e5e06aea-19e8-439e-b2c5-88262504a0c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536479728 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1536479728
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.747410929
Short name T409
Test name
Test status
Simulation time 10995059849 ps
CPU time 16.92 seconds
Started May 21 12:32:13 PM PDT 24
Finished May 21 12:32:32 PM PDT 24
Peak memory 211360 kb
Host smart-596a49dd-9344-4571-88f4-6d2f719ef017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747410929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.747410929
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1564193135
Short name T440
Test name
Test status
Simulation time 7536227842 ps
CPU time 14.41 seconds
Started May 21 12:32:11 PM PDT 24
Finished May 21 12:32:27 PM PDT 24
Peak memory 211100 kb
Host smart-5458c3c7-cfae-43bf-a2a4-b01d77561fa0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564193135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1564193135
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3120124896
Short name T403
Test name
Test status
Simulation time 1321940652 ps
CPU time 11.34 seconds
Started May 21 12:32:31 PM PDT 24
Finished May 21 12:32:45 PM PDT 24
Peak memory 211136 kb
Host smart-0f652504-6878-4159-a609-2302e48f5e3e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120124896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3120124896
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2784681757
Short name T104
Test name
Test status
Simulation time 6493597644 ps
CPU time 52.54 seconds
Started May 21 12:32:30 PM PDT 24
Finished May 21 12:33:25 PM PDT 24
Peak memory 211328 kb
Host smart-051cf945-e13d-4a08-8831-8963980cd486
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784681757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2784681757
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1274997637
Short name T391
Test name
Test status
Simulation time 1621272172 ps
CPU time 14.26 seconds
Started May 21 12:32:13 PM PDT 24
Finished May 21 12:32:28 PM PDT 24
Peak memory 211264 kb
Host smart-3c8803ce-409a-4552-b9b5-6c66ab68687e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274997637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1274997637
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3197465080
Short name T438
Test name
Test status
Simulation time 172019044 ps
CPU time 6.66 seconds
Started May 21 12:32:21 PM PDT 24
Finished May 21 12:32:28 PM PDT 24
Peak memory 219548 kb
Host smart-0246d53b-c8fd-419a-9a30-60702e4437bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197465080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3197465080
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4237286474
Short name T456
Test name
Test status
Simulation time 2258273106 ps
CPU time 10.98 seconds
Started May 21 12:32:34 PM PDT 24
Finished May 21 12:32:50 PM PDT 24
Peak memory 212888 kb
Host smart-1f74ff6a-ab74-4cd7-8b3c-caf14882333f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237286474 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4237286474
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1100678955
Short name T385
Test name
Test status
Simulation time 168597597 ps
CPU time 4.07 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:32:44 PM PDT 24
Peak memory 211112 kb
Host smart-91d18725-436a-4521-913d-89cd499d40aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100678955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1100678955
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.807737981
Short name T464
Test name
Test status
Simulation time 39045631861 ps
CPU time 57.07 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:47 PM PDT 24
Peak memory 211252 kb
Host smart-6f667c18-d492-4fe8-9668-2314609a50d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807737981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.807737981
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3137077451
Short name T66
Test name
Test status
Simulation time 2781450225 ps
CPU time 8.54 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:32:49 PM PDT 24
Peak memory 211200 kb
Host smart-9bfb204d-dc81-4cd7-bda8-3265b274436e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137077451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3137077451
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2650893541
Short name T380
Test name
Test status
Simulation time 147613746 ps
CPU time 10.05 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:08 PM PDT 24
Peak memory 219440 kb
Host smart-da4db60b-fe66-4e54-81ae-cb71e8f02d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650893541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2650893541
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2964538816
Short name T430
Test name
Test status
Simulation time 31424580786 ps
CPU time 15.29 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:42 PM PDT 24
Peak memory 219428 kb
Host smart-6e0ba187-b80c-45cd-985d-8423b17c4a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964538816 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2964538816
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1391762801
Short name T389
Test name
Test status
Simulation time 497204239 ps
CPU time 7.38 seconds
Started May 21 12:32:33 PM PDT 24
Finished May 21 12:32:44 PM PDT 24
Peak memory 211076 kb
Host smart-23af0f73-bb98-4ebd-9e6a-686af8966510
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391762801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1391762801
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.403979760
Short name T413
Test name
Test status
Simulation time 6490409976 ps
CPU time 38.44 seconds
Started May 21 12:32:52 PM PDT 24
Finished May 21 12:33:40 PM PDT 24
Peak memory 211276 kb
Host smart-a7c26dd5-bb06-40af-a252-6a88e8f2843f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403979760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.403979760
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1250888883
Short name T461
Test name
Test status
Simulation time 85562976 ps
CPU time 4.15 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:32:44 PM PDT 24
Peak memory 211092 kb
Host smart-17a46cc1-a678-4066-b86e-da29d45d70fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250888883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1250888883
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1237975607
Short name T449
Test name
Test status
Simulation time 3173389956 ps
CPU time 17.04 seconds
Started May 21 12:32:37 PM PDT 24
Finished May 21 12:32:59 PM PDT 24
Peak memory 219456 kb
Host smart-6845f8e7-4299-482a-af5e-c2e89e6ef485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237975607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1237975607
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1293157333
Short name T428
Test name
Test status
Simulation time 428515017 ps
CPU time 37.98 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:33:18 PM PDT 24
Peak memory 212084 kb
Host smart-fe1e975d-8108-459d-a7e8-9d2b480addd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293157333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1293157333
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.260978724
Short name T364
Test name
Test status
Simulation time 88953681 ps
CPU time 4.27 seconds
Started May 21 12:33:05 PM PDT 24
Finished May 21 12:33:27 PM PDT 24
Peak memory 211992 kb
Host smart-db32efb2-4093-4ce7-ae72-9fe9d5de76e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260978724 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.260978724
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1507398865
Short name T407
Test name
Test status
Simulation time 6582531792 ps
CPU time 11.65 seconds
Started May 21 12:32:57 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 211208 kb
Host smart-795aebba-d7cc-49a9-a747-3e1357b13cda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507398865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1507398865
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3139245184
Short name T433
Test name
Test status
Simulation time 11762572668 ps
CPU time 36.2 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:29 PM PDT 24
Peak memory 211260 kb
Host smart-1991048f-2870-446f-9c92-df9b65b27500
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139245184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3139245184
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2571549465
Short name T405
Test name
Test status
Simulation time 3329408040 ps
CPU time 14.01 seconds
Started May 21 12:32:40 PM PDT 24
Finished May 21 12:33:01 PM PDT 24
Peak memory 211172 kb
Host smart-6c387e3a-2a5b-49de-b9ad-32a7f43553d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571549465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2571549465
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1050178022
Short name T379
Test name
Test status
Simulation time 208903381 ps
CPU time 7.88 seconds
Started May 21 12:32:36 PM PDT 24
Finished May 21 12:32:48 PM PDT 24
Peak memory 219436 kb
Host smart-328918e0-7dc1-400b-9504-8f6dc0b65c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050178022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1050178022
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.632074424
Short name T112
Test name
Test status
Simulation time 542496764 ps
CPU time 36.02 seconds
Started May 21 12:32:39 PM PDT 24
Finished May 21 12:33:21 PM PDT 24
Peak memory 211488 kb
Host smart-006fe7c6-373e-4011-9c22-b36e57e9ccde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632074424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.632074424
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1414439151
Short name T366
Test name
Test status
Simulation time 1299069284 ps
CPU time 9.28 seconds
Started May 21 12:32:41 PM PDT 24
Finished May 21 12:32:57 PM PDT 24
Peak memory 213352 kb
Host smart-5931d034-fead-47d6-99e0-c9fd067ed8ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414439151 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1414439151
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.587419281
Short name T415
Test name
Test status
Simulation time 2147489034 ps
CPU time 7.78 seconds
Started May 21 12:32:41 PM PDT 24
Finished May 21 12:32:56 PM PDT 24
Peak memory 211324 kb
Host smart-54d3d32f-33c7-4653-ac4c-4f8750d65365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587419281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.587419281
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.969827533
Short name T101
Test name
Test status
Simulation time 4859625007 ps
CPU time 44.36 seconds
Started May 21 12:32:45 PM PDT 24
Finished May 21 12:33:38 PM PDT 24
Peak memory 211252 kb
Host smart-29335dc4-de74-49ac-9e9c-b20e3497739c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969827533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.969827533
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3985854040
Short name T393
Test name
Test status
Simulation time 1384283025 ps
CPU time 6.71 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:02 PM PDT 24
Peak memory 211452 kb
Host smart-3c47653c-5d97-4b1e-a7a2-8b0ece6ebba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985854040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3985854040
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3192030484
Short name T439
Test name
Test status
Simulation time 191036090 ps
CPU time 7.49 seconds
Started May 21 12:32:38 PM PDT 24
Finished May 21 12:32:50 PM PDT 24
Peak memory 219356 kb
Host smart-b53da248-b3c2-4ad7-beae-70009f7458a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192030484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3192030484
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.94043205
Short name T113
Test name
Test status
Simulation time 1306155399 ps
CPU time 42.55 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:32 PM PDT 24
Peak memory 213116 kb
Host smart-9dd67b62-d060-490e-b036-64846c165deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94043205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.94043205
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4088163356
Short name T457
Test name
Test status
Simulation time 5314737124 ps
CPU time 12.29 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:02 PM PDT 24
Peak memory 215656 kb
Host smart-29259de4-053e-4948-bae5-28eaebea8c64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088163356 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4088163356
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1621389820
Short name T427
Test name
Test status
Simulation time 1181332347 ps
CPU time 4.25 seconds
Started May 21 12:32:37 PM PDT 24
Finished May 21 12:32:47 PM PDT 24
Peak memory 211132 kb
Host smart-157f2c75-783d-40f2-adc0-bb8b128c6255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621389820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1621389820
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4028740561
Short name T82
Test name
Test status
Simulation time 8477417660 ps
CPU time 70.66 seconds
Started May 21 12:32:43 PM PDT 24
Finished May 21 12:34:01 PM PDT 24
Peak memory 211276 kb
Host smart-b638ada0-a52e-4b8d-8d2d-cf655c98cbaf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028740561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4028740561
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1099942188
Short name T422
Test name
Test status
Simulation time 3915509629 ps
CPU time 14.62 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:07 PM PDT 24
Peak memory 211324 kb
Host smart-df4c96ae-124c-4e6b-902f-3d949a22acbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099942188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1099942188
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.252983208
Short name T425
Test name
Test status
Simulation time 102259387 ps
CPU time 7.59 seconds
Started May 21 12:32:39 PM PDT 24
Finished May 21 12:32:54 PM PDT 24
Peak memory 219388 kb
Host smart-d5ecfe9e-5a05-4213-9640-7322f0fa6ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252983208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.252983208
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3996906252
Short name T52
Test name
Test status
Simulation time 2141792799 ps
CPU time 40.77 seconds
Started May 21 12:32:52 PM PDT 24
Finished May 21 12:33:42 PM PDT 24
Peak memory 213056 kb
Host smart-41afba8c-2acd-4b6f-85db-4a2026e39ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996906252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3996906252
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1883450958
Short name T423
Test name
Test status
Simulation time 7677836814 ps
CPU time 14.85 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:07 PM PDT 24
Peak memory 219532 kb
Host smart-d362eaf8-7caf-4904-86e9-6996ab693dac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883450958 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1883450958
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3652414487
Short name T69
Test name
Test status
Simulation time 1770174231 ps
CPU time 13.72 seconds
Started May 21 12:32:39 PM PDT 24
Finished May 21 12:32:58 PM PDT 24
Peak memory 211140 kb
Host smart-158da1e1-95f7-4baf-aa69-42d5377afe35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652414487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3652414487
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1899050907
Short name T377
Test name
Test status
Simulation time 381241554 ps
CPU time 18.3 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:08 PM PDT 24
Peak memory 211280 kb
Host smart-b076203b-f8e4-4e1d-906f-886889c22dc9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899050907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1899050907
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3929158735
Short name T421
Test name
Test status
Simulation time 332857532 ps
CPU time 6.42 seconds
Started May 21 12:32:41 PM PDT 24
Finished May 21 12:32:55 PM PDT 24
Peak memory 211108 kb
Host smart-486b26ef-ab1b-4a3a-9d68-1d63c267c676
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929158735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3929158735
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3408320618
Short name T426
Test name
Test status
Simulation time 459879922 ps
CPU time 10.67 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:03 PM PDT 24
Peak memory 219520 kb
Host smart-4aa02c66-4ae3-4558-b6f9-9cce44d3696e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408320618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3408320618
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2630487926
Short name T116
Test name
Test status
Simulation time 1677480393 ps
CPU time 44.74 seconds
Started May 21 12:32:40 PM PDT 24
Finished May 21 12:33:32 PM PDT 24
Peak memory 212040 kb
Host smart-418c3926-fff0-4992-a8d6-4e6c3670222c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630487926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2630487926
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2818045350
Short name T387
Test name
Test status
Simulation time 1337881300 ps
CPU time 12.97 seconds
Started May 21 12:32:52 PM PDT 24
Finished May 21 12:33:15 PM PDT 24
Peak memory 219340 kb
Host smart-99ffe5e5-a2a5-4ebe-942b-56ac912d186b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818045350 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2818045350
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.331021536
Short name T94
Test name
Test status
Simulation time 2352599676 ps
CPU time 10.79 seconds
Started May 21 12:32:39 PM PDT 24
Finished May 21 12:32:56 PM PDT 24
Peak memory 211328 kb
Host smart-50c54195-42b7-4ce8-a828-cd8fb459653a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331021536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.331021536
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.340076401
Short name T62
Test name
Test status
Simulation time 863029752 ps
CPU time 24.14 seconds
Started May 21 12:32:36 PM PDT 24
Finished May 21 12:33:05 PM PDT 24
Peak memory 211216 kb
Host smart-ee51eea3-3d7b-463a-8755-ba7ee503be3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340076401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.340076401
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.453037329
Short name T57
Test name
Test status
Simulation time 353400806 ps
CPU time 6.45 seconds
Started May 21 12:32:40 PM PDT 24
Finished May 21 12:32:54 PM PDT 24
Peak memory 211140 kb
Host smart-43b8d713-0a78-4dbf-9fa6-7e80f73c8087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453037329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.453037329
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3137129701
Short name T446
Test name
Test status
Simulation time 151974761 ps
CPU time 9.61 seconds
Started May 21 12:32:43 PM PDT 24
Finished May 21 12:33:01 PM PDT 24
Peak memory 219404 kb
Host smart-4262e0e5-2927-40eb-bbd3-797ce78529d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137129701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3137129701
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3221110097
Short name T54
Test name
Test status
Simulation time 4203070072 ps
CPU time 38.75 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:31 PM PDT 24
Peak memory 219504 kb
Host smart-df449b38-08a6-48d9-8909-fc6fa0b68899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221110097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3221110097
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2610180481
Short name T375
Test name
Test status
Simulation time 408636364 ps
CPU time 5.26 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:33:12 PM PDT 24
Peak memory 219356 kb
Host smart-b88b706c-87d8-411b-a318-28a1d7648768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610180481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2610180481
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3943896290
Short name T384
Test name
Test status
Simulation time 7282773040 ps
CPU time 15.1 seconds
Started May 21 12:32:46 PM PDT 24
Finished May 21 12:33:09 PM PDT 24
Peak memory 211204 kb
Host smart-dd2b072f-fbfe-4423-a290-4714e94b3602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943896290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3943896290
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3944007073
Short name T381
Test name
Test status
Simulation time 21737262307 ps
CPU time 50.84 seconds
Started May 21 12:33:13 PM PDT 24
Finished May 21 12:34:24 PM PDT 24
Peak memory 211264 kb
Host smart-571d41e1-09fa-4da1-8c86-5e4a772d76d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944007073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3944007073
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1238341093
Short name T437
Test name
Test status
Simulation time 2309448272 ps
CPU time 8.41 seconds
Started May 21 12:32:45 PM PDT 24
Finished May 21 12:33:01 PM PDT 24
Peak memory 211544 kb
Host smart-b5df2b9e-5294-44d1-bcf4-817e4369f8ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238341093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1238341093
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2278876926
Short name T429
Test name
Test status
Simulation time 923560457 ps
CPU time 6.51 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 219440 kb
Host smart-0aa4a811-439c-46b2-8278-70c88912950c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278876926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2278876926
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2367231648
Short name T454
Test name
Test status
Simulation time 8906533602 ps
CPU time 41.68 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:32 PM PDT 24
Peak memory 211236 kb
Host smart-95a82eb5-51fa-482f-b332-49a36b31c62c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367231648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2367231648
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3874241071
Short name T372
Test name
Test status
Simulation time 374662928 ps
CPU time 5.28 seconds
Started May 21 12:32:40 PM PDT 24
Finished May 21 12:32:53 PM PDT 24
Peak memory 219348 kb
Host smart-c819eda8-5f53-4783-8a75-7fba4a42a32f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874241071 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3874241071
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.257909057
Short name T80
Test name
Test status
Simulation time 7693195957 ps
CPU time 14.9 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:33:25 PM PDT 24
Peak memory 211296 kb
Host smart-00304f66-7f90-4751-925e-b3efd174151b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257909057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.257909057
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1463607511
Short name T441
Test name
Test status
Simulation time 28571265876 ps
CPU time 43.6 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:49 PM PDT 24
Peak memory 211244 kb
Host smart-e8b2fc58-f502-470b-a7a5-66f0a0f14f4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463607511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1463607511
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2440826952
Short name T410
Test name
Test status
Simulation time 171838819 ps
CPU time 4.3 seconds
Started May 21 12:32:41 PM PDT 24
Finished May 21 12:32:52 PM PDT 24
Peak memory 211216 kb
Host smart-620437c9-2693-4aa9-8b4b-57d7980972ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440826952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2440826952
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2604150245
Short name T436
Test name
Test status
Simulation time 173094260 ps
CPU time 8.17 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:33:19 PM PDT 24
Peak memory 219548 kb
Host smart-c3bd8cc3-e19e-484f-98a0-6c2d0af8c8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604150245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2604150245
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3786607805
Short name T414
Test name
Test status
Simulation time 1323196877 ps
CPU time 11.72 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:07 PM PDT 24
Peak memory 212664 kb
Host smart-d53125b1-d1c3-4e7a-9d45-20746d73d040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786607805 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3786607805
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2739855074
Short name T78
Test name
Test status
Simulation time 1032942579 ps
CPU time 5.85 seconds
Started May 21 12:32:45 PM PDT 24
Finished May 21 12:33:00 PM PDT 24
Peak memory 211172 kb
Host smart-4fd38c68-accc-42c1-9913-ba0778250549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739855074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2739855074
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1898956765
Short name T383
Test name
Test status
Simulation time 6524599296 ps
CPU time 14.21 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 211224 kb
Host smart-4643b188-0419-44e9-8dc3-13c328610732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898956765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1898956765
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.71767788
Short name T411
Test name
Test status
Simulation time 2124646422 ps
CPU time 19.84 seconds
Started May 21 12:32:38 PM PDT 24
Finished May 21 12:33:04 PM PDT 24
Peak memory 219424 kb
Host smart-15cb2f01-0cb2-4fd1-bdef-9786a046db3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71767788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.71767788
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3857032782
Short name T107
Test name
Test status
Simulation time 1640602140 ps
CPU time 43.89 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 211920 kb
Host smart-35776ff0-b480-4548-932c-89dce9071adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857032782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3857032782
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3509821522
Short name T65
Test name
Test status
Simulation time 3577206345 ps
CPU time 10.04 seconds
Started May 21 12:32:23 PM PDT 24
Finished May 21 12:32:34 PM PDT 24
Peak memory 211252 kb
Host smart-89a3af7e-cf72-4207-aaca-21894fc1901d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509821522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3509821522
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2232509502
Short name T390
Test name
Test status
Simulation time 85578511 ps
CPU time 4.65 seconds
Started May 21 12:32:34 PM PDT 24
Finished May 21 12:32:43 PM PDT 24
Peak memory 211192 kb
Host smart-0dd4cf41-387e-4030-a7bb-8bf879b942fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232509502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2232509502
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1354202078
Short name T392
Test name
Test status
Simulation time 9613968656 ps
CPU time 20.05 seconds
Started May 21 12:32:23 PM PDT 24
Finished May 21 12:32:44 PM PDT 24
Peak memory 211340 kb
Host smart-3d36e79b-0bd5-45c0-b457-71747eeb0414
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354202078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1354202078
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3992732479
Short name T447
Test name
Test status
Simulation time 3951072412 ps
CPU time 15.84 seconds
Started May 21 12:32:28 PM PDT 24
Finished May 21 12:32:45 PM PDT 24
Peak memory 213740 kb
Host smart-449f3e37-42d4-467d-805e-93451ad1d581
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992732479 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3992732479
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2489128650
Short name T396
Test name
Test status
Simulation time 1817101457 ps
CPU time 14.56 seconds
Started May 21 12:32:27 PM PDT 24
Finished May 21 12:32:43 PM PDT 24
Peak memory 211184 kb
Host smart-94b23462-649b-4cd3-9fe8-4460718caf09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489128650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2489128650
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1038330627
Short name T452
Test name
Test status
Simulation time 3693743786 ps
CPU time 14.65 seconds
Started May 21 12:32:22 PM PDT 24
Finished May 21 12:32:38 PM PDT 24
Peak memory 211100 kb
Host smart-93d4ae4a-9a6b-4516-beda-c0ec6265dec1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038330627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1038330627
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2183859899
Short name T424
Test name
Test status
Simulation time 437858810 ps
CPU time 7.11 seconds
Started May 21 12:32:23 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 211096 kb
Host smart-e5189ed8-bcc1-4913-9335-fe133d7f5bee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183859899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2183859899
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2834201498
Short name T378
Test name
Test status
Simulation time 33494458827 ps
CPU time 78.7 seconds
Started May 21 12:32:27 PM PDT 24
Finished May 21 12:33:47 PM PDT 24
Peak memory 211244 kb
Host smart-03f52c9a-0129-4c10-b44f-e2d9af94d993
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834201498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2834201498
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1823065811
Short name T435
Test name
Test status
Simulation time 10300283506 ps
CPU time 15.86 seconds
Started May 21 12:32:28 PM PDT 24
Finished May 21 12:32:46 PM PDT 24
Peak memory 211184 kb
Host smart-de999bd7-cde6-422b-8748-635f600c7fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823065811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1823065811
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2154323666
Short name T434
Test name
Test status
Simulation time 1928138731 ps
CPU time 18.88 seconds
Started May 21 12:32:22 PM PDT 24
Finished May 21 12:32:42 PM PDT 24
Peak memory 219416 kb
Host smart-7cf1dab3-33b9-4a11-b163-e15a999d906d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154323666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2154323666
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2864025390
Short name T110
Test name
Test status
Simulation time 8140853761 ps
CPU time 79.63 seconds
Started May 21 12:32:22 PM PDT 24
Finished May 21 12:33:43 PM PDT 24
Peak memory 212740 kb
Host smart-8abff118-39ad-4273-b19b-89a3a0eccf15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864025390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2864025390
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1192083717
Short name T70
Test name
Test status
Simulation time 1962628099 ps
CPU time 15.47 seconds
Started May 21 12:32:27 PM PDT 24
Finished May 21 12:32:43 PM PDT 24
Peak memory 211132 kb
Host smart-31f25e27-03d1-42f8-a6ed-2bb0a3a584ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192083717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1192083717
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3246214958
Short name T448
Test name
Test status
Simulation time 308934900 ps
CPU time 4.44 seconds
Started May 21 12:32:23 PM PDT 24
Finished May 21 12:32:28 PM PDT 24
Peak memory 211268 kb
Host smart-587eb92c-f232-4fd5-b1fc-9d97ceeec68c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246214958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3246214958
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3668525869
Short name T99
Test name
Test status
Simulation time 382823656 ps
CPU time 7.52 seconds
Started May 21 12:32:33 PM PDT 24
Finished May 21 12:32:44 PM PDT 24
Peak memory 211272 kb
Host smart-c8380952-96d8-4403-b792-6e07b47e100a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668525869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3668525869
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2441165293
Short name T370
Test name
Test status
Simulation time 520411899 ps
CPU time 6.57 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:03 PM PDT 24
Peak memory 219376 kb
Host smart-a60d6e05-9281-4564-9211-a6ec0f98418f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441165293 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2441165293
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.609686477
Short name T431
Test name
Test status
Simulation time 1624932884 ps
CPU time 8.89 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:32:49 PM PDT 24
Peak memory 211188 kb
Host smart-a820ce24-b676-4ed4-b3a2-ea1c6cd2415f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609686477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.609686477
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1312509927
Short name T367
Test name
Test status
Simulation time 2209324081 ps
CPU time 6.26 seconds
Started May 21 12:32:27 PM PDT 24
Finished May 21 12:32:35 PM PDT 24
Peak memory 211088 kb
Host smart-6e5c3bca-8e33-49b4-be2f-e5553ca25bd0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312509927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1312509927
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1582553148
Short name T451
Test name
Test status
Simulation time 7356182612 ps
CPU time 14.76 seconds
Started May 21 12:32:25 PM PDT 24
Finished May 21 12:32:41 PM PDT 24
Peak memory 211112 kb
Host smart-28df4289-9dac-4e51-875e-094eac7fbfa9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582553148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1582553148
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.659631570
Short name T81
Test name
Test status
Simulation time 5291797296 ps
CPU time 47.86 seconds
Started May 21 12:32:29 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 211256 kb
Host smart-61b94ad3-9b08-4793-a1cf-bf33fccef7e4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659631570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.659631570
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1176940299
Short name T450
Test name
Test status
Simulation time 1558932146 ps
CPU time 13.48 seconds
Started May 21 12:32:23 PM PDT 24
Finished May 21 12:32:38 PM PDT 24
Peak memory 211180 kb
Host smart-a358a590-1ae1-4004-8d97-e0a02f2c169c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176940299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1176940299
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1467282937
Short name T462
Test name
Test status
Simulation time 3369269957 ps
CPU time 18.88 seconds
Started May 21 12:32:51 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 219460 kb
Host smart-572a93eb-60b3-45b3-a13e-16180dec0416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467282937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1467282937
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.30105843
Short name T114
Test name
Test status
Simulation time 962075596 ps
CPU time 39.14 seconds
Started May 21 12:32:34 PM PDT 24
Finished May 21 12:33:18 PM PDT 24
Peak memory 211192 kb
Host smart-6153b3a1-cfc3-4f46-a39c-e481a218d277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg
_err.30105843
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.732639706
Short name T406
Test name
Test status
Simulation time 12740558527 ps
CPU time 15.77 seconds
Started May 21 12:32:28 PM PDT 24
Finished May 21 12:32:45 PM PDT 24
Peak memory 211232 kb
Host smart-427a56f6-c004-483c-a124-e42adc7f7fd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732639706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.732639706
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3468976857
Short name T442
Test name
Test status
Simulation time 1819670221 ps
CPU time 7.76 seconds
Started May 21 12:32:39 PM PDT 24
Finished May 21 12:32:53 PM PDT 24
Peak memory 211164 kb
Host smart-f48af02f-10f6-4155-8f83-08fd01b6cddb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468976857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3468976857
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2331328446
Short name T67
Test name
Test status
Simulation time 482574293 ps
CPU time 7.53 seconds
Started May 21 12:32:22 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 211116 kb
Host smart-bf857bb6-a6f9-4287-9598-e765c3a20cbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331328446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2331328446
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3835072309
Short name T419
Test name
Test status
Simulation time 16747864569 ps
CPU time 16.83 seconds
Started May 21 12:32:32 PM PDT 24
Finished May 21 12:32:51 PM PDT 24
Peak memory 219424 kb
Host smart-95095d0b-3ba0-4896-b6c3-869dae782da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835072309 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3835072309
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3202516173
Short name T443
Test name
Test status
Simulation time 175383848 ps
CPU time 4.16 seconds
Started May 21 12:32:23 PM PDT 24
Finished May 21 12:32:29 PM PDT 24
Peak memory 211104 kb
Host smart-7aeb2dc4-204a-449d-b7ee-a1167023969e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202516173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3202516173
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3120106968
Short name T371
Test name
Test status
Simulation time 922118537 ps
CPU time 4.03 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:32:43 PM PDT 24
Peak memory 211040 kb
Host smart-87b952ae-d739-4792-b69b-fbeb07462e00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120106968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3120106968
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3433867738
Short name T394
Test name
Test status
Simulation time 1160961954 ps
CPU time 10.33 seconds
Started May 21 12:32:29 PM PDT 24
Finished May 21 12:32:41 PM PDT 24
Peak memory 211048 kb
Host smart-e64e49c8-0a28-4ac5-ba80-cbc7cad6c32c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433867738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3433867738
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1763090952
Short name T79
Test name
Test status
Simulation time 14007005767 ps
CPU time 85.62 seconds
Started May 21 12:32:34 PM PDT 24
Finished May 21 12:34:03 PM PDT 24
Peak memory 211232 kb
Host smart-c7879911-c70d-4cd4-9402-4188867fdb69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763090952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1763090952
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.831825957
Short name T95
Test name
Test status
Simulation time 1496088256 ps
CPU time 6.25 seconds
Started May 21 12:32:23 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 211156 kb
Host smart-e3303f01-c0d9-4b0f-9c3e-8e6cfa8c9862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831825957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.831825957
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4045861972
Short name T382
Test name
Test status
Simulation time 346701895 ps
CPU time 6.86 seconds
Started May 21 12:32:35 PM PDT 24
Finished May 21 12:32:46 PM PDT 24
Peak memory 219400 kb
Host smart-31e2c2c0-695a-4dd2-83d6-70005a747d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045861972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4045861972
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.604093258
Short name T388
Test name
Test status
Simulation time 2383180814 ps
CPU time 81.69 seconds
Started May 21 12:32:25 PM PDT 24
Finished May 21 12:33:48 PM PDT 24
Peak memory 212208 kb
Host smart-4ed0dccd-5e2b-4334-abe1-8e81a45ba69d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604093258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.604093258
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.829489112
Short name T412
Test name
Test status
Simulation time 375003442 ps
CPU time 4.58 seconds
Started May 21 12:32:45 PM PDT 24
Finished May 21 12:32:58 PM PDT 24
Peak memory 213864 kb
Host smart-25a425b4-3edb-4ecc-8276-adf16081aa5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829489112 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.829489112
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2443141864
Short name T418
Test name
Test status
Simulation time 741871892 ps
CPU time 6.92 seconds
Started May 21 12:32:26 PM PDT 24
Finished May 21 12:32:34 PM PDT 24
Peak memory 211136 kb
Host smart-cc9bc667-b0d5-48bf-b520-1977bafe89c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443141864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2443141864
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3752553383
Short name T77
Test name
Test status
Simulation time 545831908 ps
CPU time 28.17 seconds
Started May 21 12:32:24 PM PDT 24
Finished May 21 12:32:53 PM PDT 24
Peak memory 211212 kb
Host smart-f0135450-7c18-4c2d-b610-124e388042a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752553383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3752553383
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1566101761
Short name T398
Test name
Test status
Simulation time 4682451073 ps
CPU time 11.6 seconds
Started May 21 12:32:39 PM PDT 24
Finished May 21 12:32:57 PM PDT 24
Peak memory 211196 kb
Host smart-1ba5e49d-ffb4-47cf-9b08-600062d6f4fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566101761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1566101761
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4196667398
Short name T463
Test name
Test status
Simulation time 3825626567 ps
CPU time 13.1 seconds
Started May 21 12:32:37 PM PDT 24
Finished May 21 12:32:55 PM PDT 24
Peak memory 219448 kb
Host smart-0658a9a6-c9f5-424e-a287-17ccf555f089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196667398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4196667398
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1934563666
Short name T109
Test name
Test status
Simulation time 23500451767 ps
CPU time 80.04 seconds
Started May 21 12:32:24 PM PDT 24
Finished May 21 12:33:45 PM PDT 24
Peak memory 212288 kb
Host smart-b8000d55-aa69-4c99-ad6e-6125926016a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934563666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1934563666
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2872215848
Short name T386
Test name
Test status
Simulation time 8165041322 ps
CPU time 15.57 seconds
Started May 21 12:32:36 PM PDT 24
Finished May 21 12:32:56 PM PDT 24
Peak memory 213344 kb
Host smart-e5183734-7ffe-4433-8978-69db5fdd5a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872215848 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2872215848
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.770896595
Short name T97
Test name
Test status
Simulation time 2377808675 ps
CPU time 10.81 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:01 PM PDT 24
Peak memory 211156 kb
Host smart-4808d104-7101-48da-905c-897c0222116d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770896595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.770896595
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1330627306
Short name T103
Test name
Test status
Simulation time 11944525891 ps
CPU time 46.41 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:36 PM PDT 24
Peak memory 211248 kb
Host smart-d0bbbd09-84b5-4cb6-94f0-54f2c9a06f60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330627306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1330627306
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1602902247
Short name T68
Test name
Test status
Simulation time 839942029 ps
CPU time 6.01 seconds
Started May 21 12:32:37 PM PDT 24
Finished May 21 12:32:48 PM PDT 24
Peak memory 211120 kb
Host smart-8094c60a-419c-4942-bed4-94e59102515c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602902247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1602902247
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.706602250
Short name T373
Test name
Test status
Simulation time 176210333 ps
CPU time 7.06 seconds
Started May 21 12:32:38 PM PDT 24
Finished May 21 12:32:50 PM PDT 24
Peak memory 219424 kb
Host smart-716a0cb3-e8aa-444c-8e98-4ca9d546f710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706602250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.706602250
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3935601459
Short name T460
Test name
Test status
Simulation time 2292749032 ps
CPU time 71.54 seconds
Started May 21 12:32:37 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 212136 kb
Host smart-32abe404-5535-44d8-a0b6-6d871945e1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935601459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3935601459
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2822133476
Short name T401
Test name
Test status
Simulation time 7327575172 ps
CPU time 11.93 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:07 PM PDT 24
Peak memory 219584 kb
Host smart-649ca402-fa97-4869-a015-ff8249fa5d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822133476 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2822133476
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3034368154
Short name T408
Test name
Test status
Simulation time 549924789 ps
CPU time 7.73 seconds
Started May 21 12:32:40 PM PDT 24
Finished May 21 12:32:55 PM PDT 24
Peak memory 211212 kb
Host smart-37bca705-d9e0-40af-be08-52563f140122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034368154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3034368154
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3914306463
Short name T83
Test name
Test status
Simulation time 21111177774 ps
CPU time 88.7 seconds
Started May 21 12:32:36 PM PDT 24
Finished May 21 12:34:10 PM PDT 24
Peak memory 211228 kb
Host smart-97514fd8-41cb-4427-b24c-e99ad2b8aa5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914306463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3914306463
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.774187741
Short name T400
Test name
Test status
Simulation time 7488266416 ps
CPU time 15.38 seconds
Started May 21 12:32:36 PM PDT 24
Finished May 21 12:32:57 PM PDT 24
Peak memory 211200 kb
Host smart-ba52cac4-e78e-4d67-af0c-9a4d48e94142
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774187741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.774187741
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2981275647
Short name T374
Test name
Test status
Simulation time 3745202916 ps
CPU time 10.1 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:05 PM PDT 24
Peak memory 219412 kb
Host smart-16ee121d-fd04-4875-867a-c20297142925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981275647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2981275647
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2137557985
Short name T105
Test name
Test status
Simulation time 2672076860 ps
CPU time 39.62 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 219392 kb
Host smart-541de079-2b48-4e5e-8175-e35df7c65297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137557985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2137557985
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1137587590
Short name T420
Test name
Test status
Simulation time 3635153812 ps
CPU time 13.98 seconds
Started May 21 12:33:04 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 213992 kb
Host smart-664d9c38-9f1e-4acf-a909-234a5b63de69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137587590 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1137587590
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3043067958
Short name T445
Test name
Test status
Simulation time 1658564825 ps
CPU time 4.27 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:01 PM PDT 24
Peak memory 211184 kb
Host smart-82e1f3d4-c0d2-44fc-8075-2190f3304e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043067958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3043067958
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4088969839
Short name T76
Test name
Test status
Simulation time 6748947163 ps
CPU time 36.84 seconds
Started May 21 12:32:37 PM PDT 24
Finished May 21 12:33:18 PM PDT 24
Peak memory 211272 kb
Host smart-b50ddf44-428a-41af-9f16-24926e82909e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088969839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4088969839
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3976131114
Short name T55
Test name
Test status
Simulation time 158237673 ps
CPU time 6.07 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 12:33:05 PM PDT 24
Peak memory 211136 kb
Host smart-ee90d916-d300-4124-b5de-f68af53a8989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976131114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3976131114
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.768000836
Short name T365
Test name
Test status
Simulation time 7527739961 ps
CPU time 16.91 seconds
Started May 21 12:32:36 PM PDT 24
Finished May 21 12:32:58 PM PDT 24
Peak memory 219484 kb
Host smart-c4ce78b2-a16e-4028-ad61-1233258a9054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768000836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.768000836
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2765836734
Short name T115
Test name
Test status
Simulation time 4352029148 ps
CPU time 72.96 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:34:03 PM PDT 24
Peak memory 219420 kb
Host smart-9e212cb3-bdbb-4b5d-bcd4-617061ea7c71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765836734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2765836734
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.833337787
Short name T416
Test name
Test status
Simulation time 362454832 ps
CPU time 5.27 seconds
Started May 21 12:32:37 PM PDT 24
Finished May 21 12:32:48 PM PDT 24
Peak memory 219468 kb
Host smart-3d2ed5c2-0534-4c86-969f-17857e4715f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833337787 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.833337787
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3214236518
Short name T96
Test name
Test status
Simulation time 3458709374 ps
CPU time 9.38 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:07 PM PDT 24
Peak memory 211272 kb
Host smart-72c334d6-f238-4139-844a-56db1abf62ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214236518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3214236518
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2188742628
Short name T397
Test name
Test status
Simulation time 3580955731 ps
CPU time 9.87 seconds
Started May 21 12:32:29 PM PDT 24
Finished May 21 12:32:40 PM PDT 24
Peak memory 211168 kb
Host smart-fbe4c74e-9912-4447-956c-6ee83282dbaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188742628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2188742628
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.293420835
Short name T376
Test name
Test status
Simulation time 5594959750 ps
CPU time 13.94 seconds
Started May 21 12:32:46 PM PDT 24
Finished May 21 12:33:09 PM PDT 24
Peak memory 219476 kb
Host smart-5b1cc067-b5f8-4632-8ad3-7295db77a363
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293420835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.293420835
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1101157981
Short name T198
Test name
Test status
Simulation time 2100857497 ps
CPU time 16.57 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:06 PM PDT 24
Peak memory 211160 kb
Host smart-a5290c97-bb16-4e88-a035-80f7d24e3962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101157981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1101157981
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3735735493
Short name T281
Test name
Test status
Simulation time 1683606585 ps
CPU time 111.37 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:35:14 PM PDT 24
Peak memory 228564 kb
Host smart-c31e055e-e5f3-4d84-8654-3981e528261d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735735493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3735735493
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2239177138
Short name T327
Test name
Test status
Simulation time 3443515854 ps
CPU time 20.67 seconds
Started May 21 12:33:02 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 211736 kb
Host smart-2168b009-4d7b-4a85-8c18-c2ff49a8f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239177138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2239177138
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.635834654
Short name T71
Test name
Test status
Simulation time 7864713333 ps
CPU time 38.44 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:33:43 PM PDT 24
Peak memory 213636 kb
Host smart-faef2458-7171-4889-b0b7-048040e2c600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635834654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.635834654
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2242765091
Short name T196
Test name
Test status
Simulation time 8555636235 ps
CPU time 73.88 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:34:10 PM PDT 24
Peak memory 219280 kb
Host smart-50f59c45-5e5f-4ebb-bc85-64450583f45d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242765091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2242765091
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3309732403
Short name T212
Test name
Test status
Simulation time 378522976 ps
CPU time 6.94 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:32:56 PM PDT 24
Peak memory 211144 kb
Host smart-27ada161-4bb3-479d-b54c-9854fa9ab5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309732403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3309732403
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3173882232
Short name T312
Test name
Test status
Simulation time 37246148143 ps
CPU time 355.56 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:38:53 PM PDT 24
Peak memory 212396 kb
Host smart-9f35e9c2-cafe-423e-9567-d5fc32d518f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173882232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3173882232
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2530530757
Short name T162
Test name
Test status
Simulation time 3083160273 ps
CPU time 13.35 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 12:33:11 PM PDT 24
Peak memory 211860 kb
Host smart-7ad45375-d0e4-45c0-ad2d-4a9bd260b4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530530757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2530530757
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3761583698
Short name T132
Test name
Test status
Simulation time 6282076644 ps
CPU time 14.72 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:12 PM PDT 24
Peak memory 211060 kb
Host smart-997e84ec-104b-4bed-98e5-cc6a13ad8d18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761583698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3761583698
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4040241587
Short name T26
Test name
Test status
Simulation time 3210608579 ps
CPU time 56.45 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:47 PM PDT 24
Peak memory 233308 kb
Host smart-c196e3b2-8744-43ec-81f2-b9992be788f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040241587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4040241587
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1675499549
Short name T131
Test name
Test status
Simulation time 362553529 ps
CPU time 9.85 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:33:33 PM PDT 24
Peak memory 219176 kb
Host smart-8851a6d1-04b7-4350-85bf-da24763eab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675499549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1675499549
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1769453293
Short name T316
Test name
Test status
Simulation time 278390634 ps
CPU time 16.67 seconds
Started May 21 12:33:07 PM PDT 24
Finished May 21 12:33:38 PM PDT 24
Peak memory 213604 kb
Host smart-61d9c74b-fbe8-4f91-bbbe-9de1e8507cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769453293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1769453293
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1689546668
Short name T138
Test name
Test status
Simulation time 2101871826 ps
CPU time 15.99 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:31 PM PDT 24
Peak memory 211172 kb
Host smart-fad91343-fd14-4bdf-8526-10a935f971f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689546668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1689546668
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1098294731
Short name T272
Test name
Test status
Simulation time 3610526156 ps
CPU time 15.36 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:33:22 PM PDT 24
Peak memory 211924 kb
Host smart-83c5be6f-1128-4aa6-8980-fecd9944cb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098294731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1098294731
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3737485490
Short name T195
Test name
Test status
Simulation time 12422527553 ps
CPU time 16.11 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:33:27 PM PDT 24
Peak memory 211116 kb
Host smart-9f30d3bf-a8f0-4f0c-94fa-a363e19097a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737485490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3737485490
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1068895743
Short name T137
Test name
Test status
Simulation time 3675423917 ps
CPU time 29.24 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 12:33:27 PM PDT 24
Peak memory 219284 kb
Host smart-572cedda-6e69-49b8-89d3-192de414f577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068895743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1068895743
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.632162610
Short name T149
Test name
Test status
Simulation time 1404170343 ps
CPU time 27.45 seconds
Started May 21 12:32:58 PM PDT 24
Finished May 21 12:33:36 PM PDT 24
Peak memory 219200 kb
Host smart-1fe52d25-afc1-414e-92ef-6e17402b4ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632162610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.632162610
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.707157902
Short name T267
Test name
Test status
Simulation time 88186803 ps
CPU time 4.2 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:00 PM PDT 24
Peak memory 211196 kb
Host smart-db81c148-0de5-4659-8d29-685a97a363ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707157902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.707157902
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2958506005
Short name T177
Test name
Test status
Simulation time 42368347546 ps
CPU time 377.96 seconds
Started May 21 12:33:07 PM PDT 24
Finished May 21 12:39:38 PM PDT 24
Peak memory 237800 kb
Host smart-fe5781aa-e743-4167-b3e9-00cb1bcfc0ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958506005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2958506005
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.754471847
Short name T174
Test name
Test status
Simulation time 3307165735 ps
CPU time 28.51 seconds
Started May 21 12:32:58 PM PDT 24
Finished May 21 12:33:38 PM PDT 24
Peak memory 211764 kb
Host smart-1f3662de-f7c3-4a40-9f26-f510fc0bcbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754471847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.754471847
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2866753797
Short name T170
Test name
Test status
Simulation time 381789730 ps
CPU time 5.28 seconds
Started May 21 12:33:14 PM PDT 24
Finished May 21 12:33:39 PM PDT 24
Peak memory 211000 kb
Host smart-02669e03-ad6c-4d49-af85-0ff05c17b935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866753797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2866753797
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3572058441
Short name T362
Test name
Test status
Simulation time 5402487526 ps
CPU time 40.93 seconds
Started May 21 12:32:45 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 213468 kb
Host smart-edafe026-a47a-41c2-8ee2-9e5c2861de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572058441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3572058441
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3398263547
Short name T40
Test name
Test status
Simulation time 26852529119 ps
CPU time 63.11 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:34:07 PM PDT 24
Peak memory 219376 kb
Host smart-d2fdd27c-23e5-4fa8-ad08-7f4563e685d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398263547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3398263547
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.743626732
Short name T238
Test name
Test status
Simulation time 8445899240 ps
CPU time 11.45 seconds
Started May 21 12:32:58 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 211228 kb
Host smart-9cd37cb8-2b64-4ce7-876d-66fc9fc0564d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743626732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.743626732
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3431558363
Short name T117
Test name
Test status
Simulation time 195937313633 ps
CPU time 261.53 seconds
Started May 21 12:33:04 PM PDT 24
Finished May 21 12:37:38 PM PDT 24
Peak memory 233920 kb
Host smart-d18f4c6a-4c07-43b7-969a-7c733e9c5a34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431558363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3431558363
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.612297101
Short name T13
Test name
Test status
Simulation time 6061409636 ps
CPU time 14.27 seconds
Started May 21 12:32:50 PM PDT 24
Finished May 21 12:33:14 PM PDT 24
Peak memory 211104 kb
Host smart-1bb7531d-a4af-4716-a00d-5f01b38645a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612297101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.612297101
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1886641970
Short name T265
Test name
Test status
Simulation time 8627844306 ps
CPU time 26.41 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:33:50 PM PDT 24
Peak memory 219404 kb
Host smart-32b2c3f2-69d3-4dbd-9557-be8fd16b42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886641970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1886641970
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1894553124
Short name T176
Test name
Test status
Simulation time 300025600 ps
CPU time 16.63 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:33:21 PM PDT 24
Peak memory 213680 kb
Host smart-ddb4a22f-0a3a-4bee-8a95-06ea60541051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894553124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1894553124
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2064525307
Short name T51
Test name
Test status
Simulation time 27096437136 ps
CPU time 2207.05 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 01:10:17 PM PDT 24
Peak memory 227724 kb
Host smart-6fea442a-7ab2-4796-898b-1c4ac42c5af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064525307 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2064525307
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.743464551
Short name T275
Test name
Test status
Simulation time 1482367368 ps
CPU time 13.17 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:19 PM PDT 24
Peak memory 211116 kb
Host smart-ea560dae-af65-4a7b-9ab1-1b3bd8d82dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743464551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.743464551
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4160703251
Short name T168
Test name
Test status
Simulation time 125812656888 ps
CPU time 363 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:39:18 PM PDT 24
Peak memory 236748 kb
Host smart-5925d6b7-dc63-405f-803d-d2ee13f4328c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160703251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4160703251
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2750207475
Short name T302
Test name
Test status
Simulation time 175613023 ps
CPU time 9.59 seconds
Started May 21 12:32:50 PM PDT 24
Finished May 21 12:33:09 PM PDT 24
Peak memory 211796 kb
Host smart-79eba9a4-b014-4c6b-ab89-5e5c5a4d9135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750207475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2750207475
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2499286327
Short name T356
Test name
Test status
Simulation time 5283514293 ps
CPU time 13.52 seconds
Started May 21 12:33:00 PM PDT 24
Finished May 21 12:33:24 PM PDT 24
Peak memory 211216 kb
Host smart-0c9348eb-11a2-4a66-910a-acb866fbbc44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499286327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2499286327
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.626380225
Short name T271
Test name
Test status
Simulation time 14640874833 ps
CPU time 29.44 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:55 PM PDT 24
Peak memory 219344 kb
Host smart-9e474558-7799-4bb8-a6d7-472b3c05f11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626380225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.626380225
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3833614306
Short name T320
Test name
Test status
Simulation time 549871754 ps
CPU time 18.21 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:33:23 PM PDT 24
Peak memory 211716 kb
Host smart-efcf7f05-6529-4454-a815-66f793b08b11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833614306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3833614306
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1201317452
Short name T59
Test name
Test status
Simulation time 1411811604 ps
CPU time 8.92 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:33:16 PM PDT 24
Peak memory 211128 kb
Host smart-60c82e41-1ef8-478d-b172-c9067661d304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201317452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1201317452
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3791169398
Short name T145
Test name
Test status
Simulation time 17286768288 ps
CPU time 218.06 seconds
Started May 21 12:33:07 PM PDT 24
Finished May 21 12:37:00 PM PDT 24
Peak memory 238912 kb
Host smart-292f4f09-624b-4ad8-8131-c50c66a7ffc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791169398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3791169398
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2170860044
Short name T258
Test name
Test status
Simulation time 4752280967 ps
CPU time 23.72 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:29 PM PDT 24
Peak memory 210648 kb
Host smart-a16a45b2-b602-4a22-8c54-3af3c3a1b052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170860044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2170860044
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1496570650
Short name T173
Test name
Test status
Simulation time 2945240584 ps
CPU time 9.95 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:02 PM PDT 24
Peak memory 211096 kb
Host smart-f0e2a232-1e80-4c06-b011-57be8467b90c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496570650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1496570650
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.914859169
Short name T189
Test name
Test status
Simulation time 3364151281 ps
CPU time 21.29 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:47 PM PDT 24
Peak memory 213744 kb
Host smart-81b73a7b-bf60-40ee-be74-4f52367d4915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914859169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.914859169
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3294995690
Short name T346
Test name
Test status
Simulation time 68304081570 ps
CPU time 57.07 seconds
Started May 21 12:33:15 PM PDT 24
Finished May 21 12:34:33 PM PDT 24
Peak memory 215592 kb
Host smart-f902b01e-3ed3-4a8a-8765-f45320b49062
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294995690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3294995690
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2001695652
Short name T349
Test name
Test status
Simulation time 903751568 ps
CPU time 9.88 seconds
Started May 21 12:33:01 PM PDT 24
Finished May 21 12:33:23 PM PDT 24
Peak memory 211080 kb
Host smart-7588f2fd-b8fb-4425-9cf4-7ad114a336b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001695652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2001695652
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2866284856
Short name T25
Test name
Test status
Simulation time 7155747539 ps
CPU time 166.39 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:36:14 PM PDT 24
Peak memory 213544 kb
Host smart-15631674-cbba-4375-a2af-17c35d5ec5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866284856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2866284856
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1116954605
Short name T86
Test name
Test status
Simulation time 2303321330 ps
CPU time 22.51 seconds
Started May 21 12:33:04 PM PDT 24
Finished May 21 12:33:39 PM PDT 24
Peak memory 212132 kb
Host smart-c918b4af-6719-4a04-ac95-d033c689fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116954605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1116954605
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.598680689
Short name T128
Test name
Test status
Simulation time 8762251645 ps
CPU time 16.85 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:42 PM PDT 24
Peak memory 211092 kb
Host smart-edea0bad-d563-4584-8fc0-0d512516e573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598680689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.598680689
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2195220998
Short name T161
Test name
Test status
Simulation time 4147574334 ps
CPU time 32.65 seconds
Started May 21 12:32:53 PM PDT 24
Finished May 21 12:33:36 PM PDT 24
Peak memory 219324 kb
Host smart-fbb9adc3-758c-44c3-9a83-609971943aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195220998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2195220998
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2102984362
Short name T299
Test name
Test status
Simulation time 19018955842 ps
CPU time 54.15 seconds
Started May 21 12:32:57 PM PDT 24
Finished May 21 12:34:02 PM PDT 24
Peak memory 219336 kb
Host smart-91947aff-9e10-41d6-a68e-7554e59cd934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102984362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2102984362
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3585595936
Short name T353
Test name
Test status
Simulation time 164917498 ps
CPU time 4.32 seconds
Started May 21 12:33:06 PM PDT 24
Finished May 21 12:33:25 PM PDT 24
Peak memory 211204 kb
Host smart-aea12894-2e03-4335-8507-92e7455b4819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585595936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3585595936
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.936261716
Short name T269
Test name
Test status
Simulation time 32120802093 ps
CPU time 166.52 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:36:10 PM PDT 24
Peak memory 230824 kb
Host smart-5ab2e20b-02e9-4eec-8f6a-937bdcceb6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936261716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.936261716
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3477010332
Short name T209
Test name
Test status
Simulation time 10466034616 ps
CPU time 23.45 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 212172 kb
Host smart-a168e1c6-60f2-4417-9a99-1663bf302547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477010332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3477010332
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1541560680
Short name T172
Test name
Test status
Simulation time 1693860605 ps
CPU time 14.84 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:33:49 PM PDT 24
Peak memory 211004 kb
Host smart-c63192a3-bb95-4e49-ac48-35e0614df602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541560680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1541560680
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.115874721
Short name T229
Test name
Test status
Simulation time 2644433860 ps
CPU time 25.04 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:40 PM PDT 24
Peak memory 219328 kb
Host smart-671fab42-b471-40ea-b619-099a842f3819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115874721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.115874721
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1021956957
Short name T219
Test name
Test status
Simulation time 661607012 ps
CPU time 17.03 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:33:22 PM PDT 24
Peak memory 214716 kb
Host smart-812f5bf6-7d72-4737-b7c6-1aa59d7358e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021956957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1021956957
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.116806169
Short name T233
Test name
Test status
Simulation time 461494117 ps
CPU time 4.02 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:33:55 PM PDT 24
Peak memory 211180 kb
Host smart-bbdbe1b0-fe56-4611-a3da-74bee98a3d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116806169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.116806169
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2408315057
Short name T300
Test name
Test status
Simulation time 9377437878 ps
CPU time 104.21 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:34:51 PM PDT 24
Peak memory 236088 kb
Host smart-9a635a42-0af7-4d3f-bbc5-d22cde56fbd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408315057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2408315057
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3348540931
Short name T167
Test name
Test status
Simulation time 57529855642 ps
CPU time 31.21 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:34:00 PM PDT 24
Peak memory 212176 kb
Host smart-7ae1f4ec-5d90-4572-9e09-e9edf572f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348540931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3348540931
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1191624753
Short name T259
Test name
Test status
Simulation time 2178508811 ps
CPU time 17.17 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:22 PM PDT 24
Peak memory 211196 kb
Host smart-c442cf4d-9e72-4804-8d74-0a714cef08d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191624753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1191624753
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1096219942
Short name T93
Test name
Test status
Simulation time 14945845106 ps
CPU time 30.21 seconds
Started May 21 12:33:06 PM PDT 24
Finished May 21 12:33:53 PM PDT 24
Peak memory 219332 kb
Host smart-23a5a672-5b6b-43e2-9775-03143654b80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096219942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1096219942
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1607159617
Short name T339
Test name
Test status
Simulation time 5228309172 ps
CPU time 9.94 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:51 PM PDT 24
Peak memory 211244 kb
Host smart-ca2b13e9-07ef-4181-add5-1f397f586459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607159617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1607159617
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1682133572
Short name T160
Test name
Test status
Simulation time 59183636365 ps
CPU time 212.45 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:37:15 PM PDT 24
Peak memory 233676 kb
Host smart-98ac02ad-f89c-4caf-85b9-565f404cbcec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682133572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1682133572
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2004801680
Short name T134
Test name
Test status
Simulation time 2050696837 ps
CPU time 21.9 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:47 PM PDT 24
Peak memory 211152 kb
Host smart-7bf01baf-295b-48a3-ab38-53e436e8e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004801680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2004801680
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.656146230
Short name T360
Test name
Test status
Simulation time 1745761993 ps
CPU time 15.9 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 12:33:14 PM PDT 24
Peak memory 210968 kb
Host smart-e9b1816c-03b3-4fc8-aa29-33f79b0369d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=656146230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.656146230
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.394155091
Short name T122
Test name
Test status
Simulation time 817505603 ps
CPU time 10.16 seconds
Started May 21 12:32:57 PM PDT 24
Finished May 21 12:33:18 PM PDT 24
Peak memory 219200 kb
Host smart-70748326-31c9-478f-ae79-60fc229aba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394155091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.394155091
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3045823268
Short name T43
Test name
Test status
Simulation time 2209150522 ps
CPU time 42.27 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 12:33:51 PM PDT 24
Peak memory 214772 kb
Host smart-9936abb3-266e-4ea2-b164-b2ce8069c303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045823268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3045823268
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2699209185
Short name T192
Test name
Test status
Simulation time 4772690113 ps
CPU time 10.93 seconds
Started May 21 12:32:58 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 211232 kb
Host smart-e48fa27d-a74c-48d2-98f0-e58cb4cbcaf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699209185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2699209185
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2482442347
Short name T318
Test name
Test status
Simulation time 14413666522 ps
CPU time 128.06 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:35:31 PM PDT 24
Peak memory 237744 kb
Host smart-b48d1b6c-6ccc-4cdf-b060-58ea5026249f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482442347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2482442347
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2505550424
Short name T237
Test name
Test status
Simulation time 28897853569 ps
CPU time 31.99 seconds
Started May 21 12:32:57 PM PDT 24
Finished May 21 12:33:39 PM PDT 24
Peak memory 212224 kb
Host smart-183f33a2-1007-4815-8bb4-f60f21349e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505550424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2505550424
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1216608105
Short name T171
Test name
Test status
Simulation time 4505817724 ps
CPU time 12.14 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:17 PM PDT 24
Peak memory 211044 kb
Host smart-dde37de2-5fa5-4c8a-b800-40354dfa1a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216608105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1216608105
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1149971732
Short name T225
Test name
Test status
Simulation time 3774437883 ps
CPU time 33.71 seconds
Started May 21 12:33:07 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 219296 kb
Host smart-902f3f23-f716-4559-8359-34c1e559eac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149971732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1149971732
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2581408722
Short name T201
Test name
Test status
Simulation time 10290797602 ps
CPU time 46.46 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:34:17 PM PDT 24
Peak memory 214388 kb
Host smart-f0b4823a-d1b3-48df-b2b2-0a523463a838
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581408722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2581408722
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2922037560
Short name T186
Test name
Test status
Simulation time 5246407686 ps
CPU time 10.28 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:06 PM PDT 24
Peak memory 211248 kb
Host smart-465cd1e2-7ac1-4d60-bdbb-83906a3138c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922037560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2922037560
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2003670806
Short name T129
Test name
Test status
Simulation time 10764402991 ps
CPU time 158.8 seconds
Started May 21 12:32:53 PM PDT 24
Finished May 21 12:35:42 PM PDT 24
Peak memory 232784 kb
Host smart-e44af247-a128-45cf-8d4e-fa876242d4c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003670806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2003670806
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4145405275
Short name T87
Test name
Test status
Simulation time 3613019456 ps
CPU time 24.84 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:23 PM PDT 24
Peak memory 211768 kb
Host smart-cb77813c-6f88-4413-9022-404e5a36e883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145405275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4145405275
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2805642006
Short name T324
Test name
Test status
Simulation time 4021575671 ps
CPU time 18.24 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:11 PM PDT 24
Peak memory 211116 kb
Host smart-fa346648-f20f-4580-b38d-a4d92e999819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805642006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2805642006
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3220626293
Short name T37
Test name
Test status
Simulation time 162502644 ps
CPU time 52.89 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:49 PM PDT 24
Peak memory 233196 kb
Host smart-414046cd-37bb-4c1b-9319-9fed3c0205f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220626293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3220626293
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.504934022
Short name T178
Test name
Test status
Simulation time 29739628520 ps
CPU time 20.82 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 219324 kb
Host smart-cd15470a-fad3-4cea-afc0-579a1ca1ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504934022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.504934022
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1326514853
Short name T211
Test name
Test status
Simulation time 6793506426 ps
CPU time 20.72 seconds
Started May 21 12:33:00 PM PDT 24
Finished May 21 12:33:32 PM PDT 24
Peak memory 211028 kb
Host smart-69ecba55-69ad-4658-9358-8ae7ea078a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326514853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1326514853
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3940300420
Short name T204
Test name
Test status
Simulation time 9907281663 ps
CPU time 4053.41 seconds
Started May 21 12:32:41 PM PDT 24
Finished May 21 01:40:22 PM PDT 24
Peak memory 221972 kb
Host smart-874e449c-b52f-46ac-a1c0-2368aafe9da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940300420 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3940300420
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2815398126
Short name T295
Test name
Test status
Simulation time 3043696493 ps
CPU time 13.42 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:40 PM PDT 24
Peak memory 211204 kb
Host smart-2a04d2c4-b9c2-4423-962d-3a3b88f8e667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815398126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2815398126
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.825576805
Short name T264
Test name
Test status
Simulation time 14092772595 ps
CPU time 31.63 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:34:01 PM PDT 24
Peak memory 219580 kb
Host smart-45163691-caf7-46b0-827c-930d8e9fb26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825576805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.825576805
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1065558096
Short name T9
Test name
Test status
Simulation time 2007742761 ps
CPU time 16.71 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:21 PM PDT 24
Peak memory 211076 kb
Host smart-18762e9d-7067-48f1-9ddb-8c47035b4060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065558096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1065558096
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2451697234
Short name T313
Test name
Test status
Simulation time 3797205820 ps
CPU time 35.64 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:33:40 PM PDT 24
Peak memory 219432 kb
Host smart-142af0e6-26ff-4069-be17-d6c11e5063f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451697234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2451697234
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4089098852
Short name T245
Test name
Test status
Simulation time 1152174019 ps
CPU time 31.38 seconds
Started May 21 12:33:06 PM PDT 24
Finished May 21 12:33:51 PM PDT 24
Peak memory 217508 kb
Host smart-6872333d-5192-47c1-b30a-ecaff5eadbf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089098852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4089098852
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.174248215
Short name T243
Test name
Test status
Simulation time 1155851375 ps
CPU time 11.13 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:33:18 PM PDT 24
Peak memory 211124 kb
Host smart-57bb9b6c-5811-4150-8efb-b81c100a7683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174248215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.174248215
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.556815111
Short name T158
Test name
Test status
Simulation time 59321672644 ps
CPU time 319.91 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:38:47 PM PDT 24
Peak memory 218548 kb
Host smart-35fa21b4-6ed3-4531-92e8-7a2b98f4a363
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556815111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.556815111
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3236101324
Short name T152
Test name
Test status
Simulation time 333351044 ps
CPU time 9.29 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:15 PM PDT 24
Peak memory 211752 kb
Host smart-1cf765df-dda9-4a67-8454-14fc69875ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236101324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3236101324
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3834494045
Short name T309
Test name
Test status
Simulation time 1725931998 ps
CPU time 9.87 seconds
Started May 21 12:32:53 PM PDT 24
Finished May 21 12:33:13 PM PDT 24
Peak memory 210916 kb
Host smart-8a3b8821-5751-4d7b-9b28-5390b34869b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834494045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3834494045
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3311166879
Short name T276
Test name
Test status
Simulation time 8895174823 ps
CPU time 33.68 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:34:04 PM PDT 24
Peak memory 213688 kb
Host smart-93b43077-6ca2-4bc7-bb65-e6da9ca233a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311166879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3311166879
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3119941487
Short name T249
Test name
Test status
Simulation time 5766610869 ps
CPU time 58.84 seconds
Started May 21 12:33:05 PM PDT 24
Finished May 21 12:34:16 PM PDT 24
Peak memory 219644 kb
Host smart-5d9af1b8-ce11-4dfa-bb94-7cff817c491d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119941487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3119941487
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2759396562
Short name T135
Test name
Test status
Simulation time 8821576046 ps
CPU time 17.32 seconds
Started May 21 12:33:04 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 211252 kb
Host smart-fb321fba-6c12-4ad2-95dc-69069d5c5411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759396562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2759396562
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3251485903
Short name T216
Test name
Test status
Simulation time 1091099875 ps
CPU time 74.24 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:34:44 PM PDT 24
Peak memory 227564 kb
Host smart-e1d4cf77-3a40-424d-be3c-6aed8dfe1668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251485903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3251485903
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3031422992
Short name T16
Test name
Test status
Simulation time 168845416 ps
CPU time 9.23 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 211804 kb
Host smart-1b8d2113-cf22-4c50-928a-dbfff7c54072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031422992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3031422992
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1974917621
Short name T343
Test name
Test status
Simulation time 836454470 ps
CPU time 5.39 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:46 PM PDT 24
Peak memory 210916 kb
Host smart-7e3d3936-633b-4d51-80ee-48065091cf0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974917621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1974917621
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2482104552
Short name T205
Test name
Test status
Simulation time 11341732314 ps
CPU time 26.78 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 214044 kb
Host smart-5820f7cb-75e9-41c9-8b81-0541cf916add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482104552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2482104552
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.251273527
Short name T330
Test name
Test status
Simulation time 8011956417 ps
CPU time 19.14 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:33:25 PM PDT 24
Peak memory 212300 kb
Host smart-c6ed0682-b824-40e7-90c4-0bf787103fae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251273527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.251273527
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2533124805
Short name T336
Test name
Test status
Simulation time 16383784168 ps
CPU time 602.83 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:43:01 PM PDT 24
Peak memory 225628 kb
Host smart-6bf579fd-c736-4c73-b407-f1e3d26309c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533124805 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2533124805
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.278346789
Short name T58
Test name
Test status
Simulation time 1209812478 ps
CPU time 6.33 seconds
Started May 21 12:33:01 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 211220 kb
Host smart-996964c2-a575-40c3-9bc5-95adfb0bd6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278346789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.278346789
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2340040855
Short name T260
Test name
Test status
Simulation time 172429677070 ps
CPU time 224.05 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:37:08 PM PDT 24
Peak memory 237652 kb
Host smart-2a578fdd-e764-418f-9a2a-db9a43841936
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340040855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2340040855
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1709472259
Short name T214
Test name
Test status
Simulation time 13699694321 ps
CPU time 30.01 seconds
Started May 21 12:32:56 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 212348 kb
Host smart-b8dc8548-f52d-4df0-a65a-bbe8af01a3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709472259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1709472259
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3698510207
Short name T247
Test name
Test status
Simulation time 5505248303 ps
CPU time 13.1 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:39 PM PDT 24
Peak memory 211116 kb
Host smart-9a8c6058-f70c-432b-b92f-61937f442371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698510207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3698510207
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.91793524
Short name T119
Test name
Test status
Simulation time 9322893380 ps
CPU time 25.2 seconds
Started May 21 12:33:14 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 219352 kb
Host smart-ce962e4b-5e3a-46a0-8a19-a35888bec343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91793524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.91793524
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.360079819
Short name T352
Test name
Test status
Simulation time 25233834881 ps
CPU time 53.01 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:34:04 PM PDT 24
Peak memory 219312 kb
Host smart-20f1d762-cced-4fe4-9710-aa1fd6b02c64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360079819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.360079819
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.537932685
Short name T283
Test name
Test status
Simulation time 1424108672 ps
CPU time 8.59 seconds
Started May 21 12:33:01 PM PDT 24
Finished May 21 12:33:21 PM PDT 24
Peak memory 211076 kb
Host smart-9612ff59-baa1-4d8c-a44e-26fe15cdbf82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537932685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.537932685
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2397133304
Short name T331
Test name
Test status
Simulation time 4000068777 ps
CPU time 59.6 seconds
Started May 21 12:33:00 PM PDT 24
Finished May 21 12:34:10 PM PDT 24
Peak memory 233716 kb
Host smart-88767f08-1dd5-4047-ac97-a72960460f6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397133304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2397133304
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1407133141
Short name T250
Test name
Test status
Simulation time 2734827671 ps
CPU time 14.68 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 212100 kb
Host smart-7a31e4e7-5d50-43ff-aa5c-0a67ad8037a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407133141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1407133141
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3025409751
Short name T354
Test name
Test status
Simulation time 7959440479 ps
CPU time 16.55 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:33:39 PM PDT 24
Peak memory 211196 kb
Host smart-fd51750c-5160-4a62-b88c-f570a079aa26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025409751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3025409751
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1377313197
Short name T74
Test name
Test status
Simulation time 9621171087 ps
CPU time 24.62 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:33:35 PM PDT 24
Peak memory 219428 kb
Host smart-70682e75-989b-4829-a6f1-66bcf8899a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377313197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1377313197
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2731083710
Short name T143
Test name
Test status
Simulation time 848711334 ps
CPU time 11.79 seconds
Started May 21 12:33:05 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 210980 kb
Host smart-9a4cc3d5-ea49-4e2c-89ab-e51de0d41f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731083710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2731083710
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3387176116
Short name T244
Test name
Test status
Simulation time 2567698019 ps
CPU time 10.09 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:33:55 PM PDT 24
Peak memory 211584 kb
Host smart-95686ce3-d75b-4d11-9808-e7d776b07bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387176116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3387176116
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2597177717
Short name T310
Test name
Test status
Simulation time 67300171898 ps
CPU time 319.63 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:38:43 PM PDT 24
Peak memory 233720 kb
Host smart-c9c2d7a4-422c-456c-b278-817c30c0ffc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597177717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2597177717
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.19514155
Short name T355
Test name
Test status
Simulation time 623648157 ps
CPU time 11.01 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:27 PM PDT 24
Peak memory 212192 kb
Host smart-51e2869a-57e9-4e7b-95b5-7f763e64d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19514155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.19514155
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.716800738
Short name T297
Test name
Test status
Simulation time 995932491 ps
CPU time 11.17 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:26 PM PDT 24
Peak memory 210956 kb
Host smart-023178de-d592-4fee-88a9-43b73ad45fb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716800738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.716800738
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1227628399
Short name T273
Test name
Test status
Simulation time 1580160885 ps
CPU time 20.75 seconds
Started May 21 12:32:58 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 212808 kb
Host smart-0ad94b50-fa22-45b1-8831-b9d1cabe9e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227628399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1227628399
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.9750710
Short name T234
Test name
Test status
Simulation time 892566284 ps
CPU time 15.82 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:31 PM PDT 24
Peak memory 215072 kb
Host smart-11803aaa-7fc7-448b-b46f-e32f64e7b788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9750710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.rom_ctrl_stress_all.9750710
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.735540618
Short name T49
Test name
Test status
Simulation time 95850545050 ps
CPU time 5110.5 seconds
Started May 21 12:33:05 PM PDT 24
Finished May 21 01:58:28 PM PDT 24
Peak memory 235936 kb
Host smart-e3f7c38c-402e-43b4-943f-4d939fef2e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735540618 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.735540618
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1878624613
Short name T140
Test name
Test status
Simulation time 54816681518 ps
CPU time 152.25 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:35:42 PM PDT 24
Peak memory 228668 kb
Host smart-812d3c4a-ca98-4c15-b67e-93f716c8d3d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878624613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1878624613
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1455366440
Short name T326
Test name
Test status
Simulation time 6066475758 ps
CPU time 15.91 seconds
Started May 21 12:33:21 PM PDT 24
Finished May 21 12:34:04 PM PDT 24
Peak memory 211092 kb
Host smart-521d01ea-65ca-4654-a0b4-2206fa705d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455366440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1455366440
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1517967219
Short name T194
Test name
Test status
Simulation time 5422672494 ps
CPU time 24.17 seconds
Started May 21 12:33:05 PM PDT 24
Finished May 21 12:33:42 PM PDT 24
Peak memory 214044 kb
Host smart-46811c30-d7ef-425f-b01a-ef04ca1d0a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517967219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1517967219
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1434239910
Short name T307
Test name
Test status
Simulation time 95034161774 ps
CPU time 85.49 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:35:17 PM PDT 24
Peak memory 219416 kb
Host smart-65607b8c-272c-45db-9a2a-f07397d7d5e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434239910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1434239910
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2279782380
Short name T314
Test name
Test status
Simulation time 1035918304 ps
CPU time 4.16 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:31 PM PDT 24
Peak memory 211120 kb
Host smart-e2ed79f6-2cef-4d19-a9bf-ae0f462af2a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279782380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2279782380
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3909986167
Short name T363
Test name
Test status
Simulation time 540917376628 ps
CPU time 486.64 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:41:29 PM PDT 24
Peak memory 235080 kb
Host smart-e250f29b-9d25-4e7d-922b-dbad89d0a4c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909986167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3909986167
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3408387994
Short name T231
Test name
Test status
Simulation time 5032908152 ps
CPU time 23.86 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:29 PM PDT 24
Peak memory 219560 kb
Host smart-98ff1c61-5a25-495c-b81d-86db1f8157fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408387994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3408387994
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1971756487
Short name T127
Test name
Test status
Simulation time 7109472164 ps
CPU time 17.38 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:44 PM PDT 24
Peak memory 211220 kb
Host smart-adc54140-fef7-4fd4-b49d-bbcf6f5031a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971756487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1971756487
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3234267055
Short name T46
Test name
Test status
Simulation time 9743565974 ps
CPU time 26.15 seconds
Started May 21 12:33:07 PM PDT 24
Finished May 21 12:33:47 PM PDT 24
Peak memory 213464 kb
Host smart-25278ff5-0a7d-4824-b905-25ed772e81bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234267055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3234267055
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3669212970
Short name T351
Test name
Test status
Simulation time 4173583661 ps
CPU time 31.89 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:34:23 PM PDT 24
Peak memory 219352 kb
Host smart-8986077f-a885-41e5-9ca3-b85aaceed1df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669212970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3669212970
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.396279038
Short name T147
Test name
Test status
Simulation time 1990641572 ps
CPU time 10.73 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:00 PM PDT 24
Peak memory 211060 kb
Host smart-25d9ad92-2f45-4fd9-bc13-0c132de73b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396279038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.396279038
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1741103872
Short name T308
Test name
Test status
Simulation time 12305964156 ps
CPU time 25.66 seconds
Started May 21 12:33:24 PM PDT 24
Finished May 21 12:34:18 PM PDT 24
Peak memory 212376 kb
Host smart-9d035017-9052-4b95-90ea-69b994215c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741103872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1741103872
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2574621338
Short name T182
Test name
Test status
Simulation time 5689097870 ps
CPU time 13.38 seconds
Started May 21 12:33:06 PM PDT 24
Finished May 21 12:33:33 PM PDT 24
Peak memory 211188 kb
Host smart-5022862c-7e50-43b8-aad9-8a15a418ef3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574621338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2574621338
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3944671399
Short name T41
Test name
Test status
Simulation time 2372773904 ps
CPU time 17.3 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:34:00 PM PDT 24
Peak memory 219356 kb
Host smart-0a7448fb-3ab1-4fd9-b0f5-20600ec711e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944671399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3944671399
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1953153074
Short name T184
Test name
Test status
Simulation time 4024177717 ps
CPU time 41.16 seconds
Started May 21 12:33:01 PM PDT 24
Finished May 21 12:33:53 PM PDT 24
Peak memory 219364 kb
Host smart-63486b22-1ba4-40bd-a8b9-0f54c08f7102
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953153074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1953153074
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2080562127
Short name T29
Test name
Test status
Simulation time 55925885374 ps
CPU time 2143.51 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 01:09:26 PM PDT 24
Peak memory 238296 kb
Host smart-0daaaaef-73dc-45c8-b2be-d44c26bdde51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080562127 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2080562127
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1265712473
Short name T130
Test name
Test status
Simulation time 1648293430 ps
CPU time 6.81 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:33:52 PM PDT 24
Peak memory 211136 kb
Host smart-cf7471bf-19a1-4d15-bdb1-e08617c2413b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265712473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1265712473
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3858844550
Short name T45
Test name
Test status
Simulation time 35104463708 ps
CPU time 346.35 seconds
Started May 21 12:33:13 PM PDT 24
Finished May 21 12:39:19 PM PDT 24
Peak memory 219408 kb
Host smart-477c0758-bc6f-4141-8ba7-15d411abd469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858844550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3858844550
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.704547100
Short name T223
Test name
Test status
Simulation time 17397208299 ps
CPU time 14.73 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:29 PM PDT 24
Peak memory 211084 kb
Host smart-448006e9-8ee6-41c4-8135-2ba399a35164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704547100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.704547100
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2125173559
Short name T251
Test name
Test status
Simulation time 7426981068 ps
CPU time 35.53 seconds
Started May 21 12:33:16 PM PDT 24
Finished May 21 12:34:13 PM PDT 24
Peak memory 214632 kb
Host smart-92f67d42-1ce9-4003-bdf9-4ebad0b3350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125173559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2125173559
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1336333207
Short name T344
Test name
Test status
Simulation time 2749306365 ps
CPU time 33.8 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:34:16 PM PDT 24
Peak memory 213696 kb
Host smart-c25e5aea-b32f-4b5a-8a58-733d544c0d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336333207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1336333207
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.42482081
Short name T50
Test name
Test status
Simulation time 92186784685 ps
CPU time 852.78 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:47:58 PM PDT 24
Peak memory 229908 kb
Host smart-f4b704a3-6626-401e-9c8a-cb41485a9b4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42482081 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.42482081
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2121163817
Short name T321
Test name
Test status
Simulation time 853719167 ps
CPU time 9.56 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:33:53 PM PDT 24
Peak memory 211148 kb
Host smart-d99801d2-400b-432d-a9cb-45655ad44346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121163817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2121163817
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3967571212
Short name T280
Test name
Test status
Simulation time 48107182659 ps
CPU time 197.39 seconds
Started May 21 12:32:46 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 228788 kb
Host smart-3d1e60bc-d325-4368-a875-c9e079f800d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967571212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3967571212
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3456432012
Short name T286
Test name
Test status
Simulation time 4024337352 ps
CPU time 32.5 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:34:02 PM PDT 24
Peak memory 211836 kb
Host smart-18109f10-abbc-4b3f-bf88-ac4f3d749a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456432012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3456432012
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.672308593
Short name T277
Test name
Test status
Simulation time 95149694 ps
CPU time 5.43 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:33:10 PM PDT 24
Peak memory 211284 kb
Host smart-8bdf8833-7041-4652-9d3c-244dd1ab4ee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672308593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.672308593
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2099857847
Short name T38
Test name
Test status
Simulation time 2467039541 ps
CPU time 112.32 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:34:44 PM PDT 24
Peak memory 236644 kb
Host smart-556521cc-35ca-497c-9b44-4bef0039f250
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099857847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2099857847
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.105984154
Short name T213
Test name
Test status
Simulation time 6827169563 ps
CPU time 29.43 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:22 PM PDT 24
Peak memory 213712 kb
Host smart-1f1060c2-23d8-4312-aadf-424fc6623fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105984154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.105984154
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2141891326
Short name T357
Test name
Test status
Simulation time 3731726952 ps
CPU time 37.7 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:33 PM PDT 24
Peak memory 213972 kb
Host smart-68ff8a01-671c-4967-9865-40a9e31ca8af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141891326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2141891326
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1237107347
Short name T328
Test name
Test status
Simulation time 1659409522 ps
CPU time 9.27 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:35 PM PDT 24
Peak memory 211160 kb
Host smart-a5c7160a-8c0b-4134-8724-63b49fe5900f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237107347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1237107347
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1115283589
Short name T335
Test name
Test status
Simulation time 5625551957 ps
CPU time 170.35 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:36:36 PM PDT 24
Peak memory 224704 kb
Host smart-e9dd91fc-9211-4952-8213-52c849f0118b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115283589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1115283589
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3890024277
Short name T333
Test name
Test status
Simulation time 831676220 ps
CPU time 9.59 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 211884 kb
Host smart-dd54f60d-f8a2-4010-99fe-4e82d49d47e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890024277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3890024277
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.134613333
Short name T125
Test name
Test status
Simulation time 2088735224 ps
CPU time 15.62 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:57 PM PDT 24
Peak memory 210960 kb
Host smart-9198647d-fd32-425d-abe9-017472dcacc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134613333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.134613333
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2991794538
Short name T121
Test name
Test status
Simulation time 942603984 ps
CPU time 17.24 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 219228 kb
Host smart-3d53790a-8624-4319-88fe-9dbf274a2183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991794538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2991794538
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3517221169
Short name T208
Test name
Test status
Simulation time 1759955062 ps
CPU time 35.02 seconds
Started May 21 12:33:16 PM PDT 24
Finished May 21 12:34:12 PM PDT 24
Peak memory 216352 kb
Host smart-b810f83a-8a89-42bc-b7d5-9ae85403b85d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517221169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3517221169
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1298510681
Short name T31
Test name
Test status
Simulation time 237263254203 ps
CPU time 2328.02 seconds
Started May 21 12:33:15 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 237456 kb
Host smart-c9210c14-f4e8-4ee2-a16b-4cfe956d48e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298510681 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1298510681
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1145395618
Short name T60
Test name
Test status
Simulation time 964550990 ps
CPU time 10.04 seconds
Started May 21 12:33:14 PM PDT 24
Finished May 21 12:33:43 PM PDT 24
Peak memory 211168 kb
Host smart-840f4a23-5d38-4a73-905a-cd5e4480f3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145395618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1145395618
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.540216534
Short name T240
Test name
Test status
Simulation time 9180858452 ps
CPU time 48.56 seconds
Started May 21 12:33:15 PM PDT 24
Finished May 21 12:34:23 PM PDT 24
Peak memory 236736 kb
Host smart-0a7529ad-d08c-468f-bc7a-f5939cb5133b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540216534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.540216534
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.506055242
Short name T120
Test name
Test status
Simulation time 1067573261 ps
CPU time 16.69 seconds
Started May 21 12:33:13 PM PDT 24
Finished May 21 12:33:48 PM PDT 24
Peak memory 211252 kb
Host smart-f1c2b5a2-9d7d-4759-b422-2e8837b7a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506055242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.506055242
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1158547998
Short name T311
Test name
Test status
Simulation time 6025780166 ps
CPU time 14.01 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:41 PM PDT 24
Peak memory 211100 kb
Host smart-e40e6ec8-5cfd-49af-82a4-722009f01bc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158547998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1158547998
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1437577163
Short name T207
Test name
Test status
Simulation time 1815610053 ps
CPU time 15.33 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 12:34:12 PM PDT 24
Peak memory 213516 kb
Host smart-25a2f214-cfe0-489d-8e3c-d636397b695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437577163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1437577163
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2015544745
Short name T144
Test name
Test status
Simulation time 10059261018 ps
CPU time 99.78 seconds
Started May 21 12:32:53 PM PDT 24
Finished May 21 12:34:43 PM PDT 24
Peak memory 216340 kb
Host smart-c0690a44-22d8-4548-8e2c-d1a7ca7b0f9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015544745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2015544745
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4248778717
Short name T334
Test name
Test status
Simulation time 273203150254 ps
CPU time 2516.85 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 01:15:40 PM PDT 24
Peak memory 239388 kb
Host smart-54f4fc40-4ff3-488b-9215-ae5bad28d3a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248778717 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.4248778717
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1567082456
Short name T221
Test name
Test status
Simulation time 1253880387 ps
CPU time 11.59 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 211168 kb
Host smart-162644c8-4532-427b-81bd-bad88f4d3e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567082456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1567082456
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3773404817
Short name T28
Test name
Test status
Simulation time 9767733785 ps
CPU time 108.15 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:35:12 PM PDT 24
Peak memory 232480 kb
Host smart-fcef170e-4eed-4fed-a6eb-8696a3eaf598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773404817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3773404817
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2902942240
Short name T257
Test name
Test status
Simulation time 2705817311 ps
CPU time 24.75 seconds
Started May 21 12:33:21 PM PDT 24
Finished May 21 12:34:14 PM PDT 24
Peak memory 212088 kb
Host smart-becfac42-6ca8-4421-abac-9c8100a007d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902942240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2902942240
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.402480650
Short name T150
Test name
Test status
Simulation time 1569935377 ps
CPU time 7.96 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 210968 kb
Host smart-d63eeb95-091e-4621-b2df-714145df81af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402480650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.402480650
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.71951758
Short name T187
Test name
Test status
Simulation time 187264057 ps
CPU time 10.44 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:33:39 PM PDT 24
Peak memory 213468 kb
Host smart-2703533a-a35a-457a-8184-79c7d32f24f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71951758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.71951758
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2028845823
Short name T303
Test name
Test status
Simulation time 8954954497 ps
CPU time 52.75 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:43 PM PDT 24
Peak memory 217052 kb
Host smart-00d4f5e5-d423-4c88-bcb2-4f8e5076566c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028845823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2028845823
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4224000387
Short name T304
Test name
Test status
Simulation time 424485931 ps
CPU time 7.2 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 211128 kb
Host smart-65d6d61d-5ad7-42f6-9a2f-8c47ec9bdee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224000387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4224000387
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.811181396
Short name T200
Test name
Test status
Simulation time 106773589221 ps
CPU time 124.72 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 12:36:01 PM PDT 24
Peak memory 228488 kb
Host smart-d2883d12-330e-45dc-b938-e955d0a27b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811181396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.811181396
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1886970162
Short name T239
Test name
Test status
Simulation time 5225231933 ps
CPU time 24.35 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:52 PM PDT 24
Peak memory 212356 kb
Host smart-f230abe3-47fd-48ec-9e4d-a7cd85bd4bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886970162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1886970162
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3693245580
Short name T359
Test name
Test status
Simulation time 202572054 ps
CPU time 5.28 seconds
Started May 21 12:33:14 PM PDT 24
Finished May 21 12:33:38 PM PDT 24
Peak memory 211072 kb
Host smart-a1a7e4af-e528-41e0-b294-707f4af67c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693245580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3693245580
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.345795484
Short name T322
Test name
Test status
Simulation time 4108716224 ps
CPU time 32.05 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:33:55 PM PDT 24
Peak memory 213064 kb
Host smart-3c68d203-86ee-4da9-8e7e-d44b7026ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345795484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.345795484
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3970741383
Short name T181
Test name
Test status
Simulation time 5928220676 ps
CPU time 18.77 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:46 PM PDT 24
Peak memory 212040 kb
Host smart-367d0a8f-b294-4f7a-b403-323dd4ff7a2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970741383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3970741383
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3512533197
Short name T5
Test name
Test status
Simulation time 86580181 ps
CPU time 4.35 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:33:48 PM PDT 24
Peak memory 211156 kb
Host smart-4b50e73c-9216-4e80-8242-41674ff0c72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512533197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3512533197
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.739880764
Short name T24
Test name
Test status
Simulation time 26415476479 ps
CPU time 154.52 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:36:24 PM PDT 24
Peak memory 236904 kb
Host smart-d9bca079-7097-492c-9961-374e00f13efc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739880764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.739880764
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.540970088
Short name T146
Test name
Test status
Simulation time 616440543 ps
CPU time 9.44 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 211832 kb
Host smart-5a88d57b-e9fa-4a2d-96d9-76bde1759d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540970088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.540970088
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1613301481
Short name T253
Test name
Test status
Simulation time 833848331 ps
CPU time 10.13 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 210940 kb
Host smart-2fcde6aa-8cdd-4bba-8565-835d40e7d3fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613301481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1613301481
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1630229854
Short name T11
Test name
Test status
Simulation time 2071079372 ps
CPU time 24.3 seconds
Started May 21 12:33:24 PM PDT 24
Finished May 21 12:34:16 PM PDT 24
Peak memory 212736 kb
Host smart-85daf92d-559d-4a52-b6da-441d541ef12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630229854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1630229854
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1065287696
Short name T123
Test name
Test status
Simulation time 979198543 ps
CPU time 11.42 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:01 PM PDT 24
Peak memory 219296 kb
Host smart-2c62b3f3-6cb5-430b-96cc-28519ebbd6f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065287696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1065287696
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.456450833
Short name T266
Test name
Test status
Simulation time 1759788537 ps
CPU time 14.16 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:33:43 PM PDT 24
Peak memory 211440 kb
Host smart-25d59df0-2ac3-4e4a-b256-2708b947476d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456450833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.456450833
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1278735715
Short name T228
Test name
Test status
Simulation time 152052916696 ps
CPU time 327.62 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 230484 kb
Host smart-849c1795-cd59-43e8-ab4b-2803a4dc125e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278735715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1278735715
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4291598532
Short name T301
Test name
Test status
Simulation time 4076775237 ps
CPU time 32.25 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:34:16 PM PDT 24
Peak memory 211880 kb
Host smart-b20c95f3-bb5a-4822-a04b-cdc6e772bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291598532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4291598532
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2211729444
Short name T164
Test name
Test status
Simulation time 1721564521 ps
CPU time 15.34 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 210992 kb
Host smart-4b382a26-5797-4f0b-b5e1-15039c33d980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211729444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2211729444
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2610760997
Short name T199
Test name
Test status
Simulation time 183830223 ps
CPU time 10.08 seconds
Started May 21 12:33:29 PM PDT 24
Finished May 21 12:34:09 PM PDT 24
Peak memory 213480 kb
Host smart-3d9dca24-825a-4e83-beaf-69ba76110f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610760997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2610760997
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3174506480
Short name T263
Test name
Test status
Simulation time 50758308549 ps
CPU time 58.93 seconds
Started May 21 12:33:26 PM PDT 24
Finished May 21 12:34:54 PM PDT 24
Peak memory 218316 kb
Host smart-6b7bbc50-2ecb-48c7-b2ae-70ae5c1ecbbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174506480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3174506480
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4004013352
Short name T215
Test name
Test status
Simulation time 85583563 ps
CPU time 4.24 seconds
Started May 21 12:33:16 PM PDT 24
Finished May 21 12:33:41 PM PDT 24
Peak memory 211180 kb
Host smart-791dacc2-2a09-4752-9535-6e0d3eebd3f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004013352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4004013352
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.555055890
Short name T18
Test name
Test status
Simulation time 53366187191 ps
CPU time 240.14 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:37:45 PM PDT 24
Peak memory 228268 kb
Host smart-eeda40d3-d4c6-4b37-9b7d-322013dc564e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555055890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.555055890
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1644464700
Short name T23
Test name
Test status
Simulation time 8818878179 ps
CPU time 30.93 seconds
Started May 21 12:33:13 PM PDT 24
Finished May 21 12:34:04 PM PDT 24
Peak memory 212100 kb
Host smart-b7e14a68-87aa-49d9-a790-a2b7281c7122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644464700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1644464700
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1309079325
Short name T175
Test name
Test status
Simulation time 1084200153 ps
CPU time 11.12 seconds
Started May 21 12:33:21 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 210980 kb
Host smart-3d69c470-9968-46fa-98f5-b8d422aa4973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309079325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1309079325
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3871212605
Short name T203
Test name
Test status
Simulation time 745637005 ps
CPU time 9.94 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:00 PM PDT 24
Peak memory 212744 kb
Host smart-3ac3bd3c-8055-40c3-9821-f99540ca453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871212605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3871212605
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1668052291
Short name T222
Test name
Test status
Simulation time 25717239374 ps
CPU time 62.81 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:34:44 PM PDT 24
Peak memory 219316 kb
Host smart-7a75d308-1bac-4fef-ad72-baf89a5e8656
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668052291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1668052291
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.481688257
Short name T217
Test name
Test status
Simulation time 1581170052 ps
CPU time 12.79 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:03 PM PDT 24
Peak memory 211060 kb
Host smart-f7d7b4b2-9af5-4993-bf33-ff1b2bf0bba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481688257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.481688257
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.776705288
Short name T20
Test name
Test status
Simulation time 285821631857 ps
CPU time 273.54 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:38:04 PM PDT 24
Peak memory 228668 kb
Host smart-a98aba88-acc4-41d9-92a4-45d053554563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776705288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.776705288
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1422962077
Short name T166
Test name
Test status
Simulation time 1719571437 ps
CPU time 19.74 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 211636 kb
Host smart-4bd3b234-0881-4078-9d73-3cace0b2e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422962077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1422962077
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.117231442
Short name T2
Test name
Test status
Simulation time 2114988053 ps
CPU time 11.97 seconds
Started May 21 12:33:25 PM PDT 24
Finished May 21 12:34:06 PM PDT 24
Peak memory 210972 kb
Host smart-d8650756-7998-45b6-b792-c60bc19eac5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117231442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.117231442
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.371419042
Short name T139
Test name
Test status
Simulation time 748215697 ps
CPU time 15.26 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 214048 kb
Host smart-bbb33b05-db45-45ad-95d3-02690ee5994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371419042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.371419042
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1518245396
Short name T156
Test name
Test status
Simulation time 7995438848 ps
CPU time 25.02 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:34:16 PM PDT 24
Peak memory 219344 kb
Host smart-3a87e76a-7d8b-47f3-ab08-e75120c4b890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518245396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1518245396
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1479012326
Short name T306
Test name
Test status
Simulation time 523854060 ps
CPU time 7.69 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 211180 kb
Host smart-e4896d75-1001-460a-bd39-1875d0d626b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479012326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1479012326
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1704404668
Short name T348
Test name
Test status
Simulation time 68006807127 ps
CPU time 207.57 seconds
Started May 21 12:33:28 PM PDT 24
Finished May 21 12:37:25 PM PDT 24
Peak memory 230760 kb
Host smart-f8041177-b3be-40e4-937d-5e66fef9031f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704404668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1704404668
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3872227605
Short name T21
Test name
Test status
Simulation time 14956144688 ps
CPU time 31.97 seconds
Started May 21 12:33:29 PM PDT 24
Finished May 21 12:34:31 PM PDT 24
Peak memory 212092 kb
Host smart-33e918bd-7edc-41e6-af91-fa93f549e6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872227605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3872227605
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.419091555
Short name T4
Test name
Test status
Simulation time 41184259251 ps
CPU time 17.99 seconds
Started May 21 12:33:21 PM PDT 24
Finished May 21 12:34:07 PM PDT 24
Peak memory 211176 kb
Host smart-62c60cea-76db-4d7f-9ecd-89cd6706fea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419091555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.419091555
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3084292695
Short name T235
Test name
Test status
Simulation time 8408196745 ps
CPU time 38.12 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:34:22 PM PDT 24
Peak memory 219324 kb
Host smart-ead82554-9cc2-404d-bc07-d22f4cd12dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084292695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3084292695
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2422443173
Short name T268
Test name
Test status
Simulation time 3603674083 ps
CPU time 49.37 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:34:23 PM PDT 24
Peak memory 219332 kb
Host smart-f293fc7b-4c69-46b3-b1a6-e7525c2c551d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422443173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2422443173
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3129586899
Short name T36
Test name
Test status
Simulation time 949107698 ps
CPU time 10.31 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 211156 kb
Host smart-01f6d143-0962-4b1f-904a-de0a47299290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129586899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3129586899
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4131266860
Short name T279
Test name
Test status
Simulation time 162519183277 ps
CPU time 368.59 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:39:51 PM PDT 24
Peak memory 212420 kb
Host smart-bb12dd58-9e44-4288-8ba5-9ffc34e0fa57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131266860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4131266860
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.319617652
Short name T261
Test name
Test status
Simulation time 334183962 ps
CPU time 12.02 seconds
Started May 21 12:33:28 PM PDT 24
Finished May 21 12:34:10 PM PDT 24
Peak memory 211168 kb
Host smart-b32330bc-261f-45af-b7d1-d60cd7d75f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319617652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.319617652
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.617056406
Short name T287
Test name
Test status
Simulation time 8000179639 ps
CPU time 15.52 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:34:06 PM PDT 24
Peak memory 211108 kb
Host smart-1c1f2124-52e2-47c7-92df-2552b6520852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617056406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.617056406
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.591780772
Short name T340
Test name
Test status
Simulation time 201270941 ps
CPU time 10.04 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:34:02 PM PDT 24
Peak memory 219244 kb
Host smart-174f7249-52f7-40d1-873e-425fa04435ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591780772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.591780772
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1672878702
Short name T190
Test name
Test status
Simulation time 104599841 ps
CPU time 9.93 seconds
Started May 21 12:33:25 PM PDT 24
Finished May 21 12:34:03 PM PDT 24
Peak memory 210996 kb
Host smart-83459d8e-e40c-4189-8812-7d148adf2e27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672878702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1672878702
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3768519071
Short name T157
Test name
Test status
Simulation time 424464593 ps
CPU time 5.84 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 211128 kb
Host smart-a77a8942-b447-4328-b95d-ec1a076fb894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768519071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3768519071
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1985370850
Short name T270
Test name
Test status
Simulation time 33784944351 ps
CPU time 251.77 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:37:36 PM PDT 24
Peak memory 237820 kb
Host smart-84a00f96-f165-4f9a-92c1-02ddf79b8bf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985370850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1985370850
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1058043212
Short name T242
Test name
Test status
Simulation time 3190923392 ps
CPU time 26.36 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:17 PM PDT 24
Peak memory 213352 kb
Host smart-4d24c8b9-826f-4462-9070-0b1876be5296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058043212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1058043212
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2612351340
Short name T148
Test name
Test status
Simulation time 1124010797 ps
CPU time 9.29 seconds
Started May 21 12:32:45 PM PDT 24
Finished May 21 12:33:02 PM PDT 24
Peak memory 211052 kb
Host smart-07eb4f28-b261-40d4-a828-2344e23e4802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612351340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2612351340
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3967987437
Short name T35
Test name
Test status
Simulation time 6545531575 ps
CPU time 62.48 seconds
Started May 21 12:33:13 PM PDT 24
Finished May 21 12:34:34 PM PDT 24
Peak memory 229936 kb
Host smart-dcba86f0-5265-4fd0-9be2-04e64d70cf44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967987437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3967987437
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1339404482
Short name T179
Test name
Test status
Simulation time 3877943636 ps
CPU time 35.81 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:26 PM PDT 24
Peak memory 219352 kb
Host smart-2f082ee5-594e-4cb4-bce5-58e199d32b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339404482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1339404482
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3560643880
Short name T180
Test name
Test status
Simulation time 1898226553 ps
CPU time 7.17 seconds
Started May 21 12:32:52 PM PDT 24
Finished May 21 12:33:09 PM PDT 24
Peak memory 211028 kb
Host smart-272e28fb-91aa-4464-bab8-81d2e4c63dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560643880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3560643880
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1339123586
Short name T329
Test name
Test status
Simulation time 8157076204 ps
CPU time 15.87 seconds
Started May 21 12:33:21 PM PDT 24
Finished May 21 12:34:03 PM PDT 24
Peak memory 211200 kb
Host smart-cb4112da-8ff7-4d98-be87-7fb469fb40ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339123586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1339123586
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.701573186
Short name T141
Test name
Test status
Simulation time 67282249757 ps
CPU time 327.25 seconds
Started May 21 12:33:25 PM PDT 24
Finished May 21 12:39:20 PM PDT 24
Peak memory 212448 kb
Host smart-ea050d0c-0828-4d24-98b5-3b25adce8382
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701573186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.701573186
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2003311736
Short name T254
Test name
Test status
Simulation time 340229745 ps
CPU time 9.25 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 211648 kb
Host smart-10c4aad3-7187-4488-8232-941a0fbcf027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003311736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2003311736
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4108074576
Short name T136
Test name
Test status
Simulation time 905271141 ps
CPU time 10.82 seconds
Started May 21 12:33:21 PM PDT 24
Finished May 21 12:33:58 PM PDT 24
Peak memory 210996 kb
Host smart-b70fe30a-8a74-44ad-ab54-c4b403bab3c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108074576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4108074576
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2829281077
Short name T75
Test name
Test status
Simulation time 748813116 ps
CPU time 10.03 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 213820 kb
Host smart-4b3ea75b-6b42-471b-80e8-3420081df10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829281077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2829281077
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1743612483
Short name T89
Test name
Test status
Simulation time 397779967 ps
CPU time 22.27 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:34:06 PM PDT 24
Peak memory 214924 kb
Host smart-c1d82067-5d01-4c33-bbbb-a1ff2ff7327d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743612483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1743612483
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.400663911
Short name T163
Test name
Test status
Simulation time 4577726361 ps
CPU time 11.61 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 211240 kb
Host smart-da004ac6-6e3d-4f8e-87ad-3432c8116856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400663911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.400663911
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4036110817
Short name T227
Test name
Test status
Simulation time 2674413848 ps
CPU time 103.43 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:35:24 PM PDT 24
Peak memory 237844 kb
Host smart-1aa197af-83b8-4cc2-9de4-f0eb07de9eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036110817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4036110817
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3412010346
Short name T15
Test name
Test status
Simulation time 168367687 ps
CPU time 9.4 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:33:55 PM PDT 24
Peak memory 211756 kb
Host smart-0758c7fe-b838-4bed-b10b-aaf32ac8718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412010346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3412010346
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2024033662
Short name T285
Test name
Test status
Simulation time 14485494722 ps
CPU time 18.45 seconds
Started May 21 12:33:15 PM PDT 24
Finished May 21 12:33:52 PM PDT 24
Peak memory 211408 kb
Host smart-907d552c-15a7-4fbc-98ca-f0478ce8093a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024033662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2024033662
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.974249730
Short name T39
Test name
Test status
Simulation time 1205814296 ps
CPU time 16.21 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:34:01 PM PDT 24
Peak memory 213308 kb
Host smart-370cade1-3249-4284-a8f3-0801573c36cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974249730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.974249730
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3323226550
Short name T236
Test name
Test status
Simulation time 2438115414 ps
CPU time 34.72 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:25 PM PDT 24
Peak memory 219356 kb
Host smart-68800729-ebc3-428b-a935-31958655c299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323226550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3323226550
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4017225177
Short name T323
Test name
Test status
Simulation time 1056877485 ps
CPU time 10.78 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:33:55 PM PDT 24
Peak memory 211232 kb
Host smart-6246e303-5d18-4d5f-b993-9f1fe65b3ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017225177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4017225177
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4216815524
Short name T44
Test name
Test status
Simulation time 103155661025 ps
CPU time 277.14 seconds
Started May 21 12:33:28 PM PDT 24
Finished May 21 12:38:34 PM PDT 24
Peak memory 230680 kb
Host smart-1b7ab086-af3d-48d9-b392-cc54ad4bbd85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216815524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4216815524
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2818380900
Short name T317
Test name
Test status
Simulation time 1028655215 ps
CPU time 13.05 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:33:59 PM PDT 24
Peak memory 211792 kb
Host smart-bd29b93f-423a-47c3-84fc-31ccd8f15dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818380900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2818380900
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4148051885
Short name T188
Test name
Test status
Simulation time 989954429 ps
CPU time 11.15 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:33:58 PM PDT 24
Peak memory 211056 kb
Host smart-9649f810-c02b-4db1-be52-40d25aef9ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148051885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4148051885
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2689729068
Short name T92
Test name
Test status
Simulation time 4181085624 ps
CPU time 15.02 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 12:34:10 PM PDT 24
Peak memory 213752 kb
Host smart-e0cde056-0bf3-4cd3-a191-ac46ecc443e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689729068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2689729068
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1382963456
Short name T294
Test name
Test status
Simulation time 10923970200 ps
CPU time 106.87 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:35:30 PM PDT 24
Peak memory 219348 kb
Host smart-7af083c1-726f-4ead-b720-eb09cdf341b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382963456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1382963456
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2239912493
Short name T325
Test name
Test status
Simulation time 85734841 ps
CPU time 4.47 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 12:34:00 PM PDT 24
Peak memory 211140 kb
Host smart-46b0bfd7-680c-49c7-955d-f08e49c40e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239912493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2239912493
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2561452952
Short name T142
Test name
Test status
Simulation time 113081089610 ps
CPU time 290.55 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:38:40 PM PDT 24
Peak memory 213428 kb
Host smart-d26884d3-d438-4d8e-974d-36238d9ff5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561452952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2561452952
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4126717973
Short name T282
Test name
Test status
Simulation time 175768484 ps
CPU time 9.66 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:33:55 PM PDT 24
Peak memory 211668 kb
Host smart-ad462ba6-7a3c-428b-a1df-a33bcab0276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126717973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4126717973
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2132001627
Short name T292
Test name
Test status
Simulation time 2421988612 ps
CPU time 15.31 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:05 PM PDT 24
Peak memory 211064 kb
Host smart-148a243a-5792-45f3-9da9-e8342134b77c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132001627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2132001627
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3148132973
Short name T169
Test name
Test status
Simulation time 11807198187 ps
CPU time 25.07 seconds
Started May 21 12:33:28 PM PDT 24
Finished May 21 12:34:23 PM PDT 24
Peak memory 213352 kb
Host smart-3a7f5500-fba7-4a53-8528-9ae7d3bb08ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148132973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3148132973
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2591421715
Short name T226
Test name
Test status
Simulation time 17088507528 ps
CPU time 30.39 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:34:16 PM PDT 24
Peak memory 219380 kb
Host smart-fb0327eb-4f6f-4eb1-bf15-1bb821e4d7f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591421715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2591421715
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3973064074
Short name T232
Test name
Test status
Simulation time 85675567 ps
CPU time 4.34 seconds
Started May 21 12:33:13 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 211220 kb
Host smart-3f96de76-a05d-4282-a34e-61b617952e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973064074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3973064074
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1020674473
Short name T159
Test name
Test status
Simulation time 33198343151 ps
CPU time 298.28 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:38:45 PM PDT 24
Peak memory 233084 kb
Host smart-1e681411-cd93-4847-b0e6-a44b4a3945df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020674473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1020674473
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2298982933
Short name T246
Test name
Test status
Simulation time 3724474591 ps
CPU time 31.08 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:34:14 PM PDT 24
Peak memory 211988 kb
Host smart-b4bb7091-7776-43cf-a886-995c98b48e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298982933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2298982933
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3623767529
Short name T10
Test name
Test status
Simulation time 7410982250 ps
CPU time 15.69 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:34:07 PM PDT 24
Peak memory 211128 kb
Host smart-898a12cc-5ebb-4e0e-a5c2-c5a4d90913bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623767529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3623767529
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1470323735
Short name T289
Test name
Test status
Simulation time 5115451393 ps
CPU time 29.9 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:20 PM PDT 24
Peak memory 213140 kb
Host smart-37e9f096-681e-4966-a319-bab03835f4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470323735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1470323735
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.547447490
Short name T278
Test name
Test status
Simulation time 1777536748 ps
CPU time 17.07 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:34:03 PM PDT 24
Peak memory 211712 kb
Host smart-c8748ee2-b9bd-487d-9c21-dc92e19d0d50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547447490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.547447490
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.180307956
Short name T341
Test name
Test status
Simulation time 829997183 ps
CPU time 4.29 seconds
Started May 21 12:33:17 PM PDT 24
Finished May 21 12:33:45 PM PDT 24
Peak memory 211180 kb
Host smart-959cb2a1-ab51-457d-b6ce-9ed98361342c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180307956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.180307956
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3404180966
Short name T350
Test name
Test status
Simulation time 2151786293 ps
CPU time 129.27 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:35:56 PM PDT 24
Peak memory 228736 kb
Host smart-dbf29ced-b171-46e2-a8a9-a99b052c222b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404180966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3404180966
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3979314132
Short name T241
Test name
Test status
Simulation time 170694823 ps
CPU time 9.17 seconds
Started May 21 12:33:16 PM PDT 24
Finished May 21 12:33:46 PM PDT 24
Peak memory 211824 kb
Host smart-b84c957c-94e0-4224-908b-ea5b4c1bd961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979314132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3979314132
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3930584213
Short name T90
Test name
Test status
Simulation time 2673207423 ps
CPU time 12.88 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:03 PM PDT 24
Peak memory 211100 kb
Host smart-5c50b4c8-c640-4bb8-86dd-643527caf1ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930584213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3930584213
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2577193132
Short name T85
Test name
Test status
Simulation time 16166022864 ps
CPU time 43.26 seconds
Started May 21 12:33:18 PM PDT 24
Finished May 21 12:34:26 PM PDT 24
Peak memory 213956 kb
Host smart-d4822f14-f320-41ad-9005-da320e074c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577193132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2577193132
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1045002217
Short name T248
Test name
Test status
Simulation time 953418101 ps
CPU time 25.29 seconds
Started May 21 12:33:24 PM PDT 24
Finished May 21 12:34:17 PM PDT 24
Peak memory 214684 kb
Host smart-efc97763-bddb-4a31-acf1-3edf6abe2690
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045002217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1045002217
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.439952360
Short name T154
Test name
Test status
Simulation time 6369707658 ps
CPU time 14.28 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 12:34:11 PM PDT 24
Peak memory 211216 kb
Host smart-7abf23ab-9c26-4e64-9cda-93b23eda0bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439952360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.439952360
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.975736210
Short name T210
Test name
Test status
Simulation time 24100198611 ps
CPU time 237.17 seconds
Started May 21 12:33:24 PM PDT 24
Finished May 21 12:37:49 PM PDT 24
Peak memory 220140 kb
Host smart-0a5db64d-3a6a-47d4-99ee-4e4fdc0846e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975736210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.975736210
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1943555223
Short name T252
Test name
Test status
Simulation time 7167687425 ps
CPU time 20.4 seconds
Started May 21 12:33:20 PM PDT 24
Finished May 21 12:34:06 PM PDT 24
Peak memory 212332 kb
Host smart-af5a3811-1746-40aa-a73a-b8ffcc5e5e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943555223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1943555223
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3175600587
Short name T133
Test name
Test status
Simulation time 1161344555 ps
CPU time 12.69 seconds
Started May 21 12:33:22 PM PDT 24
Finished May 21 12:34:02 PM PDT 24
Peak memory 211092 kb
Host smart-cb999893-60f3-4caf-a34b-e9e07aa546bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175600587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3175600587
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.569234667
Short name T12
Test name
Test status
Simulation time 1400720906 ps
CPU time 14.84 seconds
Started May 21 12:33:26 PM PDT 24
Finished May 21 12:34:09 PM PDT 24
Peak memory 219216 kb
Host smart-ec9cda0d-81c1-4e33-aa9d-8f3ddf673c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569234667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.569234667
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1715019750
Short name T342
Test name
Test status
Simulation time 18152156747 ps
CPU time 80.99 seconds
Started May 21 12:33:28 PM PDT 24
Finished May 21 12:35:19 PM PDT 24
Peak memory 217764 kb
Host smart-c1bb9894-74ce-4c0a-bde8-d7b834731ff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715019750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1715019750
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2900343415
Short name T48
Test name
Test status
Simulation time 58410510549 ps
CPU time 440.66 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:41:12 PM PDT 24
Peak memory 235428 kb
Host smart-1b9048a2-389f-4f19-ae8d-8fd7ecfeea41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900343415 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2900343415
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4284529759
Short name T319
Test name
Test status
Simulation time 1151741233 ps
CPU time 8.29 seconds
Started May 21 12:33:21 PM PDT 24
Finished May 21 12:33:56 PM PDT 24
Peak memory 211220 kb
Host smart-67bfd96f-7416-4a5e-a518-a70223761540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284529759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4284529759
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1466641147
Short name T262
Test name
Test status
Simulation time 22179123906 ps
CPU time 220.26 seconds
Started May 21 12:33:29 PM PDT 24
Finished May 21 12:37:39 PM PDT 24
Peak memory 228424 kb
Host smart-6b69375e-8991-4ad0-b587-5218f7d7ee76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466641147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1466641147
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1980079629
Short name T290
Test name
Test status
Simulation time 68597529625 ps
CPU time 30.92 seconds
Started May 21 12:33:30 PM PDT 24
Finished May 21 12:34:31 PM PDT 24
Peak memory 212044 kb
Host smart-7742012f-9005-4531-bc01-950714eb2ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980079629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1980079629
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1511661123
Short name T191
Test name
Test status
Simulation time 1960757875 ps
CPU time 17.27 seconds
Started May 21 12:33:16 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 210972 kb
Host smart-b4b1c372-9e08-4d93-8db6-af00a7f4d49a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511661123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1511661123
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.160074695
Short name T305
Test name
Test status
Simulation time 7585071943 ps
CPU time 22.12 seconds
Started May 21 12:33:23 PM PDT 24
Finished May 21 12:34:14 PM PDT 24
Peak memory 214620 kb
Host smart-438fd744-c746-4e61-9425-83fdff372f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160074695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.160074695
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3236405298
Short name T153
Test name
Test status
Simulation time 73673534605 ps
CPU time 34.47 seconds
Started May 21 12:33:31 PM PDT 24
Finished May 21 12:34:36 PM PDT 24
Peak memory 219396 kb
Host smart-09e3c7cf-def6-4818-a60e-2e36e8cd611d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236405298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3236405298
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1856917158
Short name T284
Test name
Test status
Simulation time 1150570991 ps
CPU time 11.15 seconds
Started May 21 12:33:28 PM PDT 24
Finished May 21 12:34:08 PM PDT 24
Peak memory 211172 kb
Host smart-bc016ffb-4b62-457d-a5b4-69a122817c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856917158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1856917158
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3796402857
Short name T361
Test name
Test status
Simulation time 7192174898 ps
CPU time 131.84 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:35:57 PM PDT 24
Peak memory 225000 kb
Host smart-adcdd64f-b109-43a6-8656-747a346cc488
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796402857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3796402857
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4086333552
Short name T183
Test name
Test status
Simulation time 5763161265 ps
CPU time 31.1 seconds
Started May 21 12:33:25 PM PDT 24
Finished May 21 12:34:25 PM PDT 24
Peak memory 212400 kb
Host smart-460b37d2-7bc0-4b56-8740-a1bce01d1d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086333552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4086333552
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2015714191
Short name T98
Test name
Test status
Simulation time 100104439 ps
CPU time 5.73 seconds
Started May 21 12:33:29 PM PDT 24
Finished May 21 12:34:04 PM PDT 24
Peak memory 210940 kb
Host smart-34746d3c-5c0b-474e-85fd-4056a34e3043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015714191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2015714191
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2893885242
Short name T155
Test name
Test status
Simulation time 896236908 ps
CPU time 13.31 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 12:34:09 PM PDT 24
Peak memory 219276 kb
Host smart-9e5eca6e-c457-4ab5-95a7-a7f736cd253b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893885242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2893885242
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1411053816
Short name T91
Test name
Test status
Simulation time 38725706425 ps
CPU time 73.39 seconds
Started May 21 12:33:24 PM PDT 24
Finished May 21 12:35:06 PM PDT 24
Peak memory 219284 kb
Host smart-8a264926-8013-4482-9bf1-8b024f344344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411053816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1411053816
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1155677653
Short name T8
Test name
Test status
Simulation time 8967614943 ps
CPU time 339.64 seconds
Started May 21 12:33:29 PM PDT 24
Finished May 21 12:39:38 PM PDT 24
Peak memory 224172 kb
Host smart-eba2942e-b623-4e36-9673-c06baa2b4ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155677653 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1155677653
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1086295758
Short name T126
Test name
Test status
Simulation time 85401399 ps
CPU time 4.27 seconds
Started May 21 12:33:19 PM PDT 24
Finished May 21 12:33:48 PM PDT 24
Peak memory 211116 kb
Host smart-e6bbcb43-713e-478a-875e-38f5c50136cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086295758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1086295758
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4020417339
Short name T255
Test name
Test status
Simulation time 159355444269 ps
CPU time 391.52 seconds
Started May 21 12:33:25 PM PDT 24
Finished May 21 12:40:25 PM PDT 24
Peak memory 224816 kb
Host smart-63304dc1-c5dc-4d19-9300-263d7dd144b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020417339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4020417339
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1757657088
Short name T291
Test name
Test status
Simulation time 6250846584 ps
CPU time 28.04 seconds
Started May 21 12:33:30 PM PDT 24
Finished May 21 12:34:28 PM PDT 24
Peak memory 212180 kb
Host smart-8ee770ce-ba55-4321-ac67-8ecb0320817a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757657088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1757657088
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.276547368
Short name T293
Test name
Test status
Simulation time 2319045330 ps
CPU time 9.21 seconds
Started May 21 12:33:30 PM PDT 24
Finished May 21 12:34:10 PM PDT 24
Peak memory 211176 kb
Host smart-af102aa9-a795-45c1-9f32-e7abc9ddfe03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276547368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.276547368
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4240096393
Short name T315
Test name
Test status
Simulation time 2986191970 ps
CPU time 19.41 seconds
Started May 21 12:33:26 PM PDT 24
Finished May 21 12:34:14 PM PDT 24
Peak memory 219400 kb
Host smart-3565c1e8-d653-4ef5-bcb3-1847013e554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240096393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4240096393
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.601879973
Short name T124
Test name
Test status
Simulation time 19325544563 ps
CPU time 55.37 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 12:34:52 PM PDT 24
Peak memory 219404 kb
Host smart-353ed497-08e7-4fa4-9db6-98334bbeb4e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601879973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.601879973
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3057041641
Short name T30
Test name
Test status
Simulation time 89109361641 ps
CPU time 2930.69 seconds
Started May 21 12:33:27 PM PDT 24
Finished May 21 01:22:47 PM PDT 24
Peak memory 235976 kb
Host smart-767279bb-0d0f-4a86-a044-2dcc1a64e089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057041641 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3057041641
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2654541608
Short name T345
Test name
Test status
Simulation time 1315253647 ps
CPU time 6.32 seconds
Started May 21 12:32:40 PM PDT 24
Finished May 21 12:32:54 PM PDT 24
Peak memory 211120 kb
Host smart-acbb1536-2977-4ba0-ade4-4f94c9c083c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654541608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2654541608
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.173209865
Short name T256
Test name
Test status
Simulation time 7816977460 ps
CPU time 120.64 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:35:30 PM PDT 24
Peak memory 230744 kb
Host smart-3ba1b2c7-218c-49fd-a7d0-cfaaa34eceb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173209865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.173209865
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1555242193
Short name T224
Test name
Test status
Simulation time 1383901202 ps
CPU time 9.35 seconds
Started May 21 12:32:55 PM PDT 24
Finished May 21 12:33:14 PM PDT 24
Peak memory 211824 kb
Host smart-de3da791-ffe3-4a6c-932d-efa16c1f1a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555242193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1555242193
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4142934193
Short name T100
Test name
Test status
Simulation time 1781295207 ps
CPU time 10.52 seconds
Started May 21 12:33:08 PM PDT 24
Finished May 21 12:33:33 PM PDT 24
Peak memory 211032 kb
Host smart-471af31e-01f9-4066-aa9e-3955d8e14494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142934193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4142934193
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3129496829
Short name T72
Test name
Test status
Simulation time 43078247670 ps
CPU time 25.67 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:15 PM PDT 24
Peak memory 219336 kb
Host smart-705e907c-2a08-4931-af94-e31daf5bb2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129496829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3129496829
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.652353785
Short name T337
Test name
Test status
Simulation time 795533749 ps
CPU time 11.36 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:33:22 PM PDT 24
Peak memory 213788 kb
Host smart-dd4c31e4-f791-4ac1-b724-4ac5ce8cb7fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652353785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.652353785
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.81986112
Short name T61
Test name
Test status
Simulation time 1381455995 ps
CPU time 4.2 seconds
Started May 21 12:33:06 PM PDT 24
Finished May 21 12:33:25 PM PDT 24
Peak memory 211160 kb
Host smart-32c77125-25b9-4897-b459-a483277fcd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81986112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.81986112
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3281679434
Short name T358
Test name
Test status
Simulation time 9315272088 ps
CPU time 165.66 seconds
Started May 21 12:33:09 PM PDT 24
Finished May 21 12:36:12 PM PDT 24
Peak memory 225680 kb
Host smart-0349ce6a-bb77-4542-8eec-53d689d4f31d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281679434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3281679434
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4188374027
Short name T42
Test name
Test status
Simulation time 21168087360 ps
CPU time 34.46 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:32 PM PDT 24
Peak memory 212260 kb
Host smart-03b463af-aecd-4486-997b-0f01839f5838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188374027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4188374027
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3538199169
Short name T165
Test name
Test status
Simulation time 1478258920 ps
CPU time 13.23 seconds
Started May 21 12:32:50 PM PDT 24
Finished May 21 12:33:13 PM PDT 24
Peak memory 210904 kb
Host smart-24e5668d-e221-4e92-a3d1-56567d0ff078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538199169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3538199169
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3427639862
Short name T347
Test name
Test status
Simulation time 5235599788 ps
CPU time 26.67 seconds
Started May 21 12:32:57 PM PDT 24
Finished May 21 12:33:34 PM PDT 24
Peak memory 214224 kb
Host smart-6c390779-7531-482a-ac74-a13295d36524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427639862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3427639862
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.864714943
Short name T206
Test name
Test status
Simulation time 7367449980 ps
CPU time 36.95 seconds
Started May 21 12:32:52 PM PDT 24
Finished May 21 12:33:38 PM PDT 24
Peak memory 213204 kb
Host smart-03f46b37-cf67-4884-8ba8-d0a5ff02a095
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864714943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.864714943
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3869263857
Short name T32
Test name
Test status
Simulation time 293112561253 ps
CPU time 2768.15 seconds
Started May 21 12:32:49 PM PDT 24
Finished May 21 01:19:07 PM PDT 24
Peak memory 235420 kb
Host smart-7e735840-6d39-4942-8834-ec58b3e114d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869263857 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3869263857
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3489252110
Short name T193
Test name
Test status
Simulation time 17427815682 ps
CPU time 14.38 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:11 PM PDT 24
Peak memory 211256 kb
Host smart-97e10647-a12c-4a26-8bc7-ff484ddd479c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489252110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3489252110
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3406545381
Short name T185
Test name
Test status
Simulation time 27939995068 ps
CPU time 265.61 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:37:22 PM PDT 24
Peak memory 237404 kb
Host smart-3be319ac-831f-4559-b99f-39781db66086
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406545381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3406545381
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3939323080
Short name T230
Test name
Test status
Simulation time 18861259706 ps
CPU time 22.01 seconds
Started May 21 12:33:03 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 212060 kb
Host smart-c78d550c-6c41-44da-a086-ac4446961695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939323080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3939323080
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2122282955
Short name T338
Test name
Test status
Simulation time 3795685220 ps
CPU time 11.33 seconds
Started May 21 12:33:05 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 211084 kb
Host smart-7647ebd2-08a8-487f-8570-002c6f76181a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122282955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2122282955
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1302093577
Short name T1
Test name
Test status
Simulation time 6465723315 ps
CPU time 20.82 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:33:09 PM PDT 24
Peak memory 219316 kb
Host smart-7b250280-8111-4e9f-ac62-319668d852d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302093577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1302093577
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3383852449
Short name T296
Test name
Test status
Simulation time 16846759190 ps
CPU time 31.84 seconds
Started May 21 12:33:04 PM PDT 24
Finished May 21 12:33:48 PM PDT 24
Peak memory 219344 kb
Host smart-ce856ce0-22d0-4e7c-8f85-9628106978b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383852449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3383852449
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2199360082
Short name T220
Test name
Test status
Simulation time 6745625351 ps
CPU time 14.31 seconds
Started May 21 12:32:43 PM PDT 24
Finished May 21 12:33:05 PM PDT 24
Peak memory 211324 kb
Host smart-6c01725c-7f42-4237-915a-9b1e27383c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199360082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2199360082
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3343874019
Short name T27
Test name
Test status
Simulation time 2977487855 ps
CPU time 153.55 seconds
Started May 21 12:32:42 PM PDT 24
Finished May 21 12:35:22 PM PDT 24
Peak memory 234932 kb
Host smart-5f22910b-a8a0-4e3d-995d-bbbb8613097e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343874019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3343874019
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4212649382
Short name T151
Test name
Test status
Simulation time 5500758417 ps
CPU time 18.28 seconds
Started May 21 12:32:54 PM PDT 24
Finished May 21 12:33:22 PM PDT 24
Peak memory 212196 kb
Host smart-6c142072-d552-41db-95a5-588a57765143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212649382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4212649382
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.750217169
Short name T197
Test name
Test status
Simulation time 285769672 ps
CPU time 6.24 seconds
Started May 21 12:32:45 PM PDT 24
Finished May 21 12:33:00 PM PDT 24
Peak memory 210984 kb
Host smart-d138d851-4559-4032-9e96-73462d2f9c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750217169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.750217169
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.327429134
Short name T288
Test name
Test status
Simulation time 1572264817 ps
CPU time 9.94 seconds
Started May 21 12:32:51 PM PDT 24
Finished May 21 12:33:11 PM PDT 24
Peak memory 213492 kb
Host smart-c0dfa78b-bdff-4cfd-a27b-26e1cc3f5f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327429134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.327429134
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3974551299
Short name T202
Test name
Test status
Simulation time 2950264120 ps
CPU time 34.08 seconds
Started May 21 12:32:44 PM PDT 24
Finished May 21 12:33:27 PM PDT 24
Peak memory 214016 kb
Host smart-8a19a2fc-7a8a-49e8-803f-db012617fd5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974551299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3974551299
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1427515478
Short name T274
Test name
Test status
Simulation time 171257517 ps
CPU time 4.35 seconds
Started May 21 12:32:57 PM PDT 24
Finished May 21 12:33:12 PM PDT 24
Peak memory 211220 kb
Host smart-079aca9f-09a4-4560-8f2a-a14585ceb661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427515478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1427515478
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1426517296
Short name T218
Test name
Test status
Simulation time 43136198857 ps
CPU time 146.28 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:36:00 PM PDT 24
Peak memory 229824 kb
Host smart-61c71d77-f921-484e-b375-e8393932a262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426517296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1426517296
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.112373581
Short name T332
Test name
Test status
Simulation time 371764502 ps
CPU time 9.58 seconds
Started May 21 12:32:59 PM PDT 24
Finished May 21 12:33:20 PM PDT 24
Peak memory 212116 kb
Host smart-6b4681b1-4bbe-460f-9a6b-41d00b5477c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112373581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.112373581
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3093827143
Short name T88
Test name
Test status
Simulation time 5761106303 ps
CPU time 13.99 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:12 PM PDT 24
Peak memory 211080 kb
Host smart-4200afc2-55f4-44a6-9332-a5217c0e3697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093827143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3093827143
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3514942414
Short name T298
Test name
Test status
Simulation time 13725291562 ps
CPU time 32.3 seconds
Started May 21 12:32:48 PM PDT 24
Finished May 21 12:33:29 PM PDT 24
Peak memory 219328 kb
Host smart-fb2da87b-8f98-405a-ab4a-55b183904f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514942414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3514942414
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2641093814
Short name T73
Test name
Test status
Simulation time 14518257215 ps
CPU time 71.89 seconds
Started May 21 12:32:46 PM PDT 24
Finished May 21 12:34:07 PM PDT 24
Peak memory 219328 kb
Host smart-5b864431-27b0-4dcd-b970-fbff5541514e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641093814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2641093814
Directory /workspace/9.rom_ctrl_stress_all/latest
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