Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1530008

1

T2

214

T3

260

T4

88

full_word

973729

1

T2

17

T3

28

T4

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2503447	1			T2	231		T3	288		T4	95
auto[TlIntgErrCmd]	97	1			T59	2		T60	4		T61	6
auto[TlIntgErrData]	85	1			T59	4		T60	1		T61	5
auto[TlIntgErrBoth]	108	1			T59	4		T60	5		T61	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

409319

1

T2

231

T3

288

T4

95

auto[1]

2094418

1

T13

212690

T16

3203

T18

281280

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	178045	1			T2	214		T3	260		T4	88
auto[TlIntgErrNone]	partial	auto[1]	1351704	1			T13	137465		T16	2163		T18	184014
auto[TlIntgErrNone]	full_word	auto[0]	231148	1			T2	17		T3	28		T4	7
auto[TlIntgErrNone]	full_word	auto[1]	742550	1			T13	75225		T16	1040		T18	97266
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T59	1		T60	3		T61	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T59	1		T60	1		T61	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T109	1		T110	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T61	2		T103	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T59	1		T61	3		T111	2
auto[TlIntgErrData]	partial	auto[1]	33	1			T59	2		T60	1		T61	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T59	1		T61	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T103	1		T113	1		T112	2
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T59	2		T60	3		T61	4
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T59	1		T60	2		T61	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T61	1		T106	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T59	1		T103	1		T111	2