Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2798957

1

T3

76

T5

56

T7

223

full_word

1779006

1

T1

4

T3

10

T4

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4577643	1			T1	4		T3	86		T4	2
auto[TlIntgErrCmd]	93	1			T54	5		T55	8		T56	7
auto[TlIntgErrData]	103	1			T54	2		T55	6		T56	5
auto[TlIntgErrBoth]	124	1			T54	3		T55	6		T56	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

725773

1

T1

4

T3

86

T4

2

auto[1]

3852190

1

T9

120576

T15

70803

T16

187769

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	305649	1			T3	76		T5	56		T7	223
auto[TlIntgErrNone]	partial	auto[1]	2493018	1			T9	78424		T15	44193		T16	119057
auto[TlIntgErrNone]	full_word	auto[0]	419973	1			T1	4		T3	10		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	1359003	1			T9	42152		T15	26610		T16	68712
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T54	3		T55	2		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T54	2		T55	5		T56	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T55	1		T109	2		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T109	1		T110	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T54	1		T55	4		T56	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T54	1		T55	2		T56	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T56	1		T114	1		T118	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T119	1		T120	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T54	1		T55	2		T56	4
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T54	2		T55	4		T56	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T110	1		T119	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T116	1		T114	1		T119	1