Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1900208

1

T1

165

T2

90

T3

54

full_word

1201404

1

T1

21

T2

13

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3101312	1			T1	186		T2	103		T3	63
auto[TlIntgErrCmd]	105	1			T58	8		T59	11		T60	6
auto[TlIntgErrData]	100	1			T58	4		T59	6		T60	9
auto[TlIntgErrBoth]	95	1			T58	8		T59	3		T60	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

507672

1

T1

186

T2

103

T3

63

auto[1]

2593940

1

T4

276202

T9

117401

T17

252839

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	222253	1			T1	165		T2	90		T3	54
auto[TlIntgErrNone]	partial	auto[1]	1677674	1			T4	180171		T9	75884		T17	164537
auto[TlIntgErrNone]	full_word	auto[0]	285272	1			T1	21		T2	13		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	916113	1			T4	96031		T9	41517		T17	88302
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T58	5		T59	4		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T58	2		T59	7		T60	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T110	1		T111	1		T112	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T58	1		T113	1		T114	2
auto[TlIntgErrData]	partial	auto[0]	57	1			T58	3		T59	3		T60	7
auto[TlIntgErrData]	partial	auto[1]	40	1			T58	1		T59	3		T60	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T114	1		T115	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T58	3		T59	1		T60	3
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T58	5		T59	1		T60	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T114	1		T117	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T59	1		T114	1		T118	1